diff --git a/drivers/QSPI.cpp b/drivers/QSPI.cpp new file mode 100644 index 00000000000..2e8d4632219 --- /dev/null +++ b/drivers/QSPI.cpp @@ -0,0 +1,409 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 Nordic Semiconductor ASA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "QSPI.h" +#include "qspi_api.h" +#include "mbed_assert.h" + + +#ifdef DEVICE_QSPI + +// Command for reading status register +#define QSPI_STD_CMD_RDSR 0x05 +// Command for writing status register +#define QSPI_STD_CMD_WRSR 0x01 +// Command for reading control register (supported only by some memories) +#define QSPI_STD_CMD_RDCR 0x35 +// Command for writing control register (supported only by some memories) +#define QSPI_STD_CMD_WRCR 0x3E + +namespace mbed { + +SingletonPtr QSPI::_mutex; + +static inline bool is_aligned(uint32_t number, uint32_t alignment) +{ + if ((number % alignment) != 0) { + return false; + } else { + return true; + } +} + +QSPI::QSPI(PinName miso, PinName mosi, PinName sclk, PinName ssel, int hz, int spi_mode) : + #if DEVICE_SPI_ASYNCH + _irq(this), + _usage(DMA_USAGE_NEVER) + #endif +{ + qspi_pins_t pins; + + pins.sclk = sclk; + pins.ssel = ssel; + pins.io0 = miso; + pins.io1 = mosi; + pins.io2 = NC; + pins.io3 = NC; + + /* Preparing physical communication part */ + qspi_init(&_qspi, hz, &pins, spi_mode); + quad_mode_hw_support = false; +} + +QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int hz, int spi_mode) : + #if DEVICE_SPI_ASYNCH + _irq(this), + _usage(DMA_USAGE_NEVER) + #endif +{ + qspi_pins_t pins; + + pins.sclk = sclk; + pins.ssel = ssel; + pins.io0 = io0; + pins.io1 = io1; + pins.io2 = io2; + pins.io3 = io3; + + /* Preparing physical communication part */ + qspi_init(&_qspi, hz, &pins, spi_mode); + quad_mode_hw_support = true; +} + +QSPI::~QSPI() +{ + +} + +int QSPI::init() +{ + /* Preparing protocol communication part. We do not care about return values because + * we are using standard, most generic values. */ + (void)qspi_prepare(&_qspi, + QSPI_ADDRMODE_24BIT, + QSPI_READMODE_1_1_1, + QSPI_WRITEMODE_1_1_1); + + /* Setting default, generic flash memory values. Could works with every flash memory. */ + flash_size = 0; + page_size = 256; + sector_size = 4096; + + /* Starting QSPI */ + int ret = 0; + _mutex->lock(); + if (qspi_start(&_qspi)) { + ret = -1; + } + _mutex->unlock(); + return ret; +} + +int QSPI::init(QSPIMemSpec *memspec) +{ + uint8_t status_value[2]; + uint8_t cmd_to_send = 0; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + + int ret = 0; + + /* If there is no enough pins so why we could give a chance to start quad mode? */ + if (!quad_mode_hw_support && + (memspec->read_mode_get() != QSPI_READMODE_1_1_1) && + (memspec->write_mode_get() != QSPI_WRITEMODE_1_1_1)) + { + return -1; + } + + /* Filling peripheral registers. */ + if (qspi_prepare(&_qspi, + memspec->addr_mode_get(), + memspec->read_mode_get(), + memspec->write_mode_get())) + { + return -1; + } + + /* Filling runtime variables. */ + flash_size = memspec->flash_size_get(); + page_size = memspec->page_size_get(); + sector_size = memspec->sector_size_get(); + + _mutex->lock(); + if (qspi_start(&_qspi)) { + _mutex->unlock(); + return -1; + } + + /* Read status registers. They can be used in near future. */ + if (qspi_send_instruction(&_qspi, + QSPI_STD_CMD_RDSR, // command to send + 0, // do not transmit + NULL, // do not transmit + 2, // just receive two bytes of data + status_value)) // store received values in status_value + { + _mutex->unlock(); + return -1; + } + _mutex->unlock(); + + /* Activate quad mode if necessary. + * Lot of code placed below is based on text placed here: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/sfdp.h#613 + * Bits are ordered from zero. Bit0 -> first position in byte. Bit1 -> second position. */ + + if ((memspec->read_mode_get() != QSPI_READMODE_1_1_1) && (memspec->write_mode_get() != QSPI_WRITEMODE_1_1_1)) + { + switch(memspec->quad_mode_req_get()) + { + case QSPIMemSpec::MEMSPEC_QUADMODREQ_NO_REQ: + break; + case QSPIMemSpec::MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR2B: + status_value[1] |= 0x02; + // Send both bytes with WRSR. + + cmd_to_send = QSPI_STD_CMD_WRSR; // command to send + data_len = 2; // transmit 2 bytes of data + p_data = status_value; // source of data + + break; + case QSPIMemSpec::MEMSPEC_QUADMODREQ_6BIT_1SREG: + status_value[0] |= 0x40; + // Send only one byte with WRSR. Could be enough. + + cmd_to_send = QSPI_STD_CMD_WRSR; // command to send + data_len = 1; // transmit 1 byte of data + p_data = status_value; // source of data + + break; + case QSPIMemSpec::MEMSPEC_QUADMODREQ_7BIT_2SREG_W3EH_R3FH: + status_value[1] |= 0x80; + // Send only second byte with WRCR command. + + cmd_to_send = QSPI_STD_CMD_WRCR; // command to send + data_len = 1; // transmit 1 byte of data + p_data = &status_value[1]; // source of data + + break; + case QSPIMemSpec::MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR1B: + status_value[1] |= 0x02; + // Send both bytes with WRSR. Probably can be merged with MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR2B case. + + cmd_to_send = QSPI_STD_CMD_WRSR; // command to send + data_len = 2; // transmit 2 bytes of data + p_data = status_value; // source of data + + break; + case QSPIMemSpec::MEMSPEC_QUADMODREQ_1BIT_2SREG_R35H_W01H_W2B: + status_value[1] |= 0x02; + // Send both bytes with WRSR. Probably can be merged with MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR2B case. + + cmd_to_send = QSPI_STD_CMD_WRSR; // command to send + data_len = 2; // transmit 1 byte of data + p_data = status_value; // source of data + + break; + default: + qspi_free(&_qspi); + ret = -1; + } + + /* If there is setting to send (with memory configuration) just send it. */ + if (data_len > 0) + { + _mutex->lock(); + ret = qspi_send_instruction(&_qspi, + cmd_to_send, // command to send + data_len, // transmit 2 bytes of data + p_data, // source of data + 0, // do not receive data + NULL); // do not receive data + _mutex->unlock(); + } + } + return ret; +} + +int QSPI::deinit() +{ + int ret = 0; + _mutex->lock(); + if (qspi_free(&_qspi)) { + ret = -1; + } + _mutex->unlock(); + return ret; +} + + +int QSPI::read(void *buffer, uint32_t addr, uint32_t size) +{ + _mutex->lock(); + int result = qspi_page_read(&_qspi, addr, (uint8_t *)buffer, size); + _mutex->unlock(); + return result; +} + +int QSPI::program(const void *buffer, uint32_t addr, uint32_t size) +{ + // addr and size should be aligned to page size, and multiple of page size + // page program should not cross sector boundaries + if (!is_aligned(addr, page_size) || + !is_aligned(size, page_size) || + (size < page_size) || + (((addr % sector_size) + size) > sector_size)) { + return -1; + } + + int ret = 0; + _mutex->lock(); + if (qspi_program_page(&_qspi, addr, (const uint8_t *)buffer, size)) { + ret = -1; + } + _mutex->unlock(); + return ret; +} + +bool QSPI::is_aligned_to_sector(uint32_t addr, uint32_t size) +{ + if (!is_aligned(size, sector_size) || + !is_aligned(addr, sector_size)) { + return false; + } else { + return true; + } +} + +int QSPI::erase(uint32_t addr, uint32_t size) +{ + if (!is_aligned_to_sector(addr, size)) { + return -1; + } + + int32_t ret = 0; + _mutex->lock(); + while (size) { + ret = qspi_erase_block(&_qspi, addr); + if (ret != 0) { + ret = -1; + break; + } + while (qspi_is_busy(&_qspi) != 0); + if (!is_aligned_to_sector(addr, size)) { + ret = -1; + break; + } + size -= sector_size; + addr += sector_size; + } + _mutex->unlock(); + return ret; +} + +int QSPI::is_memory_busy(void) +{ + uint8_t status_value = 0; + int32_t ret = 0; + if (_qspi.is_busy == 1) + { + return -1; + } + _mutex->lock(); + ret = qspi_send_instruction(&_qspi, + QSPI_STD_CMD_RDSR, // command to send + 0, // do not transmit + NULL, // do not transmit + 1, // receive just one byte of data + &status_value); // store received values in status_value + _mutex->unlock(); + if (ret == 0) + { + if ((status_value & 0x01) != 0x00) // WIP bit is always first bit in status byte. 0 means ready, 1 means busy + { + return -1; + } + } + + return ret; +} + +uint32_t QSPI::get_program_size() const +{ + return page_size; +} + +uint32_t QSPI::get_read_size() const +{ + return 1; +} + +uint32_t QSPI::get_erase_size() const +{ + return sector_size; +} + +uint32_t QSPI::get_flash_size() const +{ + return flash_size; +} + +#if DEVICE_QSPI_ASYNCH + +void QSPI::irq_handler_asynch(void) +{ + int event = qspi_irq_handler_asynch(&_qspi); + if (_callback && (event & QSPI_EVENT_COMPLETE)) { + _callback.call(event & QSPI_EVENT_COMPLETE); + } +} + +int QSPI::start_read(void *buffer, uint32_t addr, uint32_t size, const event_callback_t& callback, int event) +{ + _mutex->lock(); + _callback = callback; + _irq.callback(&QSPI::irq_handler_asynch); + return qspi_start_page_read(&_qspi, addr, (uint8_t *)buffer, size, _irq.entry(), event , _usage); +} + +int QSPI::start_program(const void *buffer, uint32_t addr, uint32_t size, const event_callback_t& callback, int event) +{ + _mutex->lock(); + _callback = callback; + _irq.callback(&QSPI::irq_handler_asynch); + return qspi_start_program_page(&_qspi, addr, (const uint8_t *)buffer, size, _irq.entry(), event , _usage); +} + +int QSPI::start_erase(uint32_t addr, uint32_t size, const event_callback_t& callback, int event) +{ + /* Current implementation support only erasing of one sector with address aligned to this sector. + * Erasing more sectors could be done on higher software layers using interrupts and testing + * busy bit of memory device. */ + if (size > sector_size) + { + return -1; + } + _mutex->lock(); + _callback = callback; + _irq.callback(&QSPI::irq_handler_asynch); + return qspi_start_erase_block(&_qspi, addr, _irq.entry(), event , _usage); +} + +#endif + +} +#endif diff --git a/drivers/QSPI.h b/drivers/QSPI.h new file mode 100644 index 00000000000..d02221a1647 --- /dev/null +++ b/drivers/QSPI.h @@ -0,0 +1,235 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 Nordic Semiconductor ASA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_QSPI_H +#define MBED_QSPI_H + +#ifdef DEVICE_QSPI + +#include "qspi_api.h" +#include "QSPIMemSpec.h" +#include "platform/SingletonPtr.h" +#include "platform/PlatformMutex.h" + +#if DEVICE_QSPI_ASYNCH +#include "platform/CThunk.h" +#include "hal/dma_api.h" +#include "platform/FunctionPointer.h" +#include "platform/Transaction.h" +#endif + +namespace mbed { + +/** \addtogroup drivers */ +/** @{*/ + +/** QSPI driver. It invokes flash HAL functions. + * + * Note Synchronization level: Thread safe + */ +class QSPI { +public: + /** Create a QSPI connected to specified pins and set choosen frequency. + * + * In this case QSPI will be configured in SPI mode. There will be no possibilities to init + * QSPI device and peripheral in quad mode. + * + * @param miso QSPI Master In, Slave Out pin + * @param mosi QSPI Master Out, Slave In pin + * @param sclk QSPI Clock pin + * @param ssel QSPI chip select pin + * @param hz SCLK frequency in hz + * @param spi_mode Clock polarity and phase mode (0 or 3) + */ + QSPI(PinName miso, PinName mosi, PinName sclk, PinName ssel, int hz, int spi_mode = 0); + + /** Create a QSPI connected to specified pins and set choosen frequency. + * + * In this case QSPI will be prepared to start in quad moge. There will be possibilities to init + * QSPI device and peripheral in quad mode. + * + * @param io0 QSPI IO0 pin + * @param io1 QSPI IO1 pin + * @param io2 QSPI IO2 pin + * @param io3 QSPI IO3 pin + * @param sclk QSPI Clock pin + * @param ssel QSPI chip select pin + * @param hz SCLK frequency in hz + * @param spi_mode Clock polarity and phase mode (0 or 3) + */ + QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int hz, int spi_mode = 0); + + ~QSPI(); + + /** Initialize a QSPI device + * + * Should be called once per lifetime of the object. + * @return 0 on success or a negative error code on failure + */ + int init(); + + /** Initialize a QSPI device in most suitable mode. + * + * Should be called once per lifetime of the object. + * @return 0 on success or a negative error code on failure + */ + int init(QSPIMemSpec *memspec); + + /** Deinitialize QSPI device + * + * @return 0 on success or a negative error code on failure + */ + int deinit(); + + /** Read data from a QSPI device. + * + * This method invokes transmission between mcu and qspi memory device + * + * @param buffer Buffer to write to + * @param addr Flash address to begin reading from + * @param size Size to read in bytes + * @return 0 on success, negative error code on failure + */ + int read(void *buffer, uint32_t addr, uint32_t size); + + /** Program data to pages + * + * The sectors must have been erased prior to being programmed (in most cases) + * + * @param buffer Buffer of data to be written + * @param addr Address of a page to begin writing to, must be a multiple of program and sector sizes + * @param size Size to write in bytes, must be a multiple of program and sector sizes + * @return 0 on success, negative error code on failure + */ + int program(const void *buffer, uint32_t addr, uint32_t size); + + /** Erase sectors + * + * The state of an erased sector is undefined until it has been programmed + * + * @param addr Address of a sector to begin erasing, must be a multiple of the sector size + * @param size Size to erase in bytes, must be a multiple of the sector size + * @return 0 on success, negative error code on failure + */ + int erase(uint32_t addr, uint32_t size); + + /** Check busy bit + * + * The state of an memory after program or erase command is undefined until busy bit has checked. + * + * @return 0 on free, negative error code on busy + */ + int is_memory_busy(void); + + /** Get the sector size, generic erase unit + * + * @return Size of a sector in bytes, MBED_FLASH_INVALID_SIZE if not mapped or zero if erasing is not needed to write data. + */ + uint32_t get_erase_size(void) const; + + /** Get the program unit size + * + * Minimum programmable unit is at most cases 256B, but sometimes passes other values. Addresses should be aligned to this value. + * + * @return Size of a minimum programmable unit. + */ + uint32_t get_program_size(void) const; + + /** Get the flash size + * + * @return Flash size + */ + uint32_t get_flash_size(void) const; + + /** Get the minimum read size + * + * @return Size of a minimum read unit in bytes + */ + uint32_t get_read_size(void) const; + +#if DEVICE_QSPI_ASYNCH + /** Read data from a QSPI device. + * + * This method invokes transmission between mcu and qspi memory device + * + * @param buffer Buffer to write to + * @param addr Flash address to begin reading from + * @param size Size to read in bytes + * @param event The logical OR of events to modify + * @param callback The event callback function + * @return 0 on success, -1 if peripheral is busy + */ + int start_read(void *buffer, uint32_t addr, uint32_t size, const event_callback_t& callback, int event); + + /** Program data to pages + * + * The sectors must have been erased prior to being programmed + * + * @param buffer Buffer of data to be written + * @param addr Address of a page to begin writing to, must be a multiple of program and sector sizes + * @param size Size to write in bytes, must be a multiple of program and sector sizes + * @param event The logical OR of events to modify + * @param callback The event callback function + * @return 0 on success, -1 if peripheral is busy + */ + int start_program(const void *buffer, uint32_t addr, uint32_t size, const event_callback_t& callback, int event); + + /** Erase sectors + * + * The state of an erased sector is undefined until it has been programmed + * + * @param addr Address of a sector to begin erasing, must be a multiple of the sector size + * @param size Size to erase in bytes, must be a multiple of the sector size + * @param event The logical OR of events to modify + * @param callback The event callback function + * @return 0 on success, -1 if peripheral is busy + */ + int start_erase(uint32_t addr, uint32_t size, const event_callback_t& callback, int event); +#endif + +protected: +#if DEVICE_QSPI_ASYNCH + /** QSPI IRQ handler */ + void irq_handler_asynch(void); + CThunk _irq; + event_callback_t _callback; + DMAUsage _usage; +#endif +private: + + /** Check if address and size are aligned to a sector + * + * @param addr Address of block to check for alignment + * @param size Size of block to check for alignment + * @return true if the block is sector aligned, false otherwise + */ + bool is_aligned_to_sector(uint32_t addr, uint32_t size); + + bool quad_mode_hw_support; + qspi_t _qspi; + memspec_size_t flash_size; + uint32_t page_size; + uint32_t sector_size; + + static SingletonPtr _mutex; +}; + +} /* namespace mbed */ + +#endif /* DEVICE_FLASH */ + +#endif /* MBED_QSPI_H */ + +/** @}*/ diff --git a/drivers/QSPIMemSpec.cpp b/drivers/QSPIMemSpec.cpp new file mode 100644 index 00000000000..289dd2cf801 --- /dev/null +++ b/drivers/QSPIMemSpec.cpp @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 Nordic Semiconductor ASA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "QSPIMemSpec.h" + + +#ifdef DEVICE_QSPI + +namespace mbed { + +QSPIMemSpec::QSPIMemSpec(uint8_t cmd_32bit, + memspec_size_t flash_siz, + memspec_size_t page_siz, + memspec_size_t sector_siz, + qspi_addrmode_t addr_mod, + qspi_readmode_t read_mod, + qspi_writemode_t write_mod, + MemSpec_QuadModeReq_t quad_mode, + MemSpec_32bitAddrModeReq_t enter_32bit) +{ + cmd_enter_32bit = cmd_32bit; + flash_size = flash_siz; + page_size = page_siz; + sector_size = sector_siz; + addr_mode = addr_mod; + read_mode = read_mod; + write_mode = write_mod; + quad_mode_req = quad_mode; + enter_32bit_mode_req = enter_32bit; +} + +qspi_addrmode_t QSPIMemSpec::addr_mode_get() const +{ + return addr_mode; +} + +qspi_readmode_t QSPIMemSpec::read_mode_get() const +{ + return read_mode; +} + +qspi_writemode_t QSPIMemSpec::write_mode_get() const +{ + return write_mode; +} + +memspec_size_t QSPIMemSpec::flash_size_get() const +{ + return flash_size; +} + +memspec_size_t QSPIMemSpec::page_size_get() const +{ + return page_size; +} + +memspec_size_t QSPIMemSpec::sector_size_get() const +{ + return sector_size; +} + +QSPIMemSpec::MemSpec_32bitAddrModeReq_t QSPIMemSpec::enter_32bit_mode_req_get() const +{ + return enter_32bit_mode_req; +} + +QSPIMemSpec::MemSpec_QuadModeReq_t QSPIMemSpec::quad_mode_req_get() const +{ + return quad_mode_req; +} + +} + +#endif diff --git a/drivers/QSPIMemSpec.h b/drivers/QSPIMemSpec.h new file mode 100644 index 00000000000..17f5ce3c63f --- /dev/null +++ b/drivers/QSPIMemSpec.h @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 Nordic Semiconductor ASA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef QSPIMEMSPEC_H +#define QSPIMEMSPEC_H + +#include "qspi_api.h" + + +#ifdef DEVICE_QSPI + +/** Type representing a quantity of 8-bit bytes + */ +typedef uint64_t memspec_size_t; + +namespace mbed { + +/** \addtogroup drivers */ +/** @{*/ + +/** QSPI driver helper. Storing memory config data. Could be inherit to implement for example + * filling this class with data received from SFDP function. + * + */ +class QSPIMemSpec +{ +public: + /** Options to get into quad mode + */ + typedef enum + { + MEMSPEC_QUADMODREQ_NO_REQ, + MEMSPEC_QUADMODREQ_NOT_SUPPORTED, + MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR2B, + MEMSPEC_QUADMODREQ_6BIT_1SREG, + MEMSPEC_QUADMODREQ_7BIT_2SREG_W3EH_R3FH, + MEMSPEC_QUADMODREQ_1BIT_2SREG_CLR1B, + MEMSPEC_QUADMODREQ_1BIT_2SREG_R35H_W01H_W2B, + MEMSPEC_QUADMODREQ_NOT_DEFINED, + } MemSpec_QuadModeReq_t; + + /** Options to get into 32bit addressing mode + */ + typedef enum + { + MEMSPEC_32BITMODREQ_NOT_SUPPORTED, + MEMSPEC_32BITMODREQ_INST_B7H, + MEMSPEC_32BITMODREQ_WREN_INST_B7H, + MEMSPEC_32BITMODREQ_DEDICATED, + MEMSPEC_32BITMODREQ_ALWAYS_32BIT, + MEMSPEC_32BITMODREQ_OTHER, + MEMSPEC_32BITMODREQ_NOT_DEFINED, + } MemSpec_32bitAddrModeReq_t; + + /** Create a Memory Specification object + * + * @param cmd_32bit Command used to enter to 32bit addressing mode + * @param flash_siz Flash size of the memory device + * @param page_siz Page size supported by the memory device + * @param sector_siz Erasing sector size supported by the memory device + * @param addr_mod The best addressing mode supported by the memory device + * @param read_mod The fastest read pin configuration supported by the memory device + * @param write_mod The fastest write pin configuration supported by the memory device + * @param quad_mode hint how to enter in quad mode + * @param enter_32bit hint how to enter in 32bit addressing mode + */ + QSPIMemSpec(uint8_t cmd_32bit, + memspec_size_t flash_siz, + memspec_size_t page_siz, + memspec_size_t sector_siz, + qspi_addrmode_t addr_mod, + qspi_readmode_t read_mod, + qspi_writemode_t write_mod, + MemSpec_QuadModeReq_t quad_mode, + MemSpec_32bitAddrModeReq_t enter_32bit); + + /** Flash size getter + * @return flash size + */ + memspec_size_t flash_size_get(void) const; + + /** Page size getter + * @return Page size + */ + memspec_size_t page_size_get(void) const; + + /** Erase sector size getter + * @return Erase sector size + */ + memspec_size_t sector_size_get(void) const; + + /** Address mode getter + * @return The best addressing mode + */ + qspi_addrmode_t addr_mode_get(void) const; + + /** Read mode getter + * @return The fastest pin configuration + */ + qspi_readmode_t read_mode_get(void) const; + + /** Write mode getter + * @return The fastest pin configuration + */ + qspi_writemode_t write_mode_get(void) const; + + /** 32bit addressing mode way to obtain getter + * @return 32bit addressing mode hint + */ + MemSpec_32bitAddrModeReq_t enter_32bit_mode_req_get(void) const; + + /** Quad mode way to obtain getter + * @return Quad mode hint + */ + MemSpec_QuadModeReq_t quad_mode_req_get(void) const; + +protected: + uint8_t cmd_enter_32bit; + memspec_size_t flash_size; + memspec_size_t page_size; + memspec_size_t sector_size; + qspi_addrmode_t addr_mode; + qspi_readmode_t read_mode; + qspi_writemode_t write_mode; + MemSpec_QuadModeReq_t quad_mode_req; + MemSpec_32bitAddrModeReq_t enter_32bit_mode_req; +}; + +} +#endif + +#endif // QSPIMEMSPEC_H diff --git a/hal/qspi_api.h b/hal/qspi_api.h new file mode 100644 index 00000000000..a43fc9e360d --- /dev/null +++ b/hal/qspi_api.h @@ -0,0 +1,278 @@ +/** \addtogroup hal */ +/** @{*/ + +/* mbed Microcontroller Library + * Copyright (c) 2017 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_QSPI_API_H +#define MBED_QSPI_API_H + +#include "device.h" +#include "hal/dma_api.h" +#include + +#if DEVICE_QSPI + +#define QSPI_EVENT_COMPLETE (1 << 1) + +typedef enum { + QSPI_ADDRMODE_24BIT, + QSPI_ADDRMODE_32BIT, +} qspi_addrmode_t; + +typedef enum { + QSPI_READMODE_1_1_1, + QSPI_READMODE_1_1_2, + QSPI_READMODE_1_1_4, + QSPI_READMODE_1_2_2, + QSPI_READMODE_1_4_4 +} qspi_readmode_t; + +typedef enum { + QSPI_WRITEMODE_1_1_1, + QSPI_WRITEMODE_1_1_2, + QSPI_WRITEMODE_1_1_4, + QSPI_WRITEMODE_1_4_4 +} qspi_writemode_t; + +typedef struct { + PinName sclk; + PinName ssel; + PinName io0; + PinName io1; + PinName io2; + PinName io3; +} qspi_pins_t; + +typedef struct qspi_s qspi_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup qspi_hal Flash HAL API + * @{ + */ + +/** Initialize the qspi peripheral and the qspi_t object + * + * @param[in] obj The flash object + * @param[in] hz The baud rate in Hz + * @param[in] pins The pins structure to use for configuring pins + * @param[in] spimode The SPI mode (clock polarity, phase, and shift direction) + * @return 0 for success, -1 for error + */ +int32_t qspi_init(qspi_t *obj, int hz, qspi_pins_t * pins, int spimode); + +/** Initialize the qspi peripheral and the qspi_t object + * + * @param[in] obj The flash object + * @param[in] addrmode The address mode (24 or 32 bit) + * @param[in] readmode The read lines configuration + * @param[in] writemode The write lines configuration + * @return 0 for success, -1 for error + */ +int32_t qspi_prepare(qspi_t *obj, + qspi_addrmode_t addrmode, + qspi_readmode_t readmode, + qspi_writemode_t writemode); + +/** Start the qspi peripheral and the qspi_t object + * + * @param[in] obj The flash object + * @return 0 for success, -1 for error + */ +int32_t qspi_start(qspi_t *obj); + +/** Uninitialize the qspi peripheral and the qspi_t object + * + * @param[in] obj The flash object + * @return 0 for success, -1 for error + */ +int32_t qspi_free(qspi_t *obj); + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * Finished function informs only about finish sending command sequence. + * It is important to test status register of memory device using @ref qspi_is_busy function if device + * is ready to execute next statements. + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t qspi_erase_block(qspi_t *obj, uint32_t address); + +/** Erase whole chip + * + * Finished function informs only about finish sending command sequence. + * It is important to test status register of memory device using @ref qspi_is_busy function if device + * is ready to execute next statements. + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t qspi_erase_chip(qspi_t *obj); + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * Finished function informs only about finish sending command sequence. + * It is important to test status register of memory device using @ref qspi_is_busy function if device + * is ready to execute next statements. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t qspi_program_page(qspi_t *obj, uint32_t address, const uint8_t *data, uint32_t size); + +/** Program one page starting at defined address + * + * Finished function informs also about finish operation. Data is valid in memory pointed in data pointer. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t qspi_page_read(qspi_t *obj, uint32_t address, uint8_t *data, uint32_t size); + +/** Send custom instruction + * + * Synchronous function. No callback will be execute after using this this function. + * + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t qspi_send_instruction(qspi_t *obj, + uint8_t cmd, + uint32_t tx_size, + const uint8_t *tx_data, + uint32_t rx_size, + uint8_t *rx_data); + + +int32_t qspi_is_busy(qspi_t *obj); + +#if DEVICE_QSPI_ASYNCH +/** + * \defgroup AsynchSPI Asynchronous QSPI Hardware Abstraction Layer + * @{ + */ + +/** The asynchronous IRQ handler + * + * @param[in] obj The QSPI object that holds the transfer information + * @return Event flags if a transfer termination condition was met; otherwise 0. + */ +uint32_t qspi_irq_handler_asynch(qspi_t *obj); + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param[in] obj The flash object + * @param[in] address The sector starting address + * @param[in] handler SPI interrupt handler + * @param[in] event The logical OR of events to be registered + * @param[in] hint A suggestion for how to use DMA with this transfer + * @return 0 for success, -1 for error + */ +int32_t qspi_start_erase_block(qspi_t *obj, + uint32_t address, + uint32_t handler, + uint32_t event, + DMAUsage hint); + +/** Erase whole chip + * + * Received acknowledge in interrupt routine informs only about finish sending command sequence. + * It is important to test status register of memory device using @ref qspi_is_busy function if device + * is ready to execute next statements. + * @param[in] obj The flash object + * @param[in] address The sector starting address + * @param[in] handler SPI interrupt handler + * @param[in] event The logical OR of events to be registered + * @param[in] hint A suggestion for how to use DMA with this transfer + * @return 0 for success, -1 for error + */ +int32_t qspi_start_erase_chip(qspi_t *obj, uint32_t handler, uint32_t event, DMAUsage hint); + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * Received acknowledge in interrupt routine informs only about finish sending command sequence. + * It is important to test status register of memory device using @ref qspi_is_busy function if device + * is ready to execute next statements. + * @param[in] obj The flash object + * @param[in] address The sector starting address + * @param[in] data The data buffer to be programmed + * @param[in] size The number of bytes to program + * @param[in] handler SPI interrupt handler + * @param[in] event The logical OR of events to be registered + * @param[in] hint A suggestion for how to use DMA with this transfer + * @return 0 for success, -1 for error + */ +int32_t qspi_start_program_page(qspi_t *obj, + uint32_t address, + const uint8_t *data, + uint32_t size, + uint32_t handler, + uint32_t event, + DMAUsage hint); + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * Received acknowledge in interrupt routine informs about finish sending and reading command sequence. + * It is not necessary to test status register of memory device. Memory used by QSPI device can be processed + * in interrupt routine. Data is valid. + * @param[in] obj The flash object + * @param[in] address The sector starting address + * @param[in] data The data buffer to be programmed + * @param[in] size The number of bytes to program + * @param[in] handler SPI interrupt handler + * @param[in] event The logical OR of events to be registered + * @param[in] hint A suggestion for how to use DMA with this transfer + * @return 0 for success, -1 for error + */ +int32_t qspi_start_page_read(qspi_t *obj, + uint32_t address, + uint8_t *data, + uint32_t size, + uint32_t handler, + uint32_t event, + DMAUsage hint); + +#endif + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/** @}*/ diff --git a/mbed.h b/mbed.h index 8e689aedffa..aa5aaa6b847 100644 --- a/mbed.h +++ b/mbed.h @@ -83,6 +83,7 @@ #include "drivers/PwmOut.h" #include "drivers/Serial.h" #include "drivers/SPI.h" +#include "drivers/QSPI.h" #include "drivers/SPISlave.h" #include "drivers/I2C.h" #include "drivers/I2CSlave.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h index e456c12d4c2..3e856d7c959 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h @@ -6,51 +6,51 @@ #ifdef USE_APP_CONFIG #include "app_config.h" #endif -// Application +// Application //========================================================== -// NRF_BLE_CENTRAL_LINK_COUNT - Number of central links +// NRF_BLE_CENTRAL_LINK_COUNT - Number of central links #ifndef NRF_BLE_CENTRAL_LINK_COUNT #define NRF_BLE_CENTRAL_LINK_COUNT 0 #endif -// NRF_BLE_CENTRAL_LINK_COUNT - Number of central links +// NRF_BLE_CENTRAL_LINK_COUNT - Number of central links #ifndef NRF_BLE_CENTRAL_LINK_COUNT #define NRF_BLE_CENTRAL_LINK_COUNT 0 #endif -// NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links +// NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links #ifndef NRF_BLE_PERIPHERAL_LINK_COUNT #define NRF_BLE_PERIPHERAL_LINK_COUNT 1 #endif -// NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links +// NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links #ifndef NRF_BLE_PERIPHERAL_LINK_COUNT #define NRF_BLE_PERIPHERAL_LINK_COUNT 1 #endif -// +// //========================================================== -// nRF_BLE +// nRF_BLE //========================================================== // BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module - + #ifndef BLE_ADVERTISING_ENABLED #define BLE_ADVERTISING_ENABLED 1 #endif // BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands - + #ifndef BLE_DTM_ENABLED #define BLE_DTM_ENABLED 0 #endif // BLE_RACP_ENABLED - ble_racp - Record Access Control Point library - + #ifndef BLE_RACP_ENABLED #define BLE_RACP_ENABLED 0 @@ -62,7 +62,7 @@ #define NRF_BLE_GATT_ENABLED 1 #endif #if NRF_BLE_GATT_ENABLED -// NRF_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size that is passed to the @ref sd_ble_enable function. +// NRF_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size that is passed to the @ref sd_ble_enable function. #ifndef NRF_BLE_GATT_MAX_MTU_SIZE #define NRF_BLE_GATT_MAX_MTU_SIZE 158 #endif @@ -71,23 +71,23 @@ // // NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) - + #ifndef NRF_BLE_QWR_ENABLED #define NRF_BLE_QWR_ENABLED 0 #endif // PEER_MANAGER_ENABLED - peer_manager - Peer Manager - + #ifndef PEER_MANAGER_ENABLED #define PEER_MANAGER_ENABLED 1 #endif -// +// //========================================================== -// nRF_Drivers +// nRF_Drivers //========================================================== // APP_USBD_ENABLED - app_usbd - USB Device library @@ -110,7 +110,7 @@ #define APP_USBD_PID 0x520C #endif -// APP_USBD_DEVICE_VER_MAJOR - Device version, major part <0-99> +// APP_USBD_DEVICE_VER_MAJOR - Device version, major part <0-99> // Device version, will be converted automatically to BCD notation. Use just decimal values. @@ -119,7 +119,7 @@ #define APP_USBD_DEVICE_VER_MAJOR 1 #endif -// APP_USBD_DEVICE_VER_MINOR - Device version, minor part <0-99> +// APP_USBD_DEVICE_VER_MINOR - Device version, minor part <0-99> // Device version, will be converted automatically to BCD notation. Use just decimal values. @@ -138,35 +138,35 @@ #endif #if CLOCK_ENABLED // CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency - -// <0=> Default (64 MHz) + +// <0=> Default (64 MHz) #ifndef CLOCK_CONFIG_XTAL_FREQ #define CLOCK_CONFIG_XTAL_FREQ 0 #endif // CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth + +// <0=> RC +// <1=> XTAL +// <2=> Synth #ifndef CLOCK_CONFIG_LF_SRC #define CLOCK_CONFIG_LF_SRC 1 #endif // CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef CLOCK_CONFIG_IRQ_PRIORITY #define CLOCK_CONFIG_IRQ_PRIORITY 7 @@ -179,44 +179,44 @@ #endif #if CLOCK_CONFIG_LOG_ENABLED // CLOCK_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef CLOCK_CONFIG_LOG_LEVEL #define CLOCK_CONFIG_LOG_LEVEL 3 #endif // CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef CLOCK_CONFIG_INFO_COLOR #define CLOCK_CONFIG_INFO_COLOR 0 #endif // CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef CLOCK_CONFIG_DEBUG_COLOR #define CLOCK_CONFIG_DEBUG_COLOR 0 @@ -235,83 +235,83 @@ #endif #if COMP_ENABLED // COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef #ifndef COMP_CONFIG_REF #define COMP_CONFIG_REF 1 #endif // COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential + +// <0=> Single ended +// <1=> Differential #ifndef COMP_CONFIG_MAIN_MODE #define COMP_CONFIG_MAIN_MODE 0 #endif // COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed + +// <0=> Low power +// <1=> Normal +// <2=> High speed #ifndef COMP_CONFIG_SPEED_MODE #define COMP_CONFIG_SPEED_MODE 2 #endif // COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV + +// <0=> No +// <1=> 50mV #ifndef COMP_CONFIG_HYST #define COMP_CONFIG_HYST 0 #endif // COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA #ifndef COMP_CONFIG_ISOURCE #define COMP_CONFIG_ISOURCE 0 #endif // COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef COMP_CONFIG_INPUT #define COMP_CONFIG_INPUT 0 #endif // COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef COMP_CONFIG_IRQ_PRIORITY #define COMP_CONFIG_IRQ_PRIORITY 7 @@ -324,44 +324,44 @@ #endif #if COMP_CONFIG_LOG_ENABLED // COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef COMP_CONFIG_LOG_LEVEL #define COMP_CONFIG_LOG_LEVEL 3 #endif // COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef COMP_CONFIG_INFO_COLOR #define COMP_CONFIG_INFO_COLOR 0 #endif // COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef COMP_CONFIG_DEBUG_COLOR #define COMP_CONFIG_DEBUG_COLOR 0 @@ -386,44 +386,44 @@ #endif #if SWI_CONFIG_LOG_ENABLED // SWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef SWI_CONFIG_LOG_LEVEL #define SWI_CONFIG_LOG_LEVEL 3 #endif // SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SWI_CONFIG_INFO_COLOR #define SWI_CONFIG_INFO_COLOR 0 #endif // SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SWI_CONFIG_DEBUG_COLOR #define SWI_CONFIG_DEBUG_COLOR 0 @@ -441,23 +441,23 @@ #define GPIOTE_ENABLED 1 #endif #if GPIOTE_ENABLED -// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins #ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 #endif // GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef GPIOTE_CONFIG_IRQ_PRIORITY #define GPIOTE_CONFIG_IRQ_PRIORITY 7 @@ -470,44 +470,44 @@ #endif #if GPIOTE_CONFIG_LOG_ENABLED // GPIOTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef GPIOTE_CONFIG_LOG_LEVEL #define GPIOTE_CONFIG_LOG_LEVEL 3 #endif // GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef GPIOTE_CONFIG_INFO_COLOR #define GPIOTE_CONFIG_INFO_COLOR 0 #endif // GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef GPIOTE_CONFIG_DEBUG_COLOR #define GPIOTE_CONFIG_DEBUG_COLOR 0 @@ -525,33 +525,33 @@ #define I2S_ENABLED 0 #endif #if I2S_ENABLED -// I2S_CONFIG_SCK_PIN - SCK pin <0-31> +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> #ifndef I2S_CONFIG_SCK_PIN #define I2S_CONFIG_SCK_PIN 31 #endif -// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> #ifndef I2S_CONFIG_LRCK_PIN #define I2S_CONFIG_LRCK_PIN 30 #endif -// I2S_CONFIG_MCK_PIN - MCK pin +// I2S_CONFIG_MCK_PIN - MCK pin #ifndef I2S_CONFIG_MCK_PIN #define I2S_CONFIG_MCK_PIN 255 #endif -// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> #ifndef I2S_CONFIG_SDOUT_PIN #define I2S_CONFIG_SDOUT_PIN 29 #endif -// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> #ifndef I2S_CONFIG_SDIN_PIN @@ -559,106 +559,106 @@ #endif // I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave + +// <0=> Master +// <1=> Slave #ifndef I2S_CONFIG_MASTER #define I2S_CONFIG_MASTER 0 #endif // I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned + +// <0=> I2S +// <1=> Aligned #ifndef I2S_CONFIG_FORMAT #define I2S_CONFIG_FORMAT 0 #endif // I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right + +// <0=> Left +// <1=> Right #ifndef I2S_CONFIG_ALIGN #define I2S_CONFIG_ALIGN 0 #endif // I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 + +// <0=> 8 +// <1=> 16 +// <2=> 24 #ifndef I2S_CONFIG_SWIDTH #define I2S_CONFIG_SWIDTH 1 #endif // I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right + +// <0=> Stereo +// <1=> Left +// <2=> Right #ifndef I2S_CONFIG_CHANNELS #define I2S_CONFIG_CHANNELS 1 #endif // I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 #ifndef I2S_CONFIG_MCK_SETUP #define I2S_CONFIG_MCK_SETUP 536870912 #endif // I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x #ifndef I2S_CONFIG_RATIO #define I2S_CONFIG_RATIO 2000 #endif // I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef I2S_CONFIG_IRQ_PRIORITY #define I2S_CONFIG_IRQ_PRIORITY 7 @@ -671,44 +671,44 @@ #endif #if I2S_CONFIG_LOG_ENABLED // I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef I2S_CONFIG_LOG_LEVEL #define I2S_CONFIG_LOG_LEVEL 3 #endif // I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef I2S_CONFIG_INFO_COLOR #define I2S_CONFIG_INFO_COLOR 0 #endif // I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef I2S_CONFIG_DEBUG_COLOR #define I2S_CONFIG_DEBUG_COLOR 0 @@ -727,73 +727,73 @@ #endif #if LPCOMP_ENABLED // LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 #ifndef LPCOMP_CONFIG_REFERENCE #define LPCOMP_CONFIG_REFERENCE 3 #endif // LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down + +// <0=> Crossing +// <1=> Up +// <2=> Down #ifndef LPCOMP_CONFIG_DETECTION #define LPCOMP_CONFIG_DETECTION 2 #endif // LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef LPCOMP_CONFIG_INPUT #define LPCOMP_CONFIG_INPUT 0 #endif // LPCOMP_CONFIG_HYST - Hysteresis - + #ifndef LPCOMP_CONFIG_HYST #define LPCOMP_CONFIG_HYST 0 #endif // LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef LPCOMP_CONFIG_IRQ_PRIORITY #define LPCOMP_CONFIG_IRQ_PRIORITY 7 @@ -806,44 +806,44 @@ #endif #if LPCOMP_CONFIG_LOG_ENABLED // LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef LPCOMP_CONFIG_LOG_LEVEL #define LPCOMP_CONFIG_LOG_LEVEL 3 #endif // LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef LPCOMP_CONFIG_INFO_COLOR #define LPCOMP_CONFIG_INFO_COLOR 0 #endif // LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef LPCOMP_CONFIG_DEBUG_COLOR #define LPCOMP_CONFIG_DEBUG_COLOR 0 @@ -862,45 +862,45 @@ #endif #if PDM_ENABLED // PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono + +// <0=> Stereo +// <1=> Mono #ifndef PDM_CONFIG_MODE #define PDM_CONFIG_MODE 1 #endif // PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising + +// <0=> Left falling +// <1=> Left rising #ifndef PDM_CONFIG_EDGE #define PDM_CONFIG_EDGE 0 #endif // PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k #ifndef PDM_CONFIG_CLOCK_FREQ #define PDM_CONFIG_CLOCK_FREQ 138412032 #endif // PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef PDM_CONFIG_IRQ_PRIORITY #define PDM_CONFIG_IRQ_PRIORITY 7 @@ -913,44 +913,44 @@ #endif #if PDM_CONFIG_LOG_ENABLED // PDM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef PDM_CONFIG_LOG_LEVEL #define PDM_CONFIG_LOG_LEVEL 3 #endif // PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PDM_CONFIG_INFO_COLOR #define PDM_CONFIG_INFO_COLOR 0 #endif // PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PDM_CONFIG_DEBUG_COLOR #define PDM_CONFIG_DEBUG_COLOR 0 @@ -975,44 +975,44 @@ #endif #if COMMON_CONFIG_LOG_ENABLED // COMMON_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef COMMON_CONFIG_LOG_LEVEL #define COMMON_CONFIG_LOG_LEVEL 3 #endif // COMMON_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef COMMON_CONFIG_INFO_COLOR #define COMMON_CONFIG_INFO_COLOR 0 #endif // COMMON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef COMMON_CONFIG_DEBUG_COLOR #define COMMON_CONFIG_DEBUG_COLOR 0 @@ -1031,24 +1031,24 @@ #endif #if POWER_ENABLED // POWER_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef POWER_CONFIG_IRQ_PRIORITY #define POWER_CONFIG_IRQ_PRIORITY 7 #endif // POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - + // This settings means only that components for DCDC regulator are installed and it can be enabled. @@ -1057,7 +1057,7 @@ #endif // POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - + // This settings means only that components for DCDC regulator are installed and it can be enabled. @@ -1081,44 +1081,44 @@ #endif #if PPI_CONFIG_LOG_ENABLED // PPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef PPI_CONFIG_LOG_LEVEL #define PPI_CONFIG_LOG_LEVEL 3 #endif // PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PPI_CONFIG_INFO_COLOR #define PPI_CONFIG_INFO_COLOR 0 #endif // PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PPI_CONFIG_DEBUG_COLOR #define PPI_CONFIG_DEBUG_COLOR 0 @@ -1136,28 +1136,28 @@ #define PWM_ENABLED 1 #endif #if PWM_ENABLED -// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> #ifndef PWM_DEFAULT_CONFIG_OUT0_PIN #define PWM_DEFAULT_CONFIG_OUT0_PIN 31 #endif -// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> #ifndef PWM_DEFAULT_CONFIG_OUT1_PIN #define PWM_DEFAULT_CONFIG_OUT1_PIN 31 #endif -// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> #ifndef PWM_DEFAULT_CONFIG_OUT2_PIN #define PWM_DEFAULT_CONFIG_OUT2_PIN 31 #endif -// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> #ifndef PWM_DEFAULT_CONFIG_OUT3_PIN @@ -1165,94 +1165,94 @@ #endif // PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 MHz + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 MHz #ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK #define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 #endif // PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down + +// <0=> Up +// <1=> Up and Down #ifndef PWM_DEFAULT_CONFIG_COUNT_MODE #define PWM_DEFAULT_CONFIG_COUNT_MODE 0 #endif -// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value #ifndef PWM_DEFAULT_CONFIG_TOP_VALUE #define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 #endif // PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform #ifndef PWM_DEFAULT_CONFIG_LOAD_MODE #define PWM_DEFAULT_CONFIG_LOAD_MODE 0 #endif // PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered + +// <0=> Auto +// <1=> Triggered #ifndef PWM_DEFAULT_CONFIG_STEP_MODE #define PWM_DEFAULT_CONFIG_STEP_MODE 0 #endif // PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY #define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // PWM0_ENABLED - Enable PWM0 instance - + #ifndef PWM0_ENABLED #define PWM0_ENABLED 1 #endif // PWM1_ENABLED - Enable PWM1 instance - + #ifndef PWM1_ENABLED #define PWM1_ENABLED 1 #endif // PWM2_ENABLED - Enable PWM2 instance - + #ifndef PWM2_ENABLED #define PWM2_ENABLED 1 #endif // PWM3_ENABLED - Enable PWM3 instance - + #ifndef PWM3_ENABLED #define PWM3_ENABLED 1 @@ -1265,44 +1265,44 @@ #endif #if PWM_CONFIG_LOG_ENABLED // PWM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef PWM_CONFIG_LOG_LEVEL #define PWM_CONFIG_LOG_LEVEL 3 #endif // PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PWM_CONFIG_INFO_COLOR #define PWM_CONFIG_INFO_COLOR 0 #endif // PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef PWM_CONFIG_DEBUG_COLOR #define PWM_CONFIG_DEBUG_COLOR 0 @@ -1321,96 +1321,96 @@ #endif #if QDEC_ENABLED // QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples #ifndef QDEC_CONFIG_REPORTPER #define QDEC_CONFIG_REPORTPER 0 #endif // QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us #ifndef QDEC_CONFIG_SAMPLEPER #define QDEC_CONFIG_SAMPLEPER 7 #endif -// QDEC_CONFIG_PIO_A - A pin <0-31> +// QDEC_CONFIG_PIO_A - A pin <0-31> #ifndef QDEC_CONFIG_PIO_A #define QDEC_CONFIG_PIO_A 31 #endif -// QDEC_CONFIG_PIO_B - B pin <0-31> +// QDEC_CONFIG_PIO_B - B pin <0-31> #ifndef QDEC_CONFIG_PIO_B #define QDEC_CONFIG_PIO_B 31 #endif -// QDEC_CONFIG_PIO_LED - LED pin <0-31> +// QDEC_CONFIG_PIO_LED - LED pin <0-31> #ifndef QDEC_CONFIG_PIO_LED #define QDEC_CONFIG_PIO_LED 31 #endif -// QDEC_CONFIG_LEDPRE - LED pre +// QDEC_CONFIG_LEDPRE - LED pre #ifndef QDEC_CONFIG_LEDPRE #define QDEC_CONFIG_LEDPRE 511 #endif // QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high + +// <0=> Active low +// <1=> Active high #ifndef QDEC_CONFIG_LEDPOL #define QDEC_CONFIG_LEDPOL 1 #endif // QDEC_CONFIG_DBFEN - Debouncing enable - + #ifndef QDEC_CONFIG_DBFEN #define QDEC_CONFIG_DBFEN 0 #endif // QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - + #ifndef QDEC_CONFIG_SAMPLE_INTEN #define QDEC_CONFIG_SAMPLE_INTEN 0 #endif // QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef QDEC_CONFIG_IRQ_PRIORITY #define QDEC_CONFIG_IRQ_PRIORITY 7 @@ -1423,44 +1423,44 @@ #endif #if QDEC_CONFIG_LOG_ENABLED // QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef QDEC_CONFIG_LOG_LEVEL #define QDEC_CONFIG_LOG_LEVEL 3 #endif // QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef QDEC_CONFIG_INFO_COLOR #define QDEC_CONFIG_INFO_COLOR 0 #endif // QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef QDEC_CONFIG_DEBUG_COLOR #define QDEC_CONFIG_DEBUG_COLOR 0 @@ -1479,29 +1479,29 @@ #endif #if RNG_ENABLED // RNG_CONFIG_ERROR_CORRECTION - Error correction - + #ifndef RNG_CONFIG_ERROR_CORRECTION #define RNG_CONFIG_ERROR_CORRECTION 0 #endif -// RNG_CONFIG_POOL_SIZE - Pool size +// RNG_CONFIG_POOL_SIZE - Pool size #ifndef RNG_CONFIG_POOL_SIZE #define RNG_CONFIG_POOL_SIZE 32 #endif // RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef RNG_CONFIG_IRQ_PRIORITY #define RNG_CONFIG_IRQ_PRIORITY 7 @@ -1514,44 +1514,44 @@ #endif #if RNG_CONFIG_LOG_ENABLED // RNG_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef RNG_CONFIG_LOG_LEVEL #define RNG_CONFIG_LOG_LEVEL 3 #endif // RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef RNG_CONFIG_INFO_COLOR #define RNG_CONFIG_INFO_COLOR 0 #endif // RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef RNG_CONFIG_DEBUG_COLOR #define RNG_CONFIG_DEBUG_COLOR 0 @@ -1569,7 +1569,7 @@ #define RTC_ENABLED 1 #endif #if RTC_ENABLED -// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> #ifndef RTC_DEFAULT_CONFIG_FREQUENCY @@ -1577,51 +1577,51 @@ #endif // RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - + #ifndef RTC_DEFAULT_CONFIG_RELIABLE #define RTC_DEFAULT_CONFIG_RELIABLE 0 #endif // RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY #define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // RTC0_ENABLED - Enable RTC0 instance - + #ifndef RTC0_ENABLED #define RTC0_ENABLED 1 #endif // RTC1_ENABLED - Enable RTC1 instance - + #ifndef RTC1_ENABLED #define RTC1_ENABLED 0 #endif // RTC2_ENABLED - Enable RTC2 instance - + #ifndef RTC2_ENABLED #define RTC2_ENABLED 1 #endif -// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt #ifndef NRF_MAXIMUM_LATENCY_US #define NRF_MAXIMUM_LATENCY_US 2000 #endif @@ -1633,44 +1633,44 @@ #endif #if RTC_CONFIG_LOG_ENABLED // RTC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef RTC_CONFIG_LOG_LEVEL #define RTC_CONFIG_LOG_LEVEL 3 #endif // RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef RTC_CONFIG_INFO_COLOR #define RTC_CONFIG_INFO_COLOR 0 #endif // RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef RTC_CONFIG_DEBUG_COLOR #define RTC_CONFIG_DEBUG_COLOR 0 @@ -1689,51 +1689,51 @@ #endif #if SAADC_ENABLED // SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit #ifndef SAADC_CONFIG_RESOLUTION #define SAADC_CONFIG_RESOLUTION 1 #endif // SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x #ifndef SAADC_CONFIG_OVERSAMPLE #define SAADC_CONFIG_OVERSAMPLE 0 #endif // SAADC_CONFIG_LP_MODE - Enabling low power mode - + #ifndef SAADC_CONFIG_LP_MODE #define SAADC_CONFIG_LP_MODE 0 #endif // SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef SAADC_CONFIG_IRQ_PRIORITY #define SAADC_CONFIG_IRQ_PRIORITY 7 @@ -1746,44 +1746,44 @@ #endif #if SAADC_CONFIG_LOG_ENABLED // SAADC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef SAADC_CONFIG_LOG_LEVEL #define SAADC_CONFIG_LOG_LEVEL 3 #endif // SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SAADC_CONFIG_INFO_COLOR #define SAADC_CONFIG_INFO_COLOR 0 #endif // SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SAADC_CONFIG_DEBUG_COLOR #define SAADC_CONFIG_DEBUG_COLOR 0 @@ -1802,50 +1802,50 @@ #endif #if SPIS_ENABLED // SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY #define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 #ifndef SPIS_DEFAULT_MODE #define SPIS_DEFAULT_MODE 0 #endif // SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first + +// <0=> MSB first +// <1=> LSB first #ifndef SPIS_DEFAULT_BIT_ORDER #define SPIS_DEFAULT_BIT_ORDER 0 #endif -// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> #ifndef SPIS_DEFAULT_DEF #define SPIS_DEFAULT_DEF 255 #endif -// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> #ifndef SPIS_DEFAULT_ORC @@ -1853,21 +1853,21 @@ #endif // SPIS0_ENABLED - Enable SPIS0 instance - + #ifndef SPIS0_ENABLED #define SPIS0_ENABLED 1 #endif // SPIS1_ENABLED - Enable SPIS1 instance - + #ifndef SPIS1_ENABLED #define SPIS1_ENABLED 1 #endif // SPIS2_ENABLED - Enable SPIS2 instance - + #ifndef SPIS2_ENABLED #define SPIS2_ENABLED 1 @@ -1880,44 +1880,44 @@ #endif #if SPIS_CONFIG_LOG_ENABLED // SPIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef SPIS_CONFIG_LOG_LEVEL #define SPIS_CONFIG_LOG_LEVEL 3 #endif // SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SPIS_CONFIG_INFO_COLOR #define SPIS_CONFIG_INFO_COLOR 0 #endif // SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SPIS_CONFIG_DEBUG_COLOR #define SPIS_CONFIG_DEBUG_COLOR 0 @@ -1936,17 +1936,17 @@ #endif #if SPI_ENABLED // SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY #define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 @@ -1959,21 +1959,21 @@ #endif #if SPI0_ENABLED // SPI0_USE_EASY_DMA - Use EasyDMA - + #ifndef SPI0_USE_EASY_DMA -#define SPI0_USE_EASY_DMA 1 +#define SPI0_USE_EASY_DMA 0 #endif // SPI0_DEFAULT_FREQUENCY - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz #ifndef SPI0_DEFAULT_FREQUENCY #define SPI0_DEFAULT_FREQUENCY 1073741824 @@ -1989,21 +1989,21 @@ #endif #if SPI1_ENABLED // SPI1_USE_EASY_DMA - Use EasyDMA - + #ifndef SPI1_USE_EASY_DMA -#define SPI1_USE_EASY_DMA 1 +#define SPI1_USE_EASY_DMA 0 #endif // SPI1_DEFAULT_FREQUENCY - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz #ifndef SPI1_DEFAULT_FREQUENCY #define SPI1_DEFAULT_FREQUENCY 1073741824 @@ -2019,14 +2019,14 @@ #endif #if SPI2_ENABLED // SPI2_USE_EASY_DMA - Use EasyDMA - + #ifndef SPI2_USE_EASY_DMA -#define SPI2_USE_EASY_DMA 1 +#define SPI2_USE_EASY_DMA 0 #endif // SPI2_DEFAULT_FREQUENCY - Use EasyDMA - + #ifndef SPI2_DEFAULT_FREQUENCY #define SPI2_DEFAULT_FREQUENCY 1 @@ -2042,44 +2042,44 @@ #endif #if SPI_CONFIG_LOG_ENABLED // SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef SPI_CONFIG_LOG_LEVEL #define SPI_CONFIG_LOG_LEVEL 3 #endif // SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SPI_CONFIG_INFO_COLOR #define SPI_CONFIG_INFO_COLOR 0 #endif // SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef SPI_CONFIG_DEBUG_COLOR #define SPI_CONFIG_DEBUG_COLOR 0 @@ -2091,8 +2091,135 @@ #endif //SPI_ENABLED // +// QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver. +//========================================================== +#ifndef QSPI_ENABLED +#define QSPI_ENABLED 1 +#endif +#if QSPI_ENABLED +// QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef QSPI_CONFIG_SCK_DELAY +#define QSPI_CONFIG_SCK_DELAY 1 +#endif + +// QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef QSPI_CONFIG_READOC +#define QSPI_CONFIG_READOC 4 +#endif + +// QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef QSPI_CONFIG_WRITEOC +#define QSPI_CONFIG_WRITEOC 3 +#endif + +// QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef QSPI_CONFIG_ADDRMODE +#define QSPI_CONFIG_ADDRMODE 0 +#endif + +// QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef QSPI_CONFIG_MODE +#define QSPI_CONFIG_MODE 0 +#endif + +// QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef QSPI_CONFIG_FREQUENCY +#define QSPI_CONFIG_FREQUENCY 1 +#endif + +// QSPI_PIN_SCK - SCK pin value. +#ifndef QSPI_PIN_SCK +#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_CSN - CSN pin value. +#ifndef QSPI_PIN_CSN +#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO0 - IO0 pin value. +#ifndef QSPI_PIN_IO0 +#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO1 - IO1 pin value. +#ifndef QSPI_PIN_IO1 +#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO2 - IO2 pin value. +#ifndef QSPI_PIN_IO2 +#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO3 - IO3 pin value. +#ifndef QSPI_PIN_IO3 +#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QSPI_CONFIG_IRQ_PRIORITY +#define QSPI_CONFIG_IRQ_PRIORITY 7 +#endif + +#endif //QSPI_ENABLED +// + // SYSTICK_ENABLED - nrf_drv_systick - SysTick driver - + #ifndef SYSTICK_ENABLED #define SYSTICK_ENABLED 1 @@ -2105,89 +2232,89 @@ #endif #if TIMER_ENABLED // TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz #ifndef TIMER_DEFAULT_CONFIG_FREQUENCY #define TIMER_DEFAULT_CONFIG_FREQUENCY 0 #endif // TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter + +// <0=> Timer +// <1=> Counter #ifndef TIMER_DEFAULT_CONFIG_MODE #define TIMER_DEFAULT_CONFIG_MODE 0 #endif // TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit #ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH #define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 #endif // TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY #define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // TIMER0_ENABLED - Enable TIMER0 instance - + #ifndef TIMER0_ENABLED #define TIMER0_ENABLED 1 #endif // TIMER1_ENABLED - Enable TIMER1 instance - + #ifndef TIMER1_ENABLED #define TIMER1_ENABLED 1 #endif // TIMER2_ENABLED - Enable TIMER2 instance - + #ifndef TIMER2_ENABLED #define TIMER2_ENABLED 1 #endif // TIMER3_ENABLED - Enable TIMER3 instance - + #ifndef TIMER3_ENABLED #define TIMER3_ENABLED 1 #endif // TIMER4_ENABLED - Enable TIMER4 instance - + #ifndef TIMER4_ENABLED #define TIMER4_ENABLED 1 @@ -2200,44 +2327,44 @@ #endif #if TIMER_CONFIG_LOG_ENABLED // TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef TIMER_CONFIG_LOG_LEVEL #define TIMER_CONFIG_LOG_LEVEL 3 #endif // TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TIMER_CONFIG_INFO_COLOR #define TIMER_CONFIG_INFO_COLOR 0 #endif // TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TIMER_CONFIG_DEBUG_COLOR #define TIMER_CONFIG_DEBUG_COLOR 0 @@ -2255,69 +2382,69 @@ #define TWIS_ENABLED 1 #endif #if TWIS_ENABLED -// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 #ifndef TWIS_DEFAULT_CONFIG_ADDR0 #define TWIS_DEFAULT_CONFIG_ADDR0 0 #endif -// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 #ifndef TWIS_DEFAULT_CONFIG_ADDR1 #define TWIS_DEFAULT_CONFIG_ADDR1 0 #endif // TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up #ifndef TWIS_DEFAULT_CONFIG_SCL_PULL #define TWIS_DEFAULT_CONFIG_SCL_PULL 0 #endif // TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up #ifndef TWIS_DEFAULT_CONFIG_SDA_PULL #define TWIS_DEFAULT_CONFIG_SDA_PULL 0 #endif // TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY #define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // TWIS0_ENABLED - Enable TWIS0 instance - + #ifndef TWIS0_ENABLED #define TWIS0_ENABLED 1 #endif // TWIS1_ENABLED - Enable TWIS1 instance - + #ifndef TWIS1_ENABLED #define TWIS1_ENABLED 1 #endif // TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - + // Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. @@ -2326,7 +2453,7 @@ #endif // TWIS_NO_SYNC_MODE - Remove support for synchronous mode - + // Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. @@ -2341,44 +2468,44 @@ #endif #if TWIS_CONFIG_LOG_ENABLED // TWIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef TWIS_CONFIG_LOG_LEVEL #define TWIS_CONFIG_LOG_LEVEL 3 #endif // TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TWIS_CONFIG_INFO_COLOR #define TWIS_CONFIG_INFO_COLOR 0 #endif // TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TWIS_CONFIG_DEBUG_COLOR #define TWIS_CONFIG_DEBUG_COLOR 0 @@ -2397,41 +2524,41 @@ #endif #if TWI_ENABLED // TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k #ifndef TWI_DEFAULT_CONFIG_FREQUENCY #define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 #endif // TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init - + #ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT #define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 #endif // TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - + #ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT #define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 #endif // TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY #define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 @@ -2444,7 +2571,7 @@ #endif #if TWI0_ENABLED // TWI0_USE_EASY_DMA - Use EasyDMA (if present) - + #ifndef TWI0_USE_EASY_DMA #define TWI0_USE_EASY_DMA 0 @@ -2460,7 +2587,7 @@ #endif #if TWI1_ENABLED // TWI1_USE_EASY_DMA - Use EasyDMA (if present) - + #ifndef TWI1_USE_EASY_DMA #define TWI1_USE_EASY_DMA 0 @@ -2476,44 +2603,44 @@ #endif #if TWI_CONFIG_LOG_ENABLED // TWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef TWI_CONFIG_LOG_LEVEL #define TWI_CONFIG_LOG_LEVEL 3 #endif // TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TWI_CONFIG_INFO_COLOR #define TWI_CONFIG_INFO_COLOR 0 #endif // TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef TWI_CONFIG_DEBUG_COLOR #define TWI_CONFIG_DEBUG_COLOR 0 @@ -2532,72 +2659,72 @@ #endif #if UART_ENABLED // UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled + +// <0=> Disabled +// <1=> Enabled #ifndef UART_DEFAULT_CONFIG_HWFC #define UART_DEFAULT_CONFIG_HWFC 1 #endif // UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included + +// <0=> Excluded +// <14=> Included #ifndef UART_DEFAULT_CONFIG_PARITY #define UART_DEFAULT_CONFIG_PARITY 0 #endif // UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud #ifndef UART_DEFAULT_CONFIG_BAUDRATE #define UART_DEFAULT_CONFIG_BAUDRATE 2576384 #endif // UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY #define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA - + #ifndef UART_EASY_DMA_SUPPORT #define UART_EASY_DMA_SUPPORT 1 #endif // UART_LEGACY_SUPPORT - Driver supporting Legacy mode - + #ifndef UART_LEGACY_SUPPORT #define UART_LEGACY_SUPPORT 1 @@ -2610,7 +2737,7 @@ #endif #if UART0_ENABLED // UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA - + #ifndef UART0_CONFIG_USE_EASY_DMA #define UART0_CONFIG_USE_EASY_DMA 1 @@ -2626,7 +2753,7 @@ #endif #if UART1_ENABLED // UART1_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA - + #ifndef UART1_CONFIG_USE_EASY_DMA #define UART1_CONFIG_USE_EASY_DMA 1 @@ -2642,44 +2769,44 @@ #endif #if UART_CONFIG_LOG_ENABLED // UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef UART_CONFIG_LOG_LEVEL #define UART_CONFIG_LOG_LEVEL 3 #endif // UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef UART_CONFIG_INFO_COLOR #define UART_CONFIG_INFO_COLOR 0 #endif // UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef UART_CONFIG_DEBUG_COLOR #define UART_CONFIG_DEBUG_COLOR 0 @@ -2698,33 +2825,33 @@ #endif #if USBD_ENABLED // USBD_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef USBD_CONFIG_IRQ_PRIORITY #define USBD_CONFIG_IRQ_PRIORITY 7 #endif // NRF_DRV_USBD_DMASCHEDULER_MODE - USBD SMA scheduler working scheme - -// <0=> Prioritized access -// <1=> Round Robin + +// <0=> Prioritized access +// <1=> Round Robin #ifndef NRF_DRV_USBD_DMASCHEDULER_MODE #define NRF_DRV_USBD_DMASCHEDULER_MODE 0 #endif // NRF_USBD_DRV_LOG_ENABLED - Enable logging. - + #ifndef NRF_USBD_DRV_LOG_ENABLED #define NRF_USBD_DRV_LOG_ENABLED 0 @@ -2740,17 +2867,17 @@ #endif #if WDT_ENABLED // WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT #ifndef WDT_CONFIG_BEHAVIOUR #define WDT_CONFIG_BEHAVIOUR 1 #endif -// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> #ifndef WDT_CONFIG_RELOAD_VALUE @@ -2758,17 +2885,17 @@ #endif // WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - + // Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 #ifndef WDT_CONFIG_IRQ_PRIORITY #define WDT_CONFIG_IRQ_PRIORITY 7 @@ -2781,44 +2908,44 @@ #endif #if WDT_CONFIG_LOG_ENABLED // WDT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef WDT_CONFIG_LOG_LEVEL #define WDT_CONFIG_LOG_LEVEL 3 #endif // WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef WDT_CONFIG_INFO_COLOR #define WDT_CONFIG_INFO_COLOR 0 #endif // WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef WDT_CONFIG_DEBUG_COLOR #define WDT_CONFIG_DEBUG_COLOR 0 @@ -2830,28 +2957,28 @@ #endif //WDT_ENABLED // -// +// //========================================================== -// nRF_Libraries +// nRF_Libraries //========================================================== // APP_FIFO_ENABLED - app_fifo - Software FIFO implementation - + #ifndef APP_FIFO_ENABLED #define APP_FIFO_ENABLED 0 #endif // APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher - + #ifndef APP_GPIOTE_ENABLED #define APP_GPIOTE_ENABLED 0 #endif // APP_PWM_ENABLED - app_pwm - PWM functionality - + #ifndef APP_PWM_ENABLED #define APP_PWM_ENABLED 0 @@ -2864,14 +2991,14 @@ #endif #if APP_SCHEDULER_ENABLED // APP_SCHEDULER_WITH_PAUSE - Enabling pause feature - + #ifndef APP_SCHEDULER_WITH_PAUSE #define APP_SCHEDULER_WITH_PAUSE 0 #endif // APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling - + #ifndef APP_SCHEDULER_WITH_PROFILER #define APP_SCHEDULER_WITH_PROFILER 0 @@ -2887,14 +3014,14 @@ #endif #if APP_TIMER_ENABLED // APP_TIMER_WITH_PROFILER - Enable app_timer profiling - + #ifndef APP_TIMER_WITH_PROFILER #define APP_TIMER_WITH_PROFILER 0 #endif // APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on - + // If option is enabled RTC is kept running even if there is no active timers. // This option can be used when app_timer is used for timestamping. @@ -2907,7 +3034,7 @@ // // APP_TWI_ENABLED - app_twi - TWI transaction manager - + #ifndef APP_TWI_ENABLED #define APP_TWI_ENABLED 0 @@ -2920,8 +3047,8 @@ #endif #if APP_UART_ENABLED // APP_UART_DRIVER_INSTANCE - UART instance used - -// <0=> 0 + +// <0=> 0 #ifndef APP_UART_DRIVER_INSTANCE #define APP_UART_DRIVER_INSTANCE 0 @@ -2931,56 +3058,56 @@ // // APP_USBD_CLASS_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class - + #ifndef APP_USBD_CLASS_AUDIO_ENABLED #define APP_USBD_CLASS_AUDIO_ENABLED 0 #endif // APP_USBD_CLASS_HID_ENABLED - app_usbd_hid - USB HID class - + #ifndef APP_USBD_CLASS_HID_ENABLED #define APP_USBD_CLASS_HID_ENABLED 1 #endif // APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic - + #ifndef APP_USBD_HID_GENERIC_ENABLED #define APP_USBD_HID_GENERIC_ENABLED 1 #endif // APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard - + #ifndef APP_USBD_HID_KBD_ENABLED #define APP_USBD_HID_KBD_ENABLED 0 #endif // APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse - + #ifndef APP_USBD_HID_MOUSE_ENABLED #define APP_USBD_HID_MOUSE_ENABLED 1 #endif // BUTTON_ENABLED - app_button - buttons handling module - + #ifndef BUTTON_ENABLED #define BUTTON_ENABLED 0 #endif // CRC16_ENABLED - crc16 - CRC16 calculation routines - + #ifndef CRC16_ENABLED #define CRC16_ENABLED 1 #endif // CRC32_ENABLED - crc32 - CRC32 calculation routines - + #ifndef CRC32_ENABLED #define CRC32_ENABLED 1 @@ -2992,22 +3119,22 @@ #define FDS_ENABLED 1 #endif #if FDS_ENABLED -// FDS_OP_QUEUE_SIZE - Size of the internal queue. +// FDS_OP_QUEUE_SIZE - Size of the internal queue. #ifndef FDS_OP_QUEUE_SIZE #define FDS_OP_QUEUE_SIZE 4 #endif -// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. +// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. #ifndef FDS_CHUNK_QUEUE_SIZE #define FDS_CHUNK_QUEUE_SIZE 8 #endif -// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. #ifndef FDS_MAX_USERS #define FDS_MAX_USERS 8 #endif -// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. // One of the virtual pages is reserved by the system for garbage collection. // Therefore, the minimum is two virtual pages: one page to store data and // one page to be used by the system for garbage collection. The total amount @@ -3019,12 +3146,12 @@ #endif // FDS_VIRTUAL_PAGE_SIZE - The size of a virtual page of flash memory, expressed in number of 4-byte words. - + // By default, a virtual page is the same size as a physical page. // The size of a virtual page must be a multiple of the size of a physical page. -// <1024=> 1024 -// <2048=> 2048 +// <1024=> 1024 +// <2048=> 2048 #ifndef FDS_VIRTUAL_PAGE_SIZE #define FDS_VIRTUAL_PAGE_SIZE 1024 @@ -3039,7 +3166,7 @@ #define FSTORAGE_ENABLED 1 #endif #if FSTORAGE_ENABLED -// FS_QUEUE_SIZE - Configures the size of the internal queue. +// FS_QUEUE_SIZE - Configures the size of the internal queue. // Increase this if there are many users, or if it is likely that many // operation will be queued at once without waiting for the previous operations // to complete. In general, increase the queue size if you frequently receive @@ -3049,7 +3176,7 @@ #define FS_QUEUE_SIZE 4 #endif -// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. +// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. // Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT // error often. The SoftDevice may fail to schedule flash access due to high BLE activity. @@ -3057,7 +3184,7 @@ #define FS_OP_MAX_RETRIES 3 #endif -// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. +// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. // Tweaking this value can increase the chances of the SoftDevice being // able to fit flash operations in between radio activity. This value is bound by the // maximum number of words which the SoftDevice can write to flash in a single call to @@ -3071,14 +3198,14 @@ // // ECC_ENABLED - ecc - Elliptic Curve Cryptography Library - + #ifndef ECC_ENABLED #define ECC_ENABLED 0 #endif // HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release - + #ifndef HARDFAULT_HANDLER_ENABLED #define HARDFAULT_HANDLER_ENABLED 1 @@ -3090,17 +3217,17 @@ #define HCI_MEM_POOL_ENABLED 0 #endif #if HCI_MEM_POOL_ENABLED -// HCI_TX_BUF_SIZE - TX buffer size in bytes. +// HCI_TX_BUF_SIZE - TX buffer size in bytes. #ifndef HCI_TX_BUF_SIZE #define HCI_TX_BUF_SIZE 600 #endif -// HCI_RX_BUF_SIZE - RX buffer size in bytes. +// HCI_RX_BUF_SIZE - RX buffer size in bytes. #ifndef HCI_RX_BUF_SIZE #define HCI_RX_BUF_SIZE 600 #endif -// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. #ifndef HCI_RX_BUF_QUEUE_SIZE #define HCI_RX_BUF_QUEUE_SIZE 4 #endif @@ -3115,53 +3242,53 @@ #endif #if HCI_SLIP_ENABLED // HCI_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud #ifndef HCI_UART_BAUDRATE #define HCI_UART_BAUDRATE 30801920 #endif // HCI_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled + +// <0=> Disabled +// <1=> Enabled #ifndef HCI_UART_FLOW_CONTROL #define HCI_UART_FLOW_CONTROL 0 #endif -// HCI_UART_RX_PIN - UART RX pin +// HCI_UART_RX_PIN - UART RX pin #ifndef HCI_UART_RX_PIN #define HCI_UART_RX_PIN 8 #endif -// HCI_UART_TX_PIN - UART TX pin +// HCI_UART_TX_PIN - UART TX pin #ifndef HCI_UART_TX_PIN #define HCI_UART_TX_PIN 6 #endif -// HCI_UART_RTS_PIN - UART RTS pin +// HCI_UART_RTS_PIN - UART RTS pin #ifndef HCI_UART_RTS_PIN #define HCI_UART_RTS_PIN 5 #endif -// HCI_UART_CTS_PIN - UART CTS pin +// HCI_UART_CTS_PIN - UART CTS pin #ifndef HCI_UART_CTS_PIN #define HCI_UART_CTS_PIN 7 #endif @@ -3175,7 +3302,7 @@ #define HCI_TRANSPORT_ENABLED 0 #endif #if HCI_TRANSPORT_ENABLED -// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. #ifndef HCI_MAX_PACKET_SIZE_IN_BITS #define HCI_MAX_PACKET_SIZE_IN_BITS 8000 #endif @@ -3184,14 +3311,14 @@ // // LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module - + #ifndef LED_SOFTBLINK_ENABLED #define LED_SOFTBLINK_ENABLED 0 #endif // LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module - + #ifndef LOW_POWER_PWM_ENABLED #define LOW_POWER_PWM_ENABLED 0 @@ -3203,42 +3330,42 @@ #define MEM_MANAGER_ENABLED 0 #endif #if MEM_MANAGER_ENABLED -// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> #ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT #define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 #endif -// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. // Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. #ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE #define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 #endif -// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT #define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 #endif -// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. // Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE #define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 #endif -// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> #ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT #define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 #endif -// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. // Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. #ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE @@ -3246,14 +3373,14 @@ #endif // MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. - + #ifndef MEM_MANAGER_ENABLE_LOGS #define MEM_MANAGER_ENABLE_LOGS 0 #endif // MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. - + #ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK #define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 @@ -3268,32 +3395,32 @@ #define NRF_CSENSE_ENABLED 0 #endif #if NRF_CSENSE_ENABLED -// NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. +// NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. #ifndef NRF_CSENSE_PAD_HYSTERESIS #define NRF_CSENSE_PAD_HYSTERESIS 15 #endif -// NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. +// NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. #ifndef NRF_CSENSE_PAD_DEVIATION #define NRF_CSENSE_PAD_DEVIATION 70 #endif -// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. #ifndef NRF_CSENSE_MIN_PAD_VALUE #define NRF_CSENSE_MIN_PAD_VALUE 20 #endif -// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. #ifndef NRF_CSENSE_MAX_PADS_NUMBER #define NRF_CSENSE_MAX_PADS_NUMBER 20 #endif -// NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. +// NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. #ifndef NRF_CSENSE_MAX_VALUE #define NRF_CSENSE_MAX_VALUE 1000 #endif -// NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. +// NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. // This is only used when running on NRF51. #ifndef NRF_CSENSE_OUTPUT_PIN @@ -3309,17 +3436,17 @@ #define NRF_DRV_CSENSE_ENABLED 0 #endif #if NRF_DRV_CSENSE_ENABLED -// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) #ifndef TIMER0_FOR_CSENSE #define TIMER0_FOR_CSENSE 1 #endif -// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) #ifndef TIMER1_FOR_CSENSE #define TIMER1_FOR_CSENSE 2 #endif -// MEASUREMENT_PERIOD - Single measurement period. +// MEASUREMENT_PERIOD - Single measurement period. // Time of single measurement can be calculated as T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). I_SOURCE, VUP and VDOWN are values used to initialize COMP and C is capacitance of used pad. #ifndef MEASUREMENT_PERIOD @@ -3330,14 +3457,14 @@ // // NRF_QUEUE_ENABLED - nrf_queue - Queue module - + #ifndef NRF_QUEUE_ENABLED #define NRF_QUEUE_ENABLED 1 #endif // SLIP_ENABLED - slip - SLIP encoding decoding - + #ifndef SLIP_ENABLED #define SLIP_ENABLED 0 @@ -3347,46 +3474,46 @@ //========================================================== // APP_USBD_CLASS_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library - + #ifndef APP_USBD_CLASS_CDC_ACM_ENABLED #define APP_USBD_CLASS_CDC_ACM_ENABLED 0 #endif // APP_USBD_CDC_ACM_LOG_ENABLED - Enables logging in the module. - + #ifndef APP_USBD_CDC_ACM_LOG_ENABLED #define APP_USBD_CDC_ACM_LOG_ENABLED 0 #endif -// +// //========================================================== // app_usbd_msc - USB MSC class //========================================================== // APP_USBD_CLASS_MSC_ENABLED - Enabling USBD MSC Class library - + #ifndef APP_USBD_CLASS_MSC_ENABLED #define APP_USBD_CLASS_MSC_ENABLED 0 #endif // APP_USBD_MSC_CLASS_LOG_ENABLED - Enables logging in the module. - + #ifndef APP_USBD_MSC_CLASS_LOG_ENABLED #define APP_USBD_MSC_CLASS_LOG_ENABLED 0 #endif -// +// //========================================================== -// +// //========================================================== -// nRF_Log +// nRF_Log //========================================================== // NRF_LOG_ENABLED - nrf_log - Logging @@ -3402,48 +3529,48 @@ #endif #if NRF_LOG_USES_COLORS // NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef NRF_LOG_COLOR_DEFAULT #define NRF_LOG_COLOR_DEFAULT 0 #endif // NRF_LOG_ERROR_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef NRF_LOG_ERROR_COLOR #define NRF_LOG_ERROR_COLOR 0 #endif // NRF_LOG_WARNING_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White #ifndef NRF_LOG_WARNING_COLOR #define NRF_LOG_WARNING_COLOR 0 @@ -3453,12 +3580,12 @@ // // NRF_LOG_DEFAULT_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug #ifndef NRF_LOG_DEFAULT_LEVEL #define NRF_LOG_DEFAULT_LEVEL 3 @@ -3472,7 +3599,7 @@ #define NRF_LOG_DEFERRED 1 #endif #if NRF_LOG_DEFERRED -// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. +// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. // Must be power of 2 #ifndef NRF_LOG_DEFERRED_BUFSIZE @@ -3483,7 +3610,7 @@ // // NRF_LOG_USES_TIMESTAMP - Enable timestamping - + // Function for getting the timestamp is provided by the user @@ -3497,14 +3624,14 @@ // nrf_log_backend - Logging sink //========================================================== -// NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string +// NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string // Logger backend RAM usage is determined by this value. #ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH #define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256 #endif -// NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp +// NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp // If higher resolution timestamp source is used it might be needed to increase that #ifndef NRF_LOG_TIMESTAMP_DIGITS @@ -3518,60 +3645,60 @@ #endif #if NRF_LOG_BACKEND_SERIAL_USES_UART // NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud #ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE #define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30801920 #endif -// NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin +// NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin #ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN #define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 6 #endif -// NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin +// NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin #ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN #define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 8 #endif -// NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin +// NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin #ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN #define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 5 #endif -// NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin +// NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin #ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN #define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 7 #endif // NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled + +// <0=> Disabled +// <1=> Enabled #ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL #define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0 #endif // NRF_LOG_BACKEND_UART_INSTANCE - UART instance used - -// <0=> 0 + +// <0=> 0 #ifndef NRF_LOG_BACKEND_UART_INSTANCE #define NRF_LOG_BACKEND_UART_INSTANCE 0 @@ -3586,7 +3713,7 @@ #define NRF_LOG_BACKEND_SERIAL_USES_RTT 0 #endif #if NRF_LOG_BACKEND_SERIAL_USES_RTT -// NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. +// NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. // Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH. // This value is used in Segger RTT configuration to set the buffer size // if it is bigger than default RTT buffer size. @@ -3598,19 +3725,19 @@ #endif //NRF_LOG_BACKEND_SERIAL_USES_RTT // -// +// //========================================================== -// +// //========================================================== -// nRF_Segger_RTT +// nRF_Segger_RTT //========================================================== // segger_rtt - SEGGER RTT //========================================================== -// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. +// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. // Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE // or this value is actually used. It depends on which one is bigger. @@ -3618,40 +3745,40 @@ #define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64 #endif -// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. +// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. #ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS #define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 #endif -// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. +// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. #ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN #define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 #endif -// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. +// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. #ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS #define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 #endif // SEGGER_RTT_CONFIG_DEFAULT_MODE - RTT behavior if the buffer is full. - + // The following modes are supported: // - SKIP - Do not block, output nothing. // - TRIM - Do not block, output as much as fits. // - BLOCK - Wait until there is space in the buffer. -// <0=> SKIP -// <1=> TRIM -// <2=> BLOCK_IF_FIFO_FULL +// <0=> SKIP +// <1=> TRIM +// <2=> BLOCK_IF_FIFO_FULL #ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE #define SEGGER_RTT_CONFIG_DEFAULT_MODE 0 #endif -// +// //========================================================== -// +// //========================================================== // <<< end of configuration section >>> diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qspi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qspi.h new file mode 100644 index 00000000000..97f3d2fd307 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qspi.h @@ -0,0 +1,738 @@ +/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** + * @defgroup nrf_qspi_hal QSPI HAL + * @{ + * @ingroup nrf_qspi + * + * @brief Hardware access layer for accessing the QSPI peripheral. + */ + +#ifndef NRF_QSPI_H__ +#define NRF_QSPI_H__ + +#include +#include +#include "boards.h" +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set + * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3) + * will not be connected to a physical pin. + */ +#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF + +/** + * @brief Macro for setting proper values to pin registers. + */ + +#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin) + +/** + * @brief QSPI tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */ + NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */ + NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */ + NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */ + /*lint -restore*/ +} nrf_qspi_task_t; + +/** + * @brief QSPI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */ + /*lint -restore*/ +} nrf_qspi_event_t; + +/** + * @brief QSPI interrupts. + */ +typedef enum +{ + NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */ +} nrf_qspi_int_mask_t; + +/** + * @brief QSPI frequency divider values. + */ +typedef enum +{ + NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */ + NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */ + NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */ + NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */ + NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */ + NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */ + NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */ + NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */ + NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */ + NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */ + NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */ + NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */ + NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */ + NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */ + NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */ + NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */ +} nrf_qspi_frequency_t; + +/** + * @brief Interface configuration for a read operation. + */ +typedef enum +{ + NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */ + NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */ + NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */ + NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */ + NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */ +} nrf_qspi_readoc_t; + +/** + * @brief Interface configuration for a write operation. + */ +typedef enum +{ + NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */ + NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */ + NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */ + NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */ +} nrf_qspi_writeoc_t; + +/** + * @brief Interface configuration for addressing mode. + */ +typedef enum +{ + NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */ + NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */ +} nrf_qspi_addrmode_t; + +/** + * @brief QSPI SPI mode. Polarization and phase configuration. + */ +typedef enum +{ + NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */ + NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */ +} nrf_qspi_spi_mode_t; + +/** + * @brief Addressing configuration mode. + */ +typedef enum +{ + NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */ + NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */ + NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */ + NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */ +} nrf_qspi_addrconfig_mode_t; + +/** + * @brief Erasing data length. + */ +typedef enum +{ + NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */ + NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */ + NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */ +} nrf_qspi_erase_len_t; + +/** + * @brief Custom instruction length. + */ +typedef enum +{ + NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */ + NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */ + NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ + NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ + NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ + NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ + NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ + NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ + NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ +} nrf_qspi_cinstr_len_t; + +/** + * @brief Pins configuration. + */ +typedef struct +{ + uint8_t sck_pin; /**< SCK pin number. */ + uint8_t csn_pin; /**< Chip select pin number. */ + uint8_t io0_pin; /**< IO0/MOSI pin number. */ + uint8_t io1_pin; /**< IO1/MISO pin number. */ + uint8_t io2_pin; /**< IO2 pin number (optional). + * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. + */ + uint8_t io3_pin; /**< IO3 pin number (optional). + * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. + */ +} nrf_qspi_pins_t; + +/** + * @brief Custom instruction configuration. + */ +typedef struct +{ + uint8_t opcode; /**< Opcode used in custom instruction transmission. */ + nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */ + bool io2_level; /**< I/O line level during transmission. */ + bool io3_level; /**< I/O line level during transmission. */ + bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */ + bool wren; /**< Send write enable before instruction. */ +} nrf_qspi_cinstr_conf_t; + +/** + * @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set + */ +typedef struct +{ + uint8_t opcode; /**< Opcode used to enter proper addressing mode. */ + uint8_t byte0; /**< Byte following the opcode. */ + uint8_t byte1; /**< Byte following byte0. */ + nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */ + bool wipwait; /**< Enable/disable waiting for complete operation execution. */ + bool wren; /**< Send write enable before instruction. */ +} nrf_qspi_addrconfig_conf_t; + +/** + * @brief Structure with QSPI protocol interface configuration. + */ +typedef struct +{ + nrf_qspi_readoc_t readoc; /**< Read operation code. */ + nrf_qspi_writeoc_t writeoc; /**< Write operation code. */ + nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */ + bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */ +} nrf_qspi_prot_conf_t; + +/** + * @brief QSPI physical interface configuration. + */ +typedef struct +{ + uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */ + bool dpmen; /**< Enable the DPM feature. */ + nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */ + nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */ +} nrf_qspi_phy_conf_t; + +/** + * @brief Function for activating a specific QSPI task. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task); + +/** + * @brief Function for getting the address of a specific QSPI task register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_task_t task); + +/** + * @brief Function for clearing a specific QSPI event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Event to clear. + */ +__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event); + +/** + * @brief Function for checking the state of a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event); + +/** + * @brief Function for getting the address of a specific QSPI event register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_event_t qspi_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, + nrf_qspi_int_mask_t qspi_int); + +/** + * @brief Function for enabling the QSPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral register structure. + */ +__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg); + +/** + * @brief Function for disabling the QSPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral register structure. + */ +__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg); + +/** + * @brief Function for configuring QSPI pins. + * + * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t. + */ +__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_pins_t * p_pins); + +/** + * @brief Function for setting the QSPI IFCONFIG0 register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t. + */ +__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_prot_conf_t * p_config); + +/** + * @brief Function for setting the QSPI IFCONFIG1 register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t. + */ +__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_phy_conf_t * p_config); + +/** + * @brief Function for setting the QSPI ADDRCONF register. + * + * Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure + * is sent during the start of the peripheral. Remember that the reset instruction can set + * addressing mode to default in the memory device. If memory reset is necessary before configuring + * the addressing mode, use custom instruction feature instead of this function. + * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions + * using a custom instruction feature (reset enable and then reset), set proper addressing mode + * using the custom instruction feature. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t. +*/ +__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_addrconfig_conf_t * p_config); + +/** + * @brief Function for setting write data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_buffer Pointer to the writing buffer. + * @param[in] length Lenght of the writing data. + * @param[in] dest_addr Address in memory to write to. + */ +__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, + void const * p_buffer, + uint32_t length, + uint32_t dest_addr); + +/** + * @brief Function for setting read data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[out] p_buffer Pointer to the reading buffer. + * @param[in] length Length of the read data. + * @param[in] src_addr Address in memory to read from. + */ +__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, + void * p_buffer, + uint32_t length, + uint32_t src_addr); + +/** + * @brief Function for setting erase data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes. + * @param[in] len Size of erasing area. + */ +__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, + uint32_t erase_addr, + nrf_qspi_erase_len_t len); + +/** + * @brief Function for getting the peripheral status register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @return Peripheral status register. + */ +__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for getting the device status register stored in the peripheral status register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @return Device status register (lower byte). + */ +__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for checking if the peripheral is busy or not. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @retval true If QSPI is busy. + * @retval false If QSPI is ready. + */ +__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for setting registers sending with custom instruction transmission. + * + * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument + * (sending only opcode without data). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] length Length of the custom instruction data. + * @param[in] p_tx_data Pointer to the data to send with the custom instruction. + */ +__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, + nrf_qspi_cinstr_len_t length, + void const * p_tx_data); + +/** + * @brief Function for getting data from register after custom instruction transmission. + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] length Length of the custom instruction data. + * @param[in] p_rx_data Pointer to the reading buffer. + */ +__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_cinstr_len_t length, + void * p_rx_data); + +/** + * @brief Function for sending custom instruction to external memory. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t. + */ + +__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, + const nrf_qspi_cinstr_conf_t * p_config); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_task_t task) +{ + return ((uint32_t)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); +} + +__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_event_t qspi_event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); +} + +__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) +{ + p_reg->INTENSET = qspi_int_mask; +} + +__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) +{ + p_reg->INTENCLR = qspi_int_mask; +} + +__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, + nrf_qspi_int_mask_t qspi_int) +{ + return (bool)(p_reg->INTENSET & qspi_int); +} + +__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg) +{ + p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg) +{ + p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins) +{ + p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin); + p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin); + p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin); + p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin); + p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin); + p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin); +} + +__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_prot_conf_t * p_config) +{ + uint32_t config = p_config->readoc; + config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos; + config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos; + config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos; + + p_reg->IFCONFIG0 = config; +} + +__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_phy_conf_t * p_config) +{ + // IFCONFIG1 mask for reserved fields in the register. + uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00; + config |= p_config->sck_delay; + config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos; + config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos; + config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos; + + p_reg->IFCONFIG1 = config; +} + +__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_addrconfig_conf_t * p_config) +{ + uint32_t config = p_config->opcode; + config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos; + config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos; + config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos; + config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos; + config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos; + + p_reg->ADDRCONF = config; +} + +__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, + void const * p_buffer, + uint32_t length, + uint32_t dest_addr) +{ + p_reg->WRITE.DST = dest_addr; + p_reg->WRITE.SRC = (uint32_t) p_buffer; + p_reg->WRITE.CNT = length; +} + +__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, + void * p_buffer, + uint32_t length, + uint32_t src_addr) +{ + p_reg->READ.SRC = src_addr; + p_reg->READ.DST = (uint32_t) p_buffer; + p_reg->READ.CNT = length; +} + +__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, + uint32_t erase_addr, + nrf_qspi_erase_len_t len) +{ + p_reg->ERASE.PTR = erase_addr; + p_reg->ERASE.LEN = len; +} + +__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg) +{ + return p_reg->STATUS; +} + +__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg) +{ + return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos; +} + +__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg) +{ + return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >> + QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY; +} + +__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, + nrf_qspi_cinstr_len_t length, + void const * p_tx_data) +{ + uint32_t reg = 0; + uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data; + + // Load custom instruction. + switch (length) + { + case NRF_QSPI_CINSTR_LEN_9B: + reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_8B: + reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_7B: + reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_6B: + reg |= ((uint32_t)p_tx_data_8[4]); + p_reg->CINSTRDAT1 = reg; + reg = 0; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_5B: + reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_4B: + reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_3B: + reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_2B: + reg |= ((uint32_t)p_tx_data_8[0]); + p_reg->CINSTRDAT0 = reg; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_1B: + /* Send only opcode. Case to avoid compiler warnings. */ + break; + default: + break; + } +} + +__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_cinstr_len_t length, + void * p_rx_data) +{ + uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data; + + uint32_t reg = p_reg->CINSTRDAT1; + switch (length) + { + case NRF_QSPI_CINSTR_LEN_9B: + p_rx_data_8[7] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE7_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_8B: + p_rx_data_8[6] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE6_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_7B: + p_rx_data_8[5] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE5_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_6B: + p_rx_data_8[4] = (uint8_t)(reg); + /* fall-through */ + default: + break; + } + + reg = p_reg->CINSTRDAT0; + switch (length) + { + case NRF_QSPI_CINSTR_LEN_5B: + p_rx_data_8[3] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE3_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_4B: + p_rx_data_8[2] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE2_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_3B: + p_rx_data_8[1] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE1_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_2B: + p_rx_data_8[0] = (uint8_t)(reg); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_1B: + /* Send only opcode. Case to avoid compiler warnings. */ + break; + default: + break; + } +} + +__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, + const nrf_qspi_cinstr_conf_t * p_config) +{ + p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) | + ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) | + ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) | + ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) | + ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) | + ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#ifdef __cplusplus +} +#endif + +#endif // NRF_QSPI_H__ + +/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.c new file mode 100644 index 00000000000..e637df8f297 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.c @@ -0,0 +1,275 @@ +/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +#include "sdk_config.h" + +#if QSPI_ENABLED + +#include "nrf_drv_qspi.h" +#include "nrf_drv_common.h" +#include "nrf_gpio.h" +#include "nrf_assert.h" + +/** + * @brief Command byte used to read status register. + * + */ +#define QSPI_STD_CMD_RDSR 0x05 + +/** + * @brief Byte used to mask status register and retrieve the write-in-progess bit. + * + */ +#define QSPI_MEM_STATUSREG_WIP_Pos 0x01 + +#define QSPI_WAIT_READY() do { \ + while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)); \ + } while(0) + +/** + * @brief Control block - driver instance local data. + * + */ +typedef struct +{ + nrf_drv_qspi_handler_t handler; /**< Handler. */ + nrf_drv_state_t state; /**< Driver state. */ + volatile bool interrupt_driven; /**< Information if the current operation is performed and is interrupt-driven. */ + void * p_context; /**< Driver context used in interrupt. */ +} qspi_control_block_t; + +static qspi_control_block_t m_cb; + +static ret_code_t qspi_task_perform(nrf_qspi_task_t task) +{ + // Wait for peripheral + if (m_cb.interrupt_driven) + { + return NRF_ERROR_BUSY; + } + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + + if (m_cb.handler) + { + m_cb.interrupt_driven = true; + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + } + + nrf_qspi_task_trigger(NRF_QSPI, task); + + if (m_cb.handler == NULL) + { + QSPI_WAIT_READY(); + } + return NRF_SUCCESS; +} + +static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) +{ + // Check if the user set meaningful values to struct fields. If not, return false. + if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED)) + { + return false; + } + + nrf_qspi_pins_set(NRF_QSPI, p_config); + + return true; +} + +ret_code_t nrf_drv_qspi_init(nrf_drv_qspi_config_t const * p_config, + nrf_drv_qspi_handler_t handler, + void * p_context) +{ + if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) + { + return NRF_ERROR_INVALID_STATE; + } + + if (!qspi_pins_configure(&p_config->pins)) + { + return NRF_ERROR_INVALID_PARAM; + } + + nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if); + nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if); + + m_cb.interrupt_driven = false; + m_cb.handler = handler; + m_cb.p_context = p_context; + + /* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate + task event ready)*/ + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + if (handler) + { + nrf_drv_common_irq_enable(QSPI_IRQn, p_config->irq_priority); + } + + m_cb.state = NRF_DRV_STATE_INITIALIZED; + + nrf_qspi_enable(NRF_QSPI); + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE); + + // Waiting for the peripheral to activate + QSPI_WAIT_READY(); + + return NRF_SUCCESS; +} + +ret_code_t nrf_drv_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, + void const * p_tx_buffer, + void * p_rx_buffer) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + + + if (m_cb.interrupt_driven) + { + return NRF_ERROR_BUSY; + } + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + /* In some cases, only opcode should be sent. To prevent execution, set function code is + * surrounded by an if. + */ + if (p_tx_buffer) + { + nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer); + } + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config); + + QSPI_WAIT_READY(); + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + if (p_rx_buffer) + { + nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer); + } + + return NRF_SUCCESS; +} + +ret_code_t nrf_drv_qspi_cinstr_quick_send(uint8_t opcode, + nrf_qspi_cinstr_len_t length, + void const * p_tx_buffer) +{ + nrf_qspi_cinstr_conf_t config = NRF_DRV_QSPI_DEFAULT_CINSTR(opcode, length); + return nrf_drv_qspi_cinstr_xfer(&config, p_tx_buffer, NULL); +} + +ret_code_t nrf_drv_qspi_mem_busy_check(void) +{ + ret_code_t ret_code; + uint8_t status_value = 0; + + nrf_qspi_cinstr_conf_t config = NRF_DRV_QSPI_DEFAULT_CINSTR(QSPI_STD_CMD_RDSR, + NRF_QSPI_CINSTR_LEN_2B); + + ret_code = nrf_drv_qspi_cinstr_xfer(&config, &status_value, &status_value); + + if (ret_code != NRF_SUCCESS) + { + return ret_code; + } + + if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00) + { + return NRF_ERROR_BUSY; + } + + return NRF_SUCCESS; +} + +void nrf_drv_qspi_uninit(void) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + nrf_qspi_disable(NRF_QSPI); + + nrf_drv_common_irq_disable(QSPI_IRQn); + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + + m_cb.state = NRF_DRV_STATE_UNINITIALIZED; +} + +ret_code_t nrf_drv_qspi_write(void const * p_tx_buffer, + size_t tx_buffer_length, + uint32_t dst_address) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + ASSERT(p_tx_buffer != NULL); + + if (!nrf_drv_is_in_RAM(p_tx_buffer)) + { + return NRF_ERROR_INVALID_ADDR; + } + + nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address); + return qspi_task_perform(NRF_QSPI_TASK_WRITESTART); + +} + +ret_code_t nrf_drv_qspi_read(void * p_rx_buffer, + size_t rx_buffer_length, + uint32_t src_address) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + ASSERT(p_rx_buffer != NULL); + + if (!nrf_drv_is_in_RAM(p_rx_buffer)) + { + return NRF_ERROR_INVALID_ADDR; + } + + nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address); + return qspi_task_perform(NRF_QSPI_TASK_READSTART); +} + +ret_code_t nrf_drv_qspi_erase(nrf_qspi_erase_len_t length, + uint32_t start_address) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length); + return qspi_task_perform(NRF_QSPI_TASK_ERASESTART); +} + +ret_code_t nrf_drv_qspi_chip_erase(void) +{ + return nrf_drv_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0); +} + +void QSPI_IRQHandler(void) +{ + // Catch Event ready interrupts + if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) + { + m_cb.interrupt_driven = false; + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + m_cb.handler(NRF_DRV_QSPI_EVENT_DONE, m_cb.p_context); + } +} + +#endif // QSPI_ENABLED diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.h new file mode 100644 index 00000000000..dff908cdc91 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qspi/nrf_drv_qspi.h @@ -0,0 +1,284 @@ +/* Copyright (c) 2016 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/**@file + * @addtogroup nrf_qspi QSPI HAL and driver + * @ingroup nrf_drivers + * @brief @tagAPI52840 Quad serial peripheral interface (QSPI) APIs. + * + * @defgroup nrf_drv_qspi QSPI driver + * @{ + * @ingroup nrf_qspi + * @brief @tagAPI52840 Quad serial peripheral interface (QSPI) driver. + */ + +#ifndef NRF_DRV_QSPI_H__ +#define NRF_DRV_QSPI_H__ + +#include "nordic_common.h" +#include "sdk_config.h" +#include "nrf_qspi.h" +#include "sdk_errors.h" +#include "boards.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief QSPI driver instance configuration structure. + */ +typedef struct +{ + nrf_qspi_pins_t pins; /**< Pins configuration structure. */ + nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */ + nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */ + uint8_t irq_priority; /**< Interrupt priority. */ +} nrf_drv_qspi_config_t; + +#if QSPI_PIN_SCK == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_SCK + #define QSPI_PIN_SCK BSP_QSPI_SCK_PIN +#endif +#if QSPI_PIN_CSN == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_CSN + #define QSPI_PIN_CSN BSP_QSPI_CSN_PIN +#endif +#if QSPI_PIN_IO0 == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_IO0 + #define QSPI_PIN_IO0 BSP_QSPI_IO0_PIN +#endif +#if QSPI_PIN_IO1 == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_IO1 + #define QSPI_PIN_IO1 BSP_QSPI_IO1_PIN +#endif +#if QSPI_PIN_IO2 == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_IO2 + #define QSPI_PIN_IO2 BSP_QSPI_IO2_PIN +#endif +#if QSPI_PIN_IO3 == NRF_QSPI_PIN_NOT_CONNECTED + #undef QSPI_PIN_IO3 + #define QSPI_PIN_IO3 BSP_QSPI_IO3_PIN +#endif +/** + * @brief QSPI instance default configuration. + */ +#define NRF_DRV_QSPI_DEFAULT_CONFIG \ +{ \ + .pins = { \ + .sck_pin = QSPI_PIN_SCK, \ + .csn_pin = QSPI_PIN_CSN, \ + .io0_pin = QSPI_PIN_IO0, \ + .io1_pin = QSPI_PIN_IO1, \ + .io2_pin = QSPI_PIN_IO2, \ + .io3_pin = QSPI_PIN_IO3, \ + }, \ + .irq_priority = (uint8_t)QSPI_CONFIG_IRQ_PRIORITY, \ + .prot_if = { \ + .readoc = (nrf_qspi_readoc_t) QSPI_CONFIG_READOC, \ + .writeoc = (nrf_qspi_writeoc_t) QSPI_CONFIG_WRITEOC, \ + .addrmode = (nrf_qspi_addrmode_t) QSPI_CONFIG_ADDRMODE, \ + .dpmconfig = false, \ + }, \ + .phy_if = { \ + .sck_freq = (nrf_qspi_frequency_t) QSPI_CONFIG_FREQUENCY, \ + .sck_delay = (uint8_t) QSPI_CONFIG_SCK_DELAY, \ + .spi_mode = (nrf_qspi_spi_mode_t) QSPI_CONFIG_MODE, \ + .dpmen = false \ + } \ +} + + +/** + * @brief QSPI custom instruction helper with default configuration. + */ +#define NRF_DRV_QSPI_DEFAULT_CINSTR(opc, len) \ +{ \ + .opcode = (opc), \ + .length = (len), \ + .io2_level = false, \ + .io3_level = false, \ + .wipwait = false, \ + .wren = false \ +} + +/** + * @brief QSPI master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRF_DRV_QSPI_EVENT_DONE, /**< Transfer done. */ +} nrf_drv_qspi_evt_t; + +/** + * @brief QSPI driver event handler type. + */ +typedef void (*nrf_drv_qspi_handler_t)(nrf_drv_qspi_evt_t event, void * p_context); + +/** + * @brief Function for initializing the QSPI driver instance. + * + * @param[in] p_config Pointer to the structure with the initial configuration. + * @param[in] handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param[in] p_context Pointer to context. Use in interrupt handler. + * + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRF_ERROR_INVALID_PARAM If the pin configuration was incorrect. + */ +ret_code_t nrf_drv_qspi_init(nrf_drv_qspi_config_t const * p_config, + nrf_drv_qspi_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the QSPI driver instance. + */ +void nrf_drv_qspi_uninit(void); + +/** + * @brief Function for reading data from QSPI memory. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the read operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being read. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and reading of data are finished. + * + * @param[out] p_rx_buffer Pointer to the receive buffer. + * @param[in] rx_buffer_length Size of the data to read. + * @param[in] src_address Address in memory to read from. + * + * @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRF_ERROR_BUSY If the driver currently handles another operation. + * @retval NRF_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. + */ +ret_code_t nrf_drv_qspi_read(void * p_rx_buffer, + size_t rx_buffer_length, + uint32_t src_address); + +/** + * @brief Function for writing data to QSPI memory. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the write operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being sent. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and sending of operation data are finished. + * To manually control operation execution in the memory device, use @ref nrf_drv_qspi_mem_busy_check + * after executing the write function. + * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral + * before the write operation checked if memory was busy. + * + * @param[in] p_tx_buffer Pointer to the writing buffer. + * @param[in] tx_buffer_length Size of the data to write. + * @param[in] dst_address Address in memory to write to. + * + * @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRF_ERROR_BUSY If the driver currently handles other operation. + * @retval NRF_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. + */ +ret_code_t nrf_drv_qspi_write(void const * p_tx_buffer, + size_t tx_buffer_length, + uint32_t dst_address); + +/** + * @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the erase operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being sent. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and sending of operation data are finished. + * To manually control operation execution in the memory device, use @ref nrf_drv_qspi_mem_busy_check + * after executing the erase function. + * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral + * before the erase operation checked if memory was busy. + * + * @param[in] length Size of data to erase. See @ref nrf_qspi_erase_len_t. + * @param[in] start_address Memory address to start erasing. If chip erase is performed, address + * field is ommited. + * + * @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRF_ERROR_BUSY If the driver currently handles another operation. + */ +ret_code_t nrf_drv_qspi_erase(nrf_qspi_erase_len_t length, + uint32_t start_address); + +/** + * @brief Function for starting an erase operation of the whole chip. + * + * @retval NRF_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRF_ERROR_BUSY If the driver currently handles another operation. + */ +ret_code_t nrf_drv_qspi_chip_erase(void); + +/** + * @brief Function for getting the current driver status and status byte of memory device with + * testing WIP (write in progress) bit. + * + * @retval NRF_SUCCESS If the driver and memory are ready to handle a new operation. + * @retval NRF_ERROR_BUSY If the driver or memory currently handle another operation. + */ +ret_code_t nrf_drv_qspi_mem_busy_check(void); + +/** + * @brief Function for sending operation code, sending data, and receiving data from the memory device. + * + * Use this function to transfer configuration data to memory and to receive data from memory. + * Pointers can be addresses from flash memory. + * This function is a synchronous function and should be used only if necessary. + * See more: @ref hardware_driver_qspi. + * + * @param[in] p_config Pointer to the structure with opcode and transfer configuration. + * @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted. + * @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive. + * + * @retval NRF_SUCCESS If the operation was successful. + * @retval NRF_ERROR_BUSY If the driver currently handles other operation. + */ +ret_code_t nrf_drv_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, + void const * p_tx_buffer, + void * p_rx_buffer); +/** + * @brief Function for sending operation code and data to the memory device with simpler configuration. + * + * Use this function to transfer configuration data to memory and to receive data from memory. + * This function is a synchronous function and should be used only if necessary. + * + * @param[in] opcode Operation code. Sending first. + * @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t. + * @param[in] p_tx_buffer Pointer to input data array. + * + * @retval NRF_SUCCESS If the operation was successful. + * @retval NRF_ERROR_BUSY If the driver currently handles another operation. + */ +ret_code_t nrf_drv_qspi_cinstr_quick_send(uint8_t opcode, + nrf_qspi_cinstr_len_t length, + void const * p_tx_buffer); + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_QSPI_H__ + +/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/objects.h b/targets/TARGET_NORDIC/TARGET_NRF5/objects.h index 4ae7530509f..12707802cb1 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/objects.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/objects.h @@ -1,28 +1,28 @@ -/* +/* * Copyright (c) 2013 Nordic Semiconductor ASA * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list + * + * 1. Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior * written permission. * - * 4. This software, with or without modification, must only be used with a + * 4. This software, with or without modification, must only be used with a * Nordic Semiconductor ASA integrated circuit. * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,7 +33,7 @@ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ #ifndef MBED_OBJECTS_H @@ -81,6 +81,13 @@ struct gpio_irq_s { uint32_t ch; }; +struct qspi_s { + volatile uint32_t is_busy; +#if DEVICE_QSPI_ASYNCH + uint32_t handler; + uint32_t event; +#endif +}; #include "gpio_object.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/qspi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/qspi_api.c new file mode 100644 index 00000000000..4ac5ab4324d --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/qspi_api.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2017 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "qspi_api.h" + +#if DEVICE_QSPI +#include "nrf_drv_common.h" +#include "nrf_drv_qspi.h" + +void QSPI_IRQHandler(void); + +#define HZ_TO_CONFIG(hz) ((32000000/(hz))-1) + +nrf_drv_qspi_config_t config; + +static void qspi_irq_handler(nrf_drv_qspi_evt_t event, void * p_context) +{ + qspi_t *obj = (qspi_t *) p_context; + obj->is_busy = 0; + +#if DEVICE_QSPI_ASYNCH + if (obj->handler) + { + void (*handler)(void) = (void (*)(void))obj->handler; + obj->handler = 0; + handler(); + } +#endif +} + +int32_t qspi_init(qspi_t *obj, + int hz, + qspi_pins_t * pins, + int spi_mode) +{ + (void)(obj); + if (hz > 32000000) + { + /* Frequency is too high. */ + return -1; + } + + config.pins.sck_pin = (uint32_t)pins->sclk; + config.pins.csn_pin = (uint32_t)pins->ssel; + config.pins.io0_pin = (uint32_t)pins->io0; + config.pins.io1_pin = (uint32_t)pins->io1; + config.pins.io2_pin = (uint32_t)pins->io2; + config.pins.io3_pin = (uint32_t)pins->io3; + config.irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY; + + config.phy_if.sck_freq = HZ_TO_CONFIG(hz), + config.phy_if.sck_delay = 0x05, + config.phy_if.dpmen = false; + config.phy_if.spi_mode = spi_mode == 0 ? NRF_QSPI_MODE_0 : NRF_QSPI_MODE_1; + obj->is_busy = 0; + +#if DEVICE_QSPI_ASYNCH + obj->handler = 0; +#endif + + NVIC_SetVector(QSPI_IRQn, (uint32_t) QSPI_IRQHandler); + nrf_drv_common_irq_enable(QSPI_IRQn, config.irq_priority); + + return 0; + +} + +int32_t qspi_prepare(qspi_t *obj, + qspi_addrmode_t addrmode, + qspi_readmode_t readmode, + qspi_writemode_t writemode) +{ + switch (readmode) { + case QSPI_READMODE_1_1_2: + config.prot_if.readoc = NRF_QSPI_READOC_READ2O; + break; + case QSPI_READMODE_1_1_4: + config.prot_if.readoc = NRF_QSPI_READOC_READ4O; + break; + case QSPI_READMODE_1_2_2: + config.prot_if.readoc = NRF_QSPI_READOC_READ2IO; + break; + case QSPI_READMODE_1_4_4: + config.prot_if.readoc = NRF_QSPI_READOC_READ4IO; + break; + case QSPI_READMODE_1_1_1: + default: + config.prot_if.readoc = NRF_QSPI_READOC_FASTREAD; + } + + switch (writemode) { + case QSPI_WRITEMODE_1_1_2: + config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP2O; + break; + case QSPI_WRITEMODE_1_1_4: + config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4O; + break; + case QSPI_WRITEMODE_1_4_4: + config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4IO; + break; + case QSPI_WRITEMODE_1_1_1: + default: + config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP; + } + + config.prot_if.addrmode = addrmode == QSPI_ADDRMODE_24BIT ? + NRF_QSPI_ADDRMODE_24BIT : + NRF_QSPI_ADDRMODE_32BIT; + return 0; +} + +int32_t qspi_start(qspi_t *obj) +{ + nrf_drv_qspi_init(&config, qspi_irq_handler, (void *) obj); + return 0; +} + +int32_t qspi_free(qspi_t *obj) +{ + (void)(obj); + return 0; +} + +/* Static internal functions */ + +static int32_t _qspi_erase_block(qspi_t *obj, uint32_t address) +{ + if (obj->is_busy == 1) + { + return -1; + } + + obj->is_busy = 1; + if (nrf_drv_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, address) != NRF_SUCCESS) + { + obj->is_busy = 0; + return -1; + } + + return 0; +} + +static int32_t _qspi_erase_chip(qspi_t *obj) +{ + if (obj->is_busy == 1) + { + return -1; + } + + obj->is_busy = 1; + if (nrf_drv_qspi_erase(QSPI_ERASE_LEN_LEN_All, 0) != NRF_SUCCESS) + { + obj->is_busy = 0; + return -1; + } + + return 0; +} + +static int32_t _qspi_program_page(qspi_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + if (obj->is_busy == 1) + { + return -1; + } + + obj->is_busy = 1; + if (nrf_drv_qspi_write(data, size, address) != NRF_SUCCESS) + { + obj->is_busy = 0; + return -1; + } + + return 0; +} + +static int32_t _qspi_page_read(qspi_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + if (obj->is_busy == 1) + { + return -1; + } + + obj->is_busy = 1; + if (nrf_drv_qspi_read(data, size, address) != NRF_SUCCESS) + { + obj->is_busy = 0; + return -1; + } + + return 0; +} + +int32_t qspi_erase_block(qspi_t *obj, uint32_t address) +{ + int32_t ret = _qspi_erase_block(obj, address); + if (ret != 0) + { + return ret; + } + + while (obj->is_busy == 1); + return 0; +} + +int32_t qspi_erase_chip(qspi_t *obj) +{ + int32_t ret = _qspi_erase_chip(obj); + if (ret != 0) + { + return ret; + } + + while (obj->is_busy == 1); + return 0; +} + +int32_t qspi_program_page(qspi_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int32_t ret = _qspi_program_page(obj, address, data, size); + if (ret != 0) + { + return ret; + } + + while (obj->is_busy == 1); + return 0; +} + +int32_t qspi_page_read(qspi_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + int32_t ret = _qspi_page_read(obj, address, data, size); + if (ret != 0) + { + return ret; + } + + while (obj->is_busy == 1); + return 0; +} + +int32_t qspi_send_instruction(qspi_t *obj, + uint8_t cmd, + uint32_t tx_size, + const uint8_t *tx_data, + uint32_t rx_size, + uint8_t *rx_data) +{ + ret_code_t ret_code; + uint32_t i; + uint8_t data[8]; + uint32_t data_size = tx_size + rx_size; + + // this function is asynchronous so we can store data in function body + if (obj->is_busy == 1) + { + return -1; + } + + obj->is_busy = 1; + + nrf_qspi_cinstr_conf_t config; + config.opcode = cmd; + config.io2_level = false; + config.io3_level = false; + config.wipwait = false; + config.wren = false; + + if (data_size < 9) + { + config.length =NRF_QSPI_CINSTR_LEN_1B + data_size; + } + else + { + obj->is_busy = 0; + return -1; + } + + // preparing data to send + for (i = 0; i < tx_size; ++i) + { + data[i] = tx_data[i]; + } + + ret_code = nrf_drv_qspi_cinstr_xfer(&config, data, data); + + if (ret_code != NRF_SUCCESS) + { + obj->is_busy = 0; + return -1; + } + + // preparing received data + for (i = 0; i < rx_size; ++i) + { + // Data is sending as a normal SPI transmission so there is one buffer to send and receive data. + rx_data[i] = data[i + tx_size]; + } + + obj->is_busy = 0; + return 0; + +} + +int32_t qspi_is_busy(qspi_t *obj) +{ + return obj->is_busy; +} + +#if DEVICE_QSPI_ASYNCH + +uint32_t qspi_irq_handler_asynch(qspi_t *obj) +{ + MBED_ASSERT(obj); + return obj->event & QSPI_EVENT_COMPLETE; +} + +int32_t qspi_start_erase_block(qspi_t *obj, uint32_t address, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + (void)hint; + obj->handler = handler; + obj->event = event; + return _qspi_erase_block(obj, address); +} + +int32_t qspi_start_erase_chip(qspi_t *obj, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + (void)hint; + obj->handler = handler; + obj->event = event; + return _qspi_erase_chip(obj); +} + +int32_t qspi_start_program_page(qspi_t *obj, uint32_t address, const uint8_t *data, uint32_t size, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + (void)hint; + obj->handler = handler; + obj->event = event; + return _qspi_program_page(obj, address, data, size); +} + +int32_t qspi_start_page_read(qspi_t *obj, uint32_t address, uint8_t *data, uint32_t size, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + (void)hint; + obj->handler = handler; + obj->event = event; + return _qspi_page_read(obj, address, data, size); +} + +#endif + +#endif + +/** @}*/ diff --git a/targets/targets.json b/targets/targets.json index 34e0daef01b..9fb182511c2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2744,7 +2744,7 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52840"], "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"], - "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "QSPI", "QSPI_ASYNCH", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "device_name": "nRF52840_xxAA" },