From dddcf76b3e224de684d52fd52ad3c4e888298cf9 Mon Sep 17 00:00:00 2001 From: Jesse Marroquin Date: Wed, 9 Nov 2016 13:33:11 -0600 Subject: [PATCH] [MAX32630FTHR] Adding new platform --- .../TARGET_MAX32630/PeripheralPins.c | 197 +++ .../TARGET_MAX32630/PeripheralPins.h | 61 + .../TARGET_Maxim/TARGET_MAX32630/PortNames.h | 56 + .../TARGET_MAX32630FTHR/PeripheralNames.h | 90 ++ .../TARGET_MAX32630FTHR/PinNames.h | 180 +++ .../TARGET_MAX32630FTHR/low_level_init.c | 94 ++ .../TARGET_MAX32630/analogin_api.c | 96 ++ targets/TARGET_Maxim/TARGET_MAX32630/device.h | 40 + .../device/TOOLCHAIN_ARM_STD/MAX3263x.sct | 16 + .../TOOLCHAIN_ARM_STD/startup_MAX3263x.S | 297 +++++ .../device/TOOLCHAIN_ARM_STD/sys.cpp | 57 + .../device/TOOLCHAIN_GCC_ARM/max3263x.ld | 176 +++ .../TOOLCHAIN_GCC_ARM/startup_max3263x.S | 303 +++++ .../device/TOOLCHAIN_IAR/MAX3263x.icf | 29 + .../device/TOOLCHAIN_IAR/startup_MAX3263x.S | 450 +++++++ .../TARGET_MAX32630/device/adc_regs.h | 393 ++++++ .../TARGET_MAX32630/device/aes_regs.h | 188 +++ .../TARGET_MAX32630/device/clkman_regs.h | 493 +++++++ .../TARGET_MAX32630/device/cmsis.h | 41 + .../TARGET_MAX32630/device/crc_regs.h | 133 ++ .../TARGET_MAX32630/device/flc_regs.h | 395 ++++++ .../TARGET_MAX32630/device/gpio_regs.h | 668 ++++++++++ .../TARGET_MAX32630/device/i2cm_regs.h | 282 ++++ .../TARGET_MAX32630/device/i2cs_regs.h | 291 +++++ .../TARGET_MAX32630/device/icc_regs.h | 157 +++ .../TARGET_MAX32630/device/ioman_regs.h | 1163 +++++++++++++++++ .../TARGET_MAX32630/device/maa_regs.h | 212 +++ .../TARGET_MAX32630/device/max3263x.h | 998 ++++++++++++++ .../TARGET_MAX32630/device/mxc_device.h | 86 ++ .../TARGET_MAX32630/device/owm_regs.h | 218 +++ .../TARGET_MAX32630/device/pmu_regs.h | 411 ++++++ .../TARGET_MAX32630/device/prng_regs.h | 98 ++ .../TARGET_MAX32630/device/pt_regs.h | 404 ++++++ .../TARGET_MAX32630/device/pwrman_regs.h | 435 ++++++ .../TARGET_MAX32630/device/pwrseq_regs.h | 431 ++++++ .../TARGET_MAX32630/device/rtc_regs.h | 362 +++++ .../TARGET_MAX32630/device/spib_regs.h | 244 ++++ .../TARGET_MAX32630/device/spim_regs.h | 332 +++++ .../TARGET_MAX32630/device/spis_regs.h | 224 ++++ .../TARGET_MAX32630/device/spix_regs.h | 309 +++++ .../TARGET_MAX32630/device/sysman_regs.h | 96 ++ .../TARGET_MAX32630/device/system_max3263x.c | 275 ++++ .../TARGET_MAX32630/device/system_max3263x.h | 96 ++ .../TARGET_MAX32630/device/tmr_regs.h | 307 +++++ .../TARGET_MAX32630/device/tpu_regs.h | 94 ++ .../TARGET_MAX32630/device/trim_regs.h | 131 ++ .../TARGET_MAX32630/device/uart_regs.h | 270 ++++ .../TARGET_MAX32630/device/usb_regs.h | 299 +++++ .../TARGET_MAX32630/device/wdt2_regs.h | 320 +++++ .../TARGET_MAX32630/device/wdt_regs.h | 380 ++++++ .../TARGET_Maxim/TARGET_MAX32630/gpio_api.c | 128 ++ .../TARGET_MAX32630/gpio_irq_api.c | 183 +++ .../TARGET_MAX32630/gpio_object.h | 73 ++ .../TARGET_Maxim/TARGET_MAX32630/i2c_api.c | 213 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/adc.c | 180 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/adc.h | 217 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/aes.c | 214 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/aes.h | 206 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c | 185 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h | 271 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/crc.c | 108 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/crc.h | 191 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/flc.c | 260 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/flc.h | 117 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c | 186 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h | 315 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c | 924 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h | 340 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c | 209 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h | 215 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/icc.c | 77 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/icc.h | 83 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c | 59 + .../TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h | 323 +++++ targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c | 424 ++++++ targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h | 185 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/maa.c | 236 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/maa.h | 224 ++++ .../TARGET_MAX32630/mxc/mxc_assert.c | 60 + .../TARGET_MAX32630/mxc/mxc_assert.h | 108 ++ .../TARGET_MAX32630/mxc/mxc_config.h | 43 + .../TARGET_MAX32630/mxc/mxc_errors.h | 96 ++ .../TARGET_MAX32630/mxc/mxc_lock.h | 114 ++ .../TARGET_MAX32630/mxc/mxc_sys.c | 832 ++++++++++++ .../TARGET_MAX32630/mxc/mxc_sys.h | 496 +++++++ .../TARGET_MAX32630/mxc/nvic_table.c | 93 ++ .../TARGET_MAX32630/mxc/nvic_table.h | 88 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/owm.c | 639 +++++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/owm.h | 320 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c | 246 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h | 299 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/prng.c | 62 + .../TARGET_Maxim/TARGET_MAX32630/mxc/prng.h | 123 ++ targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c | 145 ++ targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h | 331 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c | 197 +++ .../TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h | 476 +++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/spim.c | 725 ++++++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/spim.h | 347 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/spix.c | 297 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/spix.h | 140 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c | 399 ++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h | 611 +++++++++ .../TARGET_MAX32630/mxc/tmr_utils.c | 174 +++ .../TARGET_MAX32630/mxc/tmr_utils.h | 136 ++ .../TARGET_Maxim/TARGET_MAX32630/mxc/uart.c | 661 ++++++++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/uart.h | 347 +++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c | 290 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h | 254 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c | 275 ++++ .../TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h | 218 +++ .../TARGET_Maxim/TARGET_MAX32630/objects.h | 116 ++ targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c | 81 ++ .../TARGET_Maxim/TARGET_MAX32630/port_api.c | 98 ++ .../TARGET_Maxim/TARGET_MAX32630/pwmout_api.c | 221 ++++ .../TARGET_Maxim/TARGET_MAX32630/rtc_api.c | 253 ++++ .../TARGET_Maxim/TARGET_MAX32630/serial_api.c | 381 ++++++ targets/TARGET_Maxim/TARGET_MAX32630/sleep.c | 46 + .../TARGET_Maxim/TARGET_MAX32630/spi_api.c | 181 +++ .../TARGET_Maxim/TARGET_MAX32630/us_ticker.c | 257 ++++ targets/TARGET_Maxim/mbed_rtx.h | 15 + targets/targets.json | 9 + 122 files changed, 31024 insertions(+) create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/PortNames.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PeripheralNames.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/low_level_init.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/MAX3263x.sct create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/startup_max3263x.S create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/MAX3263x.icf create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/startup_MAX3263x.S create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/cmsis.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/crc_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/i2cm_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/mxc_device.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/prng_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/pt_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/pwrman_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/spib_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/spim_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/spix_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/sysman_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/tmr_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/tpu_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/trim_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/usb_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/wdt2_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/gpio_object.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_config.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_errors.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/prng.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/prng.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/objects.h create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/port_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/pwmout_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/sleep.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c create mode 100644 targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c new file mode 100644 index 00000000000..ccb27f26937 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c @@ -0,0 +1,197 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "device.h" +#include "PeripheralPins.h" +#include "ioman_regs.h" +#include "ioman.h" +#include "adc.h" + +/* + * To select a peripheral function on Maxim microcontrollers, multiple + * configurations must be made. The mbed PinMap structure only includes one + * data member to hold this information. To extend the configuration storage, + * the "function" data member is used as a pointer to a pin_function_t + * structure. This structure is defined in objects.h. The definitions below + * include the creation of the pin_function_t structures and the assignment of + * the pointers to the "function" data members. + */ + +#ifdef TOOLCHAIN_ARM_STD +#pragma diag_suppress 1296 +#endif + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) }, + { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { P7_1, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P6_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P7_3, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_I2C_SCL[] = { + { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) }, + { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { P7_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P7_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { P8_0, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) }, + { P7_4, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) }, + { NC, NC, 0 } +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) }, + { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) }, + { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) }, + { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) }, + { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) }, + { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) }, + { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) }, + { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RX[] = { + { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) }, + { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) }, + { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) }, + { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) }, + { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) }, + { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) }, + { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) }, + { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_CTS[] = { + { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) }, + { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) }, + { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) }, + { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) }, + { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) }, + { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) }, + { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) }, + { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RTS[] = { + { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) }, + { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) }, + { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) }, + { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) }, + { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) }, + { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) }, + { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) }, + { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) }, + { NC, NC, 0 } +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) }, + { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) }, + { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P6_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_MOSI[] = { + { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) }, + { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) }, + { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P6_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_MISO[] = { + { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) }, + { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) }, + { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { P6_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_SSEL[] = { + { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) }, + { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) }, + { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) }, + { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) }, + { P6_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) }, + { NC, NC, 0 } +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, { P8_0, PWM_0, 1 }, + { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P6_1, PWM_1, 1 }, { P8_1, PWM_1, 1 }, + { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P6_2, PWM_2, 1 }, + { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P6_3, PWM_3, 1 }, + { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P6_4, PWM_4, 1 }, + { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P6_5, PWM_5, 1 }, + { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P6_6, PWM_6, 1 }, + { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P6_7, PWM_7, 1 }, + { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P7_0, PWM_8, 1 }, + { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P7_1, PWM_9, 1 }, + { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P7_2, PWM_10, 1 }, + { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P7_3, PWM_11, 1 }, + { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P7_4, PWM_12, 1 }, + { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P7_5, PWM_13, 1 }, + { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P7_6, PWM_14, 1 }, + { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P7_7, PWM_15, 1 }, + { NC, NC, 0 } +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + { AIN_0, ADC, ADC_CH_0 }, + { AIN_1, ADC, ADC_CH_1 }, + { AIN_2, ADC, ADC_CH_2 }, + { AIN_3, ADC, ADC_CH_3 }, + { AIN_4, ADC, ADC_CH_0_DIV_5 }, + { AIN_5, ADC, ADC_CH_1_DIV_5 }, + { AIN_6, ADC, ADC_CH_VDDB_DIV_4 }, + { AIN_7, ADC, ADC_CH_VDD18 }, + { AIN_8, ADC, ADC_CH_VDD12 }, + { AIN_9, ADC, ADC_CH_VRTC_DIV_2 }, + { NC, NC, 0 } +}; diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.h b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.h new file mode 100644 index 00000000000..66b40c1fc2c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.h @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" + +//************I2C*************** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//************UART*************** +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +//************SPI*************** +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +//************PWM*************** +extern const PinMap PinMap_PWM[]; + +//************ADC*************** +extern const PinMap PinMap_ADC[]; +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/PortNames.h b/targets/TARGET_Maxim/TARGET_MAX32630/PortNames.h new file mode 100644 index 00000000000..cdb32107f43 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/PortNames.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1, + Port2, + Port3, + Port4, + Port5, + Port6, + Port7, + Port8, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PeripheralNames.h new file mode 100644 index 00000000000..9d4d4a687b0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PeripheralNames.h @@ -0,0 +1,90 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1, + UART_2 = MXC_BASE_UART2, + UART_3 = MXC_BASE_UART3, + STDIO_UART = UART_1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1, + I2C_2 = MXC_BASE_I2CM2 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPIM0, + SPI_1 = MXC_BASE_SPIM1, + SPI_2 = MXC_BASE_SPIM2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7, + PWM_8 = MXC_BASE_PT8, + PWM_9 = MXC_BASE_PT9, + PWM_10 = MXC_BASE_PT10, + PWM_11 = MXC_BASE_PT11, + PWM_12 = MXC_BASE_PT12, + PWM_13 = MXC_BASE_PT13, + PWM_14 = MXC_BASE_PT14, + PWM_15 = MXC_BASE_PT15 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h new file mode 100644 index 00000000000..4367d80430b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h @@ -0,0 +1,180 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, + PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +#define NOT_CONNECTED (int)0xFFFFFFFF + +typedef enum { + P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, + P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, + P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, + P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, + P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, + P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, + P6_0 = (6 << PORT_SHIFT), P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, + P7_0 = (7 << PORT_SHIFT), P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, + P8_0 = (8 << PORT_SHIFT), P8_1, + + // Analog input pins + AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, + + // LEDs + LED_RED = P2_4, + LED_GREEN = P2_5, + LED_BLUE = P2_6, + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = NOT_CONNECTED, + + // Push button + SW1 = P2_3, + SW2 = NOT_CONNECTED, + SW3 = NOT_CONNECTED, + + // USB bridge connected UART pins + USBTX = P2_1, + USBRX = P2_0, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + + // I2C pins + I2C0_SCL = NOT_CONNECTED, + I2C0_SDA = NOT_CONNECTED, + + I2C1_SCL = P3_5, + I2C1_SDA = P3_4, + + I2C2_SCL = P6_0, + I2C2_SDA = P5_7, + + // UART pins + UART0_RX = P0_0, + UART0_TX = P0_1, + UART0_CTS = P0_2, + UART0_RTS = P0_3, + + UART1_RX = P2_0, + UART1_TX = P2_1, + UART1_CTS = NOT_CONNECTED, + UART1_RTS = NOT_CONNECTED, + + UART2_RX = P3_0, + UART2_TX = P3_1, + UART2_CTS = P3_2, + UART2_RTS = P3_3, + + UART3_RX = P5_3, + UART3_TX = P5_4, + UART3_CTS = P5_5, + UART3_RTS = P5_6, + + // SPI pins + SPI0_SCK = P0_4, + SPI0_MOSI = P0_5, + SPI0_MISO = P0_6, + SPI0_SS = P0_7, + + SPI1_SCK = P1_0, + SPI1_MOSI = P1_1, + SPI1_MISO = P1_2, + SPI1_SS = P1_3, + SPI1_DIO2 = P1_4, + SPI1_DIO3 = P1_5, + + SPI2_SCK = P5_0, + SPI2_MOSI = P5_1, + SPI2_MISO = P5_2, + SPI2_SS = P5_3, + SPI2_SDIO2 = P5_4, + SPI2_SDIO3 = P5_5, + SPI2_SRN = P5_6, + + // 1-Wire Master + OWM = P4_0, + + // BTLE Module hardwired + BT_RST = P1_6, + BT_CLK = P1_7, + + // MAX14690N hardwired + PMIC_INT = P3_7, + MPC = P2_7, + MON = AIN_0, + + // BMI160 hardwired + IMU_INT = P3_6, + + // microSD hardwired + DETECT = P2_2, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullUp, + PullDown, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/low_level_init.c b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/low_level_init.c new file mode 100644 index 00000000000..b9fd647da5a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/low_level_init.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis.h" +#include "i2cm_regs.h" +#include "ioman_regs.h" +#include "clkman_regs.h" + +//****************************************************************************** +// This function will get called early in system initialization +void low_level_init(void) +{ + /* The MAX32630FTHR board utilizes the MAX14690N PMIC which has the 3.3V + * LDO supplying the VDDB and VDDIOH disabled by default. USB cannot + * be initialized until this regulator is enabled. This code enables + * the regulator early in the process so that the system does not hang + * if USB is configured before the PMIC is configured in user code. + */ + MXC_CLKMAN->sys_clk_ctrl_9_i2cm = 1; // source clock for I2C + MXC_CLKMAN->i2c_timer_ctrl = 1; // enable timer for timeouts + MXC_IOMAN->i2cm2_req = 0x10; // Request mode A + // Configure clock divider for 96MHz (worst case) + MXC_I2CM2->fs_clk_div =((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)); + + // Reset module + MXC_I2CM2->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + MXC_I2CM2->ctrl = 0; + + // Enable tx_fifo and rx_fifo + MXC_I2CM2->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); + + // Disable and clear the interrupts + MXC_I2CM2->inten = 0; + MXC_I2CM2->intfl = MXC_I2CM2->intfl; + + // Write the address to the TXFIFO + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address + + // Start the transaction + MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START; + + // Load write data into the FIFO + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x15); // ldo2vset register addresss + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x19); // 3.3V + // Send the stop condition + MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP; + + // Wait for first write to complete + while (MXC_I2CM2->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS); + + // Write the address to the TXFIFO + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address + + // Start the transaction + MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START; + + // Load write data into the FIFO + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x14); // ldo2cfg register address + MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x02); // ldo enabled + // Send the stop condition + MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c new file mode 100644 index 00000000000..560d535314f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "adc.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#define ADC_FULL_SCALE 0x3FFU +#define INT_FULL_SCALE 0xFFFFU +#define FLOAT_FULL_SCALE 1.0f + +static int initialized = 0; + +//****************************************************************************** +void analogin_init(analogin_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC); + + // Set the object pointer and channel encoding + obj->adc = MXC_ADC; + obj->channel = pinmap_find_function(pin, PinMap_ADC); + + if (!initialized) { + MBED_ASSERT(ADC_Init() == E_NO_ERROR); + initialized = 1; + } +} + +//****************************************************************************** +float analogin_read(analogin_t *obj) +{ + uint16_t tmp; + float result; + + // Start conversion with no input scaling and no input buffer bypass + ADC_StartConvert(obj->channel, 1, 0); + + if (ADC_GetData(&tmp) == E_OVERFLOW) { + result = FLOAT_FULL_SCALE; + } else { + result = (float)tmp * (FLOAT_FULL_SCALE / (float)ADC_FULL_SCALE); + } + + return result; +} + +//****************************************************************************** +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t tmp; + uint16_t result; + + // Start conversion with no input scaling and no input buffer bypass + ADC_StartConvert(obj->channel, 1, 0); + + if (ADC_GetData(&tmp) == E_OVERFLOW) { + result = INT_FULL_SCALE; + } else { + result = ((tmp << 6) & 0xFFC0) | ((tmp >> 4) & 0x003F); + } + + return result; +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device.h b/targets/TARGET_Maxim/TARGET_MAX32630/device.h new file mode 100644 index 00000000000..3463dfe3f94 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/MAX3263x.sct b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/MAX3263x.sct new file mode 100644 index 00000000000..59f465a389b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/MAX3263x.sct @@ -0,0 +1,16 @@ +; MAX3263x +; 2MB FLASH (0x200000) @ 0x000000000 +; 512KB RAM (0x80000) @ 0x20000000 + +LR_IROM1 0x000000000 0x200000 { ; load region size_region + ER_IROM1 0x000000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) + RW_IRAM1 (0x20000000+0x110) (0x80000-0x110) { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S new file mode 100644 index 00000000000..a083d4dd4c5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S @@ -0,0 +1,297 @@ +;******************************************************************************* +; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + +__initial_sp EQU 0x20080000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Maxim MAX3263x external interrupts + DCD CLKMAN_IRQHandler ; 16:01 CLKMAN + DCD PWRMAN_IRQHandler ; 17:02 PWRMAN + DCD FLC_IRQHandler ; 18:03 Flash Controller + DCD RTC0_IRQHandler ; 19:04 RTC INT0 + DCD RTC1_IRQHandler ; 20:05 RTC INT1 + DCD RTC2_IRQHandler ; 21:06 RTC INT2 + DCD RTC3_IRQHandler ; 22:07 RTC INT3 + DCD PMU_IRQHandler ; 23:08 PMU + DCD USB_IRQHandler ; 24:09 USB + DCD AES_IRQHandler ; 25:10 AES + DCD MAA_IRQHandler ; 26:11 MAA + DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 + DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW + DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 + DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW + DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 + DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 + DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 + DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 + DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 + DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 + DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 + DCD TMR0_IRQHandler ; 38:23 Timer32-0 + DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 + DCD TMR1_IRQHandler ; 40:25 Timer32-1 + DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 + DCD TMR2_IRQHandler ; 42:27 Timer32-2 + DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 + DCD TMR3_IRQHandler ; 44:29 Timer32-3 + DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 + DCD TMR4_IRQHandler ; 46:31 Timer32-4 + DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 + DCD TMR5_IRQHandler ; 48:33 Timer32-5 + DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 + DCD PT_IRQHandler ; 50:35 PT + DCD UART0_IRQHandler ; 51:36 UART0 + DCD UART1_IRQHandler ; 52:37 UART1 + DCD UART2_IRQHandler ; 53:38 UART0 + DCD UART3_IRQHandler ; 54:39 UART1 + DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 + DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 + DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 + DCD I2CS_IRQHandler ; 58:43 I2C Slave + DCD SPIM0_IRQHandler ; 59:44 SPIM0 + DCD SPIM1_IRQHandler ; 60:45 SPIM1 + DCD SPIM2_IRQHandler ; 61:46 SPIM2 + DCD SPIB_IRQHandler ; 62:47 SPI Bridge + DCD OWM_IRQHandler ; 63:48 SPI Bridge + DCD AFE_IRQHandler ; 64:49 AFE + DCD SPIS_IRQHandler ; 65:50 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + IMPORT PreInit + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 +__SPIN + WFI + BL __SPIN + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Handler + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B MemManage_Handler + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B BusFault_Handler + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B UsageFault_Handler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B SVC_Handler + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B DebugMon_Handler + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B PendSV_Handler + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B SysTick_Handler + ENDP + +Default_Handler PROC + + ; MAX3263x interrupts + EXPORT CLKMAN_IRQHandler [WEAK] ; 16:01 CLKMAN + EXPORT PWRMAN_IRQHandler [WEAK] ; 17:02 PWRMAN + EXPORT FLC_IRQHandler [WEAK] ; 18:03 Flash Controller + EXPORT RTC0_IRQHandler [WEAK] ; 19:04 RTC INT0 + EXPORT RTC1_IRQHandler [WEAK] ; 20:05 RTC INT1 + EXPORT RTC2_IRQHandler [WEAK] ; 21:06 RTC INT2 + EXPORT RTC3_IRQHandler [WEAK] ; 22:07 RTC INT3 + EXPORT PMU_IRQHandler [WEAK] ; 23:08 PMU + EXPORT USB_IRQHandler [WEAK] ; 24:09 USB + EXPORT AES_IRQHandler [WEAK] ; 25:10 AES + EXPORT MAA_IRQHandler [WEAK] ; 26:11 MAA + EXPORT WDT0_IRQHandler [WEAK] ; 27:12 WATCHDOG0 + EXPORT WDT0_P_IRQHandler [WEAK] ; 28:13 WATCHDOG0 PRE-WINDOW + EXPORT WDT1_IRQHandler [WEAK] ; 29:14 WATCHDOG1 + EXPORT WDT1_P_IRQHandler [WEAK] ; 30:15 WATCHDOG1 PRE-WINDOW + EXPORT GPIO_P0_IRQHandler [WEAK] ; 31:16 GPIO Port 0 + EXPORT GPIO_P1_IRQHandler [WEAK] ; 32:17 GPIO Port 1 + EXPORT GPIO_P2_IRQHandler [WEAK] ; 33:18 GPIO Port 2 + EXPORT GPIO_P3_IRQHandler [WEAK] ; 34:19 GPIO Port 3 + EXPORT GPIO_P4_IRQHandler [WEAK] ; 35:20 GPIO Port 4 + EXPORT GPIO_P5_IRQHandler [WEAK] ; 36:21 GPIO Port 5 + EXPORT GPIO_P6_IRQHandler [WEAK] ; 37:22 GPIO Port 6 + EXPORT TMR0_IRQHandler [WEAK] ; 38:23 Timer32-0 + EXPORT TMR16_0_IRQHandler [WEAK] ; 39:24 Timer16-s0 + EXPORT TMR1_IRQHandler [WEAK] ; 40:25 Timer32-1 + EXPORT TMR16_1_IRQHandler [WEAK] ; 41:26 Timer16-s1 + EXPORT TMR2_IRQHandler [WEAK] ; 42:27 Timer32-2 + EXPORT TMR16_2_IRQHandler [WEAK] ; 43:28 Timer16-s2 + EXPORT TMR3_IRQHandler [WEAK] ; 44:29 Timer32-3 + EXPORT TMR16_3_IRQHandler [WEAK] ; 45:30 Timer16-s3 + EXPORT TMR4_IRQHandler [WEAK] ; 46:31 Timer32-4 + EXPORT TMR16_4_IRQHandler [WEAK] ; 47:32 Timer16-s4 + EXPORT TMR5_IRQHandler [WEAK] ; 48:33 Timer32-5 + EXPORT TMR16_5_IRQHandler [WEAK] ; 49:34 Timer16-s5 + EXPORT PT_IRQHandler [WEAK] ; 50:35 PT + EXPORT UART0_IRQHandler [WEAK] ; 51:36 UART0 + EXPORT UART1_IRQHandler [WEAK] ; 52:37 UART1 + EXPORT UART2_IRQHandler [WEAK] ; 53:38 UART0 + EXPORT UART3_IRQHandler [WEAK] ; 54:39 UART1 + EXPORT I2CM0_IRQHandler [WEAK] ; 55:40 I2C Master 0 + EXPORT I2CM1_IRQHandler [WEAK] ; 56:41 I2C Master 1 + EXPORT I2CM2_IRQHandler [WEAK] ; 57:42 I2C Master 2 + EXPORT I2CS_IRQHandler [WEAK] ; 58:43 I2C Slave + EXPORT SPIM0_IRQHandler [WEAK] ; 59:44 SPIM0 + EXPORT SPIM1_IRQHandler [WEAK] ; 60:45 SPIM1 + EXPORT SPIM2_IRQHandler [WEAK] ; 61:46 SPIM2 + EXPORT SPIB_IRQHandler [WEAK] ; 62:47 SPI Bridge + EXPORT OWM_IRQHandler [WEAK] ; 63:48 SPI Bridge + EXPORT AFE_IRQHandler [WEAK] ; 64:49 AFE + EXPORT SPIS_IRQHandler [WEAK] ; 65:50 SPI Slave + EXPORT GPIO_P7_IRQHandler [WEAK] ; 66:51 GPIO Port 7 + EXPORT GPIO_P8_IRQHandler [WEAK] ; 67:52 GPIO Port 8 + +CLKMAN_IRQHandler +PWRMAN_IRQHandler +FLC_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +PMU_IRQHandler +USB_IRQHandler +AES_IRQHandler +MAA_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +TMR0_IRQHandler +TMR16_0_IRQHandler +TMR1_IRQHandler +TMR16_1_IRQHandler +TMR2_IRQHandler +TMR16_2_IRQHandler +TMR3_IRQHandler +TMR16_3_IRQHandler +TMR4_IRQHandler +TMR16_4_IRQHandler +TMR5_IRQHandler +TMR16_5_IRQHandler +PT_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +I2CM0_IRQHandler +I2CM1_IRQHandler +I2CM2_IRQHandler +I2CS_IRQHandler +SPIM0_IRQHandler +SPIM1_IRQHandler +SPIM2_IRQHandler +SPIB_IRQHandler +OWM_IRQHandler +AFE_IRQHandler +SPIS_IRQHandler +GPIO_P7_IRQHandler +GPIO_P8_IRQHandler + + B . + ENDP + ALIGN + END diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..b6c24b38364 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld new file mode 100644 index 00000000000..b3db5d6ce60 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld @@ -0,0 +1,176 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00200000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/startup_max3263x.S b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/startup_max3263x.S new file mode 100644 index 00000000000..b22de39a572 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/startup_max3263x.S @@ -0,0 +1,303 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00005000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x0000A000 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* MAX3263X Interrupts */ + .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ + .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ + .long FLC_IRQHandler /* 18:03 Flash Controller */ + .long RTC0_IRQHandler /* 19:04 RTC INT0 */ + .long RTC1_IRQHandler /* 20:05 RTC INT1 */ + .long RTC2_IRQHandler /* 21:06 RTC INT2 */ + .long RTC3_IRQHandler /* 22:07 RTC INT3 */ + .long PMU_IRQHandler /* 23:08 PMU */ + .long USB_IRQHandler /* 24:09 USB */ + .long AES_IRQHandler /* 25:10 AES */ + .long MAA_IRQHandler /* 26:11 MAA */ + .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + .long TMR0_IRQHandler /* 38:23 Timer32-0 */ + .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + .long TMR1_IRQHandler /* 40:25 Timer32-1 */ + .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + .long TMR2_IRQHandler /* 42:27 Timer32-2 */ + .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + .long TMR3_IRQHandler /* 44:29 Timer32-3 */ + .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + .long TMR4_IRQHandler /* 46:31 Timer32-4 */ + .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + .long TMR5_IRQHandler /* 48:33 Timer32-5 */ + .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + .long UART0_IRQHandler /* 50:35 UART0 */ + .long UART1_IRQHandler /* 51:36 UART1 */ + .long UART2_IRQHandler /* 52:37 UART2 */ + .long UART3_IRQHandler /* 53:38 UART3 */ + .long PT_IRQHandler /* 54:39 PT */ + .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + .long I2CS_IRQHandler /* 58:43 I2C Slave */ + .long SPIM0_IRQHandler /* 59:44 SPIM0 */ + .long SPIM1_IRQHandler /* 60:45 SPIM1 */ + .long SPIM2_IRQHandler /* 61:46 SPIM2 */ + .long SPIB_IRQHandler /* 62:47 SPI Bridge */ + .long OWM_IRQHandler /* 63:48 One-wire Master */ + .long AFE_IRQHandler /* 64:49 AFE */ + .long SPIS_IRQHandler /* 65:50 SPI Slave */ + .long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + .long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =__StackTop + mov sp, r0 + + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ + ldr r0, =PreInit + blx r0 + cbnz r0, .SKIPRAMINIT + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * _data /_edata: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 0 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +/* + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * _bss : start of BSS section. Must align to 4 + * _ebss : end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 + +.SKIPRAMINIT: + + /* Perform system initialization after RAM initialization */ + ldr r0, =SystemInit + blx r0 + + /* This must be called to walk the constructor array for static C++ objects */ + /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */ + /* where X is {preinit, init, fini} */ + ldr r0, =_start + blx r0 + +.SPIN: + /* Enter LP2 if main() ever returns. */ + wfi + bl .SPIN + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + /* MAX3263X Interrupts */ + def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ + def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ + def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */ + def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ + def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ + def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ + def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ + def_irq_handler PMU_IRQHandler /* 23:08 PMU */ + def_irq_handler USB_IRQHandler /* 24:09 USB */ + def_irq_handler AES_IRQHandler /* 25:10 AES */ + def_irq_handler MAA_IRQHandler /* 26:11 MAA */ + def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ + def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ + def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ + def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ + def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ + def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ + def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + def_irq_handler PT_IRQHandler /* 50:35 PT */ + def_irq_handler UART0_IRQHandler /* 51:36 UART0 */ + def_irq_handler UART1_IRQHandler /* 52:37 UART1 */ + def_irq_handler UART2_IRQHandler /* 53:38 UART0 */ + def_irq_handler UART3_IRQHandler /* 54:39 UART1 */ + def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */ + def_irq_handler SPIM0_IRQHandler /* 59:44 SPIM0 */ + def_irq_handler SPIM1_IRQHandler /* 60:45 SPIM1 */ + def_irq_handler SPIM2_IRQHandler /* 61:46 SPIM2 */ + def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ + def_irq_handler OWM_IRQHandler /* 63:48 SPI Bridge */ + def_irq_handler AFE_IRQHandler /* 64:49 AFE */ + def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */ + def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + .end diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/MAX3263x.icf b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/MAX3263x.icf new file mode 100644 index 00000000000..7cb8fbadc99 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/MAX3263x.icf @@ -0,0 +1,29 @@ +/* [ROM] */ +define symbol __intvec_start__ = 0x00000000; +define symbol __region_ROM_start__ = 0x00000000; +define symbol __region_ROM_end__ = 0x001FFFFF; + +/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */ +define symbol __NVIC_start__ = 0x00000000; +define symbol __NVIC_end__ = 0x00000110; /* to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000000; +define symbol __region_RAM_end__ = 0x2007FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x5000; +define symbol __size_heap__ = 0xA000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/startup_MAX3263x.S b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/startup_MAX3263x.S new file mode 100644 index 00000000000..094d4517e34 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/startup_MAX3263x.S @@ -0,0 +1,450 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN PreInit + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_modify + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_modify + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; MAX3263x Specific Interrupts + DCD CLKMAN_IRQHandler ; 16:01 CLKMAN */ + DCD PWRMAN_IRQHandler ; 17:02 PWRMAN */ + DCD FLC_IRQHandler ; 18:03 Flash Controller */ + DCD RTC0_IRQHandler ; 19:04 RTC INT0 */ + DCD RTC1_IRQHandler ; 20:05 RTC INT1 */ + DCD RTC2_IRQHandler ; 21:06 RTC INT2 */ + DCD RTC3_IRQHandler ; 22:07 RTC INT3 */ + DCD PMU_IRQHandler ; 23:08 PMU */ + DCD USB_IRQHandler ; 24:09 USB */ + DCD AES_IRQHandler ; 25:10 AES */ + DCD MAA_IRQHandler ; 26:11 MAA */ + DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 */ + DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 */ + DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 */ + DCD TMR0_IRQHandler ; 38:23 Timer32-0 */ + DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 */ + DCD TMR1_IRQHandler ; 40:25 Timer32-1 */ + DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 */ + DCD TMR2_IRQHandler ; 42:27 Timer32-2 */ + DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 */ + DCD TMR3_IRQHandler ; 44:29 Timer32-3 */ + DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 */ + DCD TMR4_IRQHandler ; 46:31 Timer32-4 */ + DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 */ + DCD TMR5_IRQHandler ; 48:33 Timer32-5 */ + DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 */ + DCD UART0_IRQHandler ; 50:35 UART0 */ + DCD UART1_IRQHandler ; 51:36 UART1 */ + DCD UART2_IRQHandler ; 52:37 UART2 */ + DCD UART3_IRQHandler ; 53:38 UART3 */ + DCD PT_IRQHandler ; 54:39 PT */ + DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 */ + DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 */ + DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 */ + DCD I2CS_IRQHandler ; 58:43 I2C Slave */ + DCD SPIM0_IRQHandler ; 59:44 SPI Master 0 */ + DCD SPIM1_IRQHandler ; 60:45 SPI Master 1 */ + DCD SPIM2_IRQHandler ; 61:46 SPI Master 2 */ + DCD SPIB_IRQHandler ; 62:47 SPI Bridge */ + DCD OWM_IRQHandler ; 63:48 One-wire Master */ + DCD AFE_IRQHandler ; 64:49 AFE */ + DCD SPIS_IRQHandler ; 65:50 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK CLKMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLKMAN_IRQHandler + B CLKMAN_IRQHandler + + PUBWEAK PWRMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWRMAN_IRQHandler + B PWRMAN_IRQHandler + + PUBWEAK FLC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B RTC0_IRQHandler + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B RTC1_IRQHandler + + PUBWEAK RTC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC2_IRQHandler + B RTC2_IRQHandler + + PUBWEAK RTC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC3_IRQHandler + B RTC3_IRQHandler + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PMU_IRQHandler + B PMU_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK MAA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MAA_IRQHandler + B MAA_IRQHandler + + PUBWEAK WDT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK WDT0_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_P_IRQHandler + B WDT0_P_IRQHandler + + PUBWEAK WDT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_IRQHandler + B WDT1_IRQHandler + + PUBWEAK WDT1_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_P_IRQHandler + B WDT1_P_IRQHandler + + PUBWEAK GPIO_P0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P0_IRQHandler + B GPIO_P0_IRQHandler + + PUBWEAK GPIO_P1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P1_IRQHandler + B GPIO_P1_IRQHandler + + PUBWEAK GPIO_P2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P2_IRQHandler + B GPIO_P2_IRQHandler + + PUBWEAK GPIO_P3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P3_IRQHandler + B GPIO_P3_IRQHandler + + PUBWEAK GPIO_P4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P4_IRQHandler + B GPIO_P4_IRQHandler + + PUBWEAK GPIO_P5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P5_IRQHandler + B GPIO_P5_IRQHandler + + PUBWEAK GPIO_P6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P6_IRQHandler + B GPIO_P6_IRQHandler + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR16_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_0_IRQHandler + B TMR16_0_IRQHandler + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR16_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_1_IRQHandler + B TMR16_1_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR16_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_2_IRQHandler + B TMR16_2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR16_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_3_IRQHandler + B TMR16_3_IRQHandler + + PUBWEAK TMR4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR4_IRQHandler + B TMR4_IRQHandler + + PUBWEAK TMR16_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_4_IRQHandler + B TMR16_4_IRQHandler + + PUBWEAK TMR5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR5_IRQHandler + B TMR5_IRQHandler + + PUBWEAK TMR16_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_5_IRQHandler + B TMR16_5_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK PT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PT_IRQHandler + B PT_IRQHandler + + PUBWEAK I2CM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM0_IRQHandler + B I2CM0_IRQHandler + + PUBWEAK I2CM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM1_IRQHandler + B I2CM1_IRQHandler + + PUBWEAK I2CM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM2_IRQHandler + B I2CM2_IRQHandler + + PUBWEAK I2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CS_IRQHandler + B I2CS_IRQHandler + + PUBWEAK SPIM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM0_IRQHandler + B SPIM0_IRQHandler + + PUBWEAK SPIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM1_IRQHandler + B SPIM1_IRQHandler + + PUBWEAK SPIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM2_IRQHandler + B SPIM2_IRQHandler + + PUBWEAK SPIB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIB_IRQHandler + B SPIB_IRQHandler + + PUBWEAK OWM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OWM_IRQHandler + B OWM_IRQHandler + + PUBWEAK AFE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AFE_IRQHandler + B AFE_IRQHandler + + PUBWEAK SPIS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS_IRQHandler + B SPIS_IRQHandler + + PUBWEAK GPIO_P7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P7_IRQHandler + B GPIO_P7_IRQHandler + + PUBWEAK GPIO_P8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P8_IRQHandler + B GPIO_P8_IRQHandler + END diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h new file mode 100644 index 00000000000..2edc70edb1a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h @@ -0,0 +1,393 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-30 19:43:43 -0500 (Fri, 30 Sep 2016) $ + * $Revision: 24540 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ADC_REGS_H_ +#define _MXC_ADC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup adc + * @defgroup adc_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. + */ + +/** + * @ingroup adc_registers + * Structure type to access the ADC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: ADC CTRL Register */ + __IO uint32_t status; /**< \b 0x004: ADC STATUS Register */ + __IO uint32_t data; /**< \b 0x008: ADC DATA Register */ + __IO uint32_t intr; /**< \b 0x00C: ADC INTR Register */ + __IO uint32_t limit[4]; /**< \b 0x010: ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */ + __IO uint32_t afe_ctrl; /**< \b 0x020: ADC AFE_CTRL Register */ + __IO uint32_t ro_cal0; /**< \b 0x024: ADC RO_CAL0 Register */ + __IO uint32_t ro_cal1; /**< \b 0x028: ADC RO_CAL1 Register */ + __IO uint32_t ro_cal2; /**< \b 0x02C: ADC RO_CAL2 Register */ +} mxc_adc_regs_t; + + +/* Register offsets for module ADC. */ +/** + * @ingroup adc_registers + * @defgroup ADC_Register_Offsets Register Offsets + * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. + * @{ + */ +#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: \b 0x000 */ +#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: \b 0x004 */ +#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: \b 0x008 */ +#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: \b 0x00C */ +#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: \b 0x010 */ +#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: \b 0x014 */ +#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: \b 0x018 */ +#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: \b 0x01C */ +#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: \b 0x020 */ +#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: \b 0x024 */ +#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: \b 0x028 */ +#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: \b 0x02C */ +/**@} end of group adc_registers */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CTRL_Register ADC_CTRL + * @brief Field Positions and Bit Masks for the ADC_CTRL register + * @{ + */ +#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */ +#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */ +#define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */ +#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */ +#define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */ +#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */ +#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */ +#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */ +#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */ +#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */ +#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */ +#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */ +#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */ +#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */ +#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */ +#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */ +#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */ +#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */ +#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */ +#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */ +#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */ +#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */ +#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */ +#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */ +#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */ +#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */ + +#if (MXC_ADC_REV == 0) +#define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */ +#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */ +#endif +#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */ +#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */ +#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */ +#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */ + +/**@} end of group adc_ctrl_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_STATUS_Register ADC_STATUS + * @brief Field Positions and Bit Masks for the ADC_STATUS register + * @{ + */ +#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */ +#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */ +#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */ +#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */ +#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */ +#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */ +#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */ +#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */ +/**@} end of group ADC_STATUS_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_DATA_Register ADC_DATA + * @brief Field Positions and Bit Masks for the ADC_DATA register + * @{ + */ +#define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */ +#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */ +/**@} end of group ADC_DATA_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_INTR_Register ADC_INTR Register + * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks + */ +/** + * @ingroup ADC_INTR_Register + * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits + * @brief Interrupt Enable Bit Positions and Masks + * @{ + */ +#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */ +#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */ +#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */ +#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */ +#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */ +#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */ +#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */ +#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */ +#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */ +#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */ +#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */ +#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */ +/**@} end of group ADC_INTR_IE_Register */ + + +/** + * @ingroup ADC_INTR_Register + * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits + * @brief Interrupt Flag Bit Positions and Masks + * @{ + */ +#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */ +#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */ +#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */ +#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */ +#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */ +#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */ +#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */ +#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */ +#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */ +#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */ +#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */ +#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */ +#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */ +#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */ +/**@} end of group ADC_INTR_IF_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_LIMIT0_Register ADC_LIMIT0 + * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register + * @{ + */ +#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ +#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ +#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ +#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ +#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */ +#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */ +#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ +#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ +/**@} end of group ADC_LIMIT0_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_LIMIT1_Register ADC_LIMIT1 + * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register + * @{ + */ +#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ +#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ +#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ +#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ +#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */ +#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */ +#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ +#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ +/**@} end of group ADC_LIMIT1_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_LIMIT2_Register ADC_LIMIT2 + * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register + * @{ + */ +#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ +#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ +#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ +#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ +#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */ +#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */ +#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ +#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ +/**@} end of group ADC_LIMIT2_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_LIMIT3_Register ADC_LIMIT3 + * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register + * @{ + */ +#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ +#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ +#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ +#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ +#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */ +#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */ +#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ +#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ +/**@} end of group ADC_LIMIT3_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL + * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register + * @{ + */ +#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */ +#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */ +#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */ +#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */ +/**@} end of group ADC_AFE_CTRL_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0 + * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register + * @{ + */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */ +#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */ +#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */ +#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */ +#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */ +#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */ +#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */ +#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */ +/**@} end of group ADC_RO_CAL0_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1 + * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register + * @{ + */ +#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */ +#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */ +#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */ +#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */ +#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */ +#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */ +/**@} end of group RO_CAL1_register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2 + * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register + * @{ + */ +#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */ +#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */ +/**@} end of group RO_CAL2_register */ + +/** + * @ingroup ADC_CTRL_Register + * @defgroup ADC_CHSEL_values ADC Channel Select Values + * @brief Channel Select Values + * @{ + */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */ + +#if(MXC_ADC_REV > 0) +#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */ +#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */ +#endif +/**@} end of group ADC_CHSEL_values */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_ADC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h new file mode 100644 index 00000000000..161da812cd5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h @@ -0,0 +1,188 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24655 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_AES_REGS_H_ +#define _MXC_AES_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* **** Includes **** */ +#include + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aes + * @defgroup aes_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @{ + */ + +/** + * Structure type to access the AES Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: AES_CTRL Register */ + __RO uint32_t rsv004; /**< \b 0x0004: RESERVED */ + __IO uint32_t erase_all; /**< \b 0x0008: AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */ +} mxc_aes_regs_t; + +/** + * Structure type to access the AES Memory Registers. + */ +typedef struct { + __IO uint32_t inp[4]; /**< \b 0x0000-0x000C: AES Input (128 bits) */ + __IO uint32_t key[8]; /**< \b 0x0010-0x002C: AES Symmetric Key (up to 256 bits) */ + __IO uint32_t out[4]; /**< \b 0x0030-0x003C: AES Output Data (128 bits) */ + __IO uint32_t expkey[8]; /**< \b 0x0040-0x005C: AES Expanded Key Data (256 bits) */ +} mxc_aes_mem_regs_t; +/**@} end of group aes_registers */ + + /** + * @ingroup aes_registers + * @defgroup AES_Register_Offsets Register Offsets + * @brief AES Register Offsets from the AES Base Peripheral Address. + * @{ + */ +/** + * AES Register offsets from the AES base peripheral address. + */ +#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: \b 0x0000 */ +#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: \b 0x0008 */ +#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: \b 0x0000 */ +#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: \b 0x0004 */ +#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: \b 0x0008 */ +#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: \b 0x000C */ +#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: \b 0x0010 */ +#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: \b 0x0014 */ +#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: \b 0x0018 */ +#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: \b 0x001C */ +#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: \b 0x0020 */ +#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: \b 0x0024 */ +#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: \b 0x0028 */ +#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: \b 0x002C */ +#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: \b 0x0030 */ +#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: \b 0x0034 */ +#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: \b 0x0038 */ +#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: \b 0x003C */ +#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: \b 0x0040 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: \b 0x0044 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: \b 0x0048 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: \b 0x004C */ +#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: \b 0x0050 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: \b 0x0054 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: \b 0x0058 */ +#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: \b 0x005C */ +/**@} end of group AES_Register_Offsets */ + +/** + * @ingroup aes_registers + * @defgroup AES_CTRL_Register AES_CTRL + * @brief Field Positions and Bit Masks for the AES_CTRL register + * @{ + */ +#define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */ +#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */ +#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */ +#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */ +#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */ +#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */ +#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */ +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */ +#define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */ +#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */ +#define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */ +#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */ +#define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */ +#define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */ +/**@} end of aes_registers group */ + +/* + Field values and shifted values for module AES. +*/ +///@cond +#define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */ +#define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */ + +#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/ +#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/ + +#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */ +#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */ + +#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/ +#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/ + +#define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */ +#define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */ +#define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */ + +#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */ +///@endcond +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_AES_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h new file mode 100644 index 00000000000..613a5c9f334 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h @@ -0,0 +1,493 @@ +/** + * @file + * @brief Type definitions for the Clock Management Interface + * + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $ + * $Revision: 24058 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_CLKMAN_REGS_H_ +#define _MXC_CLKMAN_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond + +/** + * @ingroup clkman + * @defgroup clkman_registers Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ + +/** + * Structure type for the Clock Management module registers allowing direct 32-bit access to each register. + */ +typedef struct { + __IO uint32_t clk_config; /**< \b 0x0000: CLKMAN_CLK_CONFIG Register - System Clock Configuration */ + __IO uint32_t clk_ctrl; /**< \b 0x0004: CLKMAN_CLK_CTRL Register - System Clock Controls */ + __IO uint32_t intfl; /**< \b 0x0008: CLKMAN_INTFL Register - Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x000C: CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */ + __IO uint32_t trim_calc; /**< \b 0x0010: CLKMAN_TRIM_CALC Register - Trim Calculation Controls */ + __IO uint32_t i2c_timer_ctrl; /**< \b 0x0014: CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */ + __IO uint32_t cm4_start_clk_en0; /**< \b 0x0018: CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */ + __IO uint32_t cm4_start_clk_en1; /**< \b 0x001C: CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */ + __IO uint32_t cm4_start_clk_en2; /**< \b 0x0020: CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */ + __RO uint32_t rsv024[7]; /**< \b 0x0024-0x003C: RESERVED */ + __IO uint32_t sys_clk_ctrl_0_cm4; /**< \b 0x0040: CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */ + __IO uint32_t sys_clk_ctrl_1_sync; /**< \b 0x0044: CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */ + __IO uint32_t sys_clk_ctrl_2_spix; /**< \b 0x0048: CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */ + __IO uint32_t sys_clk_ctrl_3_prng; /**< \b 0x004C: CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */ + __IO uint32_t sys_clk_ctrl_4_wdt0; /**< \b 0x0050: CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */ + __IO uint32_t sys_clk_ctrl_5_wdt1; /**< \b 0x0054: CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */ + __IO uint32_t sys_clk_ctrl_6_gpio; /**< \b 0x0058: CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */ + __IO uint32_t sys_clk_ctrl_7_pt; /**< \b 0x005C: CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */ + __IO uint32_t sys_clk_ctrl_8_uart; /**< \b 0x0060: CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */ + __IO uint32_t sys_clk_ctrl_9_i2cm; /**< \b 0x0064: CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */ + __IO uint32_t sys_clk_ctrl_10_i2cs; /**< \b 0x0068: CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */ + __IO uint32_t sys_clk_ctrl_11_spi0; /**< \b 0x006C: CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */ + __IO uint32_t sys_clk_ctrl_12_spi1; /**< \b 0x0070: CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */ + __IO uint32_t sys_clk_ctrl_13_spi2; /**< \b 0x0074: CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */ + __IO uint32_t sys_clk_ctrl_14_spib; /**< \b 0x0078: CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */ + __IO uint32_t sys_clk_ctrl_15_owm; /**< \b 0x007C: CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */ + __IO uint32_t sys_clk_ctrl_16_spis; /**< \b 0x0080: CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */ + __RO uint32_t rsv084[31]; /**< \b 0x0084-0x00FC: RESERVED: */ + __IO uint32_t crypt_clk_ctrl_0_aes; /**< \b 0x0100: CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */ + __IO uint32_t crypt_clk_ctrl_1_maa; /**< \b 0x0104: CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */ + __IO uint32_t crypt_clk_ctrl_2_prng; /**< \b 0x0108: CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */ + __RO uint32_t rsv10C[13]; /**< \b 0x010C-0x013C: RESERVED */ + __IO uint32_t clk_gate_ctrl0; /**< \b 0x0140: CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */ + __IO uint32_t clk_gate_ctrl1; /**< \b 0x0144: CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */ + __IO uint32_t clk_gate_ctrl2; /**< \b 0x0148: CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */ +} mxc_clkman_regs_t; +/**@} end of clkman_registers */ + +/* + Register offsets for module CLKMAN. +*/ +/** + * @ingroup clkman_registers + * @defgroup CLKMAN_Register_Offsets Register Offsets + * @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address. + * @{ + */ +#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0000 */ +#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0004 */ +#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0008 */ +#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x000C */ +#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0010 */ +#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0014 */ +#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0018 */ +#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x001C */ +#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0020 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0040 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0044 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0048 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x004C */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0050 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0054 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0058 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x005C */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0060 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0064 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0068 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x006C */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0070 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0074 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0078 */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x007C */ +#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0080 */ +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0100 */ +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0104 */ +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0108 */ +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0140 */ +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0144 */ +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:\b 0x0148 */ +/**@} end of CLKMAN_Register_Offsets */ +/** + * @ingroup clkman_registers + * @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */ +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */ +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */ +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */ +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */ +#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */ +#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */ +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */ +#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */ +#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_int_flags CLKMAN_INTFL Register + * @brief Interrupt Flag Positions and Masks + */ +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */ +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */ +#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */ +#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_int_enable CLKMAN_INTEN Register + * @brief Interrupt Enable Positions and Masks + */ +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */ +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */ +#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */ +#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */ +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */ +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_cm4 CLKMAN_CM4 Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */ +#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */ + +#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */ +#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */ + +#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */ +#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */ +#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register + * @brief Field Positions and Masks + */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */ +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */ +/**@}*/ +/** + * @ingroup clkman_registers + * @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register + * @brief Peripheral Clock Gating Field Positions and Masks + */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */ +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */ +/**@}*/ +/** + * @ingroup clkman_clk_config + * @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings + * @brief Crypto Clock Stability Count Setting Values and Shifted Values + */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 28 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 29 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 210 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 211 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 212 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 213 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 214 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 215 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 216 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 217 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 218 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 219 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 220 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 221 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 222 */ +#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 223 */ + +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 28 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 29 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 210 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 211 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 212 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 213 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 214 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 215 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 216 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 217 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 218 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 219 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 220 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 221 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 222 */ +#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 223 */ + +/**@} clkman_crypto_stability_count */ + +/** + * @ingroup clkman_clk_ctrl + * @defgroup clkman_sysclock_select System Clock Select Values + * @brief System Clock Selection Values and Shifted Values for selecting the system clock source + * @{ + */ +#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */ +#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */ +#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */ +#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */ +/**@} end of clkman_sysclock_select group */ +///@cond + +#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL)) +#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) +#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) +#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) +#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) +#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL)) +#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) +#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) +#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) +#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) +#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) +#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL)) +#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL)) +#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) +///@endcond + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_CLKMAN_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/cmsis.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/cmsis.h new file mode 100644 index 00000000000..b979c56c1d1 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/cmsis.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max3263x.h" +#include "nvic_table.h" + +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/crc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/crc_regs.h new file mode 100644 index 00000000000..18ab8f44798 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/crc_regs.h @@ -0,0 +1,133 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24657 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_CRC_REGS_H_ +#define _MXC_CRC_REGS_H_ +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/* **** Definitions **** */ + +/** + * @ingroup crc + * @defgroup crc_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @{ + */ + +/** + * Structure type for the CRC peripheral registers for reseeding and seeding the CRC16/32 + */ +typedef struct { + __IO uint32_t reseed; /**< \b 0x0000: CRC_RESEED Register */ + __IO uint32_t seed16; /**< \b 0x0004: CRC_SEED16 Register */ + __IO uint32_t seed32; /**< \b 0x0008: CRC_SEED32 Register */ +} mxc_crc_regs_t; + +/** + * Structure type for the CRC Data Values. + */ +typedef struct { + __IO uint32_t value16[512]; /**< \b 0x0000: CRC16_DATA Register */ + __IO uint32_t value32[512]; /**< \b 0x8000: CRC32_DATA Register */ +} mxc_crc_data_regs_t; +/**@} end of group crc_registers */ + +/* Register offsets for module CRC. */ +/** + * @ingroup crc_registers + * @defgroup CRC_Register_Offsets Register Offsets + * @brief CRC Peripheral Module Register Offsets from the CRC Base Peripheral Address. + * @{ + */ +#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: \b 0x0000 */ +#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: \b 0x0004 */ +#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: \b 0x0008 */ +#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) /**< Offset from CRC DATA Base Address: \b 0x0000 */ +#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) /**< Offset from CRC DATA Base Address: \b 0x8000 */ +/**@} end of group CRC_Register_offsets */ + +/** + * @ingroup crc_registers + * @defgroup CRC_RESEED_Register CRC_RESEED + * @brief Field Positions and Bit Masks for the CRC_RESEED register + * @{ + */ +#define MXC_F_CRC_RESEED_CRC16_POS 0 /**< CRC16 Position */ +#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) /**< CRC16 Mask */ +#define MXC_F_CRC_RESEED_CRC32_POS 1 /**< CRC32 Position */ +#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) /**< CRC32 Mask */ +#define MXC_F_CRC_RESEED_REV_ENDIAN16_POS 4 /**< REV_ENDIAN16 Position */ +#define MXC_F_CRC_RESEED_REV_ENDIAN16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN16_POS)) /**< REV_ENDIAN16 Mask */ +#define MXC_F_CRC_RESEED_REV_ENDIAN32_POS 5 /**< REV_ENDIAN32 Position */ +#define MXC_F_CRC_RESEED_REV_ENDIAN32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN32_POS)) /**< REV_ENDIAN32 Mask */ +#define MXC_F_CRC_RESEED_CCITT_MODE_POS 8 /**< CCITT_MODE Position */ +#define MXC_F_CRC_RESEED_CCITT_MODE ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CCITT_MODE_POS)) /**< CCITT_MODE Mask */ +/**@} end of CRC_RESEED_Fields */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_CRC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h new file mode 100644 index 00000000000..fcfc29d5254 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h @@ -0,0 +1,395 @@ +/** + * @file + * @brief registers, bit masks and bit positions for the Flash + * Controller (FLC) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, Maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24658 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_FLC_REGS_H_ +#define _MXC_FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond +/** + * @ingroup flc + * @defgroup flc_registers Registers + * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module. + */ +/* **** Definitions **** */ +/** + * @ingroup flc_registers + * @defgroup flc_special_codes Flash Controller Codes/Keys. + * @brief Required values to pass to the flash controller to perform restricted + * operations. + * @{ + */ +#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */ +#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */ +#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */ +/**@} end of flc_special_codes */ + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/** + * @ingroup flc_registers + * @brief Structure type to access the Flash Controller registers with + * direct 32-bit access to each. + */ +typedef struct { + __IO uint32_t faddr; /**< \b 0x0000: FLC_FADDR Register - Flash Operation Address */ + __IO uint32_t fckdiv; /**< \b 0x0004: FLC_FCKDIV Register - Flash Clock Pulse Divisor */ + __IO uint32_t ctrl; /**< \b 0x0008: FLC_CTRL Register - Flash Control Register */ + __RO uint32_t rsv00C[6]; /**< \b 0x000C-0x0020: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t intr; /**< \b 0x0024: FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */ + __RO uint32_t rsv028[2]; /**< \b 0x0028-0x002C: RESERVED */ + __IO uint32_t fdata; /**< \b 0x0030: FLC_FDATA Register - Flash Operation Data Register */ + __RO uint32_t rsv034[7]; /**< \b 0x0034-0x004C: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t perform; /**< \b 0x0050: FLC_PERFORM Register - Flash Performance Settings */ + __IO uint32_t tacc; /**< \b 0x0054: FLC_TACC Register - Flash Read Cycle Config */ + __IO uint32_t tprog; /**< \b 0x0058: FLC_TPROG Register - Flash Write Cycle Config */ + __RO uint32_t rsv05C[9]; /**< \b 0x005C-0x007C: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t status; /**< \b 0x0080: FLC_STATUS Register - Security Status Flags */ + __RO uint32_t rsv084; /**< \b 0x0084: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t security; /**< \b 0x0088: FLC_SECURITY Register - Flash Controller Security Settings */ + __RO uint32_t rsv08C[4]; /**< \b 0x008C-0x0098: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t bypass; /**< \b 0x009C: FLC_BYPASS Register - Status Flags for DSB Operations */ + __RO uint32_t rsv0A0[24]; /**< \b 0x00A0-0x00FC: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t user_option; /**< \b 0x0100: FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */ + __RO uint32_t rsv104[15]; /**< \b 0x0104-0x013C: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t ctrl2; /**< \b 0x0140: FLC_CTRL2 Register - Flash Control Register 2 */ + __IO uint32_t intfl1; /**< \b 0x0144: FLC_INTFL1 Register - Interrupt Flags Register 1 */ + __IO uint32_t inten1; /**< \b 0x0148: FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */ + __RO uint32_t rsv14C[9]; /**< \b 0x014C-0x016C: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t bl_ctrl; /**< \b 0x0170: FLC_BL_CTRL Register - Bootloader Control Register */ + __IO uint32_t twk; /**< \b 0x0174: FLC_TWK Register - PDM33 Register */ + __RO uint32_t rsv178; /**< \b 0x0178: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t slm; /**< \b 0x017C: FLC_SLM Register - Sleep Mode Register */ + __RO uint32_t rsv180[32]; /**< \b 0x0180-0x01FC: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t disable_xr0; /**< \b 0x0200: FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */ + __IO uint32_t disable_xr1; /**< \b 0x0204: FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */ + __IO uint32_t disable_xr2; /**< \b 0x0208: FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */ + __IO uint32_t disable_xr3; /**< \b 0x020C: FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */ + __IO uint32_t disable_xr4; /**< \b 0x0210: FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */ + __IO uint32_t disable_xr5; /**< \b 0x0214: FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */ + __IO uint32_t disable_xr6; /**< \b 0x0218: FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */ + __IO uint32_t disable_xr7; /**< \b 0x021C: FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */ + __RO uint32_t rsv220[56]; /**< \b 0x0220-0x02FC: RESERVED \warning Do Not Modify Reserved Locations! */ + __IO uint32_t disable_we0; /**< \b 0x0300: FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */ + __IO uint32_t disable_we1; /**< \b 0x0304: FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */ + __IO uint32_t disable_we2; /**< \b 0x0308: FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */ + __IO uint32_t disable_we3; /**< \b 0x030C: FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */ + __IO uint32_t disable_we4; /**< \b 0x0310: FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */ + __IO uint32_t disable_we5; /**< \b 0x0314: FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */ + __IO uint32_t disable_we6; /**< \b 0x0318: FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */ + __IO uint32_t disable_we7; /**< \b 0x031C: FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */ +} mxc_flc_regs_t; +/* + Register offsets for module FLC. +*/ + +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address. + * @{ + */ +#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: \b 0x0000 */ +#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: \b 0x0004 */ +#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: \b 0x0008 */ +#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: \b 0x0024 */ +#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: \b 0x0030 */ +#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: \b 0x0050 */ +#define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: \b 0x0054 */ +#define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: \b 0x0058 */ +#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: \b 0x0080 */ +#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: \b 0x0088 */ +#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: \b 0x009C */ +#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: \b 0x0100 */ +#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: \b 0x0140 */ +#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: \b 0x0144 */ +#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: \b 0x0148 */ +#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: \b 0x0170 */ +#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: \b 0x0174 */ +#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: \b 0x017C */ +#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: \b 0x0200 */ +#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: \b 0x0204 */ +#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: \b 0x0208 */ +#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: \b 0x020C */ +#define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: \b 0x0210 */ +#define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: \b 0x0214 */ +#define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: \b 0x0218 */ +#define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: \b 0x021C */ +#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: \b 0x0300 */ +#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: \b 0x0304 */ +#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: \b 0x0308 */ +#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: \b 0x030C */ +#define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: \b 0x0310 */ +#define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: \b 0x0314 */ +#define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: \b 0x0318 */ +#define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: \b 0x031C */ +/**@} end of group FLC_Register_Offsets */ + +/** + * @ingroup flc_registers + * @defgroup FLC_FADDR_Register FLC_FADDR + * @brief Field Positions and Bit Masks for the FLC_FADDR register. + * @{ + */ +#define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */ +#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */ +/**@} end of group FLC_FADDR */ +/** + * @ingroup flc_registers + * @defgroup FLC_FCKDIV_Register FLC_FCKDIV + * @brief Field Positions and Bit Masks for the FLC_FCKDIV register. + * @{ + */ +#define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */ +#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */ +#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */ +#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */ +/**@} end of group FLC_FCKDIV */ +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL_Register FLC_CTRL + * @brief Field Positions and Bit Masks for the FLC_CTRL register. + * @{ + */ +#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */ +#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */ +#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */ +#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */ +#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */ +#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */ +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */ +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */ +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */ +#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */ +#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */ +#define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */ +#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */ +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */ +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */ +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */ +#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */ +#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */ +/**@} end of group FLC_CTRL */ +/** + * @ingroup flc_registers + * @defgroup FLC_INTR_Register FLC_INTR + * @brief Field Positions and Bit Masks for the FLC_INTR register. + * @{ + */ +#define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */ +#define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */ +#define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */ +#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */ +#define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */ +#define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */ +#define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */ +#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */ +#define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */ +#define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */ +/**@} end of group FLC_INTR */ +/** + * @ingroup flc_registers + * @defgroup FLC_PERFORM_Register FLC_PERFORM + * @brief Field Positions and Bit Masks for the FLC_PERFORM register. + * @{ + */ +#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */ +#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */ +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */ +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */ +#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */ +#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */ +#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */ +#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */ +#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */ +#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */ +#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */ +#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */ +#define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */ +#define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */ +#define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */ +#define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */ +/**@} end of group FLC_PERFORM */ +/** + * @ingroup flc_registers + * @defgroup FLC_STATUS_Register FLC_STATUS + * @brief Field Positions and Bit Masks for the FLC_STATUS register. + * @{ + */ +#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */ +#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */ +#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */ +#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */ +#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */ +#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */ +#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */ +#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ +#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */ +#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ +/**@} end of group FLC_STATUS*/ +/** + * @ingroup flc_registers + * @defgroup FLC_SECURITY_Register FLC_SECURITY + * @brief Field Positions and Bit Masks for the FLC_SECURITY register. + * @{ + */ +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */ +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */ +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */ +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */ +#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */ +#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */ +#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */ +#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */ +#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */ +#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */ +/**@} end of group FLC_SECURITY */ +/** + * @ingroup flc_registers + * @defgroup FLC_BYPASS_Register FLC_BYPASS + * @brief Field Positions and Bit Masks for the FLC_BYPASS register. + * @{ + */ +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */ +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */ +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */ +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */ +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */ +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */ +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */ +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */ +/**@} end of group FLC_BYPASS*/ +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL2_Register FLC_CTRL2 + * @brief Field Positions and Bit Masks for the FLC_CTRL2 register. + * @{ + */ +#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */ +#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */ +#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */ +#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */ +#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */ +#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */ +#define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */ +#define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */ +#define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */ +#define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */ +#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */ +#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */ +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */ +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */ +/**@} end of group FLC_CTRL2*/ + /** + * @ingroup flc_registers + * @defgroup FLC_INTFL1_Register FLC_INTFL1 + * @brief Field Positions and Bit Masks for the FLC_INTFL1 register. + * @{ + */ +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ +#define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ +#define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ +#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ +#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ +/**@} end of group FLC_INTFL1 */ +/** + * @ingroup flc_registers + * @defgroup FLC_INTEN1_Register FLC_INTEN1 + * @brief Field Positions and Bit Masks for the FLC_INTEN1 register. + * @{ + */ +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ +#define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ +#define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ +#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ +#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ +/**@} end of group FLC_INTEN1*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_FLC_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h new file mode 100644 index 00000000000..f6968f15ce9 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h @@ -0,0 +1,668 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24659 $ + * +*************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_GPIO_REGS_H_ +#define _MXC_GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @{ + */ + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/** + * Structure type to access the GPIO Registers + */ +typedef struct { + __IO uint32_t rst_mode[16]; /**< \b 0x0000-0x003C GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */ + __IO uint32_t free[16]; /**< \b 0x0040-0x007C GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */ + __IO uint32_t out_mode[16]; /**< \b 0x0080-0x00BC GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */ + __IO uint32_t out_val[16]; /**< \b 0x00C0-0x00FC GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */ + __IO uint32_t func_sel[16]; /**< \b 0x0100-0x013C GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */ + __IO uint32_t in_mode[16]; /**< \b 0x0140-0x017C GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */ + __IO uint32_t in_val[16]; /**< \b 0x0180-0x01BC GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */ + __IO uint32_t int_mode[16]; /**< \b 0x01C0-0x01FC GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */ + __IO uint32_t intfl[16]; /**< \b 0x0200-0x023C GPIO_INTFL_P[0..15] Registers - Interrupt Flags */ + __IO uint32_t inten[16]; /**< \b 0x0240-0x027C GPIO_INTEN_P[0..15] Registers - Interrupt Enables */ +} mxc_gpio_regs_t; +/**@} end of gpio_registers group */ + +/* + Register offsets for module GPIO. +*/ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Register Offsets from the GPIO Base Address. + * @{ + */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets + * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: \b 0x0000 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: \b 0x0004 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: \b 0x0008 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: \b 0x000C */ +#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: \b 0x0010 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: \b 0x0014 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: \b 0x0018 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: \b 0x001C */ +#define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: \b 0x0020 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: \b 0x0024 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: \b 0x0028 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: \b 0x002C */ +#define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: \b 0x0030 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: \b 0x0034 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: \b 0x0038 */ +#define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: \b 0x003C */ +/**@} end of gpio_rst_mode group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets + * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: \b 0x0040 */ +#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: \b 0x0044 */ +#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: \b 0x0048 */ +#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: \b 0x004C */ +#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: \b 0x0050 */ +#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: \b 0x0054 */ +#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: \b 0x0058 */ +#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: \b 0x005C */ +#define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: \b 0x0060 */ +#define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: \b 0x0064 */ +#define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: \b 0x0068 */ +#define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: \b 0x006C */ +#define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: \b 0x0070 */ +#define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: \b 0x0074 */ +#define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: \b 0x0078 */ +#define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: \b 0x007C */ +/**@} end of gpio_free group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers + * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: \b 0x0080 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: \b 0x0084 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: \b 0x0088 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: \b 0x008C */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: \b 0x0090 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: \b 0x0094 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: \b 0x0098 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: \b 0x009C */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: \b 0x00A0 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: \b 0x00A4 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: \b 0x00A8 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: \b 0x00AC */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: \b 0x00B0 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: \b 0x00B4 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: \b 0x00B8 */ +#define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: \b 0x00BC */ +/**@} end of gpio_out_mode group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers + * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: \b 0x00C0 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: \b 0x00C4 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: \b 0x00C8 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: \b 0x00CC */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: \b 0x00D0 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: \b 0x00D4 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: \b 0x00D8 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: \b 0x00DC */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: \b 0x00E0 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: \b 0x00E4 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: \b 0x00E8 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: \b 0x00EC */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: \b 0x00F0 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: \b 0x00F4 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: \b 0x00F8 */ +#define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: \b 0x00FC */ +/**@} end of gpio_out_val group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers + * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: \b 0x0100 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: \b 0x0104 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: \b 0x0108 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: \b 0x010C */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: \b 0x0110 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: \b 0x0114 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: \b 0x0118 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: \b 0x011C */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: \b 0x0120 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: \b 0x0124 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: \b 0x0128 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: \b 0x012C */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: \b 0x0130 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: \b 0x0134 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: \b 0x0138 */ +#define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: \b 0x013C */ +/**@} end of gpio_func_sel */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers + * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: \b 0x0140 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: \b 0x0144 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: \b 0x0148 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: \b 0x014C */ +#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: \b 0x0150 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: \b 0x0154 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: \b 0x0158 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: \b 0x015C */ +#define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: \b 0x0160 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: \b 0x0164 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: \b 0x0168 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: \b 0x016C */ +#define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: \b 0x0170 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: \b 0x0174 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: \b 0x0178 */ +#define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: \b 0x017C */ +/**@} end of gpio_in_mode group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers + * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: \b 0x0180 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: \b 0x0184 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: \b 0x0188 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: \b 0x018C */ +#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: \b 0x0190 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: \b 0x0194 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: \b 0x0198 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: \b 0x019C */ +#define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: \b 0x01A0 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: \b 0x01A4 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: \b 0x01A8 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: \b 0x01AC */ +#define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: \b 0x01B0 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: \b 0x01B4 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: \b 0x01B8 */ +#define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: \b 0x01BC */ +/**@} end of gpio_in_val group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers + * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: \b 0x01C0 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: \b 0x01C4 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: \b 0x01C8 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: \b 0x01CC */ +#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: \b 0x01D0 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: \b 0x01D4 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: \b 0x01D8 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: \b 0x01DC */ +#define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: \b 0x01E0 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: \b 0x01E4 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: \b 0x01E8 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: \b 0x01EC */ +#define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: \b 0x01F0 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: \b 0x01F4 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: \b 0x01F8 */ +#define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: \b 0x01FC */ +/**@} end of gpio_int_mode group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers + * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: \b 0x0200 */ +#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: \b 0x0204 */ +#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: \b 0x0208 */ +#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: \b 0x020C */ +#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: \b 0x0210 */ +#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: \b 0x0214 */ +#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: \b 0x0218 */ +#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: \b 0x021C */ +#define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: \b 0x0220 */ +#define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: \b 0x0224 */ +#define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: \b 0x0228 */ +#define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: \b 0x022C */ +#define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: \b 0x0230 */ +#define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: \b 0x0234 */ +#define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: \b 0x0238 */ +#define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: \b 0x023C */ +/**@} end of gpio_int_flag group */ +/** + * @ingroup GPIO_Register_Offsets + * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers + * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: \b 0x0240 */ +#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: \b 0x0244 */ +#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: \b 0x0248 */ +#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: \b 0x024C */ +#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: \b 0x0250 */ +#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: \b 0x0254 */ +#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: \b 0x0258 */ +#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: \b 0x025C */ +#define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: \b 0x0260 */ +#define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: \b 0x0264 */ +#define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: \b 0x0268 */ +#define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: \b 0x026C */ +#define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: \b 0x0270 */ +#define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: \b 0x0274 */ +#define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: \b 0x0278 */ +#define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: \b 0x027C */ +/**@}*/ +/**@} end of GPIO_Register_Offsets */ + +/* + Field positions and masks for module GPIO. +*/ +/** + * @ingroup gpio_registers + * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE + * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register. + * @{ + */ +#define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */ +#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */ +#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */ +#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */ +#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */ +#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */ +#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */ +#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_FREE */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_FREE_Register GPIO_FREE + * @brief Field Positions and Bit Masks for the GPIO_FREE register. + * @{ + */ +#define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */ +#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */ +#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */ +#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */ +#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */ +#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */ +#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */ +#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_FREE */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE + * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register. + * @{ + */ +#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */ +#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_OUT_MODE */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL + * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register. + * @{ + */ +#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */ +#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_OUT_VAL */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL + * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register. + * @{ + */ +#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */ +#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_FUNC_SEL */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE + * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register. + * @{ + */ +#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */ +#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */ +#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */ +#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */ +#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */ +#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */ +#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */ +#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_IN_MODE */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL + * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register. + * @{ + */ +#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */ +#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */ +#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */ +#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */ +#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */ +#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */ +#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */ +#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_IN_VAL */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE + * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register. + * @{ + */ +#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */ +#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */ +#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */ +#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */ +#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */ +#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */ +#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */ +#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_INT_MODE */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL_Register GPIO_INTFL + * @brief Field Positions and Bit Masks for the GPIO_INTFL register. + * @{ + */ +#define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */ +#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */ +#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */ +#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */ +#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */ +#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */ +#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */ +#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */ +/**@} end of group GPIO_INTFL */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_Register GPIO_INTEN + * @brief Field Positions and Bit Masks for the GPIO_INTEN register. + * @{ + */ +#define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */ +#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */ +#define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */ +#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */ +#define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */ +#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */ +#define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */ +#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */ +#define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */ +#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */ +#define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */ +#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */ +#define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */ +#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */ +#define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */ +#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */ +/**@} end group GPIO_INTEN_Register */ + + +/* + Field values and shifted values for module GPIO. +*/ +/** + * @ingroup GPIO_RST_MODE_Register + * @defgroup GPIO_RST_MODE_Values Reset Mode Values + * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes + * @{ + */ +#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */ +#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */ +#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */ +#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */ +#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */ +/**@}*/ + +/** + * @ingroup GPIO_FREE_Register + * @defgroup GPIO_FREE_Values Reset Mode Values + * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable + * @{ + */ +#define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */ +#define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */ +/**@}*/ + +/** + * @ingroup GPIO_FREE_Register + * @defgroup GPIO_OUT_MODE_Values Output Mode Values + * @brief GPIO_OUT_MODE values for setting the different port pin output modes + * @{ + */ +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */ +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */ +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */ +#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */ +#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */ +#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */ +#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */ +#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */ +#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */ +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */ +#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */ +#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */ +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */ +/**@}*/ + +/** + * @ingroup GPIO_FUNC_SEL_Register + * @defgroup GPIO_FUNC_SEL_Values Function type selection values + * @brief Function selection values for the GPIO_FUNC_SEL Register. + * @{ + */ +#define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */ +#define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */ +#define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */ +/**@}*/ + +/** + * @ingroup GPIO_IN_MODE_Register + * @defgroup GPIO_IN_MODE_Values Input mode selection values + * @brief Input mode values for selecting the GPIO input mode. + * @{ + */ +#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */ +#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */ +#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */ +#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */ +/**@}*/ + +/** + * @ingroup GPIO_INT_MODE_Register + * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values + * @brief Values for setting the interrupt mode of a GPIO input pin. + * @{ + */ +#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */ +#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */ +#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */ +#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */ +#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */ +#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */ +/**@}*/ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_GPIO_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cm_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cm_regs.h new file mode 100644 index 00000000000..e79bb7a9d56 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cm_regs.h @@ -0,0 +1,282 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24660 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_I2CM_REGS_H_ +#define _MXC_I2CM_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +#define MXC_S_I2CM_TRANS_TAG_START 0x000 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 +#define MXC_S_I2CM_TRANS_TAG_STOP 0x700 +#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 +#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 +///@endcond + +/** + * @ingroup i2cm + * @defgroup i2cm_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module. + * @{ + */ + +/** + * Structure type to access the I2CM Peripheral Module Registers + */ +typedef struct { + __IO uint32_t fs_clk_div; /**< \b 0x0000 \b I2CM_FS_CLK_DIV Register - Full Speed SCL Clock Settings */ + __RO uint32_t rsv004[2]; /**< \b 0x0004-0x0008 \b RESERVED \warning Do Not Modify, Read Only */ + __IO uint32_t timeout; /**< \b 0x000C \b I2CM_TIMEOUT Register - Timeout and Auto-Stop Settings */ + __IO uint32_t ctrl; /**< \b 0x0010 \b I2CM_CTRL Register - Master Control Register */ + __IO uint32_t trans; /**< \b 0x0014 \b I2CM_TRANS Register - Master Transaction Start and Status Flags */ + __IO uint32_t intfl; /**< \b 0x0018 \b I2CM_INTFL Register - Master Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x001C \b I2CM_INTEN Register - Master Interrupt Enable/Disable Controls */ + __RO uint32_t rsv020[2]; /**< \b 0x0020-0x0024 \b RESERVED \warning Do Not Modify, Read Only */ + __IO uint32_t bb; /**< \b 0x0028 \b I2CM_BB Register - Master Bit-Bang Control Register */ +} mxc_i2cm_regs_t; + + +/** + * Structure type for the I2CM Transmit and Receive FIFOs. + * The @c tx member is the write location for transmitting data and @c rx member is the read point for reading data. + * + */ +typedef struct { + union { + __IO uint16_t tx; /**< tx FIFO address */ + __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO */ + __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO */ + __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO */ + }; + union { + __IO uint16_t rx; /**< RX FIFO address */ + __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO */ + __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO */ + __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO */ + }; +} mxc_i2cm_fifo_regs_t; +/**@} end of group i2cm_registers */ + +/* + Register offsets for module I2CM. +*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_Register_Offsets Register Offsets + * @brief I2C Master Register Offsets from the I2CM[n] Base Peripheral Address. + * @{ + */ +#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CM Base Address: \b 0x0000 */ +#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) /**< Offset from I2CM Base Address: \b 0x000C */ +#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) /**< Offset from I2CM Base Address: \b 0x0010 */ +#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) /**< Offset from I2CM Base Address: \b 0x0014 */ +#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) /**< Offset from I2CM Base Address: \b 0x0018 */ +#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) /**< Offset from I2CM Base Address: \b 0x001C */ +#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) /**< Offset from I2CM Base Address: \b 0x0028 */ +#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from I2CM FIFO Base Address: \b 0x0000 */ +#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from I2CM FIFO Base Address: \b 0x8000 */ +/**@} end of group i2cm_registers */ + +/* + Field positions and masks for module I2CM. +*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_FS_CLK_DIV_Register I2CM_FS_CLK_DIV + * @brief Field Positions and Bit Masks for the I2CM_FS_CLK_DIV register + * @{ + */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 /**< FS_FILTER_CLK_DIV Position */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) /**< FS_FILTER_CLK_DIV Mask */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 /**< FS_SCL_LO_CNT Position */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) /**< FS_SCL_LO_CNT Mask */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 /**< FS_SCL_HI_CNT Position */ +#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) /**< FS_SCL_HI_CNT Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_TIMEOUT_Register I2CM_TIMEOUT + * @brief Field Positions and Bit Masks for the I2CM_TIMEOUT register + * @{ + */ +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 /**< TX_TIMEOUT Position */ +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 /**< AUTO_STOP_EN Position */ +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) /**< AUTO_STOP_EN Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_CTRL_Register I2CM_CTRL + * @brief Field Positions and Bit Masks for the I2CM_CTRL register + * @{ + */ +#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 /**< TX_FIFO_EN Position */ +#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */ +#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 /**< RX_FIFO_EN Position */ +#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */ +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 /**< MSTR_RESET_EN Position */ +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) /**< MSTR_RESET_EN Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_TRANS_Register I2CM_TRANS + * @brief Field Positions and Bit Masks for the I2CM_TRANS register + * @{ + */ +#define MXC_F_I2CM_TRANS_TX_START_POS 0 /**< TX_START Position */ +#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) /**< TX_START Mask */ +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 /**< TX_IN_PROGRESS Position */ +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) /**< TX_IN_PROGRESS Mask */ +#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 /**< TX_DONE Position */ +#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) /**< TX_DONE Mask */ +#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 /**< TX_NACKED Position */ +#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) /**< TX_NACKED Mask */ +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 /**< TX_LOST_ARBITR Position */ +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ +#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 /**< TX_TIMEOUT Position */ +#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_INTFL_Register I2CM_INTFL + * @brief Field Positions and Bit Masks for the I2CM_INTFL register + * @{ + */ +#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 /**< TX_DONE Position */ +#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) /**< TX_DONE Mask */ +#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 /**< TX_NACKED Position */ +#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) /**< TX_NACKED Mask */ +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */ +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ +#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */ +#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */ +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */ +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */ +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */ +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */ +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */ +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */ +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */ +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */ +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */ +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */ +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_INTEN_Register I2CM_INTEN + * @brief Field Positions and Bit Masks for the I2CM_INTEN register + * @{ + */ +#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 /**< TX_DONE Position */ +#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) /**< TX_DONE Mask */ +#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 /**< TX_NACKED Position */ +#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) /**< TX_NACKED Mask */ +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */ +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ +#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */ +#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */ +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */ +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */ +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */ +#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */ +#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */ +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */ +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */ +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */ +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */ +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */ +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */ +/**@}*/ +/** + * @ingroup i2cm_registers + * @defgroup I2CM_BB_Register I2CM_BB + * @brief Field Positions and Bit Masks for the I2CM_BB register + * @{ + */ +#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 /**< BB_SCL_OUT Position */ +#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) /**< BB_SCL_OUT Mask */ +#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 /**< BB_SDA_OUT Position */ +#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) /**< BB_SDA_OUT Mask */ +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 /**< BB_SCL_IN_VAL Position */ +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) /**< BB_SCL_IN_VAL Mask */ +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 /**< BB_SDA_IN_VAL Position */ +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) /**< BB_SDA_IN_VAL Mask */ +#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 /**< RX_FIFO_CNT Position */ +#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) /**< RX_FIFO_CNT Mask */ +/**@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_I2CM_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h new file mode 100644 index 00000000000..4526ac6336b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h @@ -0,0 +1,291 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24661 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_I2CS_REGS_H_ +#define _MXC_I2CS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup i2cs + * @defgroup i2cs_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module. + * @{ + */ + +/** + * Structure type to access the I2CS Peripheral Module Registers + */ + typedef struct { + __IO uint32_t clk_div; /**< \b 0x0000: I2CS_CLK_DIV Register - Clock Divisor Control */ + __IO uint32_t dev_id; /**< \b 0x0004: I2CS_DEV_ID Register - Device ID Register */ + __IO uint32_t intfl; /**< \b 0x0008: I2CS_INTFL Register - Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x000C: I2CS_INTEN Register - Interrupt Enable */ + __IO uint32_t data_byte[32]; /**< \b 0x0010-0x008C: I2CS_DATA_BYTE - Data Byte */ +} mxc_i2cs_regs_t; +/**@} end of i2cs_registers */ + + +/* + Register offsets for module I2CS. +*/ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_Register_Offsets Register Offsets + * @brief I2C Slave Register Offsets from the I2CS Base Peripheral Address. + * @{ + */ +#define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CS Base Peripheral Address: \b 0x0000 */ +#define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) /**< Offset from I2CS Base Peripheral Address: \b 0x0004 */ +#define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from I2CS Base Peripheral Address: \b 0x0008 */ +#define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from I2CS Base Peripheral Address: \b 0x000C */ +#define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) /**< Offset from I2CS Base Peripheral Address: \b 0x0010-0x008C */ +/**@} I2CS_Register_Offsets */ +/* + Field positions and masks for module I2CS. +*/ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_CLK_DIV_Register I2CS_CLK_DIV + * @brief Field Positions and Bit Masks for the I2CS_CLK_DIV register + * @{ + */ +#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 /**< FS_FILTER_CLOCK_DIV Position */ +#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) /**< FS_FILTER_CLOCK_DIV Mask */ +/**@} end group I2CS_CLK_DIV */ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_DEV_ID_Register I2CS_DEV_ID + * @brief Field Positions and Bit Masks for the I2CS_DEV_ID register + * @{ + */ +#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 /**< SLAVE_DEV_ID Position */ +#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) /**< SLAVE_DEV_ID Mask */ +#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 /**< TEN_BIT_ID_MODE Position */ +#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) /**< TEN_BIT_ID_MODE Mask */ +#define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 /**< SLAVE_RESET Position */ +#define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) /**< SLAVE_RESET Mask */ +/**@} end group I2CS_DEV_ID */ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_INTFL_Register I2CS_INTFL + * @brief Field Positions and Bit Masks for the I2CS_INTFL register + * @{ + */ +#define MXC_F_I2CS_INTFL_BYTE0_POS 0 /**< BYTE0 Position */ +#define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) /**< BYTE0 Mask */ +#define MXC_F_I2CS_INTFL_BYTE1_POS 1 /**< BYTE1 Position */ +#define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) /**< BYTE1 Mask */ +#define MXC_F_I2CS_INTFL_BYTE2_POS 2 /**< BYTE2 Position */ +#define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) /**< BYTE2 Mask */ +#define MXC_F_I2CS_INTFL_BYTE3_POS 3 /**< BYTE3 Position */ +#define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) /**< BYTE3 Mask */ +#define MXC_F_I2CS_INTFL_BYTE4_POS 4 /**< BYTE4 Position */ +#define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) /**< BYTE4 Mask */ +#define MXC_F_I2CS_INTFL_BYTE5_POS 5 /**< BYTE5 Position */ +#define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) /**< BYTE5 Mask */ +#define MXC_F_I2CS_INTFL_BYTE6_POS 6 /**< BYTE6 Position */ +#define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) /**< BYTE6 Mask */ +#define MXC_F_I2CS_INTFL_BYTE7_POS 7 /**< BYTE7 Position */ +#define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) /**< BYTE7 Mask */ +#define MXC_F_I2CS_INTFL_BYTE8_POS 8 /**< BYTE8 Position */ +#define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) /**< BYTE8 Mask */ +#define MXC_F_I2CS_INTFL_BYTE9_POS 9 /**< BYTE9 Position */ +#define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) /**< BYTE9 Mask */ +#define MXC_F_I2CS_INTFL_BYTE10_POS 10 /**< BYTE10 Position */ +#define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) /**< BYTE10 Mask */ +#define MXC_F_I2CS_INTFL_BYTE11_POS 11 /**< BYTE11 Position */ +#define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) /**< BYTE11 Mask */ +#define MXC_F_I2CS_INTFL_BYTE12_POS 12 /**< BYTE12 Position */ +#define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) /**< BYTE12 Mask */ +#define MXC_F_I2CS_INTFL_BYTE13_POS 13 /**< BYTE13 Position */ +#define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) /**< BYTE13 Mask */ +#define MXC_F_I2CS_INTFL_BYTE14_POS 14 /**< BYTE14 Position */ +#define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) /**< BYTE14 Mask */ +#define MXC_F_I2CS_INTFL_BYTE15_POS 15 /**< BYTE15 Position */ +#define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) /**< BYTE15 Mask */ +#define MXC_F_I2CS_INTFL_BYTE16_POS 16 /**< BYTE16 Position */ +#define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) /**< BYTE16 Mask */ +#define MXC_F_I2CS_INTFL_BYTE17_POS 17 /**< BYTE17 Position */ +#define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) /**< BYTE17 Mask */ +#define MXC_F_I2CS_INTFL_BYTE18_POS 18 /**< BYTE18 Position */ +#define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) /**< BYTE18 Mask */ +#define MXC_F_I2CS_INTFL_BYTE19_POS 19 /**< BYTE19 Position */ +#define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) /**< BYTE19 Mask */ +#define MXC_F_I2CS_INTFL_BYTE20_POS 20 /**< BYTE20 Position */ +#define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) /**< BYTE20 Mask */ +#define MXC_F_I2CS_INTFL_BYTE21_POS 21 /**< BYTE21 Position */ +#define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) /**< BYTE21 Mask */ +#define MXC_F_I2CS_INTFL_BYTE22_POS 22 /**< BYTE22 Position */ +#define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) /**< BYTE22 Mask */ +#define MXC_F_I2CS_INTFL_BYTE23_POS 23 /**< BYTE23 Position */ +#define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) /**< BYTE23 Mask */ +#define MXC_F_I2CS_INTFL_BYTE24_POS 24 /**< BYTE24 Position */ +#define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) /**< BYTE24 Mask */ +#define MXC_F_I2CS_INTFL_BYTE25_POS 25 /**< BYTE25 Position */ +#define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) /**< BYTE25 Mask */ +#define MXC_F_I2CS_INTFL_BYTE26_POS 26 /**< BYTE26 Position */ +#define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) /**< BYTE26 Mask */ +#define MXC_F_I2CS_INTFL_BYTE27_POS 27 /**< BYTE27 Position */ +#define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) /**< BYTE27 Mask */ +#define MXC_F_I2CS_INTFL_BYTE28_POS 28 /**< BYTE28 Position */ +#define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) /**< BYTE28 Mask */ +#define MXC_F_I2CS_INTFL_BYTE29_POS 29 /**< BYTE29 Position */ +#define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) /**< BYTE29 Mask */ +#define MXC_F_I2CS_INTFL_BYTE30_POS 30 /**< BYTE30 Position */ +#define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) /**< BYTE30 Mask */ +#define MXC_F_I2CS_INTFL_BYTE31_POS 31 /**< BYTE31 Position */ +#define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) /**< BYTE31 Mask */ +/**@} end group I2CS_INTFL */ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_INTEN_Register I2CS_INTEN + * @brief Field Positions and Bit Masks for the I2CS_INTEN register + * @{ + */ +#define MXC_F_I2CS_INTEN_BYTE0_POS 0 /**< BYTE0 Position */ +#define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) /**< BYTE0 Mask */ +#define MXC_F_I2CS_INTEN_BYTE1_POS 1 /**< BYTE1 Position */ +#define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) /**< BYTE1 Mask */ +#define MXC_F_I2CS_INTEN_BYTE2_POS 2 /**< BYTE2 Position */ +#define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) /**< BYTE2 Mask */ +#define MXC_F_I2CS_INTEN_BYTE3_POS 3 /**< BYTE3 Position */ +#define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) /**< BYTE3 Mask */ +#define MXC_F_I2CS_INTEN_BYTE4_POS 4 /**< BYTE4 Position */ +#define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) /**< BYTE4 Mask */ +#define MXC_F_I2CS_INTEN_BYTE5_POS 5 /**< BYTE5 Position */ +#define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) /**< BYTE5 Mask */ +#define MXC_F_I2CS_INTEN_BYTE6_POS 6 /**< BYTE6 Position */ +#define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) /**< BYTE6 Mask */ +#define MXC_F_I2CS_INTEN_BYTE7_POS 7 /**< BYTE7 Position */ +#define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) /**< BYTE7 Mask */ +#define MXC_F_I2CS_INTEN_BYTE8_POS 8 /**< BYTE8 Position */ +#define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) /**< BYTE8 Mask */ +#define MXC_F_I2CS_INTEN_BYTE9_POS 9 /**< BYTE9 Position */ +#define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) /**< BYTE9 Mask */ +#define MXC_F_I2CS_INTEN_BYTE10_POS 10 /**< BYTE10 Position */ +#define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) /**< BYTE10 Mask */ +#define MXC_F_I2CS_INTEN_BYTE11_POS 11 /**< BYTE11 Position */ +#define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) /**< BYTE11 Mask */ +#define MXC_F_I2CS_INTEN_BYTE12_POS 12 /**< BYTE12 Position */ +#define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) /**< BYTE12 Mask */ +#define MXC_F_I2CS_INTEN_BYTE13_POS 13 /**< BYTE13 Position */ +#define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) /**< BYTE13 Mask */ +#define MXC_F_I2CS_INTEN_BYTE14_POS 14 /**< BYTE14 Position */ +#define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) /**< BYTE14 Mask */ +#define MXC_F_I2CS_INTEN_BYTE15_POS 15 /**< BYTE15 Position */ +#define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) /**< BYTE15 Mask */ +#define MXC_F_I2CS_INTEN_BYTE16_POS 16 /**< BYTE16 Position */ +#define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) /**< BYTE16 Mask */ +#define MXC_F_I2CS_INTEN_BYTE17_POS 17 /**< BYTE17 Position */ +#define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) /**< BYTE17 Mask */ +#define MXC_F_I2CS_INTEN_BYTE18_POS 18 /**< BYTE18 Position */ +#define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) /**< BYTE18 Mask */ +#define MXC_F_I2CS_INTEN_BYTE19_POS 19 /**< BYTE19 Position */ +#define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) /**< BYTE19 Mask */ +#define MXC_F_I2CS_INTEN_BYTE20_POS 20 /**< BYTE20 Position */ +#define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) /**< BYTE20 Mask */ +#define MXC_F_I2CS_INTEN_BYTE21_POS 21 /**< BYTE21 Position */ +#define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) /**< BYTE21 Mask */ +#define MXC_F_I2CS_INTEN_BYTE22_POS 22 /**< BYTE22 Position */ +#define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) /**< BYTE22 Mask */ +#define MXC_F_I2CS_INTEN_BYTE23_POS 23 /**< BYTE23 Position */ +#define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) /**< BYTE23 Mask */ +#define MXC_F_I2CS_INTEN_BYTE24_POS 24 /**< BYTE24 Position */ +#define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) /**< BYTE24 Mask */ +#define MXC_F_I2CS_INTEN_BYTE25_POS 25 /**< BYTE25 Position */ +#define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) /**< BYTE25 Mask */ +#define MXC_F_I2CS_INTEN_BYTE26_POS 26 /**< BYTE26 Position */ +#define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) /**< BYTE26 Mask */ +#define MXC_F_I2CS_INTEN_BYTE27_POS 27 /**< BYTE27 Position */ +#define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) /**< BYTE27 Mask */ +#define MXC_F_I2CS_INTEN_BYTE28_POS 28 /**< BYTE28 Position */ +#define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) /**< BYTE28 Mask */ +#define MXC_F_I2CS_INTEN_BYTE29_POS 29 /**< BYTE29 Position */ +#define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) /**< BYTE29 Mask */ +#define MXC_F_I2CS_INTEN_BYTE30_POS 30 /**< BYTE30 Position */ +#define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) /**< BYTE30 Mask */ +#define MXC_F_I2CS_INTEN_BYTE31_POS 31 /**< BYTE31 Position */ +#define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) /**< BYTE31 Mask */ +/**@} end group I2CS_INTEN */ +/** + * @ingroup i2cs_registers + * @defgroup I2CS_DATA_BYTE_Register I2CS_DATA_BYTE + * @brief Field Positions and Bit Masks for the I2CS_DATA_BYTE register + * @{ + */ +#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 /**< DATA_FIELD Position */ +#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) /**< DATA_FIELD */ +#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 /**< READ_ONLY_FL Position */ +#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) /**< READ_ONLY_FL */ +#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 /**< DATA_UPDATED_FL Position */ +#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) /**< DATA_UPDATED_FL */ +/**@} end group I2CS_DATA_BYTE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_I2CS_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h new file mode 100644 index 00000000000..defd5984b77 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h @@ -0,0 +1,157 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the Instruction Cache Controller. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24662 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ICC_REGS_H_ +#define _MXC_ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC. + * @{ + */ + +/** + * Structure type to access the ICC Registers. + */ +typedef struct { + __IO uint32_t id; /**< \b 0x0000: ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */ + __IO uint32_t mem_cfg; /**< \b 0x0004: ICC_MEM_CFG Register */ + __RO uint32_t rsv008[62]; /**< \b 0x0008-0x00FC: RESERVED */ + __IO uint32_t ctrl_stat; /**< \b 0x0100: ICC_CTRL_STAT Register */ + __RO uint32_t rsv104[383]; /**< \b 0x0104-0x06FC: RESERVED */ + __IO uint32_t invdt_all; /**< \b 0x0700: ICC_INVDT_ALL Register */ +} mxc_icc_regs_t; +/**@} end of group icc_registers*/ + + + + + +/* + Register offsets for module ICC. +*/ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief Instruction Cache Controller Register Offsets from the ICC Base Address. + * @{ + */ +#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: \b 0x0000 */ +#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: \b 0x0004 */ +#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: \b 0x0100 */ +#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: \b 0x0700 */ +/**@} end of group icc_registers */ + +/* + Field positions and masks for module ICC. +*/ +/** + * @ingroup icc_registers + * @defgroup ICC_ID_Register ICC_ID + * @brief Field Positions and Bit Masks for the ICC_ID register + * @{ + */ +#define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */ +#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */ +#define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */ +#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */ +#define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */ +#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */ +/**@} end of group ICC_ID_register */ +/** + * @ingroup icc_registers + * @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG + * @brief Field Positions and Bit Masks for the ICC_MEM_CFG register + * @{ + */ +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */ +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */ +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */ +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */ +/**@} end of group ICC_MEM_CFG_register */ +/** + * @ingroup icc_registers + * @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT + * @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register + * @{ + */ +#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */ +#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */ +#define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */ +#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */ +/**@} end of group ICC_CTRL_STAT_register */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_ICC_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h new file mode 100644 index 00000000000..d8bf2935432 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h @@ -0,0 +1,1163 @@ +/** + * @file + * @brief IOMAN hardware register definitions. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-31 17:07:02 -0500 (Mon, 31 Oct 2016) $ + * $Revision: 24857 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion. */ +#ifndef _MXC_IOMAN_REGS_H_ +#define _MXC_IOMAN_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +///@cond +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/* **** Definitions **** */ +/** + * Structure type for wakeup detection @b request for port 4, port 5, port 6 and port 7. + */ +typedef struct { + uint32_t wud_req_p4 : 8; /**< Port 4 wake-up detection @b request bit field. */ + uint32_t wud_req_p5 : 8; /**< Port 5 wake-up detection @b request bit field. */ + uint32_t wud_req_p6 : 8; /**< Port 6 wake-up detection @b request bit field. */ + uint32_t wud_req_p7 : 8; /**< Port 7 wake-up detection @b request bit field. */ +} mxc_ioman_wud_req1_t; +/** + * Structure type for wakeup detection @b acknowledgement for port 0, port 1, port 2 and port 3. + */ +typedef struct { + uint32_t wud_ack_p0 : 8; /**< Port 0 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p1 : 8; /**< Port 1 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p2 : 8; /**< Port 2 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p3 : 8; /**< Port 3 wake-up detection @b acknowledgement bit field. */ +} mxc_ioman_wud_ack0_t; + +/** + * @ingroup ioman + * @defgroup ioman_req_ack_bit_fields IOMAN Bit Field Structures + * @brief Bit Field Structes used to request and configure all I/O for all + * port pins and peripherals with external I/O. + * @{ + */ +typedef struct { + uint32_t wud_req_p0 : 8; /**< Port 0 wake-up detection @b request bit field. */ + uint32_t wud_req_p1 : 8; /**< Port 1 wake-up detection @b request bit field. */ + uint32_t wud_req_p2 : 8; /**< Port 2 wake-up detection @b request bit field. */ + uint32_t wud_req_p3 : 8; /**< Port 3 wake-up detection @b request bit field. */ +} mxc_ioman_wud_req0_t; +/** + * Structure type for wakeup detection @b acknowledgement for port 4, port 5, port 6 and port 7. + */ +typedef struct { + uint32_t wud_ack_p4 : 8; /**< Port 4 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p5 : 8; /**< Port 5 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p6 : 8; /**< Port 6 wake-up detection @b acknowledgement bit field. */ + uint32_t wud_ack_p7 : 8; /**< Port 7 wake-up detection @b acknowledgement bit field. */ +} mxc_ioman_wud_ack1_t; +/** + * Structure type for analog input @b request for port 0, port 1, port 2 and port 3. + */ +typedef struct { + uint32_t ali_req_p0 : 8; /**< Port 0 analog input @b request bit field. */ + uint32_t ali_req_p1 : 8; /**< Port 1 analog input @b request bit field. */ + uint32_t ali_req_p2 : 8; /**< Port 2 analog input @b request bit field. */ + uint32_t ali_req_p3 : 8; /**< Port 3 analog input @b request bit field. */ +} mxc_ioman_ali_req0_t; +/** + * Structure type for analog input @b request for port 4, port 5, port 6 and port 7. + */ +typedef struct { + uint32_t ali_req_p4 : 8; /**< Port 4 analog input @b request bit field. */ + uint32_t ali_req_p5 : 8; /**< Port 5 analog input @b request bit field. */ + uint32_t ali_req_p6 : 8; /**< Port 6 analog input @b request bit field. */ + uint32_t ali_req_p7 : 8; /**< Port 7 analog input @b request bit field. */ +} mxc_ioman_ali_req1_t; +/** + * Structure type for analog input @b acknowledgement for port 0, port 1, port 2 and port 3. + */ +typedef struct { + uint32_t ali_ack_p0 : 8; /**< Port 0 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p1 : 8; /**< Port 1 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p2 : 8; /**< Port 2 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p3 : 8; /**< Port 3 analog input @b acknowledgement bit field. */ +} mxc_ioman_ali_ack0_t; +/** + * Structure type for analog input @b acknowledgement for port 4, port 5, port 6 and port 7. + */ +typedef struct { + uint32_t ali_ack_p4 : 8; /**< Port 4 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p5 : 8; /**< Port 5 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p6 : 8; /**< Port 6 analog input @b acknowledgement bit field. */ + uint32_t ali_ack_p7 : 8; /**< Port 7 analog input @b acknowledgement bit field. */ +} mxc_ioman_ali_ack1_t; +/** + * Structure type for SPI XIP configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to request the SPIX core external pins. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ + uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ + uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ + uint32_t : 1; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ + uint32_t : 15; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spix_req_t; +/** + * Structure type for SPI XIP configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Is set if the request for the SPIX core external pins succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ + uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ + uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ + uint32_t : 1; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 15; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spix_ack_t; +/** + * Structure type for UART0 configuration @b requests. + */ +typedef struct { + uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ + uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ + uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart0_req_t; +/** + * Structure type for UART0 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart0_ack_t; +/** + * Structure type for UART1 configuration @b requests. + */ +typedef struct { + uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ + uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ + uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart1_req_t; +/** + * Structure type for UART1 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart1_ack_t; +/** + * Structure type for UART2 configuration @b requests. + */ +typedef struct { + uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ + uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ + uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart2_req_t; +/** + * Structure type for UART2 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart2_ack_t; +/** + * Structure type for UART3 configuration @b requests. + */ +typedef struct { + uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ + uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ + uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart3_req_t; +/** + * Structure type for UART3 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 25; /**< Reserved: Do No Modify. */ +} mxc_ioman_uart3_ack_t; +/** + * Structure type for I2C Master 0 configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do No Modify. */ + uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM0 pins. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm0_req_t; +/** + * Structure type for I2C Master 0 configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do No Modify. */ + uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm0_ack_t; +/** + * Structure type for I2C Master 1 configuration @b requests. + */ +typedef struct { + uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM1 CLK and Data pins. */ + uint32_t : 2; /**< Reserved: Do No Modify. */ + uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM1 pins. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm1_req_t; +/** + * Structure type for I2C Master 1 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */ + uint32_t : 2; /**< Reserved: Do No Modify. */ + uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm1_ack_t; +/** + * Structure type for I2C Master 2 configuration @b requests. + */ +typedef struct { + uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM2 CLK and Data pins. */ + uint32_t : 2; /**< Reserved: Do No Modify. */ + uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM2 pins. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm2_req_t; +/** + * Structure type for I2C Master 2 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */ + uint32_t : 2; /**< Reserved: Do No Modify. */ + uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cm2_ack_t; +/** + * Structure type for I2C Slave 0 configuration @b requests. + */ +typedef struct { + uint32_t io_sel : 3; /**< Value for the desired pin mapping for the I2CS0 CLK and Data pins. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CS0 pins. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cs_req_t; +/** + * Structure type for I2C Slave 0 configuration @b acknowledgements. + */ +typedef struct { + uint32_t io_sel : 3; /**< Non-zero if mapping request successful. */ + uint32_t : 1; /**< Reserved: Do No Modify. */ + uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ + uint32_t : 27; /**< Reserved: Do No Modify. */ +} mxc_ioman_i2cs_ack_t; +/** + * Structure type for SPI Master 0 configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to request the SPIM0 core external pins. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ + uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ + uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ + uint32_t ss3_io_req : 1; /**< Set to request slave select 3 active out. */ + uint32_t ss4_io_req : 1; /**< Set to request slave select 4 active out. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to 1 to request Quad I/O for SPIM0. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation for SPIM0. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim0_req_t; +/** + * Structure type for SPI Master 0 configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM0 core external pins succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ + uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ + uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ + uint32_t ss3_io_ack : 1; /**< Is set if the request for the slave select 3 active out succeeded. */ + uint32_t ss4_io_ack : 1; /**< Is set if the request for the slave select 4 active out succeeded. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim0_ack_t; +/** + * Structure type for SPI Master 1 configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to request the SPIM1 core external pins. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ + uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ + uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ + uint32_t : 9; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim1_req_t; +/** + * Structure type for SPI Master 1 configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM1 core external pins succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ + uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ + uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ + uint32_t : 9; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim1_ack_t; +/** + * Structure type for SPI Master 2 configuration @b requests. + */ +typedef struct { + uint32_t mapping_req : 2; /**< Set to the desired port pin mapping for the SPIM2. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to request the SPIM2 core external pins. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ + uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ + uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ + uint32_t : 5; /**< Reserved: Do Not Modify. */ + uint32_t sr0_io_req : 1; /**< Set to 1 to request slave ready 0 input. */ + uint32_t sr1_io_req : 1; /**< Set to 1 to request slave ready 1 input. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim2_req_t; +/** + * Structure type for SPI Master 2 configuration @b acknowledgements. + */ +typedef struct { + uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM2 core external pins succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ + uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ + uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ + uint32_t : 5; /**< Reserved: Do Not Modify. */ + uint32_t sr0_io_req : 1; /**< Is set if the request for the slave ready 0 active input succeeded. */ + uint32_t sr1_io_req : 1; /**< Is set if the request for the slave ready 1 active input succeeded. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 7; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spim2_ack_t; +/** + * Structure type for SPI Bridge configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to request the SPIB core external pins. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ + uint32_t : 19; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spib_req_t; +/** + * Structure type for SPI Bridge configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Non-zero if mapping request successful. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 19; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spib_ack_t; +/** + * Structure type for 1-Wire Master (OWM) configuration @b requests. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t mapping_req : 1; /**< Set to the desired port pin mapping for the 1-Wire Master. */ + uint32_t epu_io_req : 1; /**< Set to 1 to request External Pull-up for the 1-Wire Master. */ + uint32_t : 26; /**< Reserved: Do Not Modify. */ +} mxc_ioman_owm_req_t; +/** + * Structure type for 1-Wire Master configuration @b acknowledgements. + */ +typedef struct { + uint32_t : 4; /**< Reserved: Do Not Modify. */ + uint32_t mapping_ack : 1; /**< Non-zero if mapping request successful. */ + uint32_t epu_io_ack : 1; /**< Non-zero if external pull-up request successful. */ + uint32_t : 26; /**< Reserved: Do Not Modify. */ +} mxc_ioman_owm_ack_t; +/** + * Structure type for SPI Slave configuration @b requests. + */ +typedef struct { + uint32_t mapping_req : 2; /**< Set to desired port pin mapping for the SPIS peripheral. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t core_io_req : 1; /**< Set to 1 to request the I/O be assigned to the SPIS. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ + uint32_t : 19; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spis_req_t; +/** + * Structure type for SPI Slave configuration @b acknowledgements. + */ +typedef struct { + uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */ + uint32_t : 2; /**< Reserved: Do Not Modify. */ + uint32_t core_io_ack : 1; /**< Non-zero if core io request successful. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ + uint32_t : 3; /**< Reserved: Do Not Modify. */ + uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ + uint32_t : 19; /**< Reserved: Do Not Modify. */ +} mxc_ioman_spis_ack_t; +/** + * Structure type to configure the I/O pad mode options. + */ +typedef struct { + uint32_t slow_mode : 1; /**< Slow mode I/O operation */ + uint32_t alt_rcvr_mode : 1; /**< Alternative receive mode. */ + uint32_t : 30; /**< Reserved: Do not modify. */ +} mxc_ioman_pad_mode_t; +/** + * Structure type for Wake-Up Detect (WUD) configuration @b requests. + */ +typedef struct { + uint32_t wud_req_p8 : 2; /**< Request bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */ + uint32_t : 30; /**< Reserved: Do not modify. */ +} mxc_ioman_wud_req2_t; +/** + * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements. + */ +typedef struct { + uint32_t wud_ack_p8 : 2; /**< Acknowledgement bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */ + uint32_t : 30; /**< Reserved: Do not modify. */ +} mxc_ioman_wud_ack2_t; +/** + * Structure type for Analog Wake-Up Detect (WUD) configuration @b requests. + */ +typedef struct { + uint32_t ali_req_p8 : 2; /**< Request bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */ + uint32_t : 30; /**< Reserved: Do not modify. */ +} mxc_ioman_ali_req2_t; +/** + * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements. + */ +typedef struct { + uint32_t ali_ack_p8 : 2; /**< Acknowledgement bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */ + uint32_t : 30; /**< Reserved: Do not modify. */ +} mxc_ioman_ali_ack2_t; +/**@} end of group ioman_req_ack_bit_fields */ +/** + * @ingroup ioman + * @defgroup ioman_registers IOMAN Registers + * @{ + * Structure type for the IOMAN Register Interface. + * The table below shows the IOMAN Regsiter Offsets from the Base IOMAN Peripheral Address #MXC_BASE_IOMAN. + */ +typedef struct { + __IO uint32_t wud_req0; /**< Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ + __IO uint32_t wud_req1; /**< Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */ + __IO uint32_t wud_ack0; /**< Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ + __IO uint32_t wud_ack1; /**< Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */ + __IO uint32_t ali_req0; /**< Analog Input Request Register 0 (P0/P1/P2/P3) */ + __IO uint32_t ali_req1; /**< Analog Input Request Register 1 (P4/P5/P6/P7) */ + __IO uint32_t ali_ack0; /**< Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ + __IO uint32_t ali_ack1; /**< Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */ + __IO uint32_t ali_connect0; /**< Analog I/O Connection Control Register 0 */ + __IO uint32_t ali_connect1; /**< Analog I/O Connection Control Register 1 */ + __IO uint32_t spix_req; /**< SPIX I/O Mode Request */ + __IO uint32_t spix_ack; /**< SPIX I/O Mode Acknowledge */ + __IO uint32_t uart0_req; /**< UART0 I/O Mode Request */ + __IO uint32_t uart0_ack; /**< UART0 I/O Mode Acknowledge */ + __IO uint32_t uart1_req; /**< UART1 I/O Mode Request */ + __IO uint32_t uart1_ack; /**< UART1 I/O Mode Acknowledge */ + __IO uint32_t uart2_req; /**< UART2 I/O Mode Request */ + __IO uint32_t uart2_ack; /**< UART2 I/O Mode Acknowledge */ + __IO uint32_t uart3_req; /**< UART3 I/O Mode Request */ + __IO uint32_t uart3_ack; /**< UART3 I/O Mode Acknowledge */ + __IO uint32_t i2cm0_req; /**< I2C Master 0 I/O Request */ + __IO uint32_t i2cm0_ack; /**< I2C Master 0 I/O Acknowledge */ + __IO uint32_t i2cm1_req; /**< I2C Master 1 I/O Request */ + __IO uint32_t i2cm1_ack; /**< I2C Master 1 I/O Acknowledge */ + __IO uint32_t i2cm2_req; /**< I2C Master 2 I/O Request */ + __IO uint32_t i2cm2_ack; /**< I2C Master 2 I/O Acknowledge */ + __IO uint32_t i2cs_req; /**< I2C Slave I/O Request */ + __IO uint32_t i2cs_ack; /**< I2C Slave I/O Acknowledge */ + __IO uint32_t spim0_req; /**< SPI Master 0 I/O Mode Request */ + __IO uint32_t spim0_ack; /**< SPI Master 0 I/O Mode Acknowledge */ + __IO uint32_t spim1_req; /**< SPI Master 1 I/O Mode Request */ + __IO uint32_t spim1_ack; /**< SPI Master 1 I/O Mode Acknowledge */ + __IO uint32_t spim2_req; /**< SPI Master 2 I/O Mode Request */ + __IO uint32_t spim2_ack; /**< SPI Master 2 I/O Mode Acknowledge */ + __IO uint32_t spib_req; /**< SPI Bridge I/O Mode Request */ + __IO uint32_t spib_ack; /**< SPI Bridge I/O Mode Acknowledge */ + __IO uint32_t owm_req; /**< 1-Wire Master I/O Mode Request */ + __IO uint32_t owm_ack; /**< 1-Wire Master I/O Mode Acknowledge */ + __IO uint32_t spis_req; /**< SPI Slave I/O Mode Request */ + __IO uint32_t spis_ack; /**< SPI Slave I/O Mode Acknowledge */ + __RO uint32_t rsv0A0[24]; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t use_vddioh_0; /**< Enable VDDIOH Register 0 */ + __IO uint32_t use_vddioh_1; /**< Enable VDDIOH Register 1 */ + __IO uint32_t use_vddioh_2; /**< Enable VDDIOH Register 2 */ + __RO uint32_t rsv10C; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t pad_mode; /**< Pad Mode Control Register */ + __RO uint32_t rsv114[27]; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t wud_req2; /**< Wakeup Detect Mode Request Register 2 (Port 8) */ + __RO uint32_t rsv184; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t wud_ack2; /**< Wakeup Detect Mode Acknowledge Register 2 (Port 8) */ + __RO uint32_t rsv18C; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t ali_req2; /**< Analog Input Request Register 2 (Port 8) */ + __RO uint32_t rsv194; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t ali_ack2; /**< Analog Input Acknowledge Register 2 (Port 8) */ + __RO uint32_t rsv19C; /**< RESERVED: DO NOT MODIFY */ + __IO uint32_t ali_connect2; /**< Analog I/O Connection Control Register 2 */ +} mxc_ioman_regs_t; +/**@}*/ + +/* + Register offsets for module IOMAN. +*/ +/** + * @ingroup ioman_registers + * @defgroup ioman_reg_offs IOMAN Register Offsets + * @{ + * @details The @ref IOMAN_REGS_OFFS_TABLE "IOMAN Register Offset Table" + * shows the register offsets for the IOMAN registers from the base + * IOMAN peripheral address, #MXC_BASE_IOMAN. + * @anchor IOMAN_REGS_OFFS_TABLE + * | Register | Offset | + * | :----------- | ------:| + * | WUD_REQ0 | 0x0000 | + * | WUD_REQ1 | 0x0004 | + * | WUD_ACK0 | 0x0008 | + * | WUD_ACK1 | 0x000C | + * | ALI_REQ0 | 0x0010 | + * | ALI_REQ1 | 0x0014 | + * | ALI_ACK0 | 0x0018 | + * | ALI_ACK1 | 0x001C | + * | ALI_CONNECT0 | 0x0020 | + * | ALI_CONNECT1 | 0x0024 | + * | SPIX_REQ | 0x0028 | + * | SPIX_ACK | 0x002C | + * | UART0_REQ | 0x0030 | + * | UART0_ACK | 0x0034 | + * | UART1_REQ | 0x0038 | + * | UART1_ACK | 0x003C | + * | UART2_REQ | 0x0040 | + * | UART2_ACK | 0x0044 | + * | UART3_REQ | 0x0048 | + * | UART3_ACK | 0x004C | + * | I2CM0_REQ | 0x0050 | + * | I2CM0_ACK | 0x0054 | + * | I2CM1_REQ | 0x0058 | + * | I2CM1_ACK | 0x005C | + * | I2CM2_REQ | 0x0060 | + * | I2CM2_ACK | 0x0064 | + * | I2CS_REQ | 0x0068 | + * | I2CS_ACK | 0x006C | + * | SPIM0_REQ | 0x0070 | + * | SPIM0_ACK | 0x0074 | + * | SPIM1_REQ | 0x0078 | + * | SPIM1_ACK | 0x007C | + * | SPIM2_REQ | 0x0080 | + * | SPIM2_ACK | 0x0084 | + * | SPIB_REQ | 0x0088 | + * | SPIB_ACK | 0x008C | + * | OWM_REQ | 0x0090 | + * | OWM_ACK | 0x0094 | + * | SPIS_REQ | 0x0098 | + * | SPIS_ACK | 0x009C | + * | USE_VDDIOH_0 | 0x0100 | + * | USE_VDDIOH_1 | 0x0104 | + * | USE_VDDIOH_2 | 0x0108 | + * | PAD_MODE | 0x0110 | + * | WUD_REQ2 | 0x0180 | + * | WUD_ACK2 | 0x0188 | + * | ALI_REQ2 | 0x0190 | + * | ALI_ACK2 | 0x0198 | + * | ALI_CONNECT2 | 0x01A0 | + */ +#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) /**< WUD_REQ0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) /**< WUD_REQ1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) /**< WUD_ACK0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) /**< WUD_ACK1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) /**< ALI_REQ0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) /**< ALI_REQ1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) /**< ALI_ACK0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) /**< ALI_ACK1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) /**< ALI_CONNECT0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) /**< ALI_CONNECT1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) /**< SPIX_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) /**< SPIX_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) /**< UART0_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) /**< UART0_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) /**< UART1_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) /**< UART1_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) /**< UART2_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) /**< UART2_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) /**< UART3_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) /**< UART3_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) /**< I2CM0_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) /**< I2CM0_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) /**< I2CM1_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) /**< I2CM1_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) /**< I2CM2_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) /**< I2CM2_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) /**< I2CS_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) /**< I2CS_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) /**< SPIM0_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) /**< SPIM0_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) /**< SPIM1_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) /**< SPIM1_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) /**< SPIM2_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) /**< SPIM2_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) /**< SPIB_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) /**< SPIB_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) /**< OWM_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) /**< OWM_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) /**< SPIS_REQ Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) /**< SPIS_ACK Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) /**< USE_VDDIOH_0 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) /**< USE_VDDIOH_1 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) /**< USE_VDDIOH_2 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) /**< PAD_MODE Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) /**< WUD_REQ2 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) /**< WUD_ACK2 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) /**< ALI_REQ2 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) /**< ALI_ACK2 Register Offset from base IOMAN Peripheral Address. */ +#define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) /**< ALI_CONNECT2 Register Offset from base IOMAN Peripheral Address. */ +/**@}*/ + +/* + Field positions and masks for module IOMAN. +*/ +/** + * @ingroup ioman_registers + * @defgroup Bit and Field Positions Masks for the IOMAN Registers. + * @{ + */ +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 +#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) + +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8 +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS)) +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16 +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS)) +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24 +#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS)) + +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 +#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) + +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8 +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS)) +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16 +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS)) +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24 +#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS)) + +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 +#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) + +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8 +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS)) +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16 +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS)) +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24 +#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS)) + +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 +#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) + +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8 +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS)) +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16 +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS)) +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24 +#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS)) + +#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 +#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 +#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 +#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 +#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 +#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 +#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 +#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 +#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) +#define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 +#define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) +#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 +#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) +#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 +#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) + +#define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) +#define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 +#define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) +#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 +#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) +#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 +#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) + +#define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) +#define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 +#define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) +#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 +#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) +#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 +#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) + +#define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) +#define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 +#define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) +#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 +#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) +#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 +#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) + +#define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) +#define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 +#define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) +#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 +#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) +#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 +#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) + +#define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) +#define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 +#define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) +#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 +#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) +#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 +#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) + +#define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS)) +#define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4 +#define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS)) +#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5 +#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS)) +#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6 +#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS)) + +#define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0 +#define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS)) +#define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1 +#define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS)) +#define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2 +#define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS)) +#define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4 +#define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS)) +#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5 +#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS)) +#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6 +#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS)) + +#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 +#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) + +#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 +#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) + +#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 +#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) + +#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 +#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) + +#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4 +#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS)) + +#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4 +#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS)) + +#define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 +#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) + +#define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 +#define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) +#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 +#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) + +#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 +#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 +#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 +#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 +#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 +#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 +#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 +#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 +#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 +#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 +#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 +#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 +#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 +#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 +#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 +#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 +#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 +#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 +#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 +#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 +#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 +#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20 +#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 +#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 +#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 +#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16 +#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17 +#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20 +#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12 +#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12 +#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 +#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) +#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 +#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) + +#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 +#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) +#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 +#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) + +#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0 +#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS)) +#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 +#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 +#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) +#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 +#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) + +#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0 +#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS)) +#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 +#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 +#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) +#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 +#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) + +#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 +#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) +#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 +#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) + +#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0 +#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS)) + +#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0 +#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS)) + +#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0 +#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS)) + +#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0 +#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS)) + +/* + Generic field positions and masks +*/ +#define MXC_F_IOMAN_UART_REQ_IO_REQ MXC_F_IOMAN_UART0_REQ_IO_REQ +#define MXC_F_IOMAN_UART_ACK_IO_ACK MXC_F_IOMAN_UART0_ACK_IO_ACK +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_IOMAN_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h new file mode 100644 index 00000000000..babfd2399d0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h @@ -0,0 +1,212 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + * $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24665 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_MAA_REGS_H_ +#define _MXC_MAA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + + + +/** + * @ingroup icc_registers + * @defgroup maa_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module. +x * @{ + */ + +/** + * Structure type to access the MAA Peripheral Module Registers. + */ + typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000 MAA_CTRL - MAA Control, Configuration and Status */ + __IO uint32_t maws; /**< \b 0x0004 MAA_MAWS - MAA Word (Operand) Size, Big/Little Endian Mode Select */ +} mxc_maa_regs_t; +/**@} end of maa_registers group */ + + +/** + * @ingroup maa + * @defgroup maa_mem_segments Memory Segment Registers + * @brief Registers, Bit Masks and Bit Positions for the MAA Memory Mapped Segments + * @{ + */ +/** + * Structure type to access the MAA Peripheral Module Memory Mapped Registers. + */ +typedef struct { + __IO uint32_t seg0[32]; /* 0x0000-0x007C [128 bytes] MAA Memory Segment 0 */ + __IO uint32_t seg1[32]; /* 0x0080-0x00FC [128 bytes] MAA Memory Segment 1 */ + __IO uint32_t seg2[32]; /* 0x0100-0x017C [128 bytes] MAA Memory Segment 2 */ + __IO uint32_t seg3[32]; /* 0x0180-0x01FC [128 bytes] MAA Memory Segment 3 */ + __IO uint32_t seg4[32]; /* 0x0200-0x027C [128 bytes] MAA Memory Segment 4 */ + __IO uint32_t seg5[32]; /* 0x0280-0x02FC [128 bytes] MAA Memory Segment 5 */ +} mxc_maa_mem_regs_t; +/**@} end of maa_mem_segments group */ + +/** + * @ingroup maa_registers + * @defgroup MAA_Register_Offsets Register Offsets + * @brief MAA Register Offsets from the MAA Peripheral Module Base Address. + * @{ + */ +#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Address: \b 0x0000 */ +#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) /**< Offset from MAA Base Peripheral Address: \b 0x0004 */ +/**@} end of group MAA_Register_Offsets */ +/** + * @ingroup maa_mem_segments + * @defgroup MAA_Register_Mem_Offsets Register Offsets + * @brief MAA Memory Mapped Register Offsets from the MAA Peripheral Module Base Memory Mapped Address. + * @{ + */ +#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0000 */ +#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000080UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0080 */ +#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000100UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0100 */ +#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x00000180UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0180 */ +#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000200UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0200 */ +#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000280UL) /**< Offset from MAA Base Peripheral Memory Address: \b 0x0280 */ +/**@} end of group MAA_Register_Mem_Offsets */ + +/* + Field positions and masks for module MAA. +*/ +/** + * @ingroup maa_registers + * @defgroup maa_ctrl MAA_CTRL + * @brief Field Positions and Masks + */ +#define MXC_F_MAA_CTRL_START_POS 0 /**< START Position */ +#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) /**< START Mask */ +#define MXC_F_MAA_CTRL_OPSEL_POS 1 /**< OPSEL Position */ +#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< OPSEL Mask */ +#define MXC_F_MAA_CTRL_OCALC_POS 4 /**< OCALC Position */ +#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) /**< OCALC Mask */ +#define MXC_F_MAA_CTRL_IF_DONE_POS 5 /**< IF_DONE Position */ +#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) /**< IF_DONE Mask */ +#define MXC_F_MAA_CTRL_INTEN_POS 6 /**< INTEN Position */ +#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) /**< INTEN Mask */ +#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 /**< IF_ERROR Position */ +#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) /**< IF_ERROR Mask */ +#define MXC_F_MAA_CTRL_OFS_A_POS 8 /**< OFS_A Position */ +#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) /**< OFS_A Mask */ +#define MXC_F_MAA_CTRL_OFS_B_POS 10 /**< OFS_B Position */ +#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) /**< OFS_B Mask */ +#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 /**< OFS_EXP Position */ +#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) /**< OFS_EXP Mask */ +#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 /**< OFS_MOD Position */ +#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) /**< OFS_MOD Mask */ +#define MXC_F_MAA_CTRL_SEG_A_POS 16 /**< SEG_A Position */ +#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) /**< SEG_A Mask */ +#define MXC_F_MAA_CTRL_SEG_B_POS 20 /**< SEG_B Position */ +#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) /**< SEG_B Mask */ +#define MXC_F_MAA_CTRL_SEG_RES_POS 24 /**< SEG_RES Position */ +#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) /**< SEG_RES Mask */ +#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 /**< SEG_TMP Position */ +#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) /**< SEG_TMP Mask */ +/**@} end of maa_ctrl group */ + +/** + * @ingroup maa_registers + * @defgroup maa_maws MAA_MAWS + * @brief Field Positions and Masks + */ +#define MXC_F_MAA_MAWS_MODLEN_POS 0 /**< MODLEN Position */ +#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000007FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) /**< MODLEN Mask */ +#define MXC_F_MAA_MAWS_BYTESWAP_POS 15 /**< BYTESWAP Position */ +#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) /**< BYTESWAP Mask */ +/**@} end of group MAA_MAWS */ + + +/* + Field values and shifted values for module MAA. +*/ +/** + * @ingroup maa_ctrl + * @defgroup maa_oppsel MAA_OPSEL + * @brief MAA Operation Select - Field Values and Shifted Field Values. + */ +#define MXC_V_MAA_OPSEL_EXP ((uint32_t)(0x00000000UL)) /**< Field Value: OPSEL_EXP */ +#define MXC_V_MAA_OPSEL_SQR ((uint32_t)(0x00000001UL)) /**< Field Value: OPSEL_SQR */ +#define MXC_V_MAA_OPSEL_MUL ((uint32_t)(0x00000002UL)) /**< Field Value: OPSEL_MUL */ +#define MXC_V_MAA_OPSEL_SQRMUL ((uint32_t)(0x00000003UL)) /**< Field Value: OPSEL_SQRMUL */ +#define MXC_V_MAA_OPSEL_ADD ((uint32_t)(0x00000004UL)) /**< Field Value: OPSEL_ADD */ +#define MXC_V_MAA_OPSEL_SUB ((uint32_t)(0x00000005UL)) /**< Field Value: OPSEL_SUB */ + +#define MXC_S_MAA_OPSEL_EXP ((uint32_t)(MXC_V_MAA_OPSEL_EXP << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_EXP */ +#define MXC_S_MAA_OPSEL_SQR ((uint32_t)(MXC_V_MAA_OPSEL_SQR << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQR */ +#define MXC_S_MAA_OPSEL_MUL ((uint32_t)(MXC_V_MAA_OPSEL_MUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_MUL */ +#define MXC_S_MAA_OPSEL_SQRMUL ((uint32_t)(MXC_V_MAA_OPSEL_SQRMUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQRMUL */ +#define MXC_S_MAA_OPSEL_ADD ((uint32_t)(MXC_V_MAA_OPSEL_ADD << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_ADD */ +#define MXC_S_MAA_OPSEL_SUB ((uint32_t)(MXC_V_MAA_OPSEL_SUB << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SUB */ +/**@} end of group maa_opsel_values */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_MAA_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h new file mode 100644 index 00000000000..c26c8412ba3 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h @@ -0,0 +1,998 @@ +/** + * @file + * @brief MAX3263X device specific definitions for the core, peripherals, + * features, memory, and IRQs. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + * $Date: 2016-10-31 17:08:23 -0500 (Mon, 31 Oct 2016) $ + * $Revision: 24858 $ + * +*************************************************************************** */ + +/* **** Includes **** */ +#include + +/* Define to prevent redundant inclusion */ +#ifndef _MAX3263X_H_ +#define _MAX3263X_H_ + + +/** + * @ingroup cmsis_product + * @defgroup product_name MAX3263X + * @brief MAX3263X device specific definitions for the core, peripherals, + * features, memory, and IRQs. + * @details The MAX32630/MAX32631 is an ARM® + * Cortex®-M4F 32-bit microcontroller with a floating point + * unit, ideal for the emerging category of wearable medical and + * fitness applications. The architecture combines ultra-low power + * high-efficiency signal processing functionality with + * significantly reduced power consumption and ease of use. The + * device features four powerful and flexible power modes. A + * peripheral management unit (PMU) enables intelligent peripheral + * control with up to six channels to significantly reduce power + * consumption. Built-in dynamic clock gating and + * firmware-controlled power gating allows the user to optimize + * power for the specific application. Multiple SPI, UART and + * I²C serial interfaces, as well as 1-Wire® master and + * USB, allow for interconnection to a wide variety of external + * sensors. A four-input, 10-bit ADC with selectable references is + * available to monitor analog input from external sensors and + * meters. The small 100-ball WLP package provides a tiny, 4.37mm x + * 4.37mm footprint. The MAX32630/MAX32631 include + * a hardware AES engine. The @em MAX32631 is a secure + * version of the @em MAX32630. It incorporates a trust + * protection unit (TPU) with encryption and advanced security + * features. These features include a modular arithmetic + * accelerator (MAA) for fast ECDSA, a hardware PRNG entropy + * generator, and a secure boot loader. + * @{ + */ +#ifndef FALSE +/** + * @internal False + */ +#define FALSE (0) +#endif + +#ifndef TRUE +/** + * @internal True + */ +#define TRUE (1) +#endif + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined ( __GNUC__ ) +#define __weak __attribute__((weak)) /**< GNUC weak function keyword. */ +#elif defined ( __CC_ARM) +#define inline __inline /**< inline keyword for Keil compiler. */ +#pragma anon_unions +#endif +/**@}*/ +/** + * @ingroup product_name + * @defgroup nvic_table Nested Interrupt Vector Table (NVIC) + * Device specific interrupt request NVIC entries. + * @{ + */ +/** + * \MXIM_Device Nested Interrupt Vector Table (NVIC). + * @details + * NVIC Peripheral Entry numbers and Offsets are shown in the table below. + * + * | Entry | Offset | Peripheral | + * |-------: | ------: | :------------------------------------ | + * | 0x10 | 0x0040 | CLKMAN | + * | 0x11 | 0x0044 | PWRMAN | + * | 0x12 | 0x0048 | Flash Controller | + * | 0x13 | 0x004C | RTC Counter match with Compare 0 | + * | 0x14 | 0x0050 | RTC Counter match with Compare 1 | + * | 0x15 | 0x0054 | RTC Prescaler interval compare match | + * | 0x16 | 0x0058 | RTC Overflow | + * | 0x17 | 0x005C | Peripheral Management Unit (PMU/DMA) | + * | 0x18 | 0x0060 | USB | + * | 0x19 | 0x0064 | AES | + * | 0x1A | 0x0068 | MAA | + * | 0x1B | 0x006C | Watchdog 0 timeout | + * | 0x1C | 0x0070 | Watchdog 0 pre-window (fed too early)| + * | 0x1D | 0x0074 | Watchdog 1 timeout | + * | 0x1E | 0x0078 | Watchdog 1 pre-window (fed too early)| + * | 0x1F | 0x007C | GPIO Port 0 | + * | 0x20 | 0x0080 | GPIO Port 1 | + * | 0x21 | 0x0084 | GPIO Port 2 | + * | 0x22 | 0x0088 | GPIO Port 3 | + * | 0x23 | 0x008C | GPIO Port 4 | + * | 0x24 | 0x0090 | GPIO Port 5 | + * | 0x25 | 0x0094 | GPIO Port 6 | + * | 0x26 | 0x0098 | Timer 0 (32-bit, 16-bit #0) | + * | 0x27 | 0x009C | Timer 0 (16-bit #1) | + * | 0x28 | 0x00A0 | Timer 1 (32-bit, 16-bit #0) | + * | 0x29 | 0x00A4 | Timer 1 (16-bit #1) | + * | 0x2A | 0x00A8 | Timer 2 (32-bit, 16-bit #0) | + * | 0x2B | 0x00AC | Timer 2 (16-bit #1) | + * | 0x2C | 0x00B0 | Timer 3 (32-bit, 16-bit #0) | + * | 0x2D | 0x00B4 | Timer 3 (16-bit #1) | + * | 0x2E | 0x00B8 | Timer 4 (32-bit, 16-bit #0) | + * | 0x2F | 0x00BC | Timer 4 (16-bit #1) | + * | 0x30 | 0x00C0 | Timer 5 (32-bit, 16-bit #0) | + * | 0x31 | 0x00C4 | Timer 5 (16-bit #1) | + * | 0x32 | 0x00C8 | UART 0 | + * | 0x33 | 0x00CC | UART 1 | + * | 0x34 | 0x00D0 | UART 2 | + * | 0x35 | 0x00D4 | UART 3 | + * | 0x36 | 0x00D8 | Pulse Trains | + * | 0x37 | 0x00DC | I2C Master 0 | + * | 0x38 | 0x00E0 | I2C Master 1 | + * | 0x39 | 0x00E4 | I2C Master 2 | + * | 0x3A | 0x00E8 | I2C Slave | + * | 0x3B | 0x00EC | SPI Master 0 | + * | 0x3C | 0x00F0 | SPI Master 1 | + * | 0x3D | 0x00F4 | SPI Master 2 | + * | 0x3E | 0x00F8 | SPI Bridge | + * | 0x3F | 0x00FC | 1-Wire Master | + * | 0x40 | 0x0100 | ADC | + * | 0x41 | 0x0104 | SPI Slave | + * | 0x42 | 0x0108 | GPIO Port 7 | + * | 0x43 | 0x010C | GPIO Port 8 | + */ + +/** + * Enumeration type of all \MXIM_Device NVIC entries. + */ +typedef enum { + NonMaskableInt_IRQn = -14, /**< ARM Core : Non-maskable IRQ */ + HardFault_IRQn = -13, /**< ARM Core : Hard Fault IRQ */ + MemoryManagement_IRQn = -12, /**< ARM Core : Memory Management IRQ */ + BusFault_IRQn = -11, /**< ARM Core : Bus Fault IRQ */ + UsageFault_IRQn = -10, /**< ARM Core : Usage Fault IRQ */ + SVCall_IRQn = -5, /**< ARM Core : SVCall IRQ */ + DebugMonitor_IRQn = -4, /**< ARM Core : Debug Monitor IRQ */ + PendSV_IRQn = -2, /**< ARM Core : PendSV IRQ */ + SysTick_IRQn = -1, /**< ARM Core : SysTick IRQ */ + CLKMAN_IRQn = 0, /**< CLKMAN */ + PWRMAN_IRQn, /**< PWRMAN */ + FLC_IRQn, /**< Flash Controller */ + RTC0_IRQn, /**< RTC Counter match with Compare 0 */ + RTC1_IRQn, /**< RTC Counter match with Compare 1 */ + RTC2_IRQn, /**< RTC Prescaler interval compare match */ + RTC3_IRQn, /**< RTC Overflow */ + PMU_IRQn, /**< Peripheral Management Unit (PMU/DMA) */ + USB_IRQn, /**< USB */ + AES_IRQn, /**< AES */ + MAA_IRQn, /**< MAA */ + WDT0_IRQn, /**< Watchdog 0 timeout */ + WDT0_P_IRQn, /**< Watchdog 0 pre-window (fed too early) */ + WDT1_IRQn, /**< Watchdog 1 timeout */ + WDT1_P_IRQn, /**< Watchdog 1 pre-window (fed too early) */ + GPIO_P0_IRQn, /**< GPIO Port 0 */ + GPIO_P1_IRQn, /**< GPIO Port 1 */ + GPIO_P2_IRQn, /**< GPIO Port 2 */ + GPIO_P3_IRQn, /**< GPIO Port 3 */ + GPIO_P4_IRQn, /**< GPIO Port 4 */ + GPIO_P5_IRQn, /**< GPIO Port 5 */ + GPIO_P6_IRQn, /**< GPIO Port 6 */ + TMR0_0_IRQn, /**< Timer 0 (32-bit, 16-bit #0) */ + TMR0_1_IRQn, /**< Timer 0 (16-bit #1) */ + TMR1_0_IRQn, /**< Timer 1 (32-bit, 16-bit #0) */ + TMR1_1_IRQn, /**< Timer 1 (16-bit #1) */ + TMR2_0_IRQn, /**< Timer 2 (32-bit, 16-bit #0) */ + TMR2_1_IRQn, /**< Timer 2 (16-bit #1) */ + TMR3_0_IRQn, /**< Timer 3 (32-bit, 16-bit #0) */ + TMR3_1_IRQn, /**< Timer 3 (16-bit #1) */ + TMR4_0_IRQn, /**< Timer 4 (32-bit, 16-bit #0) */ + TMR4_1_IRQn, /**< Timer 4 (16-bit #1) */ + TMR5_0_IRQn, /**< Timer 5 (32-bit, 16-bit #0) */ + TMR5_1_IRQn, /**< Timer 5 (16-bit #1) */ + UART0_IRQn, /**< UART 0 */ + UART1_IRQn, /**< UART 1 */ + UART2_IRQn, /**< UART 2 */ + UART3_IRQn, /**< UART 3 */ + PT_IRQn, /**< Pulse Trains */ + I2CM0_IRQn, /**< I2C Master 0 */ + I2CM1_IRQn, /**< I2C Master 1 */ + I2CM2_IRQn, /**< I2C Master 2 */ + I2CS_IRQn, /**< I2C Slave */ + SPIM0_IRQn, /**< SPI Master 0 */ + SPIM1_IRQn, /**< SPI Master 1 */ + SPIM2_IRQn, /**< SPI Master 2 */ + SPIB_IRQn, /**< SPI Bridge */ + OWM_IRQn, /**< 1-Wire Master */ + AFE_IRQn, /**< ADC */ + SPIS_IRQn, /**< SPI Slave */ + GPIO_P7_IRQn, /**< GPIO Port 7 */ + GPIO_P8_IRQn, /**< GPIO Port 8 */ + MXC_IRQ_EXT_COUNT /**< Total number of non-core IRQ vectors. */ +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) /**< Total number of device IRQs inclusive of core and non-core IRQ vectors. */ +/**@}end of group nvic_table*/ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ +/** + * @ingroup product_name + * @defgroup Cortex_M4 Cortex-M Configuration + * @{ + */ +/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ +#define __CM4_REV 0x0100 /**< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /**< MPU is present */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for IRQ Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Using standard CMSIS SysTickConfig */ +#define __FPU_PRESENT 1 /**< FPU is Present */ +/**@} end of ingroup Cortex_M4*/ +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_max3263x.h" /*!< System Header */ + + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ +/** + * @ingroup product_name + * @{ + */ +#define MXC_FLASH_MEM_BASE 0x00000000UL /**< Internal Flash Memory Start Address. */ +#define MXC_FLASH_PAGE_SIZE 0x00002000UL /**< Internal Flash Memory Page Size. */ +#define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL /**< Internal Flash Memory Size. */ +#define MXC_SYS_MEM_BASE 0x20000000UL /**< System Memory Start Address. */ +#define MXC_SRAM_FULL_MEM_SIZE 0x00080000UL /**< Internal SRAM Size. */ +#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL /**< External Flash Memory Start Address, SPIX interface. */ + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/* + Base addresses and configuration settings for all MAX3263X peripheral modules. +*/ + + +/* *************************************************************************** */ +/* System Manager Settings */ + +#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL) +#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN) + + + +/* *************************************************************************** */ +/* System Clock Manager */ + +#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL) +#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) + + + +/* *************************************************************************** */ +/* System Power Manager */ + +#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL) +#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) + + + +/* *************************************************************************** */ +/* Real Time Clock */ + +#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL) +#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) +#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL) +#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) + +#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \ + i == 1 ? RTC1_IRQn : \ + i == 2 ? RTC2_IRQn : \ + i == 3 ? RTC3_IRQn : 0) + + + +/* *************************************************************************** */ +/* Power Sequencer */ + +#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) + + + +/* *************************************************************************** */ +/* System I/O Manager */ +/**@} end of ingroup product_name*/ +/** + * @ingroup ioman_registers + * @{ + */ +#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) /**< Base Peripheral Address for IOMAN */ +#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) /**< Pointer to the #mxc_ioman_regs_t structure representing the IOMAN Registers. */ +/**@}*/ + +/** + * @ingroup product_name + * @{ + */ +/* *************************************************************************** */ +/* Shadow Trim Registers */ + +#define MXC_BASE_TRIM ((uint32_t)0x40001000UL) +#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM) + + + +/* *************************************************************************** */ +/* Flash Controller */ + +#define MXC_BASE_FLC ((uint32_t)0x40002000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) + +#define MXC_FLC_PAGE_SIZE_SHIFT (13) +#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) +#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT + + + +/* *************************************************************************** */ +/* Instruction Cache */ + +#define MXC_BASE_ICC ((uint32_t)0x40003000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) + + +/**@} end of ingroup product_name*/ +/* *************************************************************************** */ +/* SPI XIP Interface */ +/** + * @ingroup spix_registers + * @{ + */ +#define MXC_BASE_SPIX ((uint32_t)0x40004000UL) /**< SPIX Base Peripheral Address. */ +#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) /**< SPIX pointer to the #mxc_spix_regs_t register structure type. */ +/**@} end of ingroup spix_registers*/ + +/** + * @ingroup product_name + * @{ + */ +/* *************************************************************************** */ +/* Peripheral Management Unit */ + +#define MXC_CFG_PMU_CHANNELS (6) + +#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL) +#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) +#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL) +#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) +#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL) +#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) +#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL) +#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) +#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL) +#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) +#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL) +#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) + +#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \ + (i) == 1 ? MXC_BASE_PMU1 : \ + (i) == 2 ? MXC_BASE_PMU2 : \ + (i) == 3 ? MXC_BASE_PMU3 : \ + (i) == 4 ? MXC_BASE_PMU4 : \ + (i) == 5 ? MXC_BASE_PMU5 : 0) + +#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \ + (i) == 1 ? MXC_PMU1 : \ + (i) == 2 ? MXC_PMU2 : \ + (i) == 3 ? MXC_PMU3 : \ + (i) == 4 ? MXC_PMU4 : \ + (i) == 5 ? MXC_PMU5 : 0) + +#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \ + (p) == MXC_PMU1 ? 1 : \ + (p) == MXC_PMU2 ? 2 : \ + (p) == MXC_PMU3 ? 3 : \ + (p) == MXC_PMU4 ? 4 : \ + (p) == MXC_PMU5 ? 5 : -1) + +/* *************************************************************************** */ +/* USB Device Controller */ + +#define MXC_BASE_USB ((uint32_t)0x40100000UL) +#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) + +#define MXC_USB_MAX_PACKET (64) +#define MXC_USB_NUM_EP (8) + + + +/* *************************************************************************** */ +/* CRC-16/CRC-32 Engine */ + +#define MXC_BASE_CRC ((uint32_t)0x40006000UL) +#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) +#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL) +#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) + +/* *************************************************************************** */ +/* Pseudo-random number generator (PRNG) */ + +#define MXC_BASE_PRNG ((uint32_t)0x40007000UL) +#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG) + +/* *************************************************************************** */ +/* AES Cryptographic Engine */ + +#define MXC_BASE_AES ((uint32_t)0x40007400UL) +#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) +#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL) +#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) + +/* *************************************************************************** */ +/* MAA Cryptographic Engine */ + +#define MXC_BASE_MAA ((uint32_t)0x40007800UL) +#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) +#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL) +#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) + +/* *************************************************************************** */ +/* Trust Protection Unit (TPU) */ + +#define MXC_BASE_TPU ((uint32_t)0x40007000UL) +#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) +#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL) +#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) +/**@} end of ingroup product_name*/ +/* *************************************************************************** */ +/* Watchdog Timers */ +/** + * @ingroup wdt_registers + * @{ + */ +#define MXC_CFG_WDT_INSTANCES (2) /**< Define for the number of timers on the \MXIM_Device */ + +#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) /**< Base Peripheral Address for WDT 0 */ +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT0 Registers. */ +#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) /**< Base Peripheral Address for WDT 1 */ +#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT1 Registers. */ +/** + * Macro that returns the WDT[i] IRQ, where i=0 to i < #MXC_CFG_WDT_INSTANCES. + */ +#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \ + (i) == 1 ? WDT1_IRQn : 0) + +#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \ + (i) == 1 ? WDT1_P_IRQn : 0) +/** + * Macro to return the base address for a requested Watchdog Timer index number. + * @p i WDT instance number. + * @p returns the base peripheral address for the requested Watchdog Timer instance. + */ +#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ + (i) == 1 ? MXC_BASE_WDT1 : 0) +/** + * Macro to return a pointer to the #mxc_tmr_regs_t object for the requested Watchdog Timer. + * @p i Watchdog Timer instance number. + * @p returns a pointer to a #mxc_wdt_regs_t for the requested WDT number. + */ +#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ + (i) == 1 ? MXC_WDT1 : 0) +/** + * Macro to return the index number for a given #mxc_wdt_regs_t structure. + * @p p pointer to a #mxc_wdt_regs_t structure. + * @p returns a watchdog timer instance number. + */ +#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \ + (i) == MXC_WDT1 ? 1: -1) + +/**@} end of ingroup wdt_registers */ +/* *************************************************************************** */ +/* Always-On Watchdog Timer */ +/** + * @ingroup wdt2_registers + * @{ + */ +#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) /**< Base Peripheral Address for WDT 2 */ +#define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2) /**< Pointer to the #mxc_wdt2_regs_t structure representing the WDT2 hardware registers. */ +/**@} end of ingroup wdt2_registers */ + + +/* *************************************************************************** */ +/* General Purpose I/O Ports (GPIO) */ +/** + * @ingroup gpio_registers + * @{ + */ +#define MXC_GPIO_NUM_PORTS (9) /**< Number of GPIO Ports for the \MXIM_Device. */ +#define MXC_GPIO_MAX_PINS_PER_PORT (8) /**< Number of port pins per port for the \MXIM_Device */ + +#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) /**< GPIO Base Peripheral Offset */ +#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) /**< Pointer to the #mxc_gpio_regs_t object representing GPIO Registers. */ +/** + * Macro that returns the GPIO[i] IRQ, where i=0 to i < #MXC_GPIO_NUM_PORTS. + */ +#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \ + (i) == 1 ? GPIO_P1_IRQn : \ + (i) == 2 ? GPIO_P2_IRQn : \ + (i) == 3 ? GPIO_P3_IRQn : \ + (i) == 4 ? GPIO_P4_IRQn : \ + (i) == 5 ? GPIO_P5_IRQn : \ + (i) == 6 ? GPIO_P6_IRQn : \ + (i) == 7 ? GPIO_P7_IRQn : \ + (i) == 8 ? GPIO_P8_IRQn : 0) + +/**@} end of ingroup gpio_registers */ + +/* *************************************************************************** */ +/* 16/32 bit Timer/Counters */ +/** + * @ingroup tmr_registers + * @{ + */ +#define MXC_CFG_TMR_INSTANCES (6) /**< Define for the number of timers on the \MXIM_Device */ +#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) /**< Base Address for Timer 0 */ +#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 0 */ +#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) /**< Base Address for Timer 1 */ +#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 1 */ +#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) /**< Base Address for Timer 2 */ +#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 2 */ +#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) /**< Base Address for Timer 3 */ +#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 3 */ +#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) /**< Base Address for Timer 4 */ +#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 4 */ +#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) /**< Base Address for Timer 5 */ +#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 5 */ + +/** + * Macro that returns an #IRQn_Type for the requested 32-bit timer interrupt. + */ +#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ + (i) == 1 ? TMR1_0_IRQn : \ + (i) == 2 ? TMR2_0_IRQn : \ + (i) == 3 ? TMR3_0_IRQn : \ + (i) == 4 ? TMR4_0_IRQn : \ + (i) == 5 ? TMR5_0_IRQn : 0) +/** + * Macro that returns an IRQn_Type for the requested 16-bit timer interrupt number. + */ +#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ + (i) == 1 ? TMR1_0_IRQn : \ + (i) == 2 ? TMR2_0_IRQn : \ + (i) == 3 ? TMR3_0_IRQn : \ + (i) == 4 ? TMR4_0_IRQn : \ + (i) == 5 ? TMR5_0_IRQn : \ + (i) == 6 ? TMR0_1_IRQn : \ + (i) == 7 ? TMR1_1_IRQn : \ + (i) == 8 ? TMR2_1_IRQn : \ + (i) == 9 ? TMR3_1_IRQn : \ + (i) == 10 ? TMR4_1_IRQn : \ + (i) == 11 ? TMR5_1_IRQn : 0) +/** + * Macro to return the base address for a given Timer index number. + * @p i Timer instance number. + * @p returns the base peripheral address for the requested timer instance. + */ +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : 0) +/** + * Macro to return a pointer to the #mxc_tmr_regs_t structure for a given Timer Instance. + * @p i Timer instance number. + * @p returns a pointer to a #mxc_tmr_regs_t for the requested timer number. + */ +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : \ + (i) == 4 ? MXC_TMR4 : \ + (i) == 5 ? MXC_TMR5 : 0) +/** + * Macro to return the index number for a given pointer to a #mxc_tmr_regs_t structure. + * @p p pointer to a #mxc_tmr_regs_t structure. + * @p returns a timer instance number. + */ +#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : -1) + +/**@} end of ingroup tmr_registers */ + +/** + * @ingroup product_name + * @{ + */ +/* *************************************************************************** */ +/* Pulse Train Generation */ +#define MXC_CFG_PT_INSTANCES (16) + +#define MXC_BASE_PTG ((uint32_t)0x40011000UL) +#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) +#define MXC_BASE_PT0 ((uint32_t)0x40011020UL) +#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) +#define MXC_BASE_PT1 ((uint32_t)0x40011040UL) +#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) +#define MXC_BASE_PT2 ((uint32_t)0x40011060UL) +#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) +#define MXC_BASE_PT3 ((uint32_t)0x40011080UL) +#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) +#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL) +#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) +#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL) +#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) +#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL) +#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) +#define MXC_BASE_PT7 ((uint32_t)0x40011100UL) +#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) +#define MXC_BASE_PT8 ((uint32_t)0x40011120UL) +#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) +#define MXC_BASE_PT9 ((uint32_t)0x40011140UL) +#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) +#define MXC_BASE_PT10 ((uint32_t)0x40011160UL) +#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) +#define MXC_BASE_PT11 ((uint32_t)0x40011180UL) +#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) +#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL) +#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12) +#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL) +#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13) +#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL) +#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14) +#define MXC_BASE_PT15 ((uint32_t)0x40011200UL) +#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15) + +#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \ + (i) == 1 ? MXC_BASE_PT1 : \ + (i) == 2 ? MXC_BASE_PT2 : \ + (i) == 3 ? MXC_BASE_PT3 : \ + (i) == 4 ? MXC_BASE_PT4 : \ + (i) == 5 ? MXC_BASE_PT5 : \ + (i) == 6 ? MXC_BASE_PT6 : \ + (i) == 7 ? MXC_BASE_PT7 : \ + (i) == 8 ? MXC_BASE_PT8 : \ + (i) == 9 ? MXC_BASE_PT9 : \ + (i) == 10 ? MXC_BASE_PT10 : \ + (i) == 11 ? MXC_BASE_PT11 : \ + (i) == 12 ? MXC_BASE_PT12 : \ + (i) == 13 ? MXC_BASE_PT13 : \ + (i) == 14 ? MXC_BASE_PT14 : \ + (i) == 15 ? MXC_BASE_PT15 : 0) + +#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \ + (i) == 1 ? MXC_PT1 : \ + (i) == 2 ? MXC_PT2 : \ + (i) == 3 ? MXC_PT3 : \ + (i) == 4 ? MXC_PT4 : \ + (i) == 5 ? MXC_PT5 : \ + (i) == 6 ? MXC_PT6 : \ + (i) == 7 ? MXC_PT7 : \ + (i) == 8 ? MXC_PT8 : \ + (i) == 9 ? MXC_PT9 : \ + (i) == 10 ? MXC_PT10 : \ + (i) == 11 ? MXC_PT11 : \ + (i) == 12 ? MXC_PT12 : \ + (i) == 13 ? MXC_PT13 : \ + (i) == 14 ? MXC_PT14 : \ + (i) == 15 ? MXC_PT15 : 0) + +#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \ + (p) == MXC_PT1 ? 1 : \ + (p) == MXC_PT2 ? 2 : \ + (p) == MXC_PT3 ? 3 : \ + (p) == MXC_PT4 ? 4 : \ + (p) == MXC_PT5 ? 5 : \ + (p) == MXC_PT6 ? 6 : \ + (p) == MXC_PT7 ? 7 : \ + (p) == MXC_PT8 ? 8 : \ + (p) == MXC_PT9 ? 9 : \ + (p) == MXC_PT10 ? 10 : \ + (p) == MXC_PT11 ? 11 : \ + (p) == MXC_PT12 ? 12 : \ + (p) == MXC_PT13 ? 13 : \ + (p) == MXC_PT14 ? 14 : \ + (p) == MXC_PT15 ? 15 : -1) + + + +/* *************************************************************************** */ +/* UART / Serial Port Interface */ + +#define MXC_CFG_UART_INSTANCES (4) +#define MXC_UART_FIFO_DEPTH (32) + +#define MXC_BASE_UART0 ((uint32_t)0x40012000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) +#define MXC_BASE_UART1 ((uint32_t)0x40013000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) /**< UART Port 1 Base Address */ +#define MXC_BASE_UART2 ((uint32_t)0x40014000UL) +#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) +#define MXC_BASE_UART3 ((uint32_t)0x40015000UL) +#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) +#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL) +#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO) +#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL) +#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO) +#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL) +#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO) +#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL) +#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO) + +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : \ + (i) == 2 ? UART2_IRQn : \ + (i) == 3 ? UART3_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : \ + (i) == 2 ? MXC_BASE_UART2 : \ + (i) == 3 ? MXC_BASE_UART3 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : \ + (i) == 2 ? MXC_UART2 : \ + (i) == 3 ? MXC_UART3 : 0) + +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ + (p) == MXC_UART1 ? 1 : \ + (p) == MXC_UART2 ? 2 : \ + (p) == MXC_UART3 ? 3 : -1) + +#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \ + (i) == 1 ? MXC_BASE_UART1_FIFO : \ + (i) == 2 ? MXC_BASE_UART2_FIFO : \ + (i) == 3 ? MXC_BASE_UART3_FIFO : 0) + +#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \ + (i) == 1 ? MXC_UART1_FIFO : \ + (i) == 2 ? MXC_UART2_FIFO : \ + (i) == 3 ? MXC_UART3_FIFO : 0) + + + +/* *************************************************************************** */ +/* I2C Master Interface */ + +#define MXC_CFG_I2CM_INSTANCES (3) +#define MXC_I2CM_FIFO_DEPTH (8) + +#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL) +#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) +#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL) +#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) +#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL) +#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2) +#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL) +#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO) +#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL) +#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO) +#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL) +#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO) + +#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \ + (i) == 1 ? I2CM1_IRQn : \ + (i) == 2 ? I2CM2_IRQn : 0) + +#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ + (i) == 1 ? MXC_BASE_I2CM1 : \ + (i) == 2 ? MXC_BASE_I2CM2 : 0) + +#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ + (i) == 1 ? MXC_I2CM1 : \ + (i) == 2 ? MXC_I2CM2 : 0) + +#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \ + (p) == MXC_I2CM1 ? 1 : \ + (p) == MXC_I2CM2 ? 2 : -1) + +#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_FIFO : \ + (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0) + +#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \ + (i) == 1 ? MXC_I2CM1_FIFO : \ + (i) == 2 ? MXC_I2CM2_FIFO : 0) + + + +/* *************************************************************************** */ +/* I2C Slave Interface (Mailbox type) */ + +#define MXC_CFG_I2CS_INSTANCES (1) +#define MXC_CFG_I2CS_BUFFER_SIZE (32) + +#define MXC_BASE_I2CS ((uint32_t)0x40019000UL) +#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS) + +#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0) + +#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0) + +#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0) + +#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1) + +/* *************************************************************************** */ +/* SPI Master Interface */ + +#define MXC_CFG_SPIM_INSTANCES (3) +#define MXC_CFG_SPIM_FIFO_DEPTH (16) + +#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL) +#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0) +#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL) +#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1) +#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL) +#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2) +#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL) +#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO) +#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL) +#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO) +#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL) +#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO) + +#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \ + (i) == 1 ? SPIM1_IRQn : \ + (i) == 2 ? SPIM2_IRQn : 0) + +#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \ + (i) == 1 ? MXC_BASE_SPIM1 : \ + (i) == 2 ? MXC_BASE_SPIM2 : 0) + +#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \ + (i) == 1 ? MXC_SPIM1 : \ + (i) == 2 ? MXC_SPIM2 : 0) + +#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \ + (p) == MXC_SPIM1 ? 1 : \ + (p) == MXC_SPIM2 ? 2 : -1) + +#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \ + (i) == 1 ? MXC_BASE_SPIM1_FIFO : \ + (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0) + +#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \ + (i) == 1 ? MXC_SPIM1_FIFO : \ + (i) == 2 ? MXC_SPIM2_FIFO : 0) + + + +/* *************************************************************************** */ +/* 1-Wire Master Interface */ + +#define MXC_CFG_OWM_INSTANCES (1) + +#define MXC_BASE_OWM ((uint32_t)0x4001E000UL) +#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) + +#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0) + +#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0) + +#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0) + +#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1) + + +/* *************************************************************************** */ +/* ADC / AFE */ + +#define MXC_CFG_ADC_FIFO_DEPTH (32) + +#define MXC_BASE_ADC ((uint32_t)0x4001F000UL) +#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) + + + +/* *************************************************************************** */ +/* SPIB AHB-to-SPI Bridge */ + +#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL) +#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB) + + + +/* *************************************************************************** */ +/* SPI Slave Interface */ + +#define MXC_BASE_SPIS ((uint32_t)0x40020000UL) +#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS) +#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL) +#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO) + + + +/* *************************************************************************** */ +/* Bit Shifting */ + +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/* *************************************************************************** */ + +#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) + +/* *************************************************************************** */ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + + +/* *************************************************************************** */ + +/* SCB CPACR Register Definitions */ +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ +/**@} end of ingroup product_name */ +#endif /* _MAX3263X_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/mxc_device.h new file mode 100644 index 00000000000..b3b9ffe5fbe --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/mxc_device.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-23 15:28:53 -0500 (Wed, 23 Mar 2016) $ + * $Revision: 22067 $ + * + ******************************************************************************/ + +#ifndef _MXC_DEVICE_H_ +#define _MXC_DEVICE_H_ + +#include "max3263x.h" + +#ifndef TARGET +#error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV +#error TARGET_REV NOT DEFINED +#endif + +#if((TARGET_REV == 0x4131) || (TARGET_REV == 0x4132)) +// A1 or A2 +#define MXC_ADC_REV 0 +#define MXC_AES_REV 0 +#define MXC_CRC_REV 0 +#define MXC_FLC_REV 0 +#define MXC_GPIO_REV 0 +#define MXC_I2CM_REV 0 +#define MXC_I2CS_REV 0 +#define MXC_ICC_REV 0 +#define MXC_MAA_REV 0 +#define MXC_OWM_REV 0 +#define MXC_PMU_REV 0 +#define MXC_PRNG_REV 0 +#define MXC_PT_REV 0 +#define MXC_RTC_REV 0 +#define MXC_SPIM_REV 0 +#define MXC_SPIS_REV 0 +#define MXC_SPIX_REV 0 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 0 +#define MXC_USB_REV 0 +#define MXC_WDT2_REV 0 +#define MXC_WDT_REV 0 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif /* if(TARGET_REV == 0x4132) */ + +#endif /* _MXC_DEVICE_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h new file mode 100644 index 00000000000..93f94517d82 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h @@ -0,0 +1,218 @@ +/** + * @file + * @brief Type definitions for the 1-Wire Master Interface + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:22:03 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24666 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_OWM_REGS_H_ +#define _MXC_OWM_REGS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +///@cond +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + + +/** + * @ingroup owm + * @defgroup owm_registers Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ +/** + * Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register. + */ +typedef struct { + __IO uint32_t cfg; /**< \b 0x0000: OWM_CFG Register - 1-Wire Master Configuration */ + __IO uint32_t clk_div_1us; /**< \b 0x0004: OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */ + __IO uint32_t ctrl_stat; /**< \b 0x0008: OWM_CTRL_STAT Register - 1-Wire Master Control/Status */ + __IO uint32_t data; /**< \b 0x000C: OWM_DATA Register - 1-Wire Master Data Buffer */ + __IO uint32_t intfl; /**< \b 0x0010: OWM_INTFL Register - 1-Wire Master Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x0014: OWM_INTEN Register - 1-Wire Master Interrupt Enables */ +} mxc_owm_regs_t; +/**@} end of group owm_registers */ + +/** + * @ingroup owm_registers + * @defgroup OWM_Register_Offsets Register Offsets + * @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address. + * @{ + */ +#define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:\b 0x0000:*/ +#define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:\b 0x0004:*/ +#define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:\b 0x0008:*/ +#define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:\b 0x000C:*/ +#define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:\b 0x0010:*/ +#define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:\b 0x0014:*/ +/**@} end of group OWM_Register_Offsets */ + +/* + Field positions and masks for module OWM. +*/ +/** + * @ingroup owm_registers + * @defgroup owm_cfg OWM_CFG + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */ +#define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */ +#define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */ +#define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */ +#define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */ +#define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */ +#define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */ +#define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */ +#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */ +#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */ +#define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */ +#define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */ +#define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */ +#define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */ +#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */ +#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */ +/**@} end of group owm_cfg*/ +/** + * @ingroup owm_registers + * @defgroup owm_clk_div OWM_CLK_DIV + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */ +#define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */ +/**@} end of group owm_clk_cfg*/ +/** + * @ingroup owm_registers + * @defgroup owm_ctrl_stat OWM_CTRL_STAT + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */ +#define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */ +#define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */ +#define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */ +#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */ +#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */ +#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */ +#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */ +#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */ +#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */ +#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */ +#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */ +#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */ +#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */ +/**@} end of group owm_ctrl*/ +/** + * @ingroup owm_registers + * @defgroup owm_data OWM_DATA + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */ +#define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */ +/**@} end of group owm_data*/ +/** + * @ingroup owm_registers + * @defgroup owm_intfl OWM_INTFL + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */ +#define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */ +#define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */ +#define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */ +#define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */ +#define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */ +#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */ +#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */ +#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */ +#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */ +/**@} end of group owm_intfl*/ +/** + * @ingroup owm_registers + * @defgroup owm_inten OWM_INTEN + * @brief Field Positions and Masks + */ +#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */ +#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */ +#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */ +#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */ +#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */ +#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */ +#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */ +#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */ +#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */ +#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */ +/**@} end of group owm_inten*/ +/** + * @ingroup owm_cfg + * @{ + */ +#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */ +#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */ +/**@}*/ +/** + * @ingroup owm_ctrl_stat + * @{ + */ +#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */ +#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */ + +#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */ +#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */ +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_OWM_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h new file mode 100644 index 00000000000..38fb30eeddd --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h @@ -0,0 +1,411 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the PMU Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24667 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_PMU_REGS_H_ +#define _MXC_PMU_REGS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ +/** + * @ingroup pmuGroup + * @defgroup pmu_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the PMU Module. + * @{ + */ +/** + * Structure type for the PMU Registers + */ +typedef struct { + __IO uint32_t dscadr; /**< \b 0x0000: PMU Channel Next Descriptor Address */ + __IO uint32_t cfg; /**< \b 0x0004: PMU Channel Configuration */ + __IO uint32_t loop; /**< \b 0x0008: PMU Channel Loop Counters */ + __RO uint32_t rsv00C[5]; /**< \b 0x000C-0x001C: RESERVED */ +} mxc_pmu_regs_t; +/**@} end of group pmu_registers */ + +/* + Register offsets for module PMU. +*/ +/** + * @ingroup pmu_registers + * @defgroup PMU_Register_Offsets Register Offsets + * @brief PMU Register Offsets from the PMU Base Peripheral Address. + * @{ + */ +#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) /**< Offset from the PMU Base Address: \b 0x0000*/ +#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) /**< Offset from the PMU Base Address: \b 0x0004*/ +#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PMU Base Address: \b 0x0008*/ +/**@} end of group PMU_Register_Offsets */ + +/* + Field positions and masks for module PMU. +*/ +///@cond +#define MXC_F_PMU_CFG_ENABLE_POS 0 +#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) +#define MXC_F_PMU_CFG_LL_STOPPED_POS 2 +#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) +#define MXC_F_PMU_CFG_MANUAL_POS 3 +#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) +#define MXC_F_PMU_CFG_BUS_ERROR_POS 4 +#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) +#define MXC_F_PMU_CFG_TO_STAT_POS 6 +#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) +#define MXC_F_PMU_CFG_TO_SEL_POS 11 +#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) +#define MXC_F_PMU_CFG_PS_SEL_POS 14 +#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) +#define MXC_F_PMU_CFG_INTERRUPT_POS 16 +#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) +#define MXC_F_PMU_CFG_INT_EN_POS 17 +#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) +#define MXC_F_PMU_CFG_BURST_SIZE_POS 24 +#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) + +#define MXC_F_PMU_LOOP_COUNTER_0_POS 0 +#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) +#define MXC_F_PMU_LOOP_COUNTER_1_POS 16 +#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) + +/* + Field values +*/ + +#define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL)) +#define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL)) + +#define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL)) +#define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL)) +#define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL)) +#define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL)) + +/* Op codes */ +#define PMU_MOVE_OP 0 +#define PMU_WRITE_OP 1 +#define PMU_WAIT_OP 2 +#define PMU_JUMP_OP 3 +#define PMU_LOOP_OP 4 +#define PMU_POLL_OP 5 +#define PMU_BRANCH_OP 6 +#define PMU_TRANSFER_OP 7 + +/* Bit values used in all decroptiors */ +#define PMU_NO_INTERRUPT 0 /**< Interrupt flag is NOT set at end of channel execution */ +#define PMU_INTERRUPT 1 /**< Interrupt flag is set at end of channel execution */ + +#define PMU_NO_STOP 0 /**< Do not stop channel after this descriptor ends */ +#define PMU_STOP 1 /**< Halt PMU channel after this descriptor ends */ + +/* Interrupt and Stop bit positions */ +#define PMU_INT_POS 3 +#define PMU_STOP_POS 4 + +/* MOVE descriptor bit values */ +#define PMU_MOVE_READ_8_BIT 0 /**< Read size = 8 */ +#define PMU_MOVE_READ_16_BIT 1 /**< Read size = 16 */ +#define PMU_MOVE_READ_32_BIT 2 /**< Read size = 32 */ + +#define PMU_MOVE_READ_NO_INC 0 /**< read address not incremented */ +#define PMU_MOVE_READ_INC 1 /**< Auto-Increment read address */ + +#define PMU_MOVE_WRITE_8_BIT 0 /**< Write Size = 8 */ +#define PMU_MOVE_WRITE_16_BIT 1 /**< Write Size = 16 */ +#define PMU_MOVE_WRITE_32_BIT 2 /**< Write Size = 32 */ + +#define PMU_MOVE_WRITE_NO_INC 0 /**< Write address not incremented */ +#define PMU_MOVE_WRITE_INC 1 /**< Auto_Increment write address */ + +#define PMU_MOVE_NO_CONT 0 /**< MOVE does not rely on previous MOVE */ +#define PMU_MOVE_CONT 1 /**< MOVE continues from read/write address and INC values defined in previous MOVE */ + +/* MOVE bit positions */ +#define PMU_MOVE_READS_POS 5 +#define PMU_MOVE_READI_POS 7 +#define PMU_MOVE_WRITES_POS 8 +#define PMU_MOVE_WRITEI_POS 10 +#define PMU_MOVE_CONT_POS 11 +#define PMU_MOVE_LEN_POS 12 + +/* WRITE descriptor bit values */ +#define PMU_WRITE_MASKED_WRITE_VALUE 0 /**< Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */ +#define PMU_WRITE_PLUS_1 1 /**< Value = READ_VALUE + 1 */ +#define PMU_WRITE_MINUS_1 2 /**< Value = READ_VALUE - 1 */ +#define PMU_WRITE_SHIFT_RT_1 3 /**< Value = READ_VALUE >> 1 */ +#define PMU_WRITE_SHIFT_LT_1 4 /**< Value = READ_VALUE << 1 */ +#define PMU_WRITE_ROTATE_RT_1 5 /**< Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */ +#define PMU_WRITE_ROTATE_LT_1 6 /**< Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */ +#define PMU_WRITE_NOT_READ_VAL 7 /**< Value = ~READ_VALUE */ +#define PMU_WRITE_XOR_MASK 8 /**< Value = READ_VALUE XOR WRITE_MASK */ +#define PMU_WRITE_OR_MASK 9 /**< Value = READ_VALUE | WRITE_MASK */ +#define PMU_WRITE_AND_MASK 10 /**< Value = READ_VALUE & WRITE_MASK */ + +/* WRITE bit positions */ +#define PMU_WRITE_METHOD_POS 8 + +/* WAIT descriptor bit values */ +#define PMU_WAIT_SEL_0 0 /**< Select the interrupt source */ +#define PMU_WAIT_SEL_1 1 + +/* WAIT bit positions */ +#define PMU_WAIT_WAIT_POS 5 +#define PMU_WAIT_SEL_POS 6 + +/* LOOP descriptor bit values */ +#define PMU_LOOP_SEL_COUNTER0 0 /**< select Counter0 to count down from */ +#define PMU_LOOP_SEL_COUNTER1 1 /**< select Counter1 to count down from */ + +/* LOOP bit positions */ +#define PMU_LOOP_SEL_COUNTER_POS 5 + +/* POLL descriptor bit values */ +#define PMU_POLL_OR 0 /**< polling ends when at least one mask bit matches expected data */ +#define PMU_POLL_AND 1 /**< polling ends when all mask bits matches expected data */ + +/* POLL bit positions */ +#define PMU_POLL_AND_POS 7 + +/* BRANCH descriptor bit values */ +#define PMU_BRANCH_OR 0 /**< branch when any mask bit = or != expected data (based on = or != branch type) */ +#define PMU_BRANCH_AND 1 /**< branch when all mask bit = or != expected data (based on = or != branch type) */ + +#define PMU_BRANCH_TYPE_NOT_EQUAL 0 /**< Branch when polled data != expected data */ +#define PMU_BRANCH_TYPE_EQUAL 1 /**< Branch when polled data = expected data */ +#define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /**< Branch when polled data <= expected data */ +#define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /**< Branch when polled data >= expected data */ +#define PMU_BRANCH_TYPE_LESSER 4 /**< Branch when polled data < expected data */ +#define PMU_BRANCH_TYPE_GREATER 5 /**< Branch when polled data > expected data */ + +/* BRANCH bit positions */ +#define PMU_BRANCH_AND_POS 7 +#define PMU_BRANCH_TYPE_POS 8 + +/* TRANSFER descriptor bit values */ +#define PMU_TX_READ_8_BIT 0 /**< Read size = 8 */ +#define PMU_TX_READ_16_BIT 1 /**< Read size = 16 */ +#define PMU_TX_READ_32_BIT 2 /**< Read size = 32 */ + +#define PMU_TX_READ_NO_INC 0 /**< read address not incremented */ +#define PMU_TX_READ_INC 1 /**< Auto-Increment read address */ + +#define PMU_TX_WRITE_8_BIT 0 /**< Write Size = 8 */ +#define PMU_TX_WRITE_16_BIT 1 /**< Write Size = 16 */ +#define PMU_TX_WRITE_32_BIT 2 /**< Write Size = 32 */ + +#define PMU_TX_WRITE_NO_INC 0 /**< Write address not incremented */ +#define PMU_TX_WRITE_INC 1 /**< Auto_Increment write address */ + +/* TRANSFER bit positions */ +#define PMU_TX_READS_POS 5 +#define PMU_TX_READI_POS 7 +#define PMU_TX_WRITES_POS 8 +#define PMU_TX_WRITEI_POS 10 +#define PMU_TX_LEN_POS 12 +#define PMU_TX_BS_POS 26 + +/* PMU interrupt sources for the WAIT opcode */ +#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6)) +#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22)) +#define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26)) +#define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27)) +#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28)) +#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29)) +#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30)) +#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31)) +#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0)) +#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1)) +#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2)) +#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14)) +#define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20)) +#define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27)) +#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28)) +#define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29)) +#define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30)) +#define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31)) +#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0)) +#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20)) +#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27)) +#define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28)) +#define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29)) +#define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30)) +#define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31)) +#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0)) +#define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1)) +#define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2)) +#define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3)) +#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4)) + +/* PMU interrupt sources for the TRANSFER opcode */ +#define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0)) +#define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1)) +#define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2)) +#define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3)) +#define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4)) +#define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5)) +#define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6)) +#define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7)) +#define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8)) +#define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9)) +#define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10)) +#define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11)) +#define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12)) +#define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13)) +#define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14)) +#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15)) +#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16)) +#define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17)) +#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18)) +#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19)) +#define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20)) +#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21)) +#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22)) +#define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23)) +#define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24)) +///@endcond +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PMU_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/prng_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/prng_regs.h new file mode 100644 index 00000000000..5b892b3a282 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/prng_regs.h @@ -0,0 +1,98 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2015-11-02 13:19:39 -0600 (Mon, 02 Nov 2015) $ + * $Revision: 19838 $ + * + ******************************************************************************/ + +#ifndef _MXC_PRNG_REGS_H_ +#define _MXC_PRNG_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t user_entropy; /* 0x0000 PRNG User Entropy and Status */ + __IO uint32_t rnd_num; /* 0x0004 PRNG Seed Output */ +} mxc_prng_regs_t; + +/* + Register offsets for module PRNG. +*/ + +#define MXC_R_PRNG_OFFS_USER_ENTROPY ((uint32_t)0x00000000UL) +#define MXC_R_PRNG_OFFS_RND_NUM ((uint32_t)0x00000004UL) + +/* + Field positions and masks for module PRNG. +*/ + +#define MXC_F_PRNG_USER_ENTROPY_VALUE_POS 0 +#define MXC_F_PRNG_USER_ENTROPY_VALUE ((uint32_t)(0x000000FFUL << MXC_F_PRNG_USER_ENTROPY_VALUE_POS)) +#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS 8 +#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY ((uint32_t)(0x00000001UL << MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PRNG_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/pt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/pt_regs.h new file mode 100644 index 00000000000..3e02b5a0e3c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pt_regs.h @@ -0,0 +1,404 @@ +/** + * @file + * @brief Type definitions for the Pulse Train Engine. + * + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24669 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_PT_REGS_H_ +#define _MXC_PT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup pulsetrain + * @defgroup pulsetrain_registers Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ + +/** + * Structure type for the Pulse Train Global module registers allowing direct 32-bit access to each register. + */ + typedef struct { + __IO uint32_t enable; /**< \b 0x0000: \c PTG_ENABLE Register - Global Enable/Disable Controls for All Pulse Trains. */ + __IO uint32_t resync; /**< \b 0x0004: \c PTG_RESYNC Register - Global Resync (All Pulse Trains) Control. */ + __IO uint32_t intfl; /**< \b 0x0008: \c PTG_INTFL Register - Pulse Train Interrupt Flags. */ + __IO uint32_t inten; /**< \b 0x000C: \c PTG_INTEN Register - Pulse Train Interrupt Enable/Disable. */ +} mxc_ptg_regs_t; + +/** + * Structure type for the Pulse Train configuration registers allowing direct 32-bit access to each register. + */ +typedef struct { + __IO uint32_t rate_length; /**< \b 0x0000:\c PT_RATE_LENGTH Register - Pulse Train Configuration. */ + __IO uint32_t train; /**< \b 0x0004:\c PT_TRAIN Register - Pulse Train Output Pattern. */ + __IO uint32_t loop; /**< \b 0x0008:\c PT_LOOP Register - Pulse Train Loop Configuration. */ + __IO uint32_t restart; /**< \b 0x000C:\c PT_RESTART Register - Pulse Train Auto-Restart Configuration. */ +} mxc_pt_regs_t; +/**@} end of pulsetrain_registers group*/ + +/* + Register offsets for module PT. +*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PTG_Register_Offsets Global Register Offsets + * @brief Pluse Train Global Control Register Offsets from the Pulse Train Global Base Peripheral Address. + * @{ + */ +#define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) /**< Offset from the PTG Base Peripheral Address:\b 0x0000 */ +#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) /**< Offset from the PTG Base Peripheral Address:\b 0x0004 */ +#define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the PTG Base Peripheral Address:\b 0x0008 */ +#define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the PTG Base Peripheral Address:\b 0x000C */ +/**@} end of group PTG_Register_Offsets*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_Register_Offsets Register Offsets: Configuration + * @brief Pluse Train Configuration Register Offsets from the Pulse Train Base Peripheral Address. + * @{ + */ +#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from the PT Base Peripheral Address:\b 0x0000 */ +#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) /**< Offset from the PT Base Peripheral Address:\b 0x0004 */ +#define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PT Base Peripheral Address:\b 0x0008 */ +#define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) /**< Offset from the PT Base Peripheral Address:\b 0x000C */ +/**@} end of group PT_Register_Offsets*/ + +/* + Field positions and masks for module PT. +*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_ENABLE_Register PT_ENABLE + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_ENABLE_PT0_POS 0 /**< PT0 Position */ +#define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) /**< PT0 Mask */ +#define MXC_F_PT_ENABLE_PT1_POS 1 /**< PT1 Position */ +#define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) /**< PT1 Mask */ +#define MXC_F_PT_ENABLE_PT2_POS 2 /**< PT2 Position */ +#define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) /**< PT2 Mask */ +#define MXC_F_PT_ENABLE_PT3_POS 3 /**< PT3 Position */ +#define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) /**< PT3 Mask */ +#define MXC_F_PT_ENABLE_PT4_POS 4 /**< PT4 Position */ +#define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) /**< PT4 Mask */ +#define MXC_F_PT_ENABLE_PT5_POS 5 /**< PT5 Position */ +#define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) /**< PT5 Mask */ +#define MXC_F_PT_ENABLE_PT6_POS 6 /**< PT6 Position */ +#define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) /**< PT6 Mask */ +#define MXC_F_PT_ENABLE_PT7_POS 7 /**< PT7 Position */ +#define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) /**< PT7 Mask */ +#define MXC_F_PT_ENABLE_PT8_POS 8 /**< PT8 Position */ +#define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) /**< PT8 Mask */ +#define MXC_F_PT_ENABLE_PT9_POS 9 /**< PT9 Position */ +#define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) /**< PT9 Mask */ +#define MXC_F_PT_ENABLE_PT10_POS 10 /**< PT10 Position */ +#define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) /**< PT10 Mask */ +#define MXC_F_PT_ENABLE_PT11_POS 11 /**< PT11 Position */ +#define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) /**< PT11 Mask */ +#define MXC_F_PT_ENABLE_PT12_POS 12 /**< PT12 Position */ +#define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) /**< PT12 Mask */ +#define MXC_F_PT_ENABLE_PT13_POS 13 /**< PT13 Position */ +#define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) /**< PT13 Mask */ +#define MXC_F_PT_ENABLE_PT14_POS 14 /**< PT14 Position */ +#define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) /**< PT14 Mask */ +#define MXC_F_PT_ENABLE_PT15_POS 15 /**< PT15 Position */ +#define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) /**< PT15 Mask */ +/**@} PT_ENABLE_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_RESYNC_Register PT_RESYNC + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_RESYNC_PT0_POS 0 /**< PT0 Position */ +#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) /**< PT0 Mask */ +#define MXC_F_PT_RESYNC_PT1_POS 1 /**< PT1 Position */ +#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) /**< PT1 Mask */ +#define MXC_F_PT_RESYNC_PT2_POS 2 /**< PT2 Position */ +#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) /**< PT2 Mask */ +#define MXC_F_PT_RESYNC_PT3_POS 3 /**< PT3 Position */ +#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) /**< PT3 Mask */ +#define MXC_F_PT_RESYNC_PT4_POS 4 /**< PT4 Position */ +#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) /**< PT4 Mask */ +#define MXC_F_PT_RESYNC_PT5_POS 5 /**< PT5 Position */ +#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) /**< PT5 Mask */ +#define MXC_F_PT_RESYNC_PT6_POS 6 /**< PT6 Position */ +#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) /**< PT6 Mask */ +#define MXC_F_PT_RESYNC_PT7_POS 7 /**< PT7 Position */ +#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) /**< PT7 Mask */ +#define MXC_F_PT_RESYNC_PT8_POS 8 /**< PT8 Position */ +#define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) /**< PT8 Mask */ +#define MXC_F_PT_RESYNC_PT9_POS 9 /**< PT9 Position */ +#define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) /**< PT9 Mask */ +#define MXC_F_PT_RESYNC_PT10_POS 10 /**< PT10 Position */ +#define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) /**< PT10 Mask */ +#define MXC_F_PT_RESYNC_PT11_POS 11 /**< PT11 Position */ +#define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) /**< PT11 Mask */ +#define MXC_F_PT_RESYNC_PT12_POS 12 /**< PT12 Position */ +#define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) /**< PT12 Mask */ +#define MXC_F_PT_RESYNC_PT13_POS 13 /**< PT13 Position */ +#define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) /**< PT13 Mask */ +#define MXC_F_PT_RESYNC_PT14_POS 14 /**< PT14 Position */ +#define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) /**< PT14 Mask */ +#define MXC_F_PT_RESYNC_PT15_POS 15 /**< PT15 Position */ +#define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) /**< PT15 Mask */ +/**@} PT_RESYNC_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_INTFL_Register PT_INTFL + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_INTFL_PT0_POS 0 /**< PT0 Position */ +#define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) /**< PT0 Mask */ +#define MXC_F_PT_INTFL_PT1_POS 1 /**< PT1 Position */ +#define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) /**< PT1 Mask */ +#define MXC_F_PT_INTFL_PT2_POS 2 /**< PT2 Position */ +#define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) /**< PT2 Mask */ +#define MXC_F_PT_INTFL_PT3_POS 3 /**< PT3 Position */ +#define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) /**< PT3 Mask */ +#define MXC_F_PT_INTFL_PT4_POS 4 /**< PT4 Position */ +#define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) /**< PT4 Mask */ +#define MXC_F_PT_INTFL_PT5_POS 5 /**< PT5 Position */ +#define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) /**< PT5 Mask */ +#define MXC_F_PT_INTFL_PT6_POS 6 /**< PT6 Position */ +#define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) /**< PT6 Mask */ +#define MXC_F_PT_INTFL_PT7_POS 7 /**< PT7 Position */ +#define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) /**< PT7 Mask */ +#define MXC_F_PT_INTFL_PT8_POS 8 /**< PT8 Position */ +#define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) /**< PT8 Mask */ +#define MXC_F_PT_INTFL_PT9_POS 9 /**< PT9 Position */ +#define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) /**< PT9 Mask */ +#define MXC_F_PT_INTFL_PT10_POS 10 /**< PT10 Position */ +#define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) /**< PT10 Mask */ +#define MXC_F_PT_INTFL_PT11_POS 11 /**< PT11 Position */ +#define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) /**< PT11 Mask */ +#define MXC_F_PT_INTFL_PT12_POS 12 /**< PT12 Position */ +#define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) /**< PT12 Mask */ +#define MXC_F_PT_INTFL_PT13_POS 13 /**< PT13 Position */ +#define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) /**< PT13 Mask */ +#define MXC_F_PT_INTFL_PT14_POS 14 /**< PT14 Position */ +#define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) /**< PT14 Mask */ +#define MXC_F_PT_INTFL_PT15_POS 15 /**< PT15 Position */ +#define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) /**< PT15 Mask */ +/**@} PT_INTFL_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_INTEN_Register PT_INTEN + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_INTEN_PT0_POS 0 /**< PT0 Position */ +#define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) /**< PT0 Mask */ +#define MXC_F_PT_INTEN_PT1_POS 1 /**< PT1 Position */ +#define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) /**< PT1 Mask */ +#define MXC_F_PT_INTEN_PT2_POS 2 /**< PT2 Position */ +#define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) /**< PT2 Mask */ +#define MXC_F_PT_INTEN_PT3_POS 3 /**< PT3 Position */ +#define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) /**< PT3 Mask */ +#define MXC_F_PT_INTEN_PT4_POS 4 /**< PT4 Position */ +#define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) /**< PT4 Mask */ +#define MXC_F_PT_INTEN_PT5_POS 5 /**< PT5 Position */ +#define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) /**< PT5 Mask */ +#define MXC_F_PT_INTEN_PT6_POS 6 /**< PT6 Position */ +#define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) /**< PT6 Mask */ +#define MXC_F_PT_INTEN_PT7_POS 7 /**< PT7 Position */ +#define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) /**< PT7 Mask */ +#define MXC_F_PT_INTEN_PT8_POS 8 /**< PT8 Position */ +#define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) /**< PT8 Mask */ +#define MXC_F_PT_INTEN_PT9_POS 9 /**< PT9 Position */ +#define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) /**< PT9 Mask */ +#define MXC_F_PT_INTEN_PT10_POS 10 /**< PT10 Position*/ +#define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) /**< PT10 Mask */ +#define MXC_F_PT_INTEN_PT11_POS 11 /**< PT11 Position*/ +#define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) /**< PT11 Mask */ +#define MXC_F_PT_INTEN_PT12_POS 12 /**< PT12 Position*/ +#define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) /**< PT12 Mask */ +#define MXC_F_PT_INTEN_PT13_POS 13 /**< PT13 Position*/ +#define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) /**< PT13 Mask */ +#define MXC_F_PT_INTEN_PT14_POS 14 /**< PT14 Position*/ +#define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) /**< PT14 Mask */ +#define MXC_F_PT_INTEN_PT15_POS 15 /**< PT15 Position*/ +#define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) /**< PT15 Mask */ +/**@} PT_INTEN_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_RATE_LENGTH_Register PT_RATE_LENGTH + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_CONTROL Position */ +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_CONTROL Mask */ +#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< MODE Position */ +#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< MODE Mask */ +/**@} PT_RATE_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_LOOP_Register PT_LOOP + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_LOOP_COUNT_POS 0 /**< COUNT Position */ +#define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< COUNT Mask */ +#define MXC_F_PT_LOOP_DELAY_POS 16 /**< DELAY Position */ +#define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< DELAY Mask */ +/**@}PT_LOOP_Register*/ +/** + * @ingroup pulsetrain_registers + * @defgroup PT_RESTART_Register PT_RESTART + * @brief Field Positions and Masks + * @{ + */ +#define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< PT_X_SELECT Position */ +#define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< PT_X_SELECT Mask */ +#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< ON_PT_X_LOOP_EXIT Position */ +#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< ON_PT_X_LOOP_EXIT Mask */ +#define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< PT_Y_SELECT Position */ +#define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< PT_Y_SELECT Mask */ +#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< ON_PT_Y_LOOP_EXIT Position */ +#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< ON_PT_Y_LOOP_EXIT Mask */ +/**@} PT_RESTART_Register */ + + +/* + Field values and shifted values for module PT. +*/ +/** + * @ingroup PT_RATE_LENGTH_Register + * @defgroup pt_mode_v_sv Mode Field Values and Shifted Values + * @brief Mode selection values and shifted values to set the PT_RATE_LENGTH register MODE Field. + */ +#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) /**< Value for 32-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) /**< Value for SQUARE_WAVE. */ +#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) /**< Value for 2-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) /**< Value for 3-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) /**< Value for 4-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) /**< Value for 5-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) /**< Value for 6-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) /**< Value for 7-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) /**< Value for 8-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) /**< Value for 9-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) /**< Value for 10-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) /**< Value for 11-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) /**< Value for 12-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) /**< Value for 13-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) /**< Value for 14-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) /**< Value for 15-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) /**< Value for 16-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) /**< Value for 17-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) /**< Value for 18-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) /**< Value for 19-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) /**< Value for 20-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) /**< Value for 21-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) /**< Value for 22-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) /**< Value for 23-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) /**< Value for 24-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) /**< Value for 25-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) /**< Value for 26-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) /**< Value for 27-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) /**< Value for 28-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) /**< Value for 29-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) /**< Value for 30-BIT. */ +#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) /**< Value for 31-BIT. */ + +#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 32-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for SQUARE_WAVE. */ +#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 2-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 3-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 4-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 5-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 6-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 7-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 8-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 9-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 10-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 11-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 12-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 13-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 14-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 15-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 16-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 17-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 18-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 19-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 20-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 21-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 22-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 23-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 24-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 25-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 26-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 27-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 28-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 29-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 30-BIT. */ +#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 31-BIT. */ +/**@} pt_mode_v_sv*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PT_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrman_regs.h new file mode 100644 index 00000000000..cd08bc5e631 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrman_regs.h @@ -0,0 +1,435 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_PWRMAN_REGS_H_ +#define _MXC_PWRMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/** + * @brief Defines PAD Modes for Wake Up Detection. + */ +typedef enum { + /** WUD Mode for Selected PAD = Clear/Activate */ + MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, + /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ + MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, + /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ + MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, + /** WUD Mode for Selected PAD = No pad state change */ + MXC_E_PWRMAN_PAD_MODE_NONE +} +mxc_pwrman_pad_mode_t; + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ + __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ + __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ + __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ + __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ + __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */ + __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */ + __IO uint32_t wud_seen2; /* 0x0024 Wake-up Detect Status for P8 */ + __RO uint32_t rsv028[2]; /* 0x0028-0x002C */ + __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */ + __RO uint32_t rsv034; /* 0x0034 */ + __IO uint32_t die_type; /* 0x0038 Die Type ID Register */ + __IO uint32_t base_part_num; /* 0x003C Base Part Number */ + __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ + __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ + __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ +} mxc_pwrman_regs_t; + + +/* + Register offsets for module PWRMAN. +*/ + +#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) +#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) +#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN2 ((uint32_t)0x00000024UL) +#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL) +#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) +#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) +#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) +#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) +#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) + + +/* + Field positions and masks for module PWRMAN. +*/ + +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) + +#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0 +#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1 +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3 +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4 +#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5 +#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6 +#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS)) + +#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0 +#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1 +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3 +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4 +#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5 +#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6 +#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS)) + +#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0 +#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1 +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS)) + +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000007FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16 +#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS)) +#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS)) + +#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0 +#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS)) + +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) + +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) + +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) + +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PWRMAN_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h new file mode 100644 index 00000000000..22929e99fe8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h @@ -0,0 +1,431 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_PWRSEQ_REGS_H_ +#define _MXC_PWRSEQ_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ + __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ + __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ + __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ + __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */ + __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ + __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ + __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */ + __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ + __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ + __RO uint32_t rsv028; /* 0x0028 */ + __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */ + __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */ + __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */ + __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */ + __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */ +} mxc_pwrseq_regs_t; + + +/* + Register offsets for module PWRSEQ. +*/ + +#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) +#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) +#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) +#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) +#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) +#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) +#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) +#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL) +#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) +#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) +#define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL) +#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL) +#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL) +#define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL) +#define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL) + + +/* + Field positions and masks for module PWRSEQ. +*/ + +#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 +#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3 +#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4 +#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5 +#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6 +#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13 +#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15 +#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19 +#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21 +#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23 +#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24 +#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25 +#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26 +#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27 +#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28 +#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29 +#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30 +#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31 +#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS)) + +#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0 +#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1 +#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2 +#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3 +#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4 +#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5 +#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6 +#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8 +#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10 +#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12 +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13 +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14 +#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16 +#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17 +#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18 +#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19 +#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS)) + +#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0 +#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2 +#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4 +#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6 +#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8 +#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10 +#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12 +#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS)) + +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3 +#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6 +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8 +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10 +#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16 +#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20 +#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)) + +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4 +#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5 +#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6 +#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7 +#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8 +#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9 +#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10 +#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS)) + +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21 +#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS)) + +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS)) + +#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0 +#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS)) +#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16 +#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS)) + +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2 +#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4 +#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5 +#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8 +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10 +#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 +#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14 +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15 +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18 +#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21 +#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22 +#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23 +#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24 +#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS)) + +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS)) + +#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0 +#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS)) +#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8 +#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS)) +#define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28 +#define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS)) +#define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29 +#define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS)) +#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30 +#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS)) +#define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31 +#define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS)) + +#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0 +#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS)) +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1 +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS)) +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2 +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS)) +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3 +#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS)) +#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4 +#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS)) + +#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0 +#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS)) +#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4 +#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS)) + +#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0 +#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS)) + +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0 +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS)) +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1 +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS)) +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2 +#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS)) +#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3 +#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS)) +#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24 +#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PWRSEQ_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h new file mode 100644 index 00000000000..d3ac3810915 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h @@ -0,0 +1,362 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the Real-Time Clock. + * + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24670 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_RTC_REGS_H_ +#define _MXC_RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +/// @cond +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ + +/** + * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register. + */ + typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: RTC_CTRL Register - RTC Timer Control */ + __IO uint32_t timer; /**< \b 0x0004: RTC_TIMER Register - RTC Timer Count Value */ + __IO uint32_t comp[2]; /**< \b 0x0008-0x000C: RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */ + __IO uint32_t flags; /**< \b 0x0010: RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */ + __IO uint32_t snz_val; /**< \b 0x0014: RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */ + __IO uint32_t inten; /**< \b 0x0018: RTC_INTEN Register - Interrupt Enable Controls */ + __IO uint32_t prescale; /**< \b 0x001C: RTC_PRESCALE Register - RTC Timer Prescale Setting */ + __RO uint32_t rsv020; /**< \b 0x0020: RESERVED */ + __IO uint32_t prescale_mask; /**< \b 0x0024: RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */ + __IO uint32_t trim_ctrl; /**< \b 0x0028: RTC_TRIM_CTRL Register - RTC Timer Trim Controls */ + __IO uint32_t trim_value; /**< \b 0x002C: RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */ +} mxc_rtctmr_regs_t; + + +/** + * Structure type for access to the RTC CFG hardware. + */ +typedef struct { + __IO uint32_t nano_cntr; /**< \b 0x0000: - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */ + __IO uint32_t clk_ctrl; /**< \b 0x0004: - RTCCFG_CLK_CTRL - RTC Clock Control Settings */ + __RO uint32_t rsv008; /**< \b 0x0008: - RESERVED */ + __IO uint32_t osc_ctrl; /**< \b 0x000C: - RTCCFG_OSC_CTRL - RTC Oscillator Control */ +} mxc_rtccfg_regs_t; +/**@} end of group rtc_registers.*/ + +/* + Register offsets for module RTC. +*/ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address. + * @{ + */ +#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0000 */ +#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0004 */ +#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0008 */ +#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:\b 0x000C */ +#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0010 */ +#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0014 */ +#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0018 */ +#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:\b 0x001C */ +#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0024 */ +#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0028 */ +#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:\b 0x002C */ +/**@} end of group RTC_Register_Offsets */ +/** + * @ingroup rtc_registers + * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets + * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address. + * @{ + */ +#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0000 */ +#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:\b 0x0004 */ +#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:\b 0x000C */ +/**@} end of group RTCCFG_Register_Offsets */ + +/* + Field positions and masks for module RTC. +*/ +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL_Register RTC_CTRL + * @{ + */ +#define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */ +#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */ +#define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */ +#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */ +#define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */ +#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */ +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */ +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */ +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */ +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */ +#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */ +#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */ +#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */ +#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */ +#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */ +#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */ +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */ +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */ +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */ +#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */ +#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */ +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */ +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */ +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */ +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */ +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */ +#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */ +#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */ +#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */ +#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */ +#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */ +/**@} end of group RTC_CTRL*/ +/** + * @ingroup rtc_registers + * @defgroup RTC_FLAGS_Register RTC_FLAGS + * @{ + */ +#define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */ +#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */ +#define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */ +#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */ +#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */ +#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */ +#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */ +#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */ +#define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */ +#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */ +#define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */ +#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */ +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */ +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */ +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */ +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */ +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */ +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */ +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */ +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */ +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */ +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */ +#define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */ +#define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */ +#define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */ +#define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */ +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */ +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */ +/**@} end of group RTC_FLAGS_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL. + * @{ + */ +#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */ +#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */ +/**@} end of group RTC_SNZ_VAL_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_INTEN_Register RTC_INTEN. + * @{ + */ +#define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */ +#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */ +#define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */ +#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */ +#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */ +#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */ +#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */ +#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */ +#define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */ +#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */ +/**@} end of group RTC_INTEN_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_PRESCALE_Register RTC_PRESCALE. + * @{ + */ +#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */ +#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */ +/**@} end of group RTC_INTEN_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK. + * @{ + */ +#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */ +#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */ +/**@} end of group RTC_PRESCALE_MASK_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL. + * @{ + */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */ +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */ +/**@} end of group RTC_TRIM_CTRL_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE. + * @{ + */ +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */ +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */ +#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */ +#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */ +/**@} end of group RTC_TRIM_VALUE_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR. + * @{ + */ +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */ +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */ +/**@} end of group RTC_NANO_CNTR_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL. + * @{ + */ +#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */ +#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */ +#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */ +#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */ +#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */ +#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */ +/**@} end of group RTC_CLK_CTRL_Register */ +/** + * @ingroup rtc_registers + * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL. + * @{ + */ +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */ +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */ +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */ +#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */ +#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */ +/**@} end of group RTC_OSC_CTRL_Register */ + +/* + Field values +*/ +/** + * @ingroup RTC_CTRL_Register + * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values + * @{ + */ +#define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */ +#define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */ +#define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */ +/**@} end of group rtc_snz_mode_values */ +/** + * @ingroup RTC_PRESCALE_Register + * @defgroup rtc_prescale_values RTC Prescale Values + * @{ + */ +#define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/ +#define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/ +/**@} end of group rtc_prescale_values*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_RTC_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/spib_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/spib_regs.h new file mode 100644 index 00000000000..827d6ea3a3f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spib_regs.h @@ -0,0 +1,244 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_SPIB_REGS_H_ +#define _MXC_SPIB_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */ + __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */ + __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */ + __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */ + __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */ +} mxc_spib_regs_t; + + +/* + Register offsets for module SPIB. +*/ + +#define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) +#define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL) +#define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL) +#define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL) + + +/* + Field positions and masks for module SPIB. +*/ + +#define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0 +#define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) +#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2 +#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) +#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8 +#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS)) +#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12 +#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS)) +#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16 +#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) +#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18 +#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) + +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0 +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1 +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2 +#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) + +#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0 +#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) +#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1 +#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) +#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2 +#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) + +#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0 +#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) +#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1 +#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) +#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2 +#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) + +#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0 +#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS)) +#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1 +#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS)) +#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2 +#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) +#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8 +#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS)) +#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16 +#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS)) + + + +/* + Field values and shifted values for module SPIB. +*/ + +#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) + +#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) +#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) + +#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) +#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) + +#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) +#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) +#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) + +#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) + +#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) +#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) +#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) + +#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) +#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) + +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) + +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) + +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) +#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) + +#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) +#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) + +#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) +#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) + +#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) +#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) + +#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) +#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) + +#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) +#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) + +#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) +#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) + +#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL)) +#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL)) + +#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) +#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SPIB_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/spim_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/spim_regs.h new file mode 100644 index 00000000000..bcc0536b08d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spim_regs.h @@ -0,0 +1,332 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24672 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_SPIM_REGS_H_ +#define _MXC_SPIM_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + + +/** + * @ingroup spim + * @defgroup spim_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module. + * @{ + */ + +/** + * Structure type to access the SPIM Peripheral Module Registers + */ +typedef struct { + __IO uint32_t mstr_cfg; /**< \b 0x0000: SPIM_MSTR_CFG Register - SPI Master Configuration Register */ + __IO uint32_t ss_sr_polarity; /**< \b 0x0004: SPIM_SS_SR_POLARITY Register - SPI Master Polarity Control for SS and SR Signals */ + __IO uint32_t gen_ctrl; /**< \b 0x0008: SPIM_GEN_CTRL Register - SPI Master General Control Register */ + __IO uint32_t fifo_ctrl; /**< \b 0x000C: SPIM_FIFO_CTRL Register - SPI Master FIFO Control Register */ + __IO uint32_t spcl_ctrl; /**< \b 0x0010: SPIM_SPCL_CTRL Register - SPI Master Special Mode Controls */ + __IO uint32_t intfl; /**< \b 0x0014: SPIM_INTFL Register - SPI Master Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x0018: SPIM_INTEN Register - SPI Master Interrupt Enable/Disable Settings */ + __IO uint32_t simple_headers; /**< \b 0x001C: SPIM_SIMPLE_HEADERS Register - SPI Master Simple Mode Transaction Headers */ +} mxc_spim_regs_t; + + +/** + * @ingroup spim_registers + * @defgroup spim_fifos SPIM TX and RX FIFOs + * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types. + * @{ + */ +/** + * Structure type for the SPIM Transmit and Receive FIFOs. + */ + typedef struct { + union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */ + __IO uint8_t trans_8[2048]; /**< 8-bit access to Transmit FIFO */ + __IO uint16_t trans_16[1024]; /**< 16-bit access to Transmit FIFO */ + __IO uint32_t trans_32[512]; /**< 32-bit access to Transmit FIFO */ + }; + union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */ + __IO uint8_t rslts_8[2048]; /**< 8-bit access to Receive FIFO */ + __IO uint16_t rslts_16[1024]; /**< 16-bit access to Receive FIFO */ + __IO uint32_t rslts_32[512]; /**< 32-bit access to Receive FIFO */ + }; +} mxc_spim_fifo_regs_t; +/**@} end of group spim_fifos */ +/**@} end of group spim_registers */ + + +/* + Register offsets for module SPIM. +*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_Register_Offsets Register Offsets + * @brief SPI Master Register Offsets from the SPIM[n] Base Peripheral Address, where \c n \c = SPIM Instance Number. + * @{ + */ +#define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base Address: \b 0x0000*/ +#define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) /**< Offset from SPIM[n] Base Address: \b 0x0004*/ +#define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIM[n] Base Address: \b 0x0008*/ +#define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIM[n] Base Address: \b 0x000C*/ +#define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIM[n] Base Address: \b 0x0010*/ +#define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIM[n] Base Address: \b 0x0014*/ +#define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIM[n] Base Address: \b 0x0018*/ +#define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL) /**< Offset from SPIM[n] Base Address: \b 0x001C*/ +/**@} end of group SPIM_Register_Offsets*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_FIFO_Offsets FIFO Offsets + * @brief SPI Master FIFO Offsets from the SPIM[n] Base FIFO Address, where \c n \c = SPIM Instance Number. + * @{ + */ +#define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base FIFO Address: \b 0x0000*/ +#define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from SPIM[n] Base FIFO Address: \b 0x0800*/ +/**@} end of group SPIM_FIFO_Offsets*/ + +/* + Field positions and masks for module SPIM. +*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_MSTR_CFG_Register SPIM_MSTR_CFG + * @brief Field Positions and Bit Masks for the SPIM_MSTR_CFG register + * @{ + */ +#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0 /**< SLAVE_SEL Position */ +#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Mask */ +#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3 /**< THREE_WIRE_MODE Position */ +#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS)) /**< THREE_WIRE_MODE Mask */ +#define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4 /**< SPI_MODE Position */ +#define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS)) /**< SPI_MODE Mask */ +#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6 /**< PAGE_SIZE Position */ +#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)) /**< PAGE_SIZE Mask */ +#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8 /**< SCK_HI_CLK Position */ +#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Mask */ +#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12 /**< SCK_LO_CLK Position */ +#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Mask */ +#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Position */ +#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Mask */ +#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Position */ +#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Mask */ +#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20 /**< SDIO_SAMPLE_POINT Position */ +#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Mask */ + +#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL) /**< PAGE_SIZE_4B Field Value */ +#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL) /**< PAGE_SIZE_8B Field Value */ +#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL) /**< PAGE_SIZE_16B Field Value */ +#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL) /**< PAGE_SIZE_32B Field Value */ + +#define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_4B Shifted Field Value */ +#define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_8B Shifted Field Value */ +#define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_16B Shifted Field Value */ +#define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_32B Shifted Field Value */ +/**@} end of group SPIM_MSTR_CFG*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_SS_SR_POLARITY_Register SPIM_SS_SR_POLARITY + * @brief Field Positions and Bit Masks for the SPIM_SS_SR_POLARITY register + * @{ + */ +#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0 /**< SS_POLARITY Position */ +#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS)) /**< SS_POLARITY Mask */ +#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8 /**< FC_POLARITY Position */ +#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS)) /**< FC_POLARITY Mask */ +/**@} end of group SPIM_SS_SR_POLARITY*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_GEN_CTRL_Register SPIM_GEN_CTRL + * @brief Field Positions and Bit Masks for the SPIM_GEN_CTRL register + * @{ + */ +#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0 /**< SPI_MSTR_EN Position */ +#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS)) /**< SPI_MSTR_EN Mask */ +#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */ +#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */ +#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */ +#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */ +#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3 /**< BIT_BANG_MODE Position */ +#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS)) /**< BIT_BANG_MODE Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4 /**< BB_SS_IN_OUT Position */ +#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS)) /**< BB_SS_IN_OUT Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5 /**< BB_SR_IN Position */ +#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS)) /**< BB_SR_IN Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6 /**< BB_SCK_IN_OUT Position */ +#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS)) /**< BB_SCK_IN_OUT Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8 /**< BB_SDIO_IN osition */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS)) /**< BB_SDIO_IN Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12 /**< BB_SDIO_OUT Position */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS)) /**< BB_SDIO_OUT Mask */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16 /**< BB_SDIO_DR_EN Position */ +#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS)) /**< BB_SDIO_DR_EN Mask */ +#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20 /**< SIMPLE_MODE Position */ +#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)) /**< SIMPLE_MODE Mask */ +#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21 /**< START_RX_ONLY Position */ +#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS)) /**< START_RX_ONLY Mask */ +#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22 /**< DEASSERT_ACT_SS Position */ +#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS)) /**< DEASSERT_ACT_SS Mask */ +#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24 /**< ENABLE_SCK_FB_MOD Position */ +#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< ENABLE_SCK_FB_MOD Mask */ +#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25 /**< INVERT_SCK_FB_CLK Position */ +#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS)) /**< INVERT_SCK_FB_CLK Mask */ +/**@} end of group SPIM_GEN_CTRL*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_FIFO_CTRL_Register SPIM_FIFO_CTRL + * @brief Field Positions and Bit Masks for the SPIM_FIFO_CTRL register + * @{ + */ +#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */ +#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */ +#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8 /**< TX_FIFO_USED Position */ +#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */ +#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< RX_FIFO_AF_LVL Position */ +#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */ +#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24 /**< RX_FIFO_USED Position */ +#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */ +/**@} end of group SPIM_FIFO_CTRL*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_SPCL_CTRL_Register SPIM_SPCL_CTRL + * @brief Field Positions and Bit Masks for the SPIM_SPCL_CTRL register + * @{ + */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 /**< SS_SAMPLE_MODE Position */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS)) /**< SS_SAMPLE_MODE Mask */ +#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1 /**< MISO_FC_EN Position */ +#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS)) /**< MISO_FC_EN Mask */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 /**< SS_SA_SDIO_OUT Position */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) /**< SS_SA_SDIO_OUT Mask */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 /**< SS_SA_SDIO_DR_EN Position */ +#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) /**< SS_SA_SDIO_DR_EN Mask */ + +#if (MXC_SPIM_REV == 0) +#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16 /**< SPECIAL_MODE_3_EN Position */ +#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS)) /**< SPECIAL_MODE_3_EN Mask */ +#else +#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12 /**< RX_FIFO_MARGIN Position */ +#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS)) /**< RX_FIFO_MARGIN Mask */ +#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16 /**< SCK_FB_DELAY Position */ +#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS)) /**< SCK_FB_DELAY Mask */ +#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20 /**< SPARE_RESERVED Position */ +#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS)) /**< SPARE_RESERVED Mask */ +#endif +/**@} end of group SPIM_SPCL_CTRL*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_INTFL_Register SPIM_INTFL + * @brief Field Positions and Bit Masks for the SPIM_INTFL register + * @{ + */ +#define MXC_F_SPIM_INTFL_TX_STALLED_POS 0 /**< TX_STALLED Position */ +#define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS)) /**< TX_STALLED Mask */ +#define MXC_F_SPIM_INTFL_RX_STALLED_POS 1 /**< RX_STALLED Position */ +#define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS)) /**< RX_STALLED Mask */ +#define MXC_F_SPIM_INTFL_TX_READY_POS 2 /**< TX_READY Position */ +#define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS)) /**< TX_READY Mask */ +#define MXC_F_SPIM_INTFL_RX_DONE_POS 3 /**< RX_DONE Position */ +#define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS)) /**< RX_DONE Mask */ +#define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */ +#define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */ +#define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */ +#define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */ +/**@} end of group SPIM_INTFL*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_INTEN_Register SPIM_INTEN + * @brief Field Positions and Bit Masks for the SPIM_INTEN register + * @{ + */ +#define MXC_F_SPIM_INTEN_TX_STALLED_POS 0 /**< TX_STALLED Position */ +#define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS)) /**< TX_STALLED Mask */ +#define MXC_F_SPIM_INTEN_RX_STALLED_POS 1 /**< RX_STALLED Position */ +#define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS)) /**< RX_STALLED Mask */ +#define MXC_F_SPIM_INTEN_TX_READY_POS 2 /**< TX_READY Position */ +#define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS)) /**< TX_READY Mask */ +#define MXC_F_SPIM_INTEN_RX_DONE_POS 3 /**< RX_DONE Position */ +#define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS)) /**< RX_DONE Mask */ +#define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */ +#define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */ +#define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */ +#define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */ +/**@} end of group SPIM_INTEN*/ +/** + * @ingroup spim_registers + * @defgroup SPIM_SIMPLE_HEADERS_Register SPIM_SIMPLE_HEADERS + * @brief Field Positions and Bit Masks for the SPIM_SIMPLE_HEADERS register + * @{ + */ +#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0 /**< TX_BIDIR_HEADER Position */ +#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS)) /**< TX_BIDIR_HEADER Mask */ +#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16 /**< RX_ONLY_HEADER Position */ +#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS)) /**< RX_ONLY_HEADER Mask */ +/**@} end of group SPIM_SIMPLE_HEADERS*/ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SPIM_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h new file mode 100644 index 00000000000..ff013ed425f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h @@ -0,0 +1,224 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $ + * $Revision: 24859 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_SPIS_REGS_H_ +#define _MXC_SPIS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup spis + * @defgroup spis_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module. + * @{ + */ + +/** + * Structure type to access the SPI Slave Peripheral Module Registers + */ +typedef struct { + __IO uint32_t gen_ctrl; /**< SPIS_GEN_CTRL Register - SPI Slave General Control Register */ + __IO uint32_t fifo_ctrl; /**< SPIS_FIFO_CTRL Register - SPI Slave FIFO Control Register */ + __IO uint32_t fifo_stat; /**< SPIS_FIFO_STAT Register - SPI Slave FIFO Status Register */ + __IO uint32_t intfl; /**< SPIS_INTFL Register - SPI Slave Interrupt Flags */ + __IO uint32_t inten; /**< SPIS_INTEN Register - SPI Slave Interrupt Enable/Disable Settings */ +} mxc_spis_regs_t; + + +/** + * Structure type for the SPI Slave Transmit and Receive FIFOs. + */ +typedef struct { + union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */ + __IO uint8_t tx_8[2048]; /**< 8-bit access to Transmit FIFO */ + __IO uint16_t tx_16[1024]; /**< 16-bit access to Transmit FIFO */ + __IO uint32_t tx_32[512]; /**< 32-bit access to Transmit FIFO */ + }; + union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */ + __IO uint8_t rx_8[2048]; /**< 8-bit access to Receive FIFO */ + __IO uint16_t rx_16[1024]; /**< 16-bit access to Receive FIFO */ + __IO uint32_t rx_32[512]; /**< 32-bit access to Receive FIFO */ + }; +} mxc_spis_fifo_regs_t; +/**@} end of group spis_registers */ + +/* + Register offsets for module SPIS. +*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_Register_Offsets Register Offsets + * @brief SPI Slave Register Offsets from the SPIS[n] Base Peripheral Address, where \c n \c = SPIS Instance Number. + * @{ + */ +#define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: \b 0x0000*/ +#define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: \b 0x0004*/ +#define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: \b 0x0008*/ +#define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) /**< /**< Offset from SPIS[n] Base Peripheral Address: \b 0x000C*/ +#define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: \b 0x0010*/ +/**@} end of group SPIS_Register_Offsets*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_FIFO_Offsets FIFO Offsets + * @brief SPI Slave FIFO Offsets from the SPIS[n] Base FIFO Address, where \c n \c = SPIS Instance Number. + * @{ + */ +#define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) /**< Offset from SPIS[n] Base FIFO Address: \b 0x0000 */ +#define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) /**< Offset from SPIS[n] Base FIFO Address: \b 0x0800 */ +/**@} end of group SPIS_FIFO_Offsets*/ + + +/* + Field positions and masks for module SPIS. +*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_GEN_CTRL_Register SPIS_GEN_CTRL + * @brief Field Positions and Bit Masks for the SPIS_GEN_CTRL register + * @{ + */ +#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 /**< SPI_SLAVE_EN Position */ +#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) /**< SPI_SLAVE_EN Mask */ +#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */ +#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */ +#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */ +#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */ +#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 /**< DATA_WIDTH Position */ +#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Mask */ +#define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 /**< SPI_MODE Position */ +#define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) /**< SPI_MODE Mask */ +#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 /**< TX_CLK_INVERT Position */ +#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) /**< TX_CLK_INVERT Mask */ +/**@} end of group SPIS_GEN_CTRL*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_FIFO_CTRL_Register SPIS_FIFO_CTRL + * @brief Field Positions and Bit Masks for the SPIS_FIFO_CTRL register + * @{ + */ +#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */ +#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */ +#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 /**< RX_FIFO_AF_LVL Position */ +#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */ +/**@} end of group SPIS_FIFO_CTRL_Register*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_FIFO_STAT_Register SPIS_FIFO_STAT + * @brief Field Positions and Bit Masks for the SPIS_FIFO_STAT register + * @{ + */ +#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 /**< TX_FIFO_USED Position */ +#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */ +#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 /**< RX_FIFO_USED Position */ +#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */ +/**@} end of group SPIS_FIFO_STAT_Register*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_INTFL_Register SPIS_INTFL + * @brief Field Positions and Bit Masks for the SPIS_INTFL register + * @{ + */ +#define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */ +#define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */ +#define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */ +#define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */ +#define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */ +#define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */ +#define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */ +#define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */ +#define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */ +#define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */ +#define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */ +#define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */ +#define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */ +#define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */ +/**@} end of group SPIS_INTFL_Register*/ +/** + * @ingroup spis_registers + * @defgroup SPIS_INTEN_Register SPIS_INTEN + * @brief Field Positions and Bit Masks for the SPIS_INTEN register + * @{ + */ +#define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */ +#define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */ +#define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */ +#define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */ +#define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */ +#define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */ +#define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */ +#define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */ +#define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */ +#define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */ +#define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */ +#define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */ +#define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */ +#define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */ +/**@} end of group SPIS_INTEN_Register*/ +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SPIS_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/spix_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/spix_regs.h new file mode 100644 index 00000000000..463af61f6c3 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spix_regs.h @@ -0,0 +1,309 @@ +/** + * @file + * @brief Registers, Fields, Field Positions, Masks and Values for the SPIX Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:45:43 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24673 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_SPIX_REGS_H_ +#define _MXC_SPIX_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spix + * @defgroup spix_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIX Peripheral Module. + */ + +/** + * @ingroup spix_registers + * Structure type to access the SPIX Registers. + */ + typedef struct { + __IO uint32_t master_cfg; /**< SPIX_MASTER_CFG Register. */ + __IO uint32_t fetch_ctrl; /**< SPIX_FETCH_CTRL Register. */ + __IO uint32_t mode_ctrl; /**< SPIX_MODE_CTRL Register. */ + __IO uint32_t mode_data; /**< SPIX_MODE_DATA Register. */ + __IO uint32_t sck_fb_ctrl; /**< SPIX_SCK_FB_CTRL Register. */ +} mxc_spix_regs_t; + +/** + * @ingroup spix_registers + * @defgroup SPIX_Register_Offsets Register Offsets + * @brief SPIX Peripheral Register Offsets from the SPIX Base Peripheral Address, #MXC_BASE_SPIX. + * @{ + */ +#define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) /**< Offset from #MXC_BASE_SPIX: \b 0x000 */ +#define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from #MXC_BASE_SPIX: \b 0x004 */ +#define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from #MXC_BASE_SPIX: \b 0x008 */ +#define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from #MXC_BASE_SPIX: \b 0x00C */ +#define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from #MXC_BASE_SPIX: \b 0x010 */ +/**@} end of SPIX_Register_Offsets */ + +/** + * @ingroup spix_registers + * @defgroup SPIX_Master_Cfg_Register SPIX_MASTER_CFG Register Fields + * @brief Register Fields and Shifted Field Masks for the SPIX_MASTER_CFG Register. + * @{ + */ +#define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 /**< SPI_MODE Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SPI_MODE Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 /**< SS_ACT_LO Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< SS_ACT_LO Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 /**< ALT_TIMING_EN Field Position */ +#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< ALT_TIMING_EN Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 /**< SLAVE_SEL Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8 /**< SCK_LO_CLK Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12 /**< SCK_HI_CLK Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Field Position */ +#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Field Position */ +#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20 /**< ALT_SCK_LO_CLK Field Position */ +#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) /**< ALT_SCK_LO_CLK Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24 /**< ALT_SCK_HI_CLK Field Position */ +#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) /**< ALT_SCK_HI_CLK Shifted Field Mask */ +#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28 /**< SDIO_SAMPLE_POINT Field Position */ +#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Shifted Field Mask */ +/**@}*/ +/** + * @ingroup spix_registers + * @defgroup SPIX_Fetch_Ctrl_Register SPIX_FETCH_CTRL Register Fields + * @brief Register Fields and Shifted Masks for the SPIX_FETCH_CTRL Register. + * @{ + */ +#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 /**< CMD_VALUE Field Position */ +#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) /**< CMD_VALUE Shifted Field Mask */ +#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 /**< CMD_WIDTH Field Position */ +#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< CMD_WIDTH Shifted Field Mask */ +#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< ADDR_WIDTH Field Position */ +#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< ADDR_WIDTH Shifted Field Mask */ +#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 /**< DATA_WIDTH Field Position */ +#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Shifted Field Mask */ +#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FOUR_BYTE_ADDR Field Position */ +#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FOUR_BYTE_ADDRField Mask */ +/**@}*/ +/** + * @ingroup spix_registers + * @defgroup SPIX_Mode_Ctrl_Register SPIX_MODE_CTRL Register Fields + * @brief Register Fields and Shifted Masks for the SPIX_MODE_CTRL Register. + * @{ + */ +#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 /**< MODE_CLOCKS Field Position */ +#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) /**< MODE_CLOCKS Shifted Field Mask */ +#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 /**< NO_CMD_MODE Field Position */ +#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) /**< NO_CMD_MODE Shifted Field Mask */ +/**@}*/ +/** + * @ingroup spix_registers + * @defgroup SPIX_Mode_Data_Register SPIX_MODE_DATA Register Fields + * @brief Register Fields and Shifted Masks for the SPIX_MODE_DATA Register. + * @{ + */ +#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 /**< MODE_DATA_BITS Field Position */ +#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) /**< MODE_DATA_BITS Shifted Field Mask */ +#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 /**< MODE_DATA_OE Field Position */ +#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) /**< MODE_DATA_OE Shifted Field Mask */ +/**@}*/ +/** + * @ingroup spix_registers + * @defgroup SPIX_SCK_Fb_Ctrl_Register SPIX_SCK_FB_CTRL Register Fields + * @brief Register Fields and Shifted Masks for the SPIX_SCK_FB_CTRL Register. + * @{ + */ +#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0 /**< Field Position */ +#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< Field Mask */ +#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1 /**< Field Position */ +#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS)) /**< Field Mask */ + +#if(MXC_SPIX_REV == 0) +#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4 /**< Field Position */ +#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)) /**< Field Mask */ +#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 /**< Field Position */ +#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) /**< Field Mask */ +#endif +/**@}*/ + + +/** + * @ingroup SPIX_Master_Cfg_Register + * @defgroup SPIX_Master_Cfg_SCK SCK Sampling Mode Field + * @brief Field values and shifted field values for setting the SPIX SCK Sampling Mode. + * @{ + */ +#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) /**< Field value for setting the sampling of the SCK on the rising edge. */ +#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) /**< Field value for setting the sampling of the SCK on the falling edge. */ + +#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on rising edge Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on falling edge Field Shifted Value. */ +/**@}*/ +/** + * @ingroup SPIX_Master_Cfg_Register + * @defgroup SPIX_Master_Cfg_SS Slave Select Polarity Field + * @brief Field values and shifted field values for setting the SPIX Slave Select Active High/Low Field. + * @{ + */ +#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) /**< Slave Select Active High Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) /**< Slave Select Active Low Field selection value. */ + +#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active High Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active Low Field Shifted Value. */ +/**@}*/ +/** + * @ingroup SPIX_Master_Cfg_Register + * @defgroup SPIX_Master_Cfg_Alt Alternate Timing + * @brief Field values and shifted field values for setting the SPIX Alternate Timing Field. + * @{ + */ +#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) /**< Alternate Timing Disabled (Default) Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) /**< Alternate Timing Enabled As Needed Field selection value. */ + +#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Disabled Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Enabled As Needed Field Shifted Value. */ +/**@}*/ +/** + * @ingroup SPIX_Master_Cfg_Register + * @defgroup SPIX_Master_Cfg_Act Active Delay Settings + * @brief Field values and shifted field values for setting the SPIX Activity Delay, the number of SPIX clocks between slave selection assert and active SPI clocking. + * @{ + */ +#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Activity Delay Off Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */ + +#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< Activity Delay Off Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */ +/**@}*/ +/** + * @ingroup SPIX_Master_Cfg_Register + * @defgroup SPIX_Master_Cfg_Inact Inactive Delay Settings + * @brief Field values and shifted field values for setting the SPIX Inactivity Delay, the number of SPIX clocks between the active SPI Clock and the Slave Select Deassertion. + * @{ + */ +#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Inactivity Delay Off Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */ +#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */ + +#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< Inactivity Delay Off Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */ +#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */ +/**@}*/ +/** + * @ingroup SPIX_Fetch_Ctrl_Register + * @defgroup SPIX_Fetch_ctrl_cmd_width Address Width Values and Shifted Values + * @brief Field values and shifted field values for selecting the SPIX Command Fetch Width + * @{ + */ +#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 command width field value. */ +#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual command field value. */ +#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad command field value. */ + +#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x1 command width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x2 Dual command width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x4 Quad command width fetch shifted value. */ +/**@}*/ +/** + * @ingroup SPIX_Fetch_Ctrl_Register + * @defgroup SPIX_Fetch_ctrl_addr_width Address Width Values and Shifted Values + * @brief Field values and shifted field values for selecting the SPIX Address Fetch Width + * @{ + */ +#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 addr width field value. */ +#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual addr field value. */ +#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad addr field value. */ + +#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x1 addr width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x2 Dual addr width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x4 Quad addr width fetch shifted value. */ +/**@}*/ +/** + * @ingroup SPIX_Fetch_Ctrl_Register + * @defgroup SPIX_Fetch_ctrl_data_width Data Width Values and Shifted Values + * @brief Field values and shifted field values for selecting the SPIX Data Fetch Width + * @{ + */ +#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< Value to select x1 data width fetch for SPIX Field selection value. */ +#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< Value to select x2 Dual Mode data width fetch for SPIX Field selection value. */ +#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< Value to select x4 Quad Mode data width fetch for SPIX Field selection value. */ + +#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x1 data width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x2 Dual data width fetch shifted value. */ +#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x4 Quad data width fetch shifted value. */ +/**@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SPIX_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/sysman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/sysman_regs.h new file mode 100644 index 00000000000..c4eb605013e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/sysman_regs.h @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_SYSMAN_REGS_H_ +#define _MXC_SYSMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t pvt_monitor; /* 0x0000 System Clock Configuration */ +} mxc_sysman_regs_t; + + +/* + Register offsets for module SYSMAN. +*/ + +#define MXC_R_SYSMAN_OFFS_PVT_MONITOR ((uint32_t)0x00000000UL) + + +/* + Field positions and masks for module SYSMAN. +*/ + +#define MXC_F_SYSMAN_PVT_MONITOR_CODE_POS 0 +#define MXC_F_SYSMAN_PVT_MONITOR_CODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_SYSMAN_PVT_MONITOR_CODE_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SYSMAN_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.c b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.c new file mode 100644 index 00000000000..6f8ada1602d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.c @@ -0,0 +1,275 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-06-09 07:43:41 -0500 (Thu, 09 Jun 2016) $ + * $Revision: 23255 $ + * + ******************************************************************************/ + +#include +#include +#include +#include "max3263x.h" +#include "clkman_regs.h" +#include "adc_regs.h" +#include "pwrseq_regs.h" +#include "pwrman_regs.h" +#include "icc_regs.h" +#include "flc_regs.h" +#include "rtc_regs.h" +#include "trim_regs.h" + +#ifndef RO_FREQ +#define RO_FREQ 96000000 +#endif + +#ifndef LP0_POST_HOOK +#define LP0_POST_HOOK +#endif + +// NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will +// be AFTER SystemInit() runs. This is required so the hal drivers will have +// the correct value when the DATA sections are initialized. +uint32_t SystemCoreClock = RO_FREQ; + +void SystemCoreClockUpdate(void) +{ +#ifdef EMULATOR + SystemCoreClock = RO_FREQ; +#else /* real hardware */ + if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) { + /* 4 MHz source */ + if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) { + SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >> + MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))); + } else { + SystemCoreClock = 4000000; + } + } else { + /* 96 MHz source */ + if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) { + SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >> + MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))); + } else { + SystemCoreClock = RO_FREQ; + } + } +#endif +} + +void CLKMAN_TrimRO(void) +{ + uint32_t running; + uint32_t trim; + + /* Step 1: enable 32KHz RTC */ + running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + + /* Wait for RTC warm-up */ + while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {} + + /* Step 2: enable RO calibration complete interrupt */ + MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE; + + /* Step 3: clear RO calibration complete interrupt */ + MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF; + + /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */ + + /* Step 5: write initial trim to frequency calibration initial condition register */ + trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS; + MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | + ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); + + /* Step 6: load initial trim to active frequency trim register */ + MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD; + + /* Step 7: enable frequency loop to control RO trim */ + MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN; + + /* Step 8: run frequency calibration in atomic mode */ + MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC; + + /* Step 9: waiting for ro_cal_done flag */ + while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF)); + + /* Step 10: stop frequency calibration */ + MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN; + + /* Step 11: disable RO calibration complete interrupt */ + MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE; + + /* Step 12: read final frequency trim value */ + trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS; + + /* Step 13: write final trim to RO flash trim shadow register */ + MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) | + ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF); + + /* Step 14: restore RTC status */ + if (!running) { + MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + } + + /* Step 15: disable frequency loop to control RO trim */ + MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN; +} + +static void ICC_Enable(void) +{ + /* Invalidate cache and wait until ready */ + MXC_ICC->invdt_all = 1; + while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); + + /* Enable cache */ + MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; + + /* Must invalidate a second time for proper use */ + MXC_ICC->invdt_all = 1; +} + +/* This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initialization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + /* Increase system clock to 96 MHz */ + MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO; + + /* Performance-measurement hook, may be defined as nothing */ + LP0_POST_HOOK; + + /* Enable cache here to reduce boot time */ + ICC_Enable(); + + return 0; +} + +/* Override this function for early platform initialization +*/ +__weak void low_level_init(void) {} + +/* This function is called just before control is transferred to main(). + */ +void SystemInit(void) +{ + /* Copy trim information from shadow registers into power manager registers */ + /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */ + if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) && + (MXC_TRIM->for_pwr_reg5 != 0xffffffff) && + (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) { + MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5; + MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6; + } else { + /* No valid info block, use some reasonable defaults */ + MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF; + MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS); + } + + /* Improve flash access timing */ + MXC_FLC->perform |= (MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS | + MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT | + MXC_F_FLC_PERFORM_AUTO_TACC | + MXC_F_FLC_PERFORM_AUTO_CLKDIV); + + /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */ + MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS | + MXC_F_RTC_CTRL_AGGRESSIVE_RST); + + /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */ + MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE | + MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR); + MXC_PWRSEQ->rtc_ctrl2 &= ~MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD; + + /* Clear the GPIO WUD event if not waking up from LP0 */ + /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/ + if ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) || + !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) { + /* Clear GPIO WUD event and configuration registers, globally */ + MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | + MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); + MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | + MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); + } else { + /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */ + MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE; + /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */ + MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW; + } + + /* Turn on retention regulator */ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | + MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP); + + /* Adjust settings in the retention controller for fastest wake-up time */ + MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY | + MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH); + MXC_PWRSEQ->retn_ctrl0 &= ~MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK; + + + /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */ + /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */ + MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) | + (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS); + + /* Improve wake-up time by changing ROSEL to 140ns */ + MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) | + (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) | + (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL | + MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL)); + + /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */ + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; + + /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */ + MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS; + +#if (__FPU_PRESENT == 1) + /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ + /* Grant full access, per "Table B3-24 CPACR bit assignments". */ + /* DDI0403D "ARMv7-M Architecture Reference Manual" */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; + __DSB(); + __ISB(); +#endif + + /* Early platform initialization */ + low_level_init(); + + /* Perform an initial trim of the internal ring oscillator */ + CLKMAN_TrimRO(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.h new file mode 100644 index 00000000000..5fe3802bc59 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.h @@ -0,0 +1,96 @@ +/** + * @file + * @brief MAX3263X System Clock Configuration and System Initialization. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $ + * $Revision: 24859 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include + +/* Define to prevent redundant inclusion */ +#ifndef _SYSTEM_MAX3263X_H_ +#define _SYSTEM_MAX3263X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + + +/** + * @ingroup max3263x + * @brief MAX3263X System File for CMSIS + * @{ + */ + +/* **************************************************************************** + Define clocks + *************************************************************************** */ +#ifndef HFXIN_FREQ +/** + * @internal External HFXIN frequency. + */ +#define HFXIN_FREQ 8000000 +#endif + +#ifndef RO_FREQ +#define RO_FREQ 96000000 /**< High Frequency Internal Relaxation Oscillator used as the default System Clock Source */ +#endif + +extern uint32_t SystemCoreClock; /*!< CMSIS System Clock Frequency (Core Clock) */ + +/** + * Initializes the system. + * + * @brief Setup the microcontroller system. + * Initialize the System and set up the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable. + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from the device hardware. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MAX3263X_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/tmr_regs.h new file mode 100644 index 00000000000..89be03339d7 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/tmr_regs.h @@ -0,0 +1,307 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the Timer Peripheral + * Module. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24675 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_TMR_REGS_H_ +#define _MXC_TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup tmr + * @defgroup tmr_registers Timer Registers + * @brief Hardware interface definitions for the Timer Peripheral. + * @details Definitions for the Hardware Access Layer of the Timer + * Peripherals. Includes: + * - Registers + * - Fields + * - Positions + * - Values + * - Masks + * @{ + */ + +/* **** Definitions **** */ + +/** + * Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000 - TMR_CTRL Register - Timer Control Register */ + __IO uint32_t count32; /**< \b 0x0004 - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */ + __IO uint32_t term_cnt32; /**< \b 0x0008 - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */ + __IO uint32_t pwm_cap32; /**< \b 0x000C - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */ + __IO uint32_t count16_0; /**< \b 0x0010 - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */ + __IO uint32_t term_cnt16_0; /**< \b 0x0014 - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */ + __IO uint32_t count16_1; /**< \b 0x0018 - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */ + __IO uint32_t term_cnt16_1; /**< \b 0x001C - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */ + __IO uint32_t intfl; /**< \b 0x0020 - TMR_INTFL Register - Timer Interrupt Flags */ + __IO uint32_t inten; /**< \b 0x0024 - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */ +} mxc_tmr_regs_t; +/**@} end of group tmr_registers. */ + + +/* + Register offsets for module TMR. +*/ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number. + * @{ + */ +#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : \b 0x0x0000 */ +#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : \b 0x0x0004 */ +#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : \b 0x0x0008 */ +#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : \b 0x0x000C */ +#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : \b 0x0x0010 */ +#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : \b 0x0x0014 */ +#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : \b 0x0x0018 */ +#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : \b 0x0x001C */ +#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : \b 0x0x0020 */ +#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : \b 0x0x0024 */ +/**@} end of group TMR_Register_Offsets */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL_Register TMR_CTRL Register + * @brief Field Positions and Bit Masks for the TMR_CTRL register + * @{ + */ +#define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */ +#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */ +#define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */ +#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */ +#define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */ +#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */ +#define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */ +#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */ +#define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */ +#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */ +#define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */ +#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */ +/**@} end of group TMR_CTRL */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register + * @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the 16-bit Timer 0 instance. + * @{ + */ +#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +/**@} end of group TMR_COUNT16_0 */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register + * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the 16-bit Timer 0 instance if the Timer is set to 2 16-bit Timers. + * @{ + */ +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +/**@} end of group TMR_TERM_CNT16_0 */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register + * @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the 16-bit Timer 0 instance. + * @{ + */ +#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +/**@} end of group TMR_COUNT16_1 */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register + * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the 16-bit Timer 1 instance if the Timer is set to 2 16-bit Timers. + * @{ + */ +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ +/**@} end of group TMR_TERM_CNT16_1 */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTFL_Register TMR_INTFL Register + * @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both 16-bit Timer 0 and 16-bit Timer 1. + * @{ + */ +#define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */ +#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */ +#define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */ +#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */ +/**@} end of group TMR_INTFL */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTEN_Register TMR_INTEN Register + * @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both 16-bit Timer 0 and 16-bit Timer 1. + * @{ + */ +#define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */ +#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */ +#define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */ +#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */ +/**@} end of group TMR_INTEN */ + + + +/* + Field values and shifted values for module TMR. +*/ +/** + * @ingroup TMR_CTRL_Register + * @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values + * @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register. + */ +/** + * @ingroup TMR_CTRL_field_values + * @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation. + * @brief This field is used to select the timer mode for a 32-bit timer. + * @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc. + * @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field. + * @{ + */ +#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */ +#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */ +#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */ +#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */ +#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */ +#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */ +#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */ +#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */ + +#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */ +#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */ +#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */ +#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */ +#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */ +#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */ +#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */ +#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */ +/**@} end of group TMR_CTRL_MODE_Field */ +/** + * @ingroup TMR_CTRL_field_values + * @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values. + * @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc. + * @{ + */ +#define MXC_F_TMR_CTRL_MODE_16_0_POS 0 +#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS)) + +#define MXC_F_TMR_CTRL_MODE_16_1_POS 1 +#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS)) +/**@} end of group TMR_CTRL_MODE_16_Field */ + +/** + * @ingroup TMR_CTRL_field_values + * @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values. + * @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value. + * @{ + */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */ +#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */ + +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */ +#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */ +/**@} end of group TMR_CTRL_PRESCALE_Field */ + + +/* + * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module + * is in dual 16-bit timer mode. + */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TMR_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/tpu_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/tpu_regs.h new file mode 100644 index 00000000000..e7af637db9b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/tpu_regs.h @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_TPU_REGS_H_ +#define _MXC_TPU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __RO uint32_t rsv000[4]; /* 0x0000-0x000C */ + __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) */ + __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) */ + __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 2 (Cleared on Tamper Detect) */ + __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 3 (Cleared on Tamper Detect) */ +} mxc_tpu_tsr_regs_t; + + +/* + Register offsets for module TPU. +*/ + +#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL) +#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL) +#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL) +#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL) + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TPU_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/trim_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/trim_regs.h new file mode 100644 index 00000000000..458ecade751 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/trim_regs.h @@ -0,0 +1,131 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-05-02 16:15:59 -0500 (Mon, 02 May 2016) $ + * $Revision: 22594 $ + * + ******************************************************************************/ + +#ifndef _MXC_TRIM_REGS_H_ +#define _MXC_TRIM_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __RO uint32_t rsv000[10]; /* 0x0000-0x0024 */ + __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */ + __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */ + __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */ + __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */ + __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */ + __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */ +} mxc_trim_regs_t; + + +/* + Register offsets for module TRIM. +*/ + +#define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL) +#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL) +#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL) +#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL) +#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL) +#define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL) + + +/* + Field positions and masks for module TRIM. +*/ + +#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0 +#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS)) +#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2 +#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS)) + +#define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL)) +#define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL)) +#define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL)) + +#define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL)) +#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL)) +#define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL)) +#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL)) +#define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL)) + +#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0 +#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS)) +#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16 +#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS)) + +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0 +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS)) +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16 +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS)) +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28 +#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TRIM_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h new file mode 100644 index 00000000000..23ae8496264 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h @@ -0,0 +1,270 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-31 17:35:11 -0500 (Mon, 31 Oct 2016) $ + * $Revision: 24860 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_UART_REGS_H_ +#define _MXC_UART_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup uart_comm + * @defgroup uart_registers UART Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ + +/** + * Structure type for the UART peripheral registers allowing direct 32-bit access to each register. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: UART_CTRL Register - UART Control Register. */ + __IO uint32_t baud; /**< \b 0x0004: UART_BAUD Register - UART Baud Control Register. */ + __IO uint32_t tx_fifo_ctrl; /**< \b 0x0008: UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */ + __IO uint32_t rx_fifo_ctrl; /**< \b 0x000C: UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */ + __IO uint32_t md_ctrl; /**< \b 0x0010: UART_MD_CTRL Register - UART Multidrop Control Register. */ + __IO uint32_t intfl; /**< \b 0x0014: UART_INTFL Register - UART Interrupt Flags. */ + __IO uint32_t inten; /**< \b 0x0018: UART_INTEN Register - UART Interrupt Enable/Disable Control. */ +#if (MXC_UART_REV > 0) + __RO uint32_t idle; /**< \b 0x001C: UART_IDLE Register - UART Idle Status */ +#endif +} mxc_uart_regs_t; +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup uart_fifos UART TX and RX FIFOs + * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types. + * @{ + */ +/** + * Structure type for accessing the UART Transmit and Receive FIFOs. + */ +typedef struct { + union { + __IO uint8_t tx; /**< TX FIFO write point for data to transmit. */ + __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */ + __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */ + __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */ + }; + union { + __IO uint8_t rx; /**< RX FIFO read point for received data. */ + __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */ + __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */ + __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */ + }; +} mxc_uart_fifo_regs_t; +/**@} end of group uart_fifos */ + +/* + Register offsets for module UART. +*/ + +#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL) +#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL) +#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL) +#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL) +#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL) +#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL) + + +/* + Field positions and masks for module UART. +*/ + +#define MXC_F_UART_CTRL_UART_EN_POS 0 +#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS)) +#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1 +#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2 +#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_UART_CTRL_DATA_SIZE_POS 4 +#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS)) +#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8 +#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS)) +#define MXC_F_UART_CTRL_PARITY_POS 12 +#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS)) +#define MXC_F_UART_CTRL_CTS_EN_POS 16 +#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS)) +#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17 +#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS)) +#define MXC_F_UART_CTRL_RTS_EN_POS 18 +#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS)) +#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19 +#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS)) +#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20 +#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS)) + +#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0 +#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS)) +#define MXC_F_UART_BAUD_BAUD_MODE_POS 8 +#define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS)) + +#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0 +#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)) +#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16 +#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS)) + +#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0 +#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS)) +#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16 +#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS)) + +#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0 +#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS)) +#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8 +#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS)) +#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16 +#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS)) +#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17 +#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS)) + +/** + * @ingroup uart_registers + * @defgroup UART_INTFL_Register UART_INTFL + * @{ + */ +#define MXC_F_UART_INTFL_TX_DONE_POS 0 +#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS)) +#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1 +#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS)) +#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2 +#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS)) +#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3 +#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS)) +#define MXC_F_UART_INTFL_RX_STALLED_POS 4 +#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS)) +#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5 +#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS)) +#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6 +#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS)) +#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7 +#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS)) +#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8 +#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS)) +/**@} end of group UART_INTFL_Register */ + +#define MXC_F_UART_INTEN_TX_DONE_POS 0 +#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS)) +#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1 +#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS)) +#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2 +#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS)) +#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3 +#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS)) +#define MXC_F_UART_INTEN_RX_STALLED_POS 4 +#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS)) +#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5 +#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS)) +#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6 +#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS)) +#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7 +#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS)) +#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8 +#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS)) + +#if (MXC_UART_REV > 0) +#define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0 +#define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS)) +#define MXC_F_UART_IDLE_TX_IDLE_POS 1 +#define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS)) +#define MXC_F_UART_IDLE_RX_IDLE_POS 2 +#define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS)) +#endif + +/* + Field values and shifted values for module UART. +*/ + +#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL)) +#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL)) +#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL)) +#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL)) + +#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) +#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) +#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) +#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) + +#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL)) +#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL)) +#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL)) +#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL)) + +#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS)) +#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS)) +#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS)) +#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_UART_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/usb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/usb_regs.h new file mode 100644 index 00000000000..dbc19639dec --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/usb_regs.h @@ -0,0 +1,299 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_USB_REGS_H_ +#define _MXC_USB_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif + + +#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL) +#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL) +#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL) +#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL) + +#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS) + +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ + +/* Offset Register Description + ============= ============================================================================ */ +typedef struct { + __IO uint32_t cn; /* 0x0000 USB Control Register */ + __RO uint32_t rsv004[127]; /* 0x0004-0x01FC */ + __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ + __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ + __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ + __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ + __RO uint32_t rsv210[4]; /* 0x0210-0x021C */ + __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ + __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ + __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ + __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ + __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ + __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ + __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ + __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ + __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ + __RO uint32_t rsv244[7]; /* 0x0244-0x025C */ + __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ + __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ + __RO uint32_t rsv268[6]; /* 0x0268-0x027C */ + __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */ +} mxc_usb_regs_t; + + +/* + Register offsets for module USB. +*/ + +#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) +#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) +#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) +#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) +#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) +#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) +#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) +#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) +#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) +#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) +#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) +#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) +#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) +#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) +#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) +#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) +#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) +#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) +#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) +#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) +#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) +#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) +#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) +#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) + + +/* + Field positions and masks for module USB. +*/ + +#define MXC_F_USB_CN_USB_EN_POS 0 +#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) +#define MXC_F_USB_CN_HOST_POS 1 +#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS)) + +#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 +#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) + +#define MXC_F_USB_DEV_CN_SIGRWU_POS 2 +#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) +#define MXC_F_USB_DEV_CN_CONNECT_POS 3 +#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) +#define MXC_F_USB_DEV_CN_ULPM_POS 4 +#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) +#define MXC_F_USB_DEV_CN_URST_POS 5 +#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) +#define MXC_F_USB_DEV_CN_VBGATE_POS 6 +#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) +#define MXC_F_USB_DEV_CN_OSCEN_POS 7 +#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS)) +#define MXC_F_USB_DEV_CN_BACT_OE_POS 8 +#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS)) +#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 +#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) + +#define MXC_F_USB_DEV_INTFL_DPACT_POS 0 +#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) +#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTFL_BACT_POS 2 +#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_POS 3 +#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) +#define MXC_F_USB_DEV_INTFL_SUSP_POS 4 +#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) +#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_POS 6 +#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTFL_SETUP_POS 8 +#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) +#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) +#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 +#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) + +#define MXC_F_USB_DEV_INTEN_DPACT_POS 0 +#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) +#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTEN_BACT_POS 2 +#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_POS 3 +#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) +#define MXC_F_USB_DEV_INTEN_SUSP_POS 4 +#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) +#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_VBUS_POS 6 +#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTEN_SETUP_POS 8 +#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) +#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) +#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) + +#define MXC_F_USB_EP_BASE_EP_BASE_POS 9 +#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) + +#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 +#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) +#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 +#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) + +#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_IN_INT_INBAV_POS 0 +#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS)) + +#define MXC_F_USB_OUT_INT_OUTDAV_POS 0 +#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS)) + +#define MXC_F_USB_NAK_INT_NAK_POS 0 +#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS)) + +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS)) + +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS)) + +#define MXC_F_USB_SETUP0_BYTE0_POS 0 +#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) +#define MXC_F_USB_SETUP0_BYTE1_POS 8 +#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) +#define MXC_F_USB_SETUP0_BYTE2_POS 16 +#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) +#define MXC_F_USB_SETUP0_BYTE3_POS 24 +#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) + +#define MXC_F_USB_SETUP1_BYTE0_POS 0 +#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS)) +#define MXC_F_USB_SETUP1_BYTE1_POS 8 +#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS)) +#define MXC_F_USB_SETUP1_BYTE2_POS 16 +#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS)) +#define MXC_F_USB_SETUP1_BYTE3_POS 24 +#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS)) + +#define MXC_F_USB_EP_DIR_POS 0 +#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS)) +#define MXC_F_USB_EP_BUF2_POS 3 +#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS)) +#define MXC_F_USB_EP_INT_EN_POS 4 +#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS)) +#define MXC_F_USB_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS)) +#define MXC_F_USB_EP_DT_POS 6 +#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS)) +#define MXC_F_USB_EP_STALL_POS 8 +#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS)) +#define MXC_F_USB_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS)) +#define MXC_F_USB_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_USB_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt2_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt2_regs.h new file mode 100644 index 00000000000..315469b9f7f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt2_regs.h @@ -0,0 +1,320 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the WDT2 Peripheral Module. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24678 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_WDT2_REGS_H_ +#define _MXC_WDT2_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup wdt2 + * @defgroup wdt2_registers WDT2 Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ +/** + * Structure type to access the WDT2 Registers, see #MXC_WDT2 to get a pointer to the WDT2 register structure. + * @note This is an always-on watchdog timer, it operates in all modes of operation. + */ +typedef struct { + __IO uint32_t ctrl; /**< WDT2_CTRL Register - WDT Control Register */ + __IO uint32_t clear; /**< WDT2_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */ + __IO uint32_t flags; /**< WDT2_FLAGS Register - WDT Interrupt and Reset Flags */ + __IO uint32_t enable; /**< WDT2_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */ + __RO uint32_t rsv010; /**< RESERVED, DO NOT MODIFY. */ + __IO uint32_t lock_ctrl; /**< WDT2_LOCK_CTRL Register - Lock for Control Register */ +} mxc_wdt2_regs_t; +/**@} end of group wdt2_registers.*/ + + +/* + Register offsets for module WDT2. +*/ +/** + * @ingroup wdt2_registers + * @defgroup WDT2_Register_Offsets Register Offsets + * @brief Watchdog Timer 2 Register Offsets from the WDT2 Base Peripheral Address. + * @details Use #MXC_WDT2 for the WDT2 Base Peripheral Address. + * @{ + */ +#define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL) /**< WDT2_CTRL Offset: 0x0000 */ +#define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< WDT2_CLEAR Offset: 0x0004 */ +#define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< WDT2_FLAGS Offset: 0x0008 */ +#define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< WDT2_ENABLE Offset: 0x000C */ +#define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< WDT2_LOCK_CTRL Offset: 0x0014 */ +/**@} end of group WDT2_Register_Offsets */ + + +/* + Field positions and masks for module WDT2. +*/ +/** + * @ingroup wdt2_registers + * @defgroup WDT2_CTRL_Register WDT2_CTRL Register + * @brief Field Positions and Bit Masks for the WDT2_CTRL register + * @{ + */ +#define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */ +#define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */ +#define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */ +#define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an + * interrupt period has expired before the device resets. If the + * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration, + * the device will not reset. */ +#define MXC_F_WDT2_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */ +#define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */ +#define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */ +#define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */ +#define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10 /**< WAIT_PERIOD Field Position */ +#define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS)) /**< WAIT_PERIOD Field Mask */ +/**@} end of group WDT2_CTRL */ +/** + * @ingroup wdt2_registers + * @defgroup WDT2_FLAGS_Register WDT2_FLAGS Register + * @brief Field Positions and Bit Masks for the WDT2_FLAGS register. Watchdog Timer 2 Flags for Interrupts and Reset. + * @{ + */ +#define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */ +#define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer 2 timed out. */ +#define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */ +#define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */ +/**@} end of group WDT2_FLAGS */ + +/** + * @ingroup wdt2_registers + * @defgroup WDT2_ENABLE_Register WDT2_ENABLE Register + * @brief Field Positions and Bit Masks for the WDT2_ENABLE register. + * @{ + */ +#define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */ +#define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */ +#define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */ +#define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */ +/**@} end of group WDT2_ENABLE */ + +/** + * @ingroup wdt2_registers + * @defgroup WDT2_LOCK_CTRL_Register WDT2_LOCK_CTRL Register + * @brief The WDT2_LOCK_CTRL register controls read/write access to the \ref WDT2_CTRL_Register. + * @{ + */ +#define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT2_LOCK_CTRL register. */ +#define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT2_LOCK_CTRL register. Reading a value of */ +/**@} end of group WDT2_ENABLE */ + + + +/* + Field values and shifted values for module WDT2. +*/ +/** + * @ingroup WDT2_CTRL_Register + * @defgroup WDT2_CTRL_field_values WDT2_CTRL Register Field and Shifted Field Values + * @brief Field values and Shifted Field values for the WDT2_CTRL register. + * @details Shifted field values are field values shifted to the loacation of the field in the register. + */ +/** + * @ingroup WDT2_CTRL_field_values + * @defgroup WDT2_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period + * @brief Sets the duration of the watchdog interrupt period. + * @details The INT_PERIOD field sets the duration of the watchdog interrupt + * period, which is the time period from the WDT2 being + * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_FLAGS_TIMEOUT, is + * set. + * The values defined are in the number of watchdog clock cycles. + * @{ + */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{15} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{14} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{13} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{12} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{11} \f$ WDT2 CLK Cycles */ +#define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{10} \f$ WDT2 CLK Cycles */ +/**@} end of group WDT2_CTRL_INT_PERIOD_Value */ + +/** + * @ingroup WDT2_CTRL_field_values + * @defgroup WDT2_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values + * @brief Shifted values for the \ref WDT2_CTRL_INT_PERIOD_Value + * @details The shifted value is + * shifted to align with the fields location in the WDT2_CTRL register. + * @{ + */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS */ +/**@} end of group WDT2_CTRL_INT_PERIOD_Shifted */ +/** + * @ingroup WDT2_CTRL_field_values + * @defgroup WDT2_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period + * @brief Sets the duration of the watchdog reset period. + * @details The RST_PERIOD field sets the duration of the watchdog reset + * period, which is the time period from the WDT being + * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_CTRL_RST_PERIOD is + * set. + * The values defined are in the number of watchdog clock cycles. + * @{ + */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{21} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{20} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{19} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{18} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{17} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{16} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{15} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{14} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{13} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{12} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{11} \f$ WDT2 CLK CYCLES */ +#define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{10} \f$ WDT2 CLK CYCLES */ +/**@} end of group WDT2_CTRL_RST_PERIOD_Value */ + +/** + * @ingroup WDT2_CTRL_field_values + * @defgroup WDT2_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values + * @brief Shifted values for the \ref WDT2_CTRL_RST_PERIOD_Value + * @details These values are shifted to align with the field's location in the WDT2_CTRL register. + * @{ + */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS */ +#define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS */ +/**@} end of group WDT2_CTRL_RST_PERIOD_Shifted */ +/** + * @ingroup WDT2_LOCK_CTRL_Register + * @defgroup WDT2_LOCK_field_values Watchdog Timer WDT2_LOCK field values + * @brief Lock/Unlock values for the watchdog timer \ref WDT2_CTRL_Register. + * @{ + */ +#define MXC_V_WDT2_LOCK_KEY 0x24 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b locks the \ref WDT2_CTRL_Register making it read only. */ +#define MXC_V_WDT2_UNLOCK_KEY 0x42 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b unlocks the \ref WDT2_CTRL_Register making it read/write. */ +/**@} end of group WDT2_LOCK_field_values */ +///@cond +/** + * @internal + * @ingroup WDT2_CLEAR_Register + * @defgroup WDT2_CLEAR_field_values Watchdog Timer Clear Sequence Values + * @brief Writing the sequence of #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 to the \ref WDT2_CLEAR_Register will clear/reset the watchdog timer count. + * @note The values #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 must be written sequentially to the \ref WDT2_CLEAR_Register to clear the watchdog counter. + * @{ + */ +#define MXC_V_WDT2_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */ +#define MXC_V_WDT2_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */ +/** + * @} end of group WDT2_CLEAR_field_values + * @endinternal + */ +///@endcond +/**@} wdt2_registers*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_WDT2_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h new file mode 100644 index 00000000000..9b3b4f6e42d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h @@ -0,0 +1,380 @@ +/** + * @file + * @brief Type definitions for the Watchdog Timer Peripheral + * + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24677 $ + * + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_WDT_REGS_H_ +#define _MXC_WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +///@cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __RO +#define __RO volatile const +#endif +///@endcond + +/** + * @ingroup wdt0 + * @defgroup wdt_registers Registers + * @brief Registers, Bit Masks and Bit Positions + * @{ + */ +/* + Typedefed structure(s) for module registers (per instance or section) with direct 32-bit + access to each register in module. +*/ +/** + * Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure. + * @note For the Always-On Watch Dog Timer, see \ref wdt2. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: WDT_CTRL Register - WDT Control Register */ + __IO uint32_t clear; /**< \b 0x0004: WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */ + __IO uint32_t flags; /**< \b 0x0008: WDT_FLAGS Register - WDT Interrupt and Reset Flags */ + __IO uint32_t enable; /**< \b 0x000C: WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */ + __RO uint32_t rsv010; /**< \b 0x0010: RESERVED, DO NOT MODIFY. */ + __IO uint32_t lock_ctrl; /**< \b 0x0014: WDT_LOCK_CTRL Register - Lock for Control Register */ +} mxc_wdt_regs_t; +/**@} end of group wdt_registers.*/ + +/* + Register offsets for module WDT. +*/ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device. + * @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance. + * @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver. + * @{ + */ +#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : \b 0x0000 */ +#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : \b 0x0004 */ +#define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : \b 0x0008 */ +#define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : \b 0x000C */ +#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : \b 0x0014 */ +/**@} end of group WDT_Register_Offsets */ + +/* + Field positions and masks for module WDT. +*/ +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL_Register WDT_CTRL Register + * @brief Field Positions and Bit Masks for the WDT_CTRL register + * @{ + */ +#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */ +#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */ +#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */ +#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an + * interrupt period has expired before the device resets. If the + * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration, + * the device will not reset. */ +#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */ +#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */ +#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */ +#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */ +#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */ +#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */ +/**@} end of group WDT_CTRL */ +/** + * @ingroup wdt_registers + * @defgroup WDT_FLAGS_Register WDT_FLAGS Register + * @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset. + * @{ + */ +#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */ +#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */ +#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */ +#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register during the pre-window period. */ +#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */ +#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */ +/**@} end of group WDT_FLAGS */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_ENABLE_Register WDT_ENABLE Register + * @brief Field Positions and Bit Masks for the WDT_ENABLE register. + * @{ + */ +#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */ +#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */ +#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */ +#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */ +#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */ +#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */ +/**@} end of group WDT_ENABLE */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register + * @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register. + * @{ + */ +#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */ +#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */ +/**@} end of group WDT_ENABLE */ + + + +/* + Field values and shifted values for module WDT. +*/ +/** + * @ingroup WDT_CTRL_Register + * @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values + * @brief Field values and Shifted Field values for the WDT_CTRL register. + * @details Shifted field values are field values shifted to the loacation of the field in the register. + */ +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period + * @brief Sets the duration of the watchdog interrupt period. + * @details The INT_PERIOD field sets the duration of the watchdog interrupt + * period, which is the time period from the WDT being + * enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is + * set. + * The values defined are in the number of watchdog clock cycles. + * @{ + */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */ +#define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */ +/**@} end of group WDT_CTRL_INT_PERIOD_Value */ + +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values + * @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value + * @details The shifted value is + * shifted to align with the fields location in the WDT_CTRL register. + * @{ + */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */ +#define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */ +/**@} end of group WDT_CTRL_INT_PERIOD_Shifted */ +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period + * @brief Sets the duration of the watchdog reset period. + * @details The RST_PERIOD field sets the duration of the watchdog reset + * period, which is the time period from the WDT being + * enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is + * set. + * The values defined are in the number of watchdog clock cycles. + * @{ + */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */ +/**@} end of group WDT_CTRL_RST_PERIOD_Value */ + +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values + * @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value + * @details These values are shifted to align with the field's location in the WDT_CTRL register. + * @{ + */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */ +#define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */ +/**@} end of group WDT_CTRL_RST_PERIOD_Shifted */ +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period + * @brief Sets the duration of the watchdog wait window period. + * @details The WAIT_PERIOD field sets the duration of the watchdog pre-window + * period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur. + * This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting + * overclocking or an invalid clock. + * The values defined are in the number of watchdog clock cycles. + * @{ + */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */ +#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */ +/**@} end of group WDT_CTRL_WAIT_PERIOD_Value */ + +/** + * @ingroup WDT_CTRL_field_values + * @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values + * @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value + * @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register. + * @{ + */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */ +#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */ +/**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */ + +/** + * @ingroup WDT_LOCK_CTRL_Register + * @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values + * @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register. + * @{ + */ +#define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */ +#define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */ +/**@} end of group WDT_LOCK_field_values */ +///@cond +/* + * @internal + * @ingroup WDT_CLEAR_Register + * @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values + * @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count. + * @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter. + * @{ + */ +#define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */ +#define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */ +/** + * @} end of group WDT_CLEAR_field_values + * @endinternal + */ +///@endcond +/**@} wdt_registers*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_WDT_REGS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c new file mode 100644 index 00000000000..2b5bb5e41b7 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c @@ -0,0 +1,128 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +uint32_t gpio_set(PinName name) +{ + MBED_ASSERT(name != (PinName)NC); + pin_function(name, 0); + return 1 << PINNAME_TO_PIN(name); +} + +void gpio_init(gpio_t *obj, PinName name) +{ + obj->name = name; + if (name == (PinName)NC) { + return; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin); + obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin); + obj->mode = PullDefault; + + /* Ensure that the GPIO clock is enabled */ + MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER; + + /* Ensure that the GPIO clock is enabled */ + MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + obj->mode = mode; + pin_mode(obj->name, mode); +} + +void pin_dir_mode(PinName name, PinDirection direction, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Set function; Firmware Control (GPIO mode) */ + MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin)); + + /* Normal input is always enabled */ + MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); + + uint32_t new_mode; + if (direction == PIN_OUTPUT) { + // PullUp = not valid, + // PullDown = not valid, + // OpenDrain = MXC_V_GPIO_OUT_MODE_OD, + // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL, + if (mode == OpenDrain) { + new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_NORMAL; + } + } else { + // PullUp = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP + // PullDown = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN + // OpenDrain = MXC_V_GPIO_OUT_MODE_OD + // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z + if (mode == PullUp) { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP; + MXC_GPIO->out_val[port] |= 1 << pin; + } else if (mode == PullDown) { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN; + MXC_GPIO->out_val[port] &= ~(1 << pin); + } else if (mode == OpenDrain) { + new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; + MXC_GPIO->out_val[port] |= 1 << pin; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z; + MXC_GPIO->out_val[port] &= ~(1 << pin); + } + } + + /* Set new mode */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + out_mode &= ~(0xF << (pin * 4)); + out_mode |= (new_mode << (pin * 4)); + MXC_GPIO->out_mode[port] = out_mode; +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + pin_dir_mode(obj->name, direction, obj->mode); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c new file mode 100644 index 00000000000..143969229a5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c @@ -0,0 +1,183 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}}; +static gpio_irq_handler irq_handler; + +static void handle_irq(unsigned int port) +{ + uint32_t intfl, in_val; + uint32_t mask; + unsigned int pin; + + /* Read pin state */ + in_val = MXC_GPIO->in_val[port]; + + /* Read interrupts */ + intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; + + mask = 1; + + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if (intfl & mask) { + MXC_GPIO->intfl[port] = mask; /* clear interrupt */ + gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL; + gpio_irq_t *obj = objs[port][pin]; + if (obj && obj->id) { + if ((event == IRQ_RISE) && obj->rise_en) { + irq_handler(obj->id, IRQ_RISE); + } else if ((event == IRQ_FALL) && obj->fall_en) { + irq_handler(obj->id, IRQ_FALL); + } + } + } + mask <<= 1; + } +} + +void gpio_irq_0(void) { handle_irq(0); } +void gpio_irq_1(void) { handle_irq(1); } +void gpio_irq_2(void) { handle_irq(2); } +void gpio_irq_3(void) { handle_irq(3); } +void gpio_irq_4(void) { handle_irq(4); } +void gpio_irq_5(void) { handle_irq(5); } +void gpio_irq_6(void) { handle_irq(6); } +void gpio_irq_7(void) { handle_irq(7); } +void gpio_irq_8(void) { handle_irq(8); } + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +{ + if (name == NC) { + return -1; + } + + uint8_t port = PINNAME_TO_PORT(name); + uint8_t pin = PINNAME_TO_PIN(name); + + if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) { + return 1; + } + + obj->port = port; + obj->pin = pin; + obj->id = id; + objs[port][pin] = obj; + + /* register handlers */ + irq_handler = handler; + NVIC_SetVector(GPIO_P0_IRQn, gpio_irq_0); + NVIC_SetVector(GPIO_P1_IRQn, gpio_irq_1); + NVIC_SetVector(GPIO_P2_IRQn, gpio_irq_2); + NVIC_SetVector(GPIO_P3_IRQn, gpio_irq_3); + NVIC_SetVector(GPIO_P4_IRQn, gpio_irq_4); + NVIC_SetVector(GPIO_P5_IRQn, gpio_irq_5); + NVIC_SetVector(GPIO_P6_IRQn, gpio_irq_6); + NVIC_SetVector(GPIO_P7_IRQn, gpio_irq_7); + NVIC_SetVector(GPIO_P8_IRQn, gpio_irq_8); + + /* disable the interrupt locally */ + MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); + + /* clear a pending request */ + MXC_GPIO->intfl[port] = 1 << pin; + + /* enable the requested interrupt */ + MXC_GPIO->inten[port] |= (1 << pin); + NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port)); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + /* disable interrupt */ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); + MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); + objs[obj->port][obj->pin] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + if (event == IRQ_FALL) { + obj->fall_en = enable; + } else if (event == IRQ_RISE) { + obj->rise_en = enable; + } + + if (obj->fall_en && obj->rise_en) { + MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); + } else if (obj->fall_en) { + uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; + int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); + int_mode |= (MXC_V_GPIO_INT_MODE_FALLING_EDGE << (obj->pin*4)); + MXC_GPIO->int_mode[obj->port] = int_mode; + } else if (obj->rise_en) { + uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; + int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); + int_mode |= (MXC_V_GPIO_INT_MODE_RISING_EDGE << (obj->pin*4)); + MXC_GPIO->int_mode[obj->port] = int_mode; + } else { + MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); + } +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] |= (1 << obj->pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); +} + +gpio_irq_t *gpio_irq_get_obj(PinName name) +{ + if (name == NC) { + return NULL; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) { + return NULL; + } + + return objs[port][pin]; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_object.h b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_object.h new file mode 100644 index 00000000000..63c5be2c37c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_object.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName name; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PinMode mode; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->name != (PinName)NC); + *obj->reg_out = !!value; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->name != (PinName)NC); + return *obj->reg_in; +} + +void pin_dir_mode(PinName name, PinDirection direction, PinMode mode); + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->name != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c new file mode 100644 index 00000000000..6264b7405f0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c @@ -0,0 +1,213 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "i2c_api.h" +#include "i2cm_regs.h" +#include "i2cm.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 +#endif + +#define MBED_NAK 0 +#define MBED_ACK 1 +#define MBED_TIMEOUT 2 + +//****************************************************************************** +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // SDA and SCL must map to same peripheral instance + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c != NC); + + obj->i2c = i2c; + obj->fifo = MXC_I2CM_GET_FIFO(MXC_I2CM_GET_IDX(i2c)); + obj->start_pending = 0; + + // Merge pin function requests for use with CMSIS init func + ioman_req_t io_req; + pin_function_t *pin_func; + pin_func = (pin_function_t *)pinmap_find_function(sda, PinMap_I2C_SDA); + io_req.value = pin_func->req_val; + pin_func = (pin_function_t *)pinmap_find_function(scl, PinMap_I2C_SCL); + io_req.value |= pin_func->req_val; + + obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req; + obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack; + obj->sys_cfg.io_cfg.req_val = io_req; + obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_1; + + I2CM_Init(obj->i2c, &obj->sys_cfg, I2CM_SPEED_400KHZ); +} + +//****************************************************************************** +void i2c_frequency(i2c_t *obj, int hz) +{ + I2CM_Init(obj->i2c, &obj->sys_cfg, hz); +} + +//****************************************************************************** +int i2c_start(i2c_t *obj) +{ + obj->start_pending = 1; + return 0; +} + +//****************************************************************************** +int i2c_stop(i2c_t *obj) +{ + obj->start_pending = 0; + I2CM_WriteTxFifo(obj->i2c, obj->fifo, MXC_S_I2CM_TRANS_TAG_STOP); + I2CM_TxInProgress(obj->i2c); + return 0; +} + +//****************************************************************************** +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + MBED_ASSERT(stop != 0); + return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length); +} + +//****************************************************************************** +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + mxc_i2cm_regs_t *i2cm = obj->i2c; + mxc_i2cm_fifo_regs_t *fifo = obj->fifo; + + if (stop) { + return I2CM_Write(i2cm, address >> 1, NULL, 0, (uint8_t *)data, length); + } + + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + if (I2CM_Tx(i2cm, fifo, address >> 1, (uint8_t *)data, length, 0) == E_NO_ERROR) { + return length; + } else { + return -1; + } +} + +//****************************************************************************** +void i2c_reset(i2c_t *obj) +{ + I2CM_Recover(obj->i2c); +} + +//****************************************************************************** +int i2c_byte_read(i2c_t *obj, int last) +{ + mxc_i2cm_regs_t *i2cm = obj->i2c; + mxc_i2cm_fifo_regs_t *fifo = obj->fifo; + int tmp; + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + + if (last) { + // NACK the last read byte + if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) { + goto byte_read_err; + } + + // Send the stop condition + if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) { + goto byte_read_err; + } + } else { + if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) { + goto byte_read_err; + } + } + + do { + // Wait for data in RX FIFO + int timeout = MXC_I2CM_RX_TIMEOUT; + while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + ((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) { + + if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) { + goto byte_read_err; + } + + if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) { + goto byte_read_err; + } + } + i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + + } while ((tmp = fifo->rx) & MXC_S_I2CM_RSTLS_TAG_EMPTY); + + return (uint8_t)tmp; + +byte_read_err: + i2c_reset(obj); + return -1; +} + +//****************************************************************************** +int i2c_byte_write(i2c_t *obj, int data) +{ + mxc_i2cm_regs_t *i2cm = obj->i2c; + mxc_i2cm_fifo_regs_t *fifo = obj->fifo; + int result; + + if (obj->start_pending) { + obj->start_pending = 0; + data |= MXC_S_I2CM_TRANS_TAG_START; + } else { + data |= MXC_S_I2CM_TRANS_TAG_TXDATA_ACK; + } + + if ((result = I2CM_WriteTxFifo(i2cm, fifo, data)) != E_NO_ERROR) { + i2c_reset(obj); + if (result == E_COMM_ERR) { + return MBED_NAK; + } + return MBED_TIMEOUT; + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + + return MBED_ACK; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.c new file mode 100644 index 00000000000..fb9158ae8f8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.c @@ -0,0 +1,180 @@ +/** + * @file + * @brief This file contains the function implementations for the Analog to + * Digital Converter (ADC) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 12:50:50 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24349 $ + * + *************************************************************************** */ + +/** + * @ingroup adc + * @{ + */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "adc.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************* */ +int ADC_Init(void) +{ + int err; + + if ((err = SYS_ADC_Init()) != E_NO_ERROR) { + return err; + } + + /* Wipe previous configuration */ + MXC_ADC->intr = 0; + + /* Clear all ADC interrupt flags (W1C) */ + MXC_ADC->intr = MXC_ADC->intr; + + /* Enable done interrupt */ + MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IE; + + /* Power up the ADC */ + MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU | + MXC_F_ADC_CTRL_ADC_CLK_EN | + MXC_F_ADC_CTRL_BUF_PU | + MXC_F_ADC_CTRL_ADC_REFBUF_PU | + MXC_F_ADC_CTRL_ADC_CHGPUMP_PU); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass) +{ + uint32_t ctrl_tmp; + + /* Clear the ADC done flag */ + ADC_ClearFlags(MXC_F_ADC_INTR_ADC_DONE_IF); + + /* Insert channel selection */ + ctrl_tmp = MXC_ADC->ctrl; + ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_CHSEL); + ctrl_tmp |= ((channel << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL); + + /* Clear channel configuration */ + ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS); + + /* ADC reference scaling must be set for all channels but two*/ + if ((channel != ADC_CH_VDD18) && (channel != ADC_CH_VDD12)) { + ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL; + } + + /* Finalize user-requested channel configuration */ + if (adc_scale || channel > ADC_CH_3) { + ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE; + } + if (bypass) { + ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS; + } + + /* Write this configuration */ + MXC_ADC->ctrl = ctrl_tmp; + + /* Start conversion */ + MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START; + +} + +/* ************************************************************************* */ +int ADC_GetData(uint16_t *outdata) +{ + /* See if a conversion is in process */ + if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_ACTIVE) { + /* Wait for conversion to complete */ + while ((MXC_ADC->intr & MXC_F_ADC_INTR_ADC_DONE_IF) == 0); + } + + /* Read 32-bit value and truncate to 16-bit for output depending on data align bit*/ + if((MXC_ADC->ctrl & MXC_F_ADC_CTRL_ADC_DATAALIGN) == 0) + *outdata = (uint16_t)(MXC_ADC->data); /* LSB justified */ + else + *outdata = (uint16_t)(MXC_ADC->data >> 6); /* MSB justified */ + + /* Check for overflow */ + if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_OVERFLOW) { + return E_OVERFLOW; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel, + unsigned int low_enable, unsigned int low_limit, + unsigned int high_enable, unsigned int high_limit) +{ + /* Check args */ + if ((unit >= ADC_LIMIT_MAX) || (channel >= ADC_CH_MAX)) + return E_BAD_PARAM; + + /* set channel using the limit */ + MXC_ADC->limit[unit] = ((channel << MXC_F_ADC_LIMIT0_CH_SEL_POS) & MXC_F_ADC_LIMIT0_CH_SEL); + + /* enable/disable the limit*/ + if (low_enable) { + MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN | + ((low_limit << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_LO_LIMIT); + } + else{ + MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN; + } + + if (high_enable) { + MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN | + ((high_limit << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_HI_LIMIT); + } + else{ + MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN; + } + + return E_NO_ERROR; +} + +/**@} end of group adc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.h new file mode 100644 index 00000000000..4729c425238 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.h @@ -0,0 +1,217 @@ +/** + * @file + * @brief Analog to Digital Converter function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-07 14:53:52 -0500 (Fri, 07 Oct 2016) $ + * $Revision: 24632 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _ADC_H +#define _ADC_H + +/* **** Includes **** */ +#include + +/* Doxy group definition for this peripheral module */ + +/** + * @ingroup periphlibs + * @defgroup adc Analog to Digital Converter (ADC) + * @{ + */ + +#include "adc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* **** Definitions **** */ + +/** + * Enumeration type for ADC Channel Selection. See \ref ADC_CHSEL_values "ADC Channel Select Values" for additional information. + */ +typedef enum { + ADC_CH_0 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0, /**< Channel 0 Select */ + ADC_CH_1 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1, /**< Channel 1 Select */ + ADC_CH_2 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN2, /**< Channel 2 Select */ + ADC_CH_3 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN3, /**< Channel 3 Select */ + ADC_CH_0_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5, /**< Channel 0 divided by 5 */ + ADC_CH_1_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5, /**< Channel 1 divided by 5 */ + ADC_CH_VDDB_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4, /**< VDDB divided by 4 */ + ADC_CH_VDD18 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD18, /**< VDD18 input select */ + ADC_CH_VDD12 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD12, /**< VDD12 input select */ + ADC_CH_VRTC_DIV_2 = MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2, /**< VRTC divided by 2 */ + ADC_CH_TMON = MXC_V_ADC_CTRL_ADC_CHSEL_TMON, /**< TMON input select */ +#if (MXC_ADC_REV > 0) + ADC_CH_VDDIO_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4, /**< VDDIO divided by 4 select */ + ADC_CH_VDDIOH_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4, /**< VDDIOH divided by 4 select */ +#endif + ADC_CH_MAX /**< Max enum value for channel selection */ +} mxc_adc_chsel_t; + +/** + * Enumeration type for the ADC limit register to set + */ +typedef enum { + ADC_LIMIT_0 = 0, /**< ADC Limit Register 0 */ + ADC_LIMIT_1 = 1, /**< ADC Limit Register 1 */ + ADC_LIMIT_2 = 2, /**< ADC Limit Register 2 */ + ADC_LIMIT_3 = 3, /**< ADC Limit Register 3 */ + ADC_LIMIT_MAX /**< Number of Limit registers */ +} mxc_adc_limitsel_t; + +///@cond +/** + * Mask for all Interrupt Flag Fields + */ +#define ADC_IF_MASK (0xffffffffUL << MXC_F_ADC_INTR_ADC_DONE_IF_POS) + +/** + * Mask for all Interrupt Enable Fields + */ +#define ADC_IE_MASK (0xffffffffUL >> MXC_F_ADC_INTR_ADC_DONE_IF_POS) +///@endcond + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the ADC hardware + * + * @return #E_NO_ERROR if successful + */ +int ADC_Init(void); + +/** + * @brief Start ADC conversion on the selected channel + * + * @param channel Channel select from #mxc_adc_chsel_t + * @param adc_scale Enable the ADC input scaling mode if non-zero + * @param bypass Bypass input buffer stage if non-zero + */ +void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass); + +/** + * @brief Gets the result from the previous ADC conversion + * + * @param outdata Pointer to store the ADC data conversion + * result. + * @return #E_OVERFLOW ADC overflow error + * @return #E_NO_ERROR Data returned in outdata parameter + */ +int ADC_GetData(uint16_t *outdata); + +/** + * @brief Set the data limits for an ADC channel monitor + * + * @param unit Which data limit unit to configure + * @param channel Channel select from mxc_adc_chsel_t + * @param low_enable Enable the lower limit on this monitor + * @param low_limit Value for lower limit monitor + * @param high_enable Enable the upper limit on this monitor + * @param high_limit Value for upper limit monitor + * + * @return #E_BAD_PARAM ADC limit or channel greater than supported + * @return #E_NO_ERROR ADC limit set successfully + */ +int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel, + unsigned int low_enable, unsigned int low_limit, + unsigned int high_enable, unsigned int high_limit); + +/** + * @brief Get interrupt flags + * + * @return ADC Interrupt flags bit mask. See the @ref ADC_INTR_IF_Register + * "ADC_INTR Register" for the interrupt flag masks. + */ +__STATIC_INLINE uint32_t ADC_GetFlags() +{ + return (MXC_ADC->intr & ADC_IF_MASK); +} + +/** + * @brief Clear interrupt flag(s) using the mask parameter. All bits set in + * the parameter will be cleared. + * + * @param mask Interrupt flags to clear. See the @ref ADC_INTR_IF_Register + * "ADC_INTR Register" for the interrupt flag masks. + */ +__STATIC_INLINE void ADC_ClearFlags(uint32_t mask) +{ + MXC_ADC->intr = ((MXC_ADC->intr & ADC_IF_MASK) | mask); +} + +/** + * @brief Get the Status of the ADC + * + * @return ADC status register. See @ref ADC_STATUS_Register "ADC_STATUS + * Register" for details. + */ +__STATIC_INLINE uint32_t ADC_GetStatus() +{ + return (MXC_ADC->status); +} + +/** + * @brief Enables the ADC interrupts specified by the mask parameter + * + * @param mask ADC interrupts to enable. See @ref ADC_INTR_IE_Register + * "ADC_INTR Register" for the interrupt enable bit masks. + */ +__STATIC_INLINE void ADC_EnableINT(uint32_t mask) +{ + MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) | mask); +} + +/** + * @brief Disable ADC interrupts based on mask + * + * @param mask ADC interrupts to disable. See @ref ADC_INTR_IE_Register + * "ADC_INTR Register" for the interrupt enable bit masks. + */ +__STATIC_INLINE void ADC_DisableINT(uint32_t mask) +{ + MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) & ~mask); +} + +/**@} end of group adc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADC_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.c new file mode 100644 index 00000000000..cf5cbd2f549 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.c @@ -0,0 +1,214 @@ +/** + * @file + * @brief This file contains the function implementations for the Advanced + * Encryption Standard (AES) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 12:50:17 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24348 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include /* Included for memcpy() & #includes stddef for NULL */ + +#include "mxc_config.h" +#include "aes.h" +#include "nvic_table.h" + +/** + * @ingroup aes + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Local Function Prototypes **** */ +static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count); + +/* **** Functions **** */ + +/* ************************************************************************* */ +int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode) +{ + unsigned int len; + + /* Erase any existing key */ + MXC_AES_MEM->key[7] = MXC_AES_MEM->key[6] = MXC_AES_MEM->key[5] = MXC_AES_MEM->key[4] \ + = MXC_AES_MEM->key[3] = MXC_AES_MEM->key[2] = MXC_AES_MEM->key[1] = MXC_AES_MEM->key[0] \ + = 0x00000000; + + /* Determine length of key */ + if (mode == MXC_E_AES_MODE_256) { + len = MXC_AES_KEY_256_LEN; + } else if (mode == MXC_E_AES_MODE_192) { + len = MXC_AES_KEY_192_LEN; + } else if (mode == MXC_E_AES_MODE_128) { + len = MXC_AES_KEY_128_LEN; + } else { + return E_BAD_PARAM; + } + + /* Load new key, based on key mode */ + if (aes_memcpy32((uint32_t *)MXC_AES_MEM->key, (uint32_t *)key, len / sizeof(uint32_t)) < 0) { + return E_NULL_PTR; + } + + return E_SUCCESS; +} + +/* ************************************************************************* */ +int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir) +{ + /* Output array can't be a NULL, unless we are in _ASYNC mode */ + if ((out == NULL) + && ((dir != MXC_E_AES_ENCRYPT_ASYNC) && (dir != MXC_E_AES_DECRYPT_ASYNC))) { + return E_NULL_PTR; + } + + /* Another encryption is already in progress */ + if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) { + return E_BUSY; + } + + /* Clear interrupt flag and any existing configuration*/ + MXC_AES->ctrl = MXC_F_AES_CTRL_INTFL; + + /* Select key size & direction + * + * Note: This is done first to detect argument errors, before sensitive data + * is loaded into AES_MEM block + * + */ + switch (mode) { + case MXC_E_AES_MODE_128: + MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_128; + break; + + case MXC_E_AES_MODE_192: + MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_192; + break; + + case MXC_E_AES_MODE_256: + MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_256; + break; + + default: + return E_BAD_PARAM; + } + + switch (dir) { + case MXC_E_AES_ENCRYPT: + case MXC_E_AES_ENCRYPT_ASYNC: + MXC_AES->ctrl |= MXC_S_AES_CTRL_ENCRYPT_MODE; + break; + + case MXC_E_AES_DECRYPT: + case MXC_E_AES_DECRYPT_ASYNC: + MXC_AES->ctrl |= MXC_S_AES_CTRL_DECRYPT_MODE; + break; + + default: + return E_BAD_PARAM; + } + + /* If non-blocking mode has been selected, interrupts are automatically enabled */ + if ((dir == MXC_E_AES_ENCRYPT_ASYNC) || + (dir == MXC_E_AES_DECRYPT_ASYNC)) { + MXC_AES->ctrl |= MXC_F_AES_CTRL_INTEN; + } + + /* Load input into engine */ + if (aes_memcpy32((uint32_t *)MXC_AES_MEM->inp, (uint32_t *)in, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) { + return E_NULL_PTR; + } + + /* Start operation */ + MXC_AES->ctrl |= MXC_F_AES_CTRL_START; + + /* Block, waiting on engine to complete, or fall through if non-blocking */ + if ((dir != MXC_E_AES_ENCRYPT_ASYNC) && + (dir != MXC_E_AES_DECRYPT_ASYNC)) { + while (MXC_AES->ctrl & MXC_F_AES_CTRL_START) { + /* Ensure that this wait loop is not optimized out */ + __NOP(); + } + + /* Get output from engine */ + return AES_GetOutput(out); + } + + return E_SUCCESS; +} + +/* ************************************************************************* */ +int AES_GetOutput(uint8_t *out) +{ + /* Don't read it out of the AES memory unless engine is idle */ + if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) { + return E_BUSY; + } + + /* Pull out result */ + if (aes_memcpy32((uint32_t *)out, (uint32_t *)MXC_AES_MEM->out, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) { + return E_NULL_PTR; + } + + /* Clear interrupt flag, write 1 to clear */ + MXC_AES->ctrl |= MXC_F_AES_CTRL_INTFL; + + return E_SUCCESS; +} + +/** + * @internal This memory copy is used only by the AES module to avoid data leakage by the standard C library. + * Copy count number of 32-bit locations from in to out + */ +static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count) +{ + if ((out == NULL) || (in == NULL)) { + /* Invalid arguments, but is internal-only so don't use error codes */ + return -1; + } + + while (count--) { + *out++ = *in++; + } + + return 0; +} + +/**@} end of group aes */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h new file mode 100644 index 00000000000..70e452d1ca6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h @@ -0,0 +1,206 @@ +/** + * @file + * @brief Advanced Encryption Standard (AES) function prototypes and data + * types. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24655 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _AES_H +#define _AES_H +/* **** Includes **** */ +#include +#include "aes_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup aes Advanced Encryption Standard (AES) + * @brief High-level API for AES encryption engine + */ + +/** + * @ingroup aes + * @defgroup aes_overview Overview and Usage + * @brief Advanced Encryption Standard API public include file. + * @details + * Key/data format in memory + * The API functions require that key and plain/ciphertext will be stored as a + * byte array in LSB .. MSB format. + * @par + * As an example, given the key @a 0x139A35422F1D61DE3C91787FE0507AFD, the proper storage order is: + * ~~~~~ + * uint8_t key[16] = { 0xFD, 0x7A, 0x50, 0xE0, + * 0x7F, 0x78, 0x91, 0x3C, + * 0xDE, 0x61, 0x1D, 0x2F, + * 0x42, 0x35, 0x9A, 0x13 }; + * ~~~~~ + * This is the same order expected by the underlying hardware. + */ + +/* **** Definitions **** */ +/** + * @ingroup aes + * @{ + */ +#define MXC_AES_DATA_LEN (128 / 8) /**< Number of bytes in an AES plaintext or cyphertext block, which are always 128-bits long. */ +#define MXC_AES_KEY_128_LEN (128 / 8) /**< Number of bytes in a AES-128 key. */ +#define MXC_AES_KEY_192_LEN (192 / 8) /**< Number of bytes in a AES-192 key. */ +#define MXC_AES_KEY_256_LEN (256 / 8) /**< Number of bytes in a AES-256 key. */ + +/** + * Enumeration type for AES key size selection (bits). + */ +typedef enum { + MXC_E_AES_MODE_128 = MXC_V_AES_CTRL_KEY_SIZE_128, /**< 128-bit key. */ + MXC_E_AES_MODE_192 = MXC_V_AES_CTRL_KEY_SIZE_192, /**< 192-bit key. */ + MXC_E_AES_MODE_256 = MXC_V_AES_CTRL_KEY_SIZE_256 /**< 256-bit key. */ +} mxc_aes_mode_t; + +/** + * Enumeration type for specifying encryption/decrytion and asynchronous or blocking behavior. + */ +typedef enum { + MXC_E_AES_ENCRYPT = 0, /**< Encrypt (synchronous/blocking). */ + MXC_E_AES_ENCRYPT_ASYNC = 1, /**< Encrypt (aynchronous/interrupt-driven). */ + MXC_E_AES_DECRYPT = 2, /**< Decrypt (synchronous/blocking). */ + MXC_E_AES_DECRYPT_ASYNC = 3 /**< Decrypt (aynchronous/interrupt-driven). */ +} mxc_aes_dir_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Configure AES block with keying material + * + * @param key 128, 192, or 256 bit keying material + * @param mode The key length, see #mxc_aes_mode_t for supported lengths. + * + * @return #E_BAD_PARAM Specified @a mode is invalid, see #mxc_aes_mode_t. + * @return #E_NULL_PTR Invalid/Null pointer for parameter @a key. + * @return #E_SUCCESS Key and mode set up correctly. + */ +int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode); + + +/** + * @brief Encrypt/decrypt an input block with the loaded AES key. + * @note The parameters @a in and @a out must be 16 bytes. + * + * @param in Pointer to input array of 16 bytes. + * @param out Pointer to output array of 16 bytes. + * @param mode AES key size to use for the transaction, see #mxc_aes_mode_t for supported key sizes. + * @param dir Operation to perform, see #mxc_aes_dir_t for supported operations. + * + * @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out. + * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured. + */ +int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir); + +/** + * @brief Read the AES output memory, used for asynchronous encryption, and + * clears interrupt flag. + * @note The parameter @a out must always be 16 bytes. + * + * @param out Pointer to a 16-byte array to store the output from the AES operation. + * + * @return #E_SUCCESS Output data was written to the location pointed + * to by @a *out. + * @return A @ref MXC_Error_Codes "Error Code" indicating the error that + * occured. + */ +int AES_GetOutput(uint8_t *out); + +/** + * @def AES_ECBEncrypt(ptxt, ctxt, mode) + * @brief Encrypt a block of plaintext with the loaded AES key, blocks + * until complete. + * @hideinitializer + * + * @param ptxt Pointer to plaintext input array (always 16 bytes) + * @param ctxt Pointer to ciphertext output array (always 16 bytes) + * @param mode Selects key length, valid modes found in mxc_aes_mode_t + */ +#define AES_ECBEncrypt(ptxt, ctxt, mode) AES_ECBOp(ptxt, ctxt, mode, MXC_E_AES_ENCRYPT) + + +/** + * @def AES_ECBDecrypt(ctxt, ptxt, mode) + * @hideinitializer + * @brief Decrypt a block of ciphertext with the loaded AES key, blocks + * until complete. + * + * @param ctxt Pointer to ciphertext output array (always 16 bytes) + * @param ptxt Pointer to plaintext input array (always 16 bytes) + * @param mode Selects key length, valid modes found in mxc_aes_mode_t + */ +#define AES_ECBDecrypt(ctxt, ptxt, mode) AES_ECBOp(ctxt, ptxt, mode, MXC_E_AES_DECRYPT) + +/** + * @def AES_ECBEncryptAsync(ptxt, mode) + * @hideinitializer + * @brief Starts encryption of a block, enables interrupt, and returns + * immediately. Use AES_GetOuput() to retrieve result after + * interrupt fires + * + * + * @param ptxt Pointer to plaintext input array (always 16 bytes) + * @param mode Selects key length, valid modes found in mxc_aes_mode_t + */ +#define AES_ECBEncryptAsync(ptxt, mode) AES_ECBOp(ptxt, NULL, mode, MXC_E_AES_ENCRYPT_ASYNC) + +/** + * @def AES_ECBDecryptAsync(ctxt, mode) + * @hideinitializer + * @brief Starts encryption of a block, enables interrupt, and returns + * immediately. Use AES_GetOuput() to retrieve result after + * interrupt fires + * + * @param ctxt Pointer to ciphertext output array (always 16 bytes) + * @param mode Selects key length, valid modes found in mxc_aes_mode_t + */ +#define AES_ECBDecryptAsync(ctxt, mode) AES_ECBOp(ctxt, NULL, mode, MXC_E_AES_DECRYPT_ASYNC) + +/**@} end of group aes*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c new file mode 100644 index 00000000000..30b7ebfb44c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c @@ -0,0 +1,185 @@ +/** + * @file + * @brief System Clock Management (CLKMAN) Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $ + * $Revision: 24058 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "clkman.h" +#include "pwrseq_regs.h" + + /** + * @ingroup clkman + * @{ + */ + +/* ************************************************************************* */ +void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale) +{ + MXC_CLKMAN->clk_ctrl = ((MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) | + (MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO)); + + switch(select) { + case CLKMAN_SYSTEM_SOURCE_96MHZ: + default: + // Enable and select the 96MHz oscillator + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN); + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT); + + // Disable the 4MHz oscillator + MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN; + + // Divide the system clock by the scale + MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RO_DIV) | + (scale << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)); + + break; + case CLKMAN_SYSTEM_SOURCE_4MHZ: + // Enable and select the 4MHz oscillator + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN); + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT); + + // Disable the 96MHz oscillator + MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN; + + // 4MHz System source can only be divided down by a maximum factor of 8 + MXC_ASSERT(scale <= CLKMAN_SYSTEM_SCALE_DIV_8); + + // Divide the system clock by the scale + MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RC_DIV) | + (scale << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)); + break; + } + + SystemCoreClockUpdate(); +} + +/* ************************************************************************* */ +void CLKMAN_CryptoClockEnable(int enable) +{ + if (enable) { + /* Enable oscillator */ + MXC_CLKMAN->clk_config |= MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE; + /* Un-gate clock to TPU modules */ + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE; + } else { + /* Gate clock off */ + MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE; + /* Disable oscillator */ + MXC_CLKMAN->clk_config &= ~MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE; + } +} + +/* ************************************************************************* */ +void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale) +{ + volatile uint32_t *clk_ctrl_reg; + + MXC_ASSERT(clk <= CLKMAN_CLK_MAX); + MXC_ASSERT(scale != CLKMAN_SCALE_AUTO); + + if (clk < CLKMAN_CRYPTO_CLK_AES) { + clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk; + } else { + clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES); + } + + *clk_ctrl_reg = scale; +} + +/* ************************************************************************* */ +clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk) +{ + volatile uint32_t *clk_ctrl_reg; + MXC_ASSERT(clk <= CLKMAN_CLK_MAX); + + if (clk < CLKMAN_CRYPTO_CLK_AES) { + clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk; + } else { + clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES); + } + + return (clkman_scale_t)*clk_ctrl_reg; +} + +/* ************************************************************************* */ +void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable) +{ + if (enable) { + MXC_CLKMAN->clk_ctrl |= clk; + } else { + MXC_CLKMAN->clk_ctrl &= ~clk; + } +} + +/* ************************************************************************ */ +int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select) +{ + MXC_ASSERT(idx < MXC_CFG_WDT_INSTANCES); + + if (select == CLKMAN_WDT_SELECT_DISABLED) { + if (idx == 0) { + MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE; + } else if (idx == 1) { + MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE; + } else { + return E_BAD_PARAM; + } + } else { + if (idx == 0) { + MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT) | + MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE | + ((select << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT); + } else if (idx == 1) { + MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT) | + MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE | + ((select << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT); + } else { + return E_BAD_PARAM; + } + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +/* NOTE: CLKMAN_TrimRO() is implemented in system_max32XXX.c */ +/* ************************************************************************* */ + +/**@} end of group clkman */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h new file mode 100644 index 00000000000..89469b18f0d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h @@ -0,0 +1,271 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the System Clock + * Management (CLKMAN) module. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $ + * $Revision: 24058 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _CLKMAN_H_ +#define _CLKMAN_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "clkman_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup clkman Clock Management + * @ingroup sysconfig + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type specifying the System Clock Rate. @see CLKMAN_SYSTEM_SOURCE_values + */ +typedef enum { + CLKMAN_SYSTEM_SOURCE_96MHZ = 0, /**< Clock select for 96MHz oscillator.*/ + CLKMAN_SYSTEM_SOURCE_4MHZ = 1 /**< Clock select for 4MHz oscillator. */ +} +clkman_system_source_select_t; + +/** + * Enumeration type for setting the system clock divider. + * @note 4MHz System source can only be divided down by a maximum factor of 8. + */ +typedef enum { + CLKMAN_SYSTEM_SCALE_DIV_1 = 0, /**< Clock scale for dividing system by 1. */ + CLKMAN_SYSTEM_SCALE_DIV_2 = 1, /**< Clock scale for dividing system by 2. */ + CLKMAN_SYSTEM_SCALE_DIV_4 = 2, /**< Clock scale for dividing system by 4. */ + CLKMAN_SYSTEM_SCALE_DIV_8 = 3, /**< Clock scale for dividing system by 8. */ + CLKMAN_SYSTEM_SCALE_DIV_16 = 4 /**< Clock scale for dividing system by 16. */ +} clkman_system_scale_t; + +/** + * Enumeration type for selecting a peripheral module for setting and getting it's clock scale. + */ +typedef enum { + CLKMAN_CLK_CPU = 0, /**< CPU clock. */ + CLKMAN_CLK_SYNC = 1, /**< Synchronizer clock. */ + CLKMAN_CLK_SPIX = 2, /**< SPI XIP module clock. */ + CLKMAN_CLK_PRNG = 3, /**< PRNG module clock. */ + CLKMAN_CLK_WDT0 = 4, /**< Watchdog Timer 0 clock. */ + CLKMAN_CLK_WDT1 = 5, /**< Watchdog Timer 1 clock. */ + CLKMAN_CLK_GPIO = 6, /**< GPIO module clock. */ + CLKMAN_CLK_PT = 7, /**< Pulse Train engine clock. */ + CLKMAN_CLK_UART = 8, /**< UART clock. */ + CLKMAN_CLK_I2CM = 9, /**< I2C Master module clock (for all instances). */ + CLKMAN_CLK_I2CS = 10, /**< I2C Slave module clock. */ + CLKMAN_CLK_SPIM0 = 11, /**< SPI Master instance 0 module clock. */ + CLKMAN_CLK_SPIM1 = 12, /**< SPI Master instance 1 module clock. */ + CLKMAN_CLK_SPIM2 = 13, /**< SPI Master instance 2 module clock. */ + CLKMAN_CLK_SPIB = 14, /**< SPI Bridge module clock. */ + CLKMAN_CLK_OWM = 15, /**< OWM module clock. */ + CLKMAN_CLK_SPIS = 16, /**< SPI Slave module clock. */ + CLKMAN_CRYPTO_CLK_AES = 17, /**< AES engine clock. */ + CLKMAN_CRYPTO_CLK_MAA = 18, /**< Modular Arithmetic Accelerator (MAA) clock. */ + CLKMAN_CRYPTO_CLK_PRNG = 19, /**< Pseudo-random number Generator (PRNG) clock. */ + CLKMAN_CLK_MAX /**< Maximum value of enum for limit checking. */ +} clkman_clk_t; + +/** + * Enumeration type for selecting a peripheral module (USB, Cryto, ADC, WDT0, WDT1 and RTC/RTOS) + * to enable/disable clock gating. + */ +typedef enum { + CLKMAN_USB_CLOCK = MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE, /**< Enable/Disable mask for USB. */ + CLKMAN_CRYPTO_CLOCK = MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE, /**< Enable/Disable mask for Crypto Clock. */ + CLKMAN_ADC_CLOCK = MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE, /**< Enable/Disable mask for ADC. */ + CLKMAN_WDT0_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 0. */ + CLKMAN_WDT1_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 1. */ + CLKMAN_RTOS_MODE = MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE /**< Enable/Disable mask for 32kHz clock in LP1 + * required to use JTAG for debug. + */ +} clkman_enable_clk_t; + +/** + * Enumeration type for selecting the clock scale for the system or peripheral module. + */ +typedef enum { + CLKMAN_SCALE_DISABLED = MXC_V_CLKMAN_CLK_SCALE_DISABLED, /**< Clock disabled. */ + CLKMAN_SCALE_DIV_1 = MXC_V_CLKMAN_CLK_SCALE_DIV_1, /**< Clock scale for dividing by 1. */ + CLKMAN_SCALE_DIV_2 = MXC_V_CLKMAN_CLK_SCALE_DIV_2, /**< Clock scale for dividing by 2. */ + CLKMAN_SCALE_DIV_4 = MXC_V_CLKMAN_CLK_SCALE_DIV_4, /**< Clock scale for dividing by 4. */ + CLKMAN_SCALE_DIV_8 = MXC_V_CLKMAN_CLK_SCALE_DIV_8, /**< Clock scale for dividing by 8. */ + CLKMAN_SCALE_DIV_16 = MXC_V_CLKMAN_CLK_SCALE_DIV_16, /**< Clock scale for dividing by 16. */ + CLKMAN_SCALE_DIV_32 = MXC_V_CLKMAN_CLK_SCALE_DIV_32, /**< Clock scale for dividing by 32. */ + CLKMAN_SCALE_DIV_64 = MXC_V_CLKMAN_CLK_SCALE_DIV_64, /**< Clock scale for dividing by 64. */ + CLKMAN_SCALE_DIV_128 = MXC_V_CLKMAN_CLK_SCALE_DIV_128, /**< Clock scale for dividing by 128. */ + CLKMAN_SCALE_DIV_256 = MXC_V_CLKMAN_CLK_SCALE_DIV_256, /**< Clock scale for dividing by 256. */ + CLKMAN_SCALE_AUTO /**< Clock scale to auto select divider. */ +} clkman_scale_t; + +/* + * Enumeration type for selecting the source clock for the Watch Dog Timers. + * | Enumeration Selection | Value | WDT Clock Source | + * | :--------------------------------------: | :---: | :-------------------------- | + * | CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL | 0 | Scaled System Clock | + * | CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR | 1 | 32 kHz Real-Time Clock | + * | CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR | 2 | 96 MHz Oscillator unscaled | + * | CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR | 3 | Nano-ring clock | + * | CLKMAN_WDT_SELECT_DISABLED | 4 | WDT0 Clock is disabled | + */ +typedef enum { + CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0, /**< Use scaled system clock for Watchdog Timer 0. */ + CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR, /**< Use 32kHz oscillator for Watchdog Timer 0. */ + CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR, /**< Use 96MHz clock for Watchdog Timer 0. */ + CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR, /**< Use Nano-Ring Oscillator (8kHz) for Watchdog Timer 0 clock.*/ + CLKMAN_WDT_SELECT_DISABLED /**< Watchdog Timer 0 clock disabled. */ +} clkman_wdt_clk_select_t; + + +/* **** Function Prototypes **** */ + +/** + * @brief Selects the system clock source, + * @note 4MHz System source can only be divided down by a maximum factor + * of 8. + * + * @param select System clock source. + * @param scale System clock scaler. + */ +void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale); + +/** + * @brief Enables/disables the Crypto/TPU relaxation oscillator + * + * @param enable |:------- | :---: | + * | Enable | 1 | + * | Disable | 0 | + */ +void CLKMAN_CryptoClockEnable(int enable); + +/** + * @brief Enables/Disables clock gating for the specified peripheral + * module. + * + * @param clk Peripheral module to enable/disable clock gating. + * @param enable Enable (1) or Disable (0). + */ +void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable); + +/** + * @brief Sets the specified clock scaler value. + * + * @param clk Peripheral module to set the desired clock scale. + * @param scale Clock scale/divisor for the specified peripheral module. + */ +void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale); + +/** + * @brief Get the clock scaler/divisor value for the specified peripheral + * module. + * + * @param clk The peripheral module to get the current clock scale setting, see #clkman_clk_t. + * @return A value indicating the clock divisor/scale of the requested + * peripheral module. + */ +clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk); + +/** + * @brief Selects the clock source for the specified watchdog timer. + * + * @param idx Value indicating the WDT to set the clock source on. + * @param select Value of the desired clock source for the WDT. + */ +int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select); + +/** + * @brief Get the interrupt flags for the CLKMAN module. + * + * @return The current interrupt flags. + */ +__STATIC_INLINE uint32_t CLKMAN_GetFlags(void) +{ + return MXC_CLKMAN->intfl; +} + +/** + * @brief Clear the specified interrupt flags + * + * @param mask mask of clock management interrupt flags to clear + */ +__STATIC_INLINE void CLKMAN_ClrFlags(uint32_t mask) +{ + MXC_CLKMAN->intfl = mask; +} + +/** + * @brief Enable the interrupts specified in the mask parameter. + * + * @param mask Mask of clock management interrupts to enable, 1 to enable + * a specific interrupt. + */ +__STATIC_INLINE void CLKMAN_EnableInt(uint32_t mask) +{ + MXC_CLKMAN->inten |= mask; +} + +/** + * @brief Disable the specified interrupts + * + * @param mask Mask of CLKMAN interrupts to disable, 1 to disable a + * specific interrupt. + */ +__STATIC_INLINE void CLKMAN_DisableInt(uint32_t mask) +{ + MXC_CLKMAN->inten &= ~mask; +} + +/** + * @brief Trim the ring oscillator. + * @note CLKMAN_TrimRO() is implemented in system_max32XXX.c + */ +void CLKMAN_TrimRO(void); + +/**@} end of group clkman */ + +#ifdef __cplusplus +} +#endif + +#endif /* _CLKMAN_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.c new file mode 100644 index 00000000000..3d6085f2c04 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.c @@ -0,0 +1,108 @@ +/** + * @file + * @brief This file contains the function implementations for the Cyclic + * Redundency Check (CRC) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 11:49:04 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24339 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "crc.h" + +/** + * @ingroup crc + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************* */ +void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian) +{ + if(CCITT_TRUE) + MXC_CRC->reseed |= MXC_F_CRC_RESEED_CCITT_MODE; + else + MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_CCITT_MODE; + + if(lilEndian) + MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN16; + else + MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN16; +} + +/* ************************************************************************* */ +void CRC32_Init(uint8_t lilEndian) +{ + if(lilEndian) + MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN32; + else + MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN32; +} + +/* ************************************************************************* */ + +void CRC16_Reseed(uint16_t initData) +{ + //set initial value + MXC_CRC->seed16 = initData; + + //reseed the CRC16 generator + MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC16; + + //wait for reseed to clear itself + while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC16); + +} + +/* ************************************************************************* */ +void CRC32_Reseed(uint32_t initData) +{ + //set initial value + MXC_CRC->seed32 = initData; + + //reseed the CRC16 generator + MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC32; + + //wait for reseed to clear itself + while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC32); +} + +/**@} end of group crc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.h new file mode 100644 index 00000000000..112cfc4f851 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.h @@ -0,0 +1,191 @@ +/** + * @file + * @brief CRC peripheral module function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24657 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _CRC_H_ +#define _CRC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup crc Cyclic Redundancy Check (CRC) + * @brief High-level API for CRC Peripheral Module + * @{ + */ + +/** + * @page crc_overview Overview and Usage + * @parblock + * - Initialize the CRC for usage by calling either the CRC16_Init() function or the CRC32_Init() funciton + * + For CRC16, CCITT mode is enabled if the parameter is set + * + Select the Endian of the data for calculation + * - passing a 1 sets the module to little endian + * - passing a 0 sets the module to big endian + * - Set the intial CRC seed by calling CRC16_Reseed() or CRC32_Reseed() + * + This is the initial value of the CRC remainder to be used when the data is passed to the module + * - Pass data to the CRC engine using the methods: + * + CRC16_AddData() + * + CRC16_AddDataArray() + * + CRC32_AddData() + * + CRC32_AddDataArray() + * @note any data passed to the add methods of the peripheral is padded with zeros if it is less than + * 32-bits. + * @endparblock +*/ + + +/* **** Includes **** */ +#include "mxc_config.h" +#include +#include "crc_regs.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize CRC clock and select CRC16 mode and byte order. + * + * @param CCITT_TRUE CRC16-CCITT-TRUE = 1, CRC16-CCITT-FALSE = 0 + * @param lilEndian byte order, little endian = 1, big endian = 0 + */ +void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian); + +/** + * @brief Initialize CRC clock and select byte order for CRC32. + * + * @param lilEndian byte order, little endian = 1, big endian = 0 + */ +void CRC32_Init(uint8_t lilEndian); + +/** + * @brief Initialize CRC16 calculation. + * + * @param initData intial remainder to start the CRC16 calculation with + */ +void CRC16_Reseed(uint16_t initData); + +/** + * @brief Initialize CRC32 calculation. + * + * @param initData intial remainder to start the CRC32 calculation with + */ +void CRC32_Reseed(uint32_t initData); + +/** + * @brief Add data to the CRC16 calculation. + * + * @param data data to add to the CRC16 calculation + * @note data is padded with zeros if less than 32bits. + */ +__STATIC_INLINE void CRC16_AddData(uint32_t data) +{ + MXC_CRC_DATA->value16[0] = data; +} + +/** + * @brief Add data to the CRC32 calculation + * + * @param data data to add to the CRC32 calculation + * @note data is padded with zeros if less than 32bits + */ +__STATIC_INLINE void CRC32_AddData(uint32_t data) +{ + MXC_CRC_DATA->value32[0] = data; +} + +/** + * @brief Add an array of data to the CRC16 calculation + * + * @param data pointer to array of data + * @note data is padded with zeros if less than 32bits + * + * @param arrayLength number of elements in array + */ +__STATIC_INLINE void CRC16_AddDataArray(uint32_t *data, uint32_t arrayLength) +{ + memcpy((void *)(&(MXC_CRC_DATA->value16)), (void *)data, arrayLength * sizeof(data[0])); +} + +/** + * @brief Add an array of data to the CRC32 calculation + * + * @param data pointer to array of data + * @note data is padded with zeros if less than 32bits + * @param arrayLength number of elements in array + */ +__STATIC_INLINE void CRC32_AddDataArray(uint32_t *data, uint32_t arrayLength) +{ + memcpy((void *)(&(MXC_CRC_DATA->value32)), (void *)data, arrayLength * sizeof(data[0])); +} + +/** + * @brief Get the calculated CRC16 value + * + * @return CRC16 value + */ +__STATIC_INLINE uint32_t CRC16_GetCRC() +{ + return MXC_CRC_DATA->value16[0]; +} + +/** + * @brief Get the calculated CRC32 value + * + * @return CRC32 value + */ +__STATIC_INLINE uint32_t CRC32_GetCRC() +{ + return MXC_CRC_DATA->value32[0]; +} + +/**@} end of crc group */ + +#ifdef __cplusplus +} +#endif + +#endif /* _CRC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.c new file mode 100644 index 00000000000..91739bd2b54 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.c @@ -0,0 +1,260 @@ +/** + * @file + * @brief This file contains the function implementations for the Flash + * Controller (FLC) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 11:48:21 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24338 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "flc.h" + + +/** + * @ingroup flc + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************* */ +#if defined ( __GNUC__ ) +#undef IAR_PRAGMAS //Make sure this is not defined for GCC +#endif + +#if IAR_PRAGMAS +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +/** + * @brief Return the status of the busy state of the flash controller. + * + * @return 0 Flash Controller is idle. + * @return Non-zero indicates the flash controller is performing an + * erase or write request. + */ +__STATIC_INLINE int FLC_Busy(void) +{ + return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE)); +} + +/* ************************************************************************* */ +#if IAR_PRAGMAS +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Init(void) +{ + /* Check if the flash controller is busy */ + if (FLC_Busy()) { + return E_BUSY; + } + + /* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */ + MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV; + + /* The flash controller will stall any reads while flash operations are in + * progress. Disable the legacy failure detection logic that would flag reads + * during flash operations as errors. + */ + MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +#if IAR_PRAGMAS +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key) +{ + /* Check if the flash controller is busy */ + if (FLC_Busy()) { + return E_BUSY; + } + + /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + + /* Unlock flash */ + MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | + ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK); + + /* Write the Erase Code */ + MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | + ((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE); + + /* Erase the request page */ + MXC_FLC->faddr = address; + MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + /* Lock flash */ + MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE); + + /* Check for failures */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) { + /* Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + return E_UNKNOWN; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +#if IAR_PRAGMAS +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key) +{ + uint32_t *ptr = (uint32_t*)data; + + /* Can only write in full word units */ + if ((address & 3) || (length & 3)) { + return E_BAD_PARAM; + } + + if (length == 0) { + /* Nothing to do */ + return E_NO_ERROR; + } + + /* Check if the flash controller is busy */ + if (FLC_Busy()) { + return E_BUSY; + } + + /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + + /* Unlock flash */ + MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | + ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK); + + /* Set the address to write and enable auto increment */ + MXC_FLC->faddr = address; + MXC_FLC->ctrl |= MXC_F_FLC_CTRL_AUTO_INCRE_MODE; + uint32_t write_cmd = MXC_FLC->ctrl | MXC_F_FLC_CTRL_WRITE; + + for (; length > 0; length -= 4) { + /* Perform the write */ + MXC_FLC->fdata = *ptr++; + MXC_FLC->ctrl = write_cmd; + while (FLC_Busy()); + } + + /* Lock flash */ + MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK; + + /* Check for failures */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) { + /* Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + return E_UNKNOWN; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +#if IAR_PRAGMAS +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key) +{ + /* Check if the flash controller is busy */ + if (FLC_Busy()) { + return E_BUSY; + } + + /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + + /* Unlock flash */ + MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | + ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK); + + /* Write the Erase Code */ + MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | + ((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE); + + /* Start the mass erase */ + MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + /* Lock flash */ + MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE); + + /* Check for failures */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) { + /* Interrupt flags can only be written to zero, so this is safe */ + MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF; + return E_UNKNOWN; + } + + return E_NO_ERROR; +} + +/**@} end of group flc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.h new file mode 100644 index 00000000000..a69ec4e499a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.h @@ -0,0 +1,117 @@ +/** + * @file + * @brief Flash Controller (FLC) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24658 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _FLC_H_ +#define _FLC_H_ + +/* **** Includes **** */ +#include "flc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup sysconfig + * @defgroup flc Flash Controller (FLC) + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Prepares the Flash Controller for in-application flash operations. This function + * only needs to be called one time after a reset event. + * + * @return #E_NO_ERROR if flash controller initialized correctly, error if + * unsuccessful. + */ +int FLC_Init(void); + +/** + * @brief This function will erase a single page of flash. + * + * @param address Address of the page to be erased. + * @param erase_code Flash erase code; defined as + * #MXC_V_FLC_ERASE_CODE_PAGE_ERASE for page erase + * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY. + * + * @returns #E_NO_ERROR if page erase successful, error if unsuccessful. + */ +int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key); + +/** + * @brief This function writes data to the flash device through the flash + * controller interface + * + * @param address Start address for desired write. @note This address + * must be 32-bit word aligned + * @param data A pointer to the buffer containing the data to write. + * @param length Size of the data to write in bytes. @note The length + * must be in 32-bit multiples. + * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY. + * + * @returns #E_NO_ERROR if data written successfully, error if unsuccessful. + */ +int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key); + +/** + * @brief This function will mass erase the flash. + * + * @param erase_code Flash erase code, #MXC_V_FLC_ERASE_CODE_MASS_ERASE. + * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY. + * + * @returns #E_NO_ERROR if device mass erase successful, error if unsuccessful. + */ +int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key); + +/**@} end of group flc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c new file mode 100644 index 00000000000..6529e1c05cc --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c @@ -0,0 +1,186 @@ +/** + * @file + * @brief This file contains the function implementations for the + * General-Purpose Input/Output (GPIO) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 11:41:02 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24337 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "gpio.h" +#include "clkman_regs.h" + +/** + * @ingroup gpio + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* ************************************************************************* */ +static void (*callbacks[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT])(void *); +static void *cbparam[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT]; + +/* **** Functions **** */ + +/* ************************************************************************* */ +static int PinConfig(unsigned int port, unsigned int pin, gpio_func_t func, gpio_pad_t pad) +{ + /* Check if available */ + if (!(MXC_GPIO->free[port] & (1 << pin))) { + return E_BUSY; + } + + /* Set function */ + uint32_t func_sel = MXC_GPIO->func_sel[port]; + func_sel &= ~(0xF << (4 * pin)); + func_sel |= (func << (4 * pin)); + MXC_GPIO->func_sel[port] = func_sel; + + /* Normal input is always enabled */ + MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); + + /* Set requested output mode */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + out_mode &= ~(0xF << (4 * pin)); + out_mode |= (pad << (4 * pin)); + MXC_GPIO->out_mode[port] = out_mode; + + /* Enable the pull up/down if necessary */ + if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) { + MXC_GPIO->out_val[port] |= (1 << pin); + } else if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) { + MXC_GPIO->out_val[port] &= ~(1 << pin); + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int GPIO_Config(const gpio_cfg_t *cfg) +{ + unsigned int pin; + int err = E_NO_ERROR; + + MXC_ASSERT(cfg); + MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS); + + // Set system level configurations + if ((err = SYS_GPIO_Init()) != E_NO_ERROR) { + return err; + } + + // Configure each pin in the mask + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if (cfg->mask & (1 << pin)) { + if (PinConfig(cfg->port, pin, cfg->func, cfg->pad) != E_NO_ERROR) { + err = E_BUSY; + } + } + } + + return err; +} + +/* ************************************************************************* */ +static void IntConfig(unsigned int port, unsigned int pin, gpio_int_mode_t mode) +{ + uint32_t int_mode = MXC_GPIO->int_mode[port]; + int_mode &= ~(0xF << (pin*4)); + int_mode |= (mode << (pin*4)); + MXC_GPIO->int_mode[port] = int_mode; +} + +/* ************************************************************************* */ +void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode) +{ + unsigned int pin; + + MXC_ASSERT(cfg); + MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS); + + // Configure each pin in the mask + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if (cfg->mask & (1 << pin)) { + IntConfig(cfg->port, pin, mode); + } + } +} + +/* ************************************************************************* */ +void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata) +{ + unsigned int pin; + + MXC_ASSERT(cfg); + MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS); + + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if (cfg->mask & (1 << pin)) { + callbacks[cfg->port][pin] = func; + cbparam[cfg->port][pin] = cbdata; + } + } +} + +/* ************************************************************************* */ +void GPIO_Handler(unsigned int port) +{ + uint8_t intfl; + unsigned int pin; + + MXC_ASSERT(port < MXC_GPIO_NUM_PORTS); + + // Read and clear enabled interrupts. + intfl = MXC_GPIO->intfl[port]; + intfl &= MXC_GPIO->inten[port]; + MXC_GPIO->intfl[port] = intfl; + + // Process each pins' interrupt + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if ((intfl & (1 << pin)) && callbacks[port][pin]) { + callbacks[port][pin](cbparam[port][pin]); + } + } +} + +/**@} end of group gpio */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h new file mode 100644 index 00000000000..592559ea7ae --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h @@ -0,0 +1,315 @@ +/** + * @file + * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24659 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Doxy group definition for this peripheral module +/** + * @ingroup periphlibs + * @defgroup gpio General-Purpose Input/Output (GPIO) + * @{ + */ + +/* **** Definitions **** */ +/** + * @defgroup gpio_port_pin Port and Pin Definitions + * @ingroup gpio + * @{ + * @defgroup gpio_port Port Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define PORT_0 (0) /**< Port 0 Define*/ +#define PORT_1 (1) /**< Port 1 Define*/ +#define PORT_2 (2) /**< Port 2 Define*/ +#define PORT_3 (3) /**< Port 3 Define*/ +#define PORT_4 (4) /**< Port 4 Define*/ +#define PORT_5 (5) /**< Port 5 Define*/ +#define PORT_6 (6) /**< Port 6 Define*/ +#define PORT_7 (7) /**< Port 7 Define*/ +#define PORT_8 (8) /**< Port 8 Define*/ +#define PORT_9 (9) /**< Port 9 Define*/ +#define PORT_10 (10) /**< Port 10 Define*/ +#define PORT_11 (11) /**< Port 11 Define*/ +#define PORT_12 (12) /**< Port 12 Define*/ +#define PORT_13 (13) /**< Port 13 Define*/ +#define PORT_14 (14) /**< Port 14 Define*/ +#define PORT_15 (15) /**< Port 15 Define*/ +/**@} end of gpio_port group*/ +/** + * @defgroup gpio_pin Pin Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define PIN_0 (1 << 0) /**< Pin 0 Define */ +#define PIN_1 (1 << 1) /**< Pin 1 Define */ +#define PIN_2 (1 << 2) /**< Pin 2 Define */ +#define PIN_3 (1 << 3) /**< Pin 3 Define */ +#define PIN_4 (1 << 4) /**< Pin 4 Define */ +#define PIN_5 (1 << 5) /**< Pin 5 Define */ +#define PIN_6 (1 << 6) /**< Pin 6 Define */ +#define PIN_7 (1 << 7) /**< Pin 7 Define */ +/**@} end of gpio_pin group */ +/**@} end of gpio_port_pin group */ + +/** + * Enumeration type for the GPIO Function Type + */ +typedef enum { + GPIO_FUNC_GPIO = MXC_V_GPIO_FUNC_SEL_MODE_GPIO, /**< GPIO Function Selection */ + GPIO_FUNC_PT = MXC_V_GPIO_FUNC_SEL_MODE_PT, /**< Pulse Train Function Selection */ + GPIO_FUNC_TMR = MXC_V_GPIO_FUNC_SEL_MODE_TMR /**< Timer Function Selection */ +} +gpio_func_t; + +/** + * Enumeration type for the type of GPIO pad on a given pin. + */ +typedef enum { + GPIO_PAD_INPUT_PULLUP = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP, /**< Set pad to high impedance, weak pull-up */ + GPIO_PAD_OPEN_DRAIN = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN, /**< Set pad to open-drain with high impedance with input buffer */ + GPIO_PAD_OPEN_DRAIN_PULLUP = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP, /**< Set pad to open-drain with weak pull-up */ + GPIO_PAD_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, /**< Set pad to high impednace, input buffer enabled */ + GPIO_PAD_NORMAL = MXC_V_GPIO_OUT_MODE_NORMAL, /**< Set pad to normal drive mode for high an low output */ + GPIO_PAD_SLOW = MXC_V_GPIO_OUT_MODE_SLOW_DRIVE, /**< Set pad to slow drive mode, which is normal mode with negative feedback to slow edge transitions */ + GPIO_PAD_FAST = MXC_V_GPIO_OUT_MODE_FAST_DRIVE, /**< Set pad to fash drive mode, which is normal mode with a transistor drive to drive fast high and low */ + GPIO_PAD_INPUT_PULLDOWN = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN, /**< Set pad to weak pulldown mode */ + GPIO_PAD_OPEN_SOURCE = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE, /**< Set pad to open source mode, transistor drive to high */ + GPIO_PAD_OPEN_SOURCE_PULLDOWN = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN /**< Set pad to open source with weak pulldown mode, transistor drive to high, weak pulldown to GND for low */ +} gpio_pad_t; + +/** + * Structure type for configuring a GPIO port. + */ +typedef struct { + uint32_t port; /// Index of GPIO port + uint32_t mask; /// Pin mask. Multiple bits can be set. + gpio_func_t func; /// Function type + gpio_pad_t pad; /// Pad type +} gpio_cfg_t; + +/** + * Enumeration type for the interrupt type on a GPIO port. + */ +typedef enum { + GPIO_INT_DISABLE = MXC_V_GPIO_INT_MODE_DISABLE, /**< Disable interrupts */ + GPIO_INT_FALLING_EDGE = MXC_V_GPIO_INT_MODE_FALLING_EDGE, /**< Interrupt on Falling Edge */ + GPIO_INT_RISING_EDGE = MXC_V_GPIO_INT_MODE_RISING_EDGE, /**< Interrupt on Rising Edge */ + GPIO_INT_ANY_EDGE = MXC_V_GPIO_INT_MODE_ANY_EDGE, /**< Interrupt on Falling or Rising Edge */ + GPIO_INT_LOW_LEVEL = MXC_V_GPIO_INT_MODE_LOW_LVL, /**< Interrupt on a low level input detection */ + GPIO_INT_HIGH_LEVEL = MXC_V_GPIO_INT_MODE_HIGH_LVL /**< Interrupt on a high level input detection */ +} gpio_int_mode_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Configure GPIO pin(s). + * @param cfg Pointer to configuration structure describing the pin. + * + * @return #E_NO_ERROR if everything is successful. + * + */ +int GPIO_Config(const gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) input state. + * @param cfg Pointer to configuration structure describing the pin. + * + * @return The requested pin state. + * + */ +__STATIC_INLINE uint32_t GPIO_InGet(const gpio_cfg_t *cfg) +{ + return (MXC_GPIO->in_val[cfg->port] & cfg->mask); +} + +/** + * @brief Sets the pin(s) to a high level output. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +__STATIC_INLINE void GPIO_OutSet(const gpio_cfg_t *cfg) +{ + MXC_GPIO->out_val[cfg->port] |= cfg->mask; +} + +/** + * @brief Clears the pin(s) to a low level output. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +__STATIC_INLINE void GPIO_OutClr(const gpio_cfg_t *cfg) +{ + MXC_GPIO->out_val[cfg->port] &= ~(cfg->mask); +} + +/** + * @brief Gets the pin(s) output state. + * @param cfg Pointer to configuration structure describing the pin. + * + * @return The state of the requested pin. + * + */ +__STATIC_INLINE uint32_t GPIO_OutGet(const gpio_cfg_t *cfg) +{ + return (MXC_GPIO->out_val[cfg->port] & cfg->mask); +} + +/** + * @brief Write the pin(s) to a desired output level. + * @param cfg Pointer to configuration structure describing the pin. + * @param val Desired output level of the pin(s). This will be masked + * with the configuration mask. + * + */ +__STATIC_INLINE void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val) +{ + MXC_GPIO->out_val[cfg->port] = (MXC_GPIO->out_val[cfg->port] & ~cfg->mask) | (val & cfg->mask); +} + +/** + * @brief Toggles the the pin(s) output level. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +__STATIC_INLINE void GPIO_OutToggle(const gpio_cfg_t *cfg) +{ + MXC_GPIO->out_val[cfg->port] ^= cfg->mask; +} + +/** + * @brief Configure GPIO interrupt(s) + * @param cfg Pointer to configuration structure describing the pin. + * @param mode Requested interrupt mode. + * + */ +void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode); + +/** + * @brief Enables the specified GPIO interrupt + * @param cfg Pointer to configuration structure describing the pin. + * + */ +__STATIC_INLINE void GPIO_IntEnable(const gpio_cfg_t *cfg) +{ + MXC_GPIO->inten[cfg->port] |= cfg->mask; +} + +/** + * @brief Disables the specified GPIO interrupt. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +__STATIC_INLINE void GPIO_IntDisable(const gpio_cfg_t *cfg) +{ + MXC_GPIO->inten[cfg->port] &= ~cfg->mask; +} + +/** + * @brief Gets the interrupt(s) status on a GPIO pin. + * @param cfg Pointer to configuration structure describing the pin + * for which the status is being requested. + * + * @return The requested interrupt status. + * + */ +__STATIC_INLINE uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg) +{ + return (MXC_GPIO->intfl[cfg->port] & cfg->mask); +} + +/** + * @brief Clears the interrupt(s) status on a GPIO pin. + * @param cfg Pointer to configuration structure describing the pin + * to clear the interrupt state of. + * + */ +__STATIC_INLINE void GPIO_IntClr(const gpio_cfg_t *cfg) +{ + MXC_GPIO->intfl[cfg->port] = cfg->mask; +} + +/** + * @brief Type alias for a GPIO callback function with prototype: + * @code + * void callback_fn(void *cbdata); + * @endcode + * @param cbdata A void pointer to the data type as registered when + * @c GPIO_RegisterCallback() was called. + * + */ +typedef void (*gpio_callback_fn)(void *cbdata); + +/** + * @brief Registers a callback for the interrupt on a given port and pin. + * @param cfg Pointer to configuration structure describing the pin + * @param callback A pointer to a function of type #gpio_callback_fn. + * @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs. + * + */ +void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata); + +/** + * @brief GPIO IRQ Handler. @note If a callback is registered for a given + * interrupt, the callback function will be called. + * + * @param port number of the port that generated the interrupt service routine. + * + */ +void GPIO_Handler(unsigned int port); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c new file mode 100644 index 00000000000..2f56a222eee --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c @@ -0,0 +1,924 @@ +/** + * @file + * @brief This file contains the function implementations for the I2CM + * (Inter-Integrated Circuit Master) peripheral module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 11:40:02 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24336 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "i2cm.h" + + +/** + * @ingroup i2cm + * @{ + */ + +///@cond +// No Doxygen documentation for the items between here and endcond. +/* **** Definitions **** */ +#ifndef MXC_I2CM_TX_TIMEOUT +#define MXC_I2CM_TX_TIMEOUT 0x5000 /**< Master Transmit Timeout in number of repetitive attempts to receive an ACK/NACK or for a transmission to occur */ +#endif + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 /**< Master Receive Timeout in number of attempts to check FIFO for received data from a slave */ +#endif + +#define I2CM_READ_BIT 0x0001 /**< Bit location to specify a read for the I2C protocol */ +///@cond +#define I2CM_FIFO_DEPTH_3Q ((3 * MXC_I2CM_FIFO_DEPTH) / 4) +#define I2CM_FIFO_DEPTH_2Q (MXC_I2CM_FIFO_DEPTH / 2) + +// +/* **** Globals **** */ + +/* Clock divider lookup table */ +static const uint32_t clk_div_table[3][8] = { + /* I2CM_SPEED_100KHZ */ + { + // 12000000 + ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 24000000 + ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 36000000 NOT SUPPORTED + 0, + // 48000000 + ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 60000000 NOT SUPPORTED + 0, + // 72000000 NOT SUPPORTED + 0, + // 84000000 NOT SUPPORTED + 0, + // 96000000 + ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + }, + /* I2CM_SPEED_400KHZ */ + { + // 12000000 + ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 24000000 + ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 36000000 NOT SUPPORTED + 0, + // 48000000 + ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + // 60000000 NOT SUPPORTED + 0, + // 72000000 NOT SUPPORTED + 0, + // 84000000 NOT SUPPORTED + 0, + // 96000000 + ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | + (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | + (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), + }, +}; + +// Saves the state of the non-blocking requests +typedef enum { + I2CM_STATE_READING = 0, + I2CM_STATE_WRITING = 1 +} i2cm_state_t; + +typedef struct { + i2cm_req_t *req; + i2cm_state_t state; +} i2cm_req_state_t; +static i2cm_req_state_t states[MXC_CFG_I2CM_INSTANCES]; + +/* **** Local Function Prototypes **** */ + +static void I2CM_FreeCallback(int i2cm_num, int error); + +static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, + uint8_t *data, uint32_t len); + +static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req); +static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num); +static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num); +///@endcond +// +/* ************************************************************************* */ +int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed) +{ + int err, clki; + + // Check the base pointer + MXC_ASSERT(MXC_I2CM_GET_IDX(i2cm) >= 0); + + // Set system level configurations + if ((err = SYS_I2CM_Init(i2cm, sys_cfg)) != E_NO_ERROR) { + return err; + } + + // Compute clock array index + clki = ((SYS_I2CM_GetFreq(i2cm) / 12000000) - 1); + + // Get clock divider settings from lookup table + if ((speed == I2CM_SPEED_100KHZ) && (clk_div_table[I2CM_SPEED_100KHZ][clki] > 0)) { + i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_100KHZ][clki]; + + } else if ((speed == I2CM_SPEED_400KHZ) && (clk_div_table[I2CM_SPEED_400KHZ][clki] > 0)) { + i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_400KHZ][clki]; + + } else { + // Requested speed is not achievable with the current clock setup + return E_NOT_SUPPORTED; + } + + // Reset module + i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + i2cm->ctrl = 0; + + // Set timeout to 255 ms and turn on the auto-stop option + i2cm->timeout = (MXC_F_I2CM_TIMEOUT_TX_TIMEOUT | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN); + + // Enable tx_fifo and rx_fifo + i2cm->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm) +{ + int i2cm_num, err; + + // Check the base pointer + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + MXC_ASSERT(i2cm_num >= 0); + + // Disable and clear interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + + // Call all of the pending callbacks for this I2CM + if(states[i2cm_num].req != NULL) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, E_SHUTDOWN); + } + + // Clears system level configurations + if ((err = SYS_I2CM_Shutdown(i2cm)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + + +/* ************************************************************************* */ +int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data, + uint32_t cmd_len, uint8_t* data, uint32_t len) +{ + int i2cm_num; + int error = E_NO_ERROR; + int retval = E_NO_ERROR; + mxc_i2cm_fifo_regs_t *fifo; + + if(data == NULL) { + return E_NULL_PTR; + } + + // Make sure the I2CM has been initialized + if(i2cm->ctrl == 0) { + return E_UNINITIALIZED; + } + + if(!(len > 0)) { + return E_NO_ERROR; + } + + // Lock this I2CM + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {} + + // Get the FIFO pointer for this I2CM + fifo = MXC_I2CM_GET_FIFO(i2cm_num); + + // Disable and clear the interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + + // Transmit the command if there is command data and length + if((cmd_data != NULL) && (cmd_len > 0)) { + retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0); + } + + // Read data from the slave if we don't have any errors + if(retval == E_NO_ERROR) { + retval = I2CM_Rx(i2cm, fifo, addr, data, len); + } + + // Wait for the transaction to complete + if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) { + retval = error; + } + + // Unlock this I2CM + mxc_free_lock((uint32_t*)&states[i2cm_num].req); + + if(retval != E_NO_ERROR) { + return retval; + } + + return len; +} + +/* ************************************************************************* */ +int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data, + uint32_t cmd_len, uint8_t* data, uint32_t len) +{ + int i2cm_num; + int error = E_NO_ERROR; + int retval = E_NO_ERROR; + mxc_i2cm_fifo_regs_t *fifo; + + if(data == NULL) { + return E_NULL_PTR; + } + + // Make sure the I2CM has been initialized + if(i2cm->ctrl == 0) { + return E_UNINITIALIZED; + } + + if(!(len > 0)) { + return E_NO_ERROR; + } + + // Lock this I2CM + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {} + + // Get the FIFO pointer for this I2CM + fifo = MXC_I2CM_GET_FIFO(i2cm_num); + + // Disable and clear the interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + + // Transmit the command if there is command data and length, don't send stop bit + if((cmd_data != NULL) && (cmd_len > 0)) { + retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0); + } + + // Write data to the slave, send the stop bit + if(retval == E_NO_ERROR) { + retval = I2CM_Tx(i2cm, fifo, addr, data, len, 1); + } + + // Wait for the transaction to complete + if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) { + retval = error; + } + + // Unlock this I2CM + mxc_free_lock((uint32_t*)&states[i2cm_num].req); + + if(retval != E_NO_ERROR) { + return retval; + } + + return len; +} + +/* ************************************************************************* */ +int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req) +{ + int i2cm_num, error; + + if(req->data == NULL) { + return E_NULL_PTR; + } + + // Make sure the I2CM has been initialized + if(i2cm->ctrl == 0) { + return E_UNINITIALIZED; + } + + if(!(req->data_len > 0)) { + return E_NO_ERROR; + } + + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + + // Attempt to register this request + if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + states[i2cm_num].state = I2CM_STATE_READING; + + // Clear the number of bytes counter + req->cmd_num = 0; + req->data_num = 0; + + // Disable and clear the interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + + // Start the read + if((error = I2CM_ReadHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, error); + return error; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req) +{ + int i2cm_num, error; + + if(req->data == NULL) { + return E_NULL_PTR; + } + + // Make sure the I2CM has been initialized + if(i2cm->ctrl == 0) { + return E_UNINITIALIZED; + } + + if(!(req->data_len > 0)) { + return E_NO_ERROR; + } + + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + + // Attempt to register this request + if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + states[i2cm_num].state = I2CM_STATE_WRITING; + + // Clear the number of bytes counter + req->cmd_num = 0; + req->data_num = 0; + + // Disable and clear the interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + + // Start the Write + if((error = I2CM_WriteHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, error); + return error; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_AbortAsync(i2cm_req_t *req) +{ + int i2cm_num; + mxc_i2cm_regs_t *i2cm; + + // Find the request, set to NULL + for(i2cm_num = 0; i2cm_num < MXC_CFG_I2CM_INSTANCES; i2cm_num++) + { + if(req == states[i2cm_num].req) { + + i2cm = MXC_I2CM_GET_I2CM(i2cm_num); + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, E_ABORT); + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +/* ************************************************************************* */ +void I2CM_Handler(mxc_i2cm_regs_t *i2cm) +{ + uint32_t intfl; + int i2cm_num, error; + + // Save and clear the interrupts + intfl = i2cm->intfl; + i2cm->intfl = intfl; + + // Mask the disabled interrupts + intfl &= i2cm->inten; + + i2cm_num = MXC_I2CM_GET_IDX(i2cm); + + // Check for errors + if ((intfl & MXC_F_I2CM_INTFL_TX_NACKED) || (intfl & MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, E_COMM_ERR); + return; + } + + if(intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, E_TIME_OUT); + return; + } + + // Read or write + if(states[i2cm_num].state == I2CM_STATE_READING) { + if((error = I2CM_ReadHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, error); + return; + } + + } else if(states[i2cm_num].state == I2CM_STATE_WRITING) { + if((error = I2CM_WriteHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, error); + return; + } + } + + // Done with the transaction + if(intfl & MXC_F_I2CM_INTFL_TX_DONE) { + I2CM_Recover(i2cm); + I2CM_FreeCallback(i2cm_num, E_NO_ERROR); + } + +} + +/* ************************************************************************* */ +int I2CM_Busy(mxc_i2cm_regs_t *i2cm) +{ + // Check to see if there are any ongoing transactions + if((states[MXC_I2CM_GET_IDX(i2cm)].req == NULL) && + !(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************* */ +int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm) +{ + if(I2CM_Busy(i2cm) != E_NO_ERROR) { + return E_BUSY; + } + + // Disable interrupts + i2cm->inten = 0; + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm) +{ + // If SCL is low, we don't have the bus + if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SCL_IN_VAL)) { + return E_BUSY; + } + + // If SDA is low, we don't have the bus + if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SDA_IN_VAL)) { + return E_BUSY; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static void I2CM_FreeCallback(int i2cm_num, int error) +{ + // Save the request + i2cm_req_t *temp_req = states[i2cm_num].req; + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&states[i2cm_num].req); + + // Callback if not NULL + if(temp_req->callback != NULL) { + temp_req->callback(temp_req, error); + } +} + +/* ************************************************************************* */ +void I2CM_Recover(mxc_i2cm_regs_t *i2cm) +{ + // Disable and clear interrupts + i2cm->inten = 0; + i2cm->intfl = i2cm->intfl; + i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + i2cm->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN; +} + +/* ************************************************************************* */ +int I2CM_WriteTxFifo(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data) +{ + int32_t timeout = MXC_I2CM_TX_TIMEOUT; + + // Read the TX FIFO to determine if it's full + do { + + // Wait for the TX FIFO to have room and check for errors + if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED | + MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) { + + return E_COMM_ERR; + } + + if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) || !timeout--) { + return E_TIME_OUT; + } + + } while (fifo->tx); + + fifo->tx = data; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm) +{ + int32_t timeout = MXC_I2CM_TX_TIMEOUT; + + while ((i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout); + + if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED | + MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) { + + I2CM_Recover(i2cm); + return E_COMM_ERR; + } + + if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) && !timeout--) { + I2CM_Recover(i2cm); + return E_TIME_OUT; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, + const uint8_t *data, uint32_t len, uint8_t stop) +{ + uint32_t i; + int error; + + // Write the address to the TXFIFO + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (addr << 1)))) != E_NO_ERROR) { + return error; + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + + // Fill the FIFO + for (i = 0; i < len; i++) { + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != E_NO_ERROR) { + return error; + } + } + + // Send the stop condition + if(stop) { + if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) { + return error; + } + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, + uint8_t *data, uint32_t len) +{ + uint32_t i = len; + int32_t timeout; + uint16_t temp; + int error; + + // Write the address to the TXFIFO + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | + (addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) { + + return error; + } + + // Write to the TXFIFO the number of bytes we want to read + while(i > 256) { + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) { + return error; + } + + i -= 256; + } + + if(i > 1) { + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i-2)))) != E_NO_ERROR) { + return error; + } + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + + + // NACK the last read byte + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) { + return error; + } + + // Send the stop condition + if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) { + return error; + } + + // Get the data from the RX FIFO + i = 0; + while (i < len) { + + // Wait for there to be data in the RX FIFO + timeout = MXC_I2CM_RX_TIMEOUT; + while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + ((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) { + + if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) { + return E_TIME_OUT; + } + + if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) { + return E_COMM_ERR; + } + } + i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + + // Save the data from the RX FIFO + temp = fifo->rx; + if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) { + continue; + } + data[i++] = (uint8_t)temp; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req) +{ + int error; + + // Start of the command + if(req->cmd_num == 0) { + + // Write the address to the TXFIFO + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (req->addr << 1)))) != E_NO_ERROR) { + return error; + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + } + + // Write to the FIFO until it is full or we run out of command bytes + while((req->cmd_num < req->cmd_len) && (!fifo->tx)) { + fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->cmd_data[req->cmd_num++]; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num) +{ + int error, cmd_remain, data_remain; + uint16_t data; + uint32_t temp_len, inten; + mxc_i2cm_fifo_regs_t *fifo; + + // Get the FIFO pointer for this I2CM + fifo = MXC_I2CM_GET_FIFO(i2cm_num); + + cmd_remain = req->cmd_len - req->cmd_num; + data_remain = req->data_len - req->data_num; + + // Process the command portion + if((cmd_remain) && (req->cmd_data != NULL)) { + if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) { + return error; + } + + cmd_remain = req->cmd_len - req->cmd_num; + } + + // Process the data portion + if((cmd_remain == 0) && (data_remain)) { + + // Save the data from the RXFIFO + data = fifo->rx; + while((req->data_num < req->data_len) && !(data & MXC_S_I2CM_RSTLS_TAG_EMPTY)) { + req->data[req->data_num++] = data; + data = fifo->rx; + } + + // Start of the data portion + if(req->data_num == 0) { + + temp_len = req->data_len; + + // Write the address to the TXFIFO + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | + (req->addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) { + + return error; + } + + // Write to the TXFIFO the number of bytes we want to read + while(temp_len > 256) { + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) { + return error; + } + + temp_len -= 256; + } + + if(temp_len > 1) { + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (temp_len-2)))) != E_NO_ERROR) { + return error; + } + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + + // NACK the last read byte + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) { + return error; + } + + // Send the stop condition + if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) { + return error; + } + } + } + + // Enable the required interrupts + inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED | + MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT; + + if (cmd_remain) { + inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY); + } + + data_remain = req->data_len - req->data_num; + if (data_remain > I2CM_FIFO_DEPTH_3Q) { + inten |= MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL; + + } else if (data_remain > I2CM_FIFO_DEPTH_2Q) { + inten |= MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL; + + } else if (data_remain > 0) { + inten |= MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY; + } + + i2cm->inten = inten; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num) +{ + int error, cmd_remain, data_remain; + uint32_t inten; + mxc_i2cm_fifo_regs_t *fifo; + + // Get the FIFO pointer for this I2CM + fifo = MXC_I2CM_GET_FIFO(i2cm_num); + + cmd_remain = req->cmd_len - req->cmd_num; + data_remain = req->data_len - req->data_num; + + // Process the command portion + if((cmd_remain) && (req->cmd_data != NULL)) { + if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) { + return error; + } + + cmd_remain = req->cmd_len - req->cmd_num; + } + + // Process the data portion + if((cmd_remain == 0) && (data_remain)) { + + // Start of the data portion + if(req->data_num == 0) { + + // Write the address to the TXFIFO + if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | + (req->addr << 1)))) != E_NO_ERROR) { + + return error; + } + + // Start the transaction if it is not currently ongoing + if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + i2cm->trans |= MXC_F_I2CM_TRANS_TX_START; + } + } + + // Write bytes to the FIFO until it's full or we run out of bytes + while(req->data_num < req->data_len) { + fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->data[req->data_num++]; + } + + // Send the stop condition + if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) { + return error; + } + } + + // Enable the required interrupts + data_remain = req->data_len - req->data_num; + inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED | + MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT; + + if(data_remain || cmd_remain) { + inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY); + } + i2cm->inten = inten; + + return E_NO_ERROR; +} +/**@} end of group i2cm */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h new file mode 100644 index 00000000000..7535e3b05a8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h @@ -0,0 +1,340 @@ +/** + * @file + * @brief I2CM (Inter-Integrated Circuit Master) function prototypes and + * data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24660 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _I2CM_H_ +#define _I2CM_H_ + +/***** Includes *****/ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "i2cm_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @ingroup commperipherals + * @defgroup i2c_master_slave I2C + * @brief I2C Master and Slave Communications + */ +/** + * @ingroup i2c_master_slave + * @defgroup i2cm I2C Master + * @brief I2C Master + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type to select supported I2CM frequencies. + */ +typedef enum { + I2CM_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */ + I2CM_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */ +} i2cm_speed_t; + +/** + * Structure type for an I2CM Transaction request. + */ +typedef struct i2cm_req i2cm_req_t; + +/** + * Function type for the I2C Master callback. The function declaration for the + * I2CM callback is: + * @code + * void callback(i2cm_req_t * req, int error_code); + * @endcode | | | | -----: | + * :----------------------------------------- | | @p req | Pointer to an + * #i2cm_req object representing the I2CM active transaction. | | @p error_code + * | An error code if the active transaction had a failure or #E_NO_ERROR if + * successful. | + * + * @addtogroup i2cm_async + * @{ + */ +typedef void (*i2cm_callback_fn)(i2cm_req_t * req, int error_code); +/**@}*/ + + +/** + * I2CM Transaction request structure. + * @note Only supports 7-bit addressing. Driver will shift the address and + * add the read bit when necessary. + */ +struct i2cm_req { + uint8_t addr; /**< 7-Bit unshifted address of the slave for communication. */ + const uint8_t *cmd_data; /**< Pointer to a command data buffer to send to the slave before either a read or write transaction. */ + uint32_t cmd_len; /**< Number of bytes in command. */ + uint8_t *data; /**< Data to write or read. */ + uint32_t data_len; /**< Length of data. */ + uint32_t cmd_num; /**< Number of command bytes sent. */ + uint32_t data_num; /**< Number of data bytes sent. */ + i2cm_callback_fn callback; /**< Function pointer to a callback function. */ +}; + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the I2CM peripheral module. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * @param sys_cfg Pointer to an I2CM configuration structure of type + * #sys_cfg_i2cm_t. + * @param speed I2CM bus speed, see #i2cm_speed_t. + * + * @return #E_NO_ERROR if initialized successfully, error if unsuccessful. + */ +int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed); + +/** + * @brief Shutdown I2CM module. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * + * @returns #E_NO_ERROR if everything is successful, error if unsuccessful. + * + */ +int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm); + +/** + * @defgroup i2cm_blocking I2CM Blocking Functions + * @{ + */ + +/** + * @brief Read I2CM data. Will block until transaction is complete. + * + * @note Command is an optional feature where the master will write the @c + * cmd_data before reading from the slave. If command is undesired, + * set the @c *cmd_data parameter to NULL and pass 0 for the @c + * cmd_len parameter. + * @note If there is a command, the master will send a repeated start + * sequence before attempting to read from the slave. + * @note This function blocks until the transaction has completed. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * @param addr I2C address of the slave. + * @param cmd_data Data to write before reading. + * @param cmd_len Number of bytes to write before reading. + * @param data Where to store the data read. + * @param len Number of bytes to read. + * + * @return Number of bytes read if successful, error code if unsuccessful. + */ +int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data, + uint32_t cmd_len, uint8_t* data, uint32_t len); + +/** + * @brief Write data to a slave device. + * + * @note Command is an optional feature where the master will write the @c + * cmd_data before writing the @c data to the slave. If command is + * not needed, set the @c cmd_data to @c NULL and set @c cmd_len to + * 0. If there is a command, the master will send a repeated start + * sequence before attempting to read from the slave. + * @note This function blocks until the transaction has completed. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * @param addr I2C address of the slave. + * @param cmd_data Data to write before writing data. + * @param cmd_len Number of bytes to write before writing data. + * @param data Data to be written. + * @param len Number of bytes to Write. + * + * @return Number of bytes writen if successful or an @ref MXC_Error_Codes + * "Error Code" if unsuccessful. + */ +int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data, + uint32_t cmd_len, uint8_t* data, uint32_t len); +/**@} end of i2cm_blocking functions */ + +/** + * @defgroup i2cm_async I2CM Asynchrous Functions + * @{ + */ + +/** + * @brief Asynchronously read I2CM data. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * @param req Pointer to an I2CM transaction request structure, see + * #i2cm_req. + * + * @return #E_NO_ERROR if everything is successful or an @ref + * MXC_Error_Codes "Error Code" if unsuccessful. + */ +int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req); + +/** + * @brief Asynchronously write I2CM data. + * + * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t. + * @param req Pointer to an I2CM transaction request structure, see + * #i2cm_req. + * + * @return #E_NO_ERROR if everything is successful, error if unsuccessful. + */ +int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req); + +/** + * @brief Abort asynchronous request. + * @param req Pointer to request for an I2CM transaction. + * @note Will call the callback for the request. + * + * @return #E_NO_ERROR if request aborted, error if unsuccessful. + */ +int I2CM_AbortAsync(i2cm_req_t *req); + +/** + * @brief I2CM interrupt handler. + * + * @details This function is an IRQ handler and will be called by the core if + * I2CM interrupts are enabled. Alternately, if the application is + * using asynchronous methods, this function can be periodically + * called by the application if the I2CM interrupts are disabled. + * + * @param i2cm Base address of the I2CM module. + */ +void I2CM_Handler(mxc_i2cm_regs_t *i2cm); +/**@} end of i2cm_async */ + +/** + * @brief Returns the status of the I2CM peripheral module. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + * + * @return #E_NO_ERROR if idle. + * @return #E_BUSY if in use. + */ +int I2CM_Busy(mxc_i2cm_regs_t *i2cm); + +/** + * @brief Attempt to prepare the I2CM for sleep. + * @details Checks for any ongoing transactions. Disables interrupts if the + * I2CM is idle. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + * + * @return #E_NO_ERROR if ready to sleep. + * @return #E_BUSY if the bus is not ready for sleep. + */ +int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm); + +/** + * @brief Check the I2C bus to determine if any other masters are using the + * bus. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + * + * @return #E_NO_ERROR if SCL and SDA are high, + * @return #E_BUSY otherwise. + */ +int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm); + +/** + * @brief Drain/Empty all of the data in the I2CM Receive FIFO. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + */ +__STATIC_INLINE void I2CM_DrainRX(mxc_i2cm_regs_t *i2cm) +{ + i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_RX_FIFO_EN); + i2cm->ctrl |= MXC_F_I2CM_CTRL_RX_FIFO_EN; +} + +/** + * @brief Drain/Empty any data in the I2CM Transmit FIFO. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + */ +__STATIC_INLINE void I2CM_DrainTX(mxc_i2cm_regs_t *i2cm) +{ + i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_TX_FIFO_EN); + i2cm->ctrl |= MXC_F_I2CM_CTRL_TX_FIFO_EN; +} + +/** + * @brief Clear interrupt flags. + * + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + * @param mask Mask of I2CM interrupts to clear (1 to clear), + * @see I2CM_INTFL_Register for the interrupt flag masks. + */ +__STATIC_INLINE void I2CM_ClearFlags(mxc_i2cm_regs_t *i2cm, uint32_t mask) +{ + i2cm->intfl = mask; +} + +/** + * @brief Gets the current I2CM interrupt flags. + * @param i2cm Pointer to the I2CM register structure, see + * #mxc_i2cm_regs_t. + * + * @return The currently set interrupt flags, @see I2CM_INTFL_Register + * for the interrupt flag masks. + */ +__STATIC_INLINE unsigned I2CM_GetFlags(mxc_i2cm_regs_t *i2cm) +{ + return(i2cm->intfl); +} +/**@} end of group i2cm */ + +void I2CM_Recover(mxc_i2cm_regs_t *i2cm); +int I2CM_WriteTxFifo(mxc_i2cm_regs_t *regs, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data); +int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm); +int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, const uint8_t *data, uint32_t len, uint8_t stop); + +#ifdef __cplusplus +} +#endif + +#endif /* _I2CM_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c new file mode 100644 index 00000000000..64127ff11e1 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c @@ -0,0 +1,209 @@ +/** + * @file + * @brief This file contains the function implementations for the I2CS + * (Inter-Integrated Circuit Slave) peripheral module. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 18:05:59 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24332 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "i2cs.h" + +/** + * @ingroup i2cs + * @{ + */ +/* **** Definitions **** */ + +/* **** Globals ***** */ + + +// No Doxygen documentation for the items between here and endcond. +/* Clock divider lookup table */ +static const uint32_t clk_div_table[2][8] = { + /* I2CS_SPEED_100KHZ */ + { + // 12000000 + (6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 24000000 + (12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 36000000 NOT SUPPORTED + 0, + // 48000000 + (24 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 60000000 NOT SUPPORTED + 0, + // 72000000 NOT SUPPORTED + 0, + // 84000000 NOT SUPPORTED + 0, + // 96000000 + (48 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS) + }, + /* I2CS_SPEED_400KHZ */ + { + // 12000000 + (2 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 24000000 + (3 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 36000000 NOT SUPPORTED + 0, + // 48000000 + (6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS), + // 60000000 NOT SUPPORTED + 0, + // 72000000 NOT SUPPORTED + 0, + // 84000000 NOT SUPPORTED + 0, + // 96000000 + (12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS) + }, +}; + + +static void (*callbacks[MXC_CFG_I2CS_INSTANCES][MXC_CFG_I2CS_BUFFER_SIZE])(uint8_t); + +/* **** Functions **** */ + +/* ************************************************************************* */ +int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed, + uint16_t address, i2cs_addr_t addr_len) +{ + int err, i, i2cs_index; + + i2cs_index = MXC_I2CS_GET_IDX(i2cs); + MXC_ASSERT(i2cs_index >= 0); + + // Set system level configurations + if ((err = SYS_I2CS_Init(i2cs, sys_cfg)) != E_NO_ERROR) { + return err; + } + + // Compute clock array index + int clki = ((SYS_I2CS_GetFreq(i2cs) / 12000000) - 1); + + // Get clock divider settings from lookup table + if ((speed == I2CS_SPEED_100KHZ) && (clk_div_table[I2CS_SPEED_100KHZ][clki] > 0)) { + i2cs->clk_div = clk_div_table[I2CS_SPEED_100KHZ][clki]; + } else if ((speed == I2CS_SPEED_400KHZ) && (clk_div_table[I2CS_SPEED_400KHZ][clki] > 0)) { + i2cs->clk_div = clk_div_table[I2CS_SPEED_400KHZ][clki]; + } else { + MXC_ASSERT_FAIL(); + } + + // Clear the interrupt callbacks + for(i = 0; i < MXC_CFG_I2CS_BUFFER_SIZE; i++) { + callbacks[i2cs_index][i] = NULL; + } + + // Reset module + i2cs->dev_id = MXC_F_I2CS_DEV_ID_SLAVE_RESET; + i2cs->dev_id = ((((address >> 0) << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS) + & MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID) | addr_len); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs) +{ + int err; + + // Disable and clear interrupts + i2cs->inten = 0; + i2cs->intfl = i2cs->intfl; + + // clears system level configurations + if ((err = SYS_I2CS_Shutdown(i2cs)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void I2CS_Handler(mxc_i2cs_regs_t *i2cs) +{ + uint32_t intfl; + uint8_t i; + int i2cs_index = MXC_I2CS_GET_IDX(i2cs); + + // Save and clear the interrupt flags + intfl = i2cs->intfl; + i2cs->intfl = intfl; + + // Process each interrupt + for(i = 0; i < 32; i++) { + if(intfl & (0x1 << i)) { + if(callbacks[i2cs_index][i] != NULL) { + callbacks[i2cs_index][i](i); + } + } + } + +} + +/* ************************************************************************* */ +void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback) +{ + int i2cs_index = MXC_I2CS_GET_IDX(i2cs); + + // Make sure we don't overflow + MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE); + + if(callback != NULL) { + // Save the callback address + callbacks[i2cs_index][addr] = callback; + + // Clear and Enable the interrupt for the given byte + i2cs->intfl = (0x1 << addr); + i2cs->inten |= (0x1 << addr); + } else { + // Disable and clear the interrupt + i2cs->inten &= ~(0x1 << addr); + i2cs->intfl = (0x1 << addr); + + // Clear the callback address + callbacks[i2cs_index][addr] = NULL; + } +} + +/**@} end of group i2cs*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h new file mode 100644 index 00000000000..438c6afc0e5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h @@ -0,0 +1,215 @@ +/** + * @file + * @brief I2CS (Inter-Integrated Circuit Slave) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24661 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _I2CS_H_ +#define _I2CS_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "mxc_assert.h" +#include "i2cs_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup i2c_master_slave + * @defgroup i2cs I2C Slave + * @brief I2C Slave (I2CS) API + * @{ + */ + +/* **** Definitions **** */ +/** + * Internal buffer size for storing I2C Slave Messages + */ +#define I2CS_BUFFER_SIZE 32 + +/** + * Enumeration type to select supported I2CS frequencies. + */ +typedef enum { + I2CS_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */ + I2CS_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */ +} i2cs_speed_t; + +/** + * Enumeration type to select the I2CS addressing mode. + */ +typedef enum { + I2CS_ADDR_8 = 0, /**< Sets the slave address mode to 8-bits (7-bits address plus read/write bit). */ + I2CS_ADDR_10 = MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE /**< Sets the slave address mode to 10-bits. */ +} i2cs_addr_t; + +/** + * Type alias for an I2CS callback function that will be called when a given byte is updated by the Master, see I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback). + * @details The function prototype for implementing callback_fn is: + * @code + * void func(uint8_t addr); + * @endcode + */ +typedef void (*i2cs_callback_fn)(uint8_t error_code); +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize I2CS module. + * @param i2cs Pointer to I2CS regs. + * @param sys_cfg Pointer to I2CS system configuration, see + * #sys_cfg_i2cs_t. + * @param speed I2CS frequency. + * @param address I2CS address. + * @param addr_len I2CS address length. + * @return #E_NO_ERROR if everything is successful or an + * @ref MXC_Error_Codes "error code" if unsuccessful. + * + */ +int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed, uint16_t address, i2cs_addr_t addr_len); + +/** + * @brief Shutdown I2CS module. + * @param i2cs Pointer to I2CS regs. + * @return #E_NO_ERROR if everything is successful or an + * @ref MXC_Error_Codes "error code" if unsuccessful. + */ +int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs); + +/** + * @brief I2CS interrupt handler. + * @details This function should be called by the application from the + * interrupt handler if I2CS interrupts are enabled. Alternately, + * this function can be periodically called by the application if + * I2CS interrupts are disabled. + * + * @param i2cs Pointer to I2CS regs. + */ +void I2CS_Handler(mxc_i2cs_regs_t *i2cs); + +/** + * @brief Register a callback that is triggered by an update of a specified + * byte. + * @details Registering a callback causes the slave to interrupt when the + * master has updated a specified byte. + * + * @param i2cs Pointer to the I2CS register structure, see + * #mxc_i2cs_regs_t. + * @param addr Index to trigger a call to the #i2cs_callback_fn. + * @param callback callback function of type #i2cs_callback_fn to be called + * when the addr being written by the master matches \c addr. + */ +void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback); + +/** + * @brief Write I2CS data to a given byte. + * @details The slave has a buffer of registers that the external master can + * read. Use this function to write data into a specified + * address/index. + * + * @param i2cs Pointer to I2CS regs. + * @param addr Address/Index to write. + * @param data Data to be written. + */ +__STATIC_INLINE void I2CS_Write(mxc_i2cs_regs_t *i2cs, uint8_t addr, uint8_t data) +{ + // Make sure we don't overflow + MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE); + i2cs->data_byte[addr] = ((i2cs->data_byte[addr] & ~MXC_F_I2CS_DATA_BYTE_DATA_FIELD) | + (data << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)); +} + +/** + * @brief Read I2CS data from a given address . + * @details The slave has a buffer of registers that the external master can + * read. Use this function to read the data from the registers. + * + * @param i2cs Pointer to I2CS regs. + * @param addr Address/Index to read from. + * + * @return Data contained in requested @c addr register. + */ +__STATIC_INLINE uint8_t I2CS_Read(mxc_i2cs_regs_t *i2cs, uint8_t addr) +{ + // Make sure we don't overflow + MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE); + return ((i2cs->data_byte[addr] & MXC_F_I2CS_DATA_BYTE_DATA_FIELD) >> + MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS); +} + +/** + * @brief Set the given index to read only (RO). + * @details This index will be flagged as read only. The slave will NACK the + * master if it attempts to write this location. Multiple calls with + * different index/address values will yield multiple read-only + * locations within the slave register set. + * + * @param i2cs Pointer to I2CS regs. + * @param addr Address/Index of the byte to set to RO. + */ +__STATIC_INLINE void I2CS_SetRO(mxc_i2cs_regs_t *i2cs, uint8_t addr) +{ + // Make sure we don't overflow + MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE); + i2cs->data_byte[addr] |= MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL; +} + +/** + * @brief Sets the given address to R/W. + * @param i2cs Pointer to I2CS regs. + * @param addr Index to start clearing RO flag. + */ +__STATIC_INLINE void I2CS_ClearRO(mxc_i2cs_regs_t *i2cs, uint8_t addr) +{ + // Make sure we don't overflow + MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE); + i2cs->data_byte[addr] &= ~MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL; +} + +/**@} end of group i2cs */ + +#ifdef __cplusplus +} +#endif + +#endif /* _I2CS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.c new file mode 100644 index 00000000000..3964c25e553 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.c @@ -0,0 +1,77 @@ +/** + * @file + * @brief This file contains the function implementations for the + * Instruction Cache Controller. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:45:25 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24331 $ + * + *************************************************************************** */ + + +/* **** Includes **** */ +#include "mxc_config.h" +#include "icc.h" +/** + * @ingroup icc + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************* */ +void ICC_Enable(void) +{ + /* Invalidate cache and wait until ready */ + MXC_ICC->invdt_all = 1; + while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); + + /* Enable cache */ + MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; + + /* Must invalidate a second time for proper use */ + MXC_ICC->invdt_all = 1; +} + +/* ************************************************************************* */ +void ICC_Disable(void) +{ + MXC_ICC->ctrl_stat &= ~MXC_F_ICC_CTRL_STAT_ENABLE; +} +/**@} end of group icc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.h new file mode 100644 index 00000000000..2e7514f5623 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.h @@ -0,0 +1,83 @@ +/** + * @file + * @brief Instruction Cache Controller function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24662 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _ICC_H_ +#define _ICC_H_ + +/* **** Includes **** */ +#include "icc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Doxy group definition for this peripheral module */ + +/** + * @ingroup sysconfig + * @defgroup icc Instruction Cache Controller (ICC) + * @{ + */ +/** + * @brief Enable and flush the instruction cache controller. + */ +void ICC_Enable(void); + +/** + * @brief Disable the instruction cache controller. + */ +void ICC_Disable(void); + +/** + * @brief Flush the instruction cache controller. + */ +__STATIC_INLINE void ICC_Flush() +{ + ICC_Disable(); + ICC_Enable(); +} +/**@} end of group icc */ +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c new file mode 100644 index 00000000000..5ca4aaff97b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c @@ -0,0 +1,59 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $ + * $Revision: 22543 $ + * + ******************************************************************************/ + +#include +#include "mxc_config.h" +#include "ioman.h" + +/******************************************************************************/ +int IOMAN_Config(const ioman_cfg_t *cfg) +{ + if(cfg == NULL) { + return E_NULL_PTR; + } + + if (*cfg->ack_reg != cfg->req_val.value) { + /* Request pin mapping */ + *cfg->req_reg = cfg->req_val.value; + + /* Check for acknowledgment */ + if (*cfg->ack_reg != cfg->req_val.value) { + return E_BUSY; + } + } + + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h new file mode 100644 index 00000000000..5651707396e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h @@ -0,0 +1,323 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $ + * $Revision: 22543 $ + * + ******************************************************************************/ + +/** + * @file ioman.h + * @brief IOMAN provides IO Management to the device. The functions in this + * API enable requesting port pin assignment and release for all peripherals + * with external I/O. Port pin mapping support is included for peripherals + * that can support more than one pin mapping in a package. + */ + +#ifndef _IOMAN_H_ +#define _IOMAN_H_ + +#include "mxc_config.h" +#include "ioman_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***** Definitions *****/ + +/** @brief Aliases for IOMAN package mapping field values. Refer to the + * User's Guide for pinouts for each mapping. + */ +typedef enum { + IOMAN_MAP_UNUSED = 0, /**< Pin is not used */ + IOMAN_MAP_A = 0, /**< Pin Mapping A */ + IOMAN_MAP_B = 1, /**< Pin Mapping B */ + IOMAN_MAP_C = 2, /**< Pin Mapping C */ + IOMAN_MAP_D = 3, /**< Pin Mapping D */ + IOMAN_MAP_E = 4, /**< Pin Mapping E */ + IOMAN_MAP_F = 5, /**< Pin Mapping F */ + IOMAN_MAP_G = 6 /**< Pin Mapping G */ +} +ioman_map_t; + +/** @brief Typing of IOMAN Request and Acknowledge register fields */ +typedef union { + uint32_t value; + mxc_ioman_spix_req_t spix; /**< SPIX IOMAN configuration struct */ + mxc_ioman_uart0_req_t uart; /**< UART IOMAN configuration struct, see mxc_ioman_uart0_req_t */ + mxc_ioman_i2cm0_req_t i2cm0; /**< I2C Master 0 IOMAN configuration struct, see mxc_ioman_i2cm0_req_t */ + mxc_ioman_i2cm1_req_t i2cm1; /**< I2C Master 1 IOMAN configuration struct, see mxc_ioman_i2cm1_req_t */ + mxc_ioman_i2cm2_req_t i2cm2; /**< I2C Master 2 IOMAN configuration struct, see mxc_ioman_i2cm2_req_t */ + mxc_ioman_i2cs_req_t i2cs; /**< I2C Slave IOMAN configuration struct, see mxc_ioman_i2cs_req_t */ + mxc_ioman_spim0_req_t spim0; /**< SPI Master 0 IOMAN configuration struct, see mxc_ioman_spim0_req_t */ + mxc_ioman_spim1_req_t spim1; /**< SPI Master 1 IOMAN configuration struct, see mxc_ioman_spim1_req_t */ + mxc_ioman_spim2_req_t spim2; /**< SPI Master 2 IOMAN configuration struct, see mxc_ioman_spim1_req_t */ + mxc_ioman_spib_req_t spib; /**< SPI Bridge IOMAN configuration struct, see mxc_ioman_spib_req_t */ + mxc_ioman_owm_req_t owm; /**< 1-Wire Master IOMAN configuration struct, see mxc_ioman_owm_req_t */ +} ioman_req_t; + +/** @brief IOMAN configuration object */ +typedef struct { + volatile uint32_t *req_reg; /** Pointer to an IOMAN request register */ + volatile uint32_t *ack_reg; /** Pointer to an IOMAN acknowledge register */ + ioman_req_t req_val; /** IOMAN request register value, see ioman_req_t */ +} ioman_cfg_t; + + +/***** Function Prototypes *****/ + +/** + * @brief Configure the IO Manager using the specified configuration object. + * @param cfg IOMAN configuration object + * @returns E_NO_ERROR Configuration successful + */ +int IOMAN_Config(const ioman_cfg_t *cfg); + +/** + * @brief Create an IOMAN configuration object for the SPI XIP module. Call IOMAN_Config with this object. + * @param core Request (1) or release (0) SPIX core external pins + * @param ss0 Request (1) or release (0) slave select 0 active out + * @param ss1 Request (1) or release (0) slave select 1 active out + * @param ss2 Request (1) or release (0) slave select 2 active out + * @param quad Request (1) or release (0) quad IO + * @param fast Request (1) or release (0) fast mode + * @returns io_man_cfg_t IOMAN configuration object for the SPI XIP module. + */ +ioman_cfg_t IOMAN_SPIX(int core, int ss0, int ss1, int ss2, int quad, int fast); + +/** + * @brief Create an IOMAN configuration object for a UART module. Call IOMAN_Config with this object. + * @param idx Index of the UART module + * @param io_map Set the pin mapping for RX/TX pins, see ioman_map_t + * @param cts_map Set the pin mapping for CTS pin, see ioman_map_t + * @param rts_map Set the pin mapping for RTS pin, see ioman_map_t + * @param io_en Request (1) or release (0) RX and TX pins + * @param cts_en Request (1) or release (0) CTS pin + * @param rts_en Request (1) or release (0) RTS pin + * @returns ioman_cfg_t IOMAN configuration object for the UART module + */ +ioman_cfg_t IOMAN_UART(int idx, ioman_map_t io_map, ioman_map_t cts_map, ioman_map_t rts_map, int io_en, int cts_en, int rts_en); + +/** + * @brief Create an IOMAN configuration object for the I2CM0 module. Call IOMAN_Config with this object. + * @param map Set the pin mapping for I2CM1 module, see ioman_map_t + * @param io_en Request (1) or release (0) the I/O for the I2CM0 module + * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module. + */ +ioman_cfg_t IOMAN_I2CM0(ioman_map_t map, int io_en); + +/** + * @brief Create an IOMAN configuration object for the I2CM1 module. Call IOMAN_Config with this object. + * @param map Set the pin mapping for I2CM1 module, see ioman_map_t + * @param io_en Request (1) or release (0) the I/O for the I2CM1 module + * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module. + */ +ioman_cfg_t IOMAN_I2CM1(ioman_map_t map, int io_en); + +/** + * @brief Create an IOMAN configuration object for the I2CM2 module. Call IOMAN_Config with this object. + * @param map Set the pin mapping for I2CM2 module, see ioman_map_t + * @param io_en Request (1) or release (0) the I/O for the I2CM2 module + * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module. + */ +ioman_cfg_t IOMAN_I2CM2(ioman_map_t map, int io_en); + +/** + * @brief Create an IOMAN configuration object for an I2C slave module. Call IOMAN_Config with this object. + * @param map Select the pin mapping for all configured pins, see ioman_map_t + * @param io_en Request (1) or release (0) the I/O for this module + * @returns ioman_cfg_t IOMAN configuration object for the I2CS module + */ +ioman_cfg_t IOMAN_I2CS(ioman_map_t map, int io_en); + +/** + * @brief Create an IOMAN configuration object for a SPI Master (SPIM) module. Call IOMAN_Config with this object. + * @param io_en Request (1) or release (0) the core IO for the module + * @param ss0 Request (1) or release (0) slave select 0 + * @param ss1 Request (1) or release (0) slave select 1 + * @param ss2 Request (1) or release (0) slave select 2 + * @param ss3 Request (1) or release (0) slave select 3 + * @param ss4 Request (1) or release (0) slave select 4 + * @param quad Request (1) or release (0) quad IO + * @param fast Request (1) or release (0) fast mode + * @returns ioman_cfg_t IOMAN configuration object for an SPIM0 module + */ +ioman_cfg_t IOMAN_SPIM0(int io_en, int ss0, int ss1, int ss2, int ss3, int ss4, int quad, int fast); + +/** + * @brief Create an IOMAN configuration object for a SPIM module. Call IOMAN_Config with this object. + * @param io_en Request (1) or release (0) the core IO for the module + * @param ss0 Request (1) or release (0) slave select 0 + * @param ss1 Request (1) or release (0) slave select 1 + * @param ss2 Request (1) or release (0) slave select 2 + * @param quad Request (1) or release (0) quad IO + * @param fast Request (1) or release (0) fast mode + * @returns ioman_cfg_t IOMAN configuration object for the SPIM1 module. + */ +ioman_cfg_t IOMAN_SPIM1(int io_en, int ss0, int ss1, int ss2, int quad, int fast); + +/** + * @brief Create an IOMAN configuration object for a SPI module. Call IOMAN_Config with this object. + * @param map Select the pin mapping, see ioman_map_t + * @param io_en Request (1) or release (0) the core IO for the module + * @param ss0 Request (1) or release (0) slave select 0 + * @param ss1 Request (1) or release (0) slave select 1 + * @param ss2 Request (1) or release (0) slave select 2 + * @param sr0 Request (1) or release (0) slave ready 0 + * @param sr1 Request (1) or release (0) slave ready 1 + * @param quad Request (1) or release (0) quad IO + * @param fast Request (1) or release (0) fast mode + * @returns ioman_cfg_t IOMAN configuration object for the SPIM2 module + */ +ioman_cfg_t IOMAN_SPIM2(ioman_map_t map, int io_en, int ss0, int ss1, int ss2, int sr0, int sr1, int quad, int fast); + +/** + * @brief Create an IOMAN configuration object for the SPI Bridge module. Call IOMAN_Config with this object. + * @param io_en Request (1) or release (0) the core IO for the module + * @param quad Request (1) or release (0) quad IO + * @param fast Request (1) or release (0) fast mode + * @returns ioman_cfg_t IOMAN configuration object for the SPIB module + */ +ioman_cfg_t IOMAN_SPIB(int io_en, int quad, int fast); + +/** + * @brief Create an IOMAN configuration object for the 1-Wire Master module. Call IOMAN_Config with this object. + * @param io_en Request (1) or release (0) the core IO for the module + * @param epu Request (1) or release (0) external pullup + * @returns ioman_cfg_t IOMAN configuration object for the OWM module + */ +ioman_cfg_t IOMAN_OWM(int io_en, int epu); + +/** + * @} + */ + +/******************************************************************************/ +/* All the function prototypes above are implemented as macros below. The + * above prototypes are for simplicity in doxygen. + */ +#define IOMAN_SPIX(c, ss0, ss1, ss2, q, f) { \ + .req_reg = &MXC_IOMAN->spix_req, \ + .ack_reg = &MXC_IOMAN->spix_ack, \ + .req_val.spix = { .core_io_req = c, \ + .ss0_io_req = ss0, \ + .ss1_io_req = ss1, \ + .ss2_io_req = ss2, \ + .quad_io_req = q, \ + .fast_mode = f } } + +#define IOMAN_UART(i, im, cm, rm, ien, cen, ren) { \ + .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_req) + (i * 2*sizeof(uint32_t))), \ + .ack_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_ack) + (i * 2*sizeof(uint32_t))), \ + .req_val.uart = { .io_map = im, \ + .cts_map = cm, \ + .rts_map = rm, \ + .io_req = ien, \ + .cts_io_req = cen, \ + .rts_io_req = ren } } + +#define IOMAN_I2CM0(m, ien ) { \ + .req_reg = ((&MXC_IOMAN->i2cm0_req)), \ + .ack_reg = ((&MXC_IOMAN->i2cm0_ack)), \ + .req_val.i2cm0 = { .mapping_req = ien } } + +#define IOMAN_I2CM1(m, ien) { \ + .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm1_req)), \ + .ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm1_ack)), \ + .req_val.i2cm1 = { .io_sel = m, \ + .mapping_req = ien } } + +#define IOMAN_I2CM2(m, ien) { \ + .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm2_req)), \ + .ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm2_ack)), \ + .req_val.i2cm2 = { .io_sel = m, \ + .mapping_req = ien } } + +#define IOMAN_I2CS(m, ien) { \ + .req_reg = &MXC_IOMAN->i2cs_req, \ + .ack_reg = &MXC_IOMAN->i2cs_ack, \ + .req_val.i2cs = { .io_sel = m, \ + .mapping_req = ien } } + +#define IOMAN_SPIM0(io, ss0, ss1, ss2, ss3, ss4, q, f) { \ + .req_reg = &MXC_IOMAN->spim0_req, \ + .ack_reg = &MXC_IOMAN->spim0_ack, \ + .req_val.spim0 = { .core_io_req = io, \ + .ss0_io_req = ss0, \ + .ss1_io_req = ss1, \ + .ss2_io_req = ss2, \ + .ss3_io_req = ss3, \ + .ss4_io_req = ss4, \ + .quad_io_req = q, \ + .fast_mode = f } } + +#define IOMAN_SPIM1(io, ss0, ss1, ss2, q, f) { \ + .req_reg = &MXC_IOMAN->spim1_req, \ + .ack_reg = &MXC_IOMAN->spim1_ack, \ + .req_val.spim1 = { .core_io_req = io, \ + .ss0_io_req = ss0, \ + .ss1_io_req = ss1, \ + .ss2_io_req = ss2, \ + .quad_io_req = q, \ + .fast_mode = f } } + +#define IOMAN_SPIM2(m, io, ss0, ss1, ss2, sr0, sr1, q, f) { \ + .req_reg = &MXC_IOMAN->spim2_req, \ + .ack_reg = &MXC_IOMAN->spim2_ack, \ + .req_val.spim2 = { .mapping_req = m, \ + .core_io_req = io, \ + .ss0_io_req = ss0, \ + .ss1_io_req = ss1, \ + .ss2_io_req = ss2, \ + .sr0_io_req = sr0, \ + .sr1_io_req = sr1, \ + .quad_io_req = q, \ + .fast_mode = f } } + +#define IOMAN_SPIB(io, q, f) { \ + .req_reg = &MXC_IOMAN->spib_req, \ + .ack_reg = &MXC_IOMAN->spib_ack, \ + .req_val.spib = { .core_io_req = io, \ + .quad_io_req = q, \ + .fast_mode = f } } + +#define IOMAN_OWM(io, p) { \ + .req_reg = &MXC_IOMAN->owm_req, \ + .ack_reg = &MXC_IOMAN->owm_ack, \ + .req_val.owm = { .mapping_req = io, \ + .epu_io_req = p } } + +#ifdef __cplusplus +} +#endif + +#endif /* _IOMAN_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c new file mode 100644 index 00000000000..447130b72ae --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c @@ -0,0 +1,424 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-22 12:05:05 -0500 (Tue, 22 Mar 2016) $ + * $Revision: 22032 $ + * ******************************************************************************/ + +/***** Includes *****/ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "lp.h" +#include "ioman_regs.h" + +/***** Definitions *****/ + +#ifndef LP0_PRE_HOOK +#define LP0_PRE_HOOK +#endif +#ifndef LP1_PRE_HOOK +#define LP1_PRE_HOOK +#endif +#ifndef LP1_POST_HOOK +#define LP1_POST_HOOK +#endif + +/***** Globals *****/ + +/***** Functions *****/ + +/* Clear all wake-up configuration */ +void LP_ClearWakeUpConfig(void) +{ + /* Clear GPIO WUD event and configuration registers, globally */ + MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | + MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); + MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | + MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); + + /* Mask off all wake-up sources */ + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP | + MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP | + MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP | + MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 | + MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 | + MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP | + MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER); +} + +/* Clear wake-up flags */ +unsigned int LP_ClearWakeUpFlags(void) +{ + unsigned int flags_tmp; + + /* Get flags */ + flags_tmp = MXC_PWRSEQ->flags; + + /* Clear GPIO WUD event registers, globally */ + MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH); + MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH); + + /* Clear power sequencer event flags (write-1-to-clear) */ + MXC_PWRSEQ->flags = flags_tmp; + + return flags_tmp; +} + +/* Configure the selected pin for wake-up detect */ +int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd) +{ + int result = E_NO_ERROR; + unsigned int pin; + + /* Check that port and pin are within range */ + MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS); + MXC_ASSERT(gpio->mask > 0); + + /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */ + if (gpio->port < 4) { + MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3)); + if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } else if (gpio->port < 8) { + MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3)); + if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } else { + MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3)); + if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } + + if (result == E_NO_ERROR) { + + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + + if (gpio->mask & (1 << pin)) { + + /* Enable modifications to WUD configuration */ + MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE; + + /* Select pad in WUD control */ + /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */ + MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin; + + /* Configure sense level on this pad */ + MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); + + if (act_high) { + /* Select active high with PULSE0 (backwards from what you'd expect) */ + MXC_PWRMAN->wud_pulse0 = 1; + } else { + /* Select active low with PULSE1 (backwards from what you'd expect) */ + MXC_PWRMAN->wud_pulse1 = 1; + } + + /* Clear out the pad mode */ + MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); + + /* Select this pad to have the wake-up function enabled */ + MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); + + /* Activate with PULSE1 */ + MXC_PWRMAN->wud_pulse1 = 1; + + if (wk_pu_pd != LP_NO_PULL) { + /* Select weak pull-up/pull-down on this pad while in LP1 */ + MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); + + /* Again, logic is opposite of what you'd expect */ + if (wk_pu_pd == LP_WEAK_PULL_UP) { + MXC_PWRMAN->wud_pulse0 = 1; + } else { + MXC_PWRMAN->wud_pulse1 = 1; + } + } + + /* Disable configuration each time, required by hardware */ + MXC_PWRMAN->wud_ctrl = 0; + } + } + } + + /* Disable configuration */ + MXC_IOMAN->wud_req0 = 0; + MXC_IOMAN->wud_req1 = 0; + MXC_IOMAN->wud_req2 = 0; + + /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */ + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP; + + return result; +} + +uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio) +{ + uint8_t gpioWokeUp = 0; + + /* Check that port and pin are within range */ + MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS); + MXC_ASSERT(gpio->mask > 0); + + /* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1, 8 is wud_seen2 */ + if (gpio->port < 4) { + gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask; + } else if (gpio->port < 8) { + gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask; + } else { + gpioWokeUp = (MXC_PWRMAN->wud_seen2 >> ((gpio->port - 8) << 3)) & gpio->mask; + } + + return gpioWokeUp; +} + +int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio) +{ + int result = E_NO_ERROR; + unsigned int pin; + + /* Check that port and pin are within range */ + MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS); + MXC_ASSERT(gpio->mask > 0); + + /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */ + if (gpio->port < 4) { + MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3)); + if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } else if (gpio->port < 8) { + MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3)); + if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } else { + MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3)); + if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */ + result = E_BUSY; + } + } + + if (result == E_NO_ERROR) { + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { + if (gpio->mask & (1 << pin)) { + + /* Enable modifications to WUD configuration */ + MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE; + + /* Select pad in WUD control */ + /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */ + MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin; + + /* Clear out the pad mode */ + MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); + + /* Select the wake up function on this pad */ + MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); + + /* disable wake up with PULSE0 */ + MXC_PWRMAN->wud_pulse0 = 1; + + /* Disable configuration each time, required by hardware */ + MXC_PWRMAN->wud_ctrl = 0; + } + } + } + + /* Disable configuration */ + MXC_IOMAN->wud_req0 = 0; + MXC_IOMAN->wud_req1 = 0; + MXC_IOMAN->wud_req2 = 0; + + return result; +} + +int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en) +{ + /* Enable or disable wake on USB plug-in */ + if (plug_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP; + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP); + } + + /* Enable or disable wake on USB unplug */ + if (unplug_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP; + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP); + } + + return E_NO_ERROR; +} + +int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en, + unsigned int prescale_cmp_en, unsigned int rollover_en) +{ + /* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */ + + /* Enable or disable wake on RTC Compare 0 */ + if (comp0_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0; + + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0); + } + + /* Enable or disable wake on RTC Compare 1 */ + if (comp1_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1; + + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1); + } + + /* Enable or disable wake on RTC Prescaler */ + if (prescale_cmp_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP; + + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP); + } + + /* Enable or disable wake on RTC Rollover */ + if (rollover_en) { + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER; + + } else { + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER); + } + + return E_NO_ERROR; +} + + +int LP_EnterLP2(void) +{ + /* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Go into LP2 mode and wait for an interrupt to wake the processor */ + __WFI(); + + return E_NO_ERROR; +} + +int LP_EnterLP1(void) +{ + /* Turn on retention controller */ + MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN; + + /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */ + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT); + + /* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */ + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; + + /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Performance-measurement hook, may be defined as nothing */ + LP1_PRE_HOOK; + + /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */ + MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE; + + /* Dummy read to make sure SSB writes are complete */ + MXC_PWRSEQ->reg0; + + /* Enter LP1 -- sequence is per instructions from ARM, Ltd. */ + __SEV(); + __WFE(); + __WFE(); + + /* Performance-measurement hook, may be defined as nothing */ + LP1_POST_HOOK; + + /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */ + MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE); + + /* Clear SLEEPDEEP bit */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* No error */ + return E_NO_ERROR; +} + +void LP_EnterLP0(void) +{ + /* Disable interrupts, ok not to save state as exit LP0 is a reset */ + __disable_irq(); + + /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */ + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT); + + /* Turn off retention controller */ + MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN); + + /* Turn off retention regulator */ + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP); + + /* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */ + MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW; + + /* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */ + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1); + + /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Performance-measurement hook, may be defined as nothing */ + LP0_PRE_HOOK; + + /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */ + MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE; + + /* Dummy read to make sure SSB writes are complete */ + MXC_PWRSEQ->reg0; + + /* Go into LP0 -- sequence is per instructions from ARM, Ltd. */ + __SEV(); + __WFE(); + __WFE(); + + /* Catch the case where this code does not properly sleep */ + /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */ + MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE); + MXC_ASSERT_FAIL(); + while (1) { + __NOP(); + } + + /* Does not actually return */ +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h new file mode 100644 index 00000000000..55487f5a8e0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h @@ -0,0 +1,185 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-21 09:04:59 -0500 (Mon, 21 Mar 2016) $ + * $Revision: 22006 $ + * + ******************************************************************************/ + +/** + * @file lp.h + * @brief This is the high level API for the Lower Power + */ + +#ifndef _LP_H_ +#define _LP_H_ + +#include "gpio.h" +#include "pwrman_regs.h" +#include "pwrseq_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***** Definitions *****/ +/** + * @brief Enumerations for pull-up and pull-downs + * + */ +typedef enum { + LP_WEAK_PULL_DOWN = -1, + LP_NO_PULL = 0, + LP_WEAK_PULL_UP = 1 +} +lp_pu_pd_select_t; + +/***** Function Prototypes *****/ + +/** + * @brief Gets the first boot flag + * + * @returns 0 if FIRST_BOOT was not set, or 1 if FIRST_BOOT was set + */ +__STATIC_INLINE unsigned int LP_IsFirstBoot() +{ + return ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) >> MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS); +} + +/** + * @brief Clears the first boot flag + * + */ +__STATIC_INLINE void LP_ClearFirstBoot() +{ + MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; +} + +/** + * @brief Determines of program woke up from LP0 + * + * @returns 0 if not woken up from LP0, or 1 if woken from LP0 + */ +__STATIC_INLINE unsigned int LP_IsLP0WakeUp() +{ + //POR should be set and first boot clear + if((MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR) && + ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) == 0)) + return 1; + else + return 0; + +} + +__STATIC_INLINE unsigned int LP_GetWakeUpFlags(void) +{ + return MXC_PWRSEQ->flags; +} +/** + * @brief Clear ALL wake-up configuration on all pins. Disables wake-up entirely. + */ +void LP_ClearWakeUpConfig(void); + +/** + * @brief Read wake-up flags, clear flags, and return to caller. + * @returns Wake-up flags from Power Sequencer + */ +unsigned int LP_ClearWakeUpFlags(void); + +/** + * @brief This function configures one GPIO pin to wake the processor from LP0 or LP1. + * It is not used for LP2 wake-up, as normal GPIO interrupt processing is active in that mode. + * @param gpio GPIO pointer describing the port and pin for selected wake-up source + * @param act_high If non-zero, the signal is configured for active high wake-up. Otherwise, active low. + * @param wk_pu_pd Selection for the 1 Meg ohm pull-up or pull-down on this pin, see #lp_pu_pd_select_t + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd); + +/** + * @brief Clear the wake-up configuration on one specific GPIO pin + * @param gpio GPIO pointer describing the port and pin for selected wake-up source + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio); + +/** + * @brief Check if a specific gpio triggered the wake up + * @param gpio GPIO pointer describing the port and pin(s) + * @returns 0 = gpio passed in did not trigger a wake up + * nonzero = at least one of the gpio passed in triggered a wake up + * the bit set represents which pin is the wake up source + */ +uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio); + +/** + * @brief Wake on USB plug or unplug + * @param plug_en set to 1 to enable wake-up when USB VBUS is detected + * @param unplug_en set to 1 to enable wake-up when USB VBUS disappears + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en); + +/** + * @brief Wake on any enabled event signal from RTC + * @param comp0_en set to 1 to enable wake-up when RTC Comparison 0 is set + * @param comp1_en set to 1 to enable wake-up when RTC Comparison 1 is set + * @param prescale_cmp_en set to 1 to enable wake-up when RTC Prescaler Compare is set + * @param rollover_en set to 1 to enable wake-up when RTC Roll-over is set + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en, unsigned int prescale_cmp_en, unsigned int rollover_en); + +/** + * @brief Enter LP2 power-saving mode + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_EnterLP2(void); + +/** + * @brief Enter LP1 mode, which saves CPU state and SRAM. Execution resumes after this call. + * @note Interrupts should be globally disabled before calling this function. + * @returns #E_NO_ERROR on success, error if unsuccessful. + */ +int LP_EnterLP1(void); + +/** + * @brief Enter the lowest-possible power mode, known as LP0. SRAM contents are lost. + * Waking up from LP0 is like a system reset. This function does not return. + * @note Interrupts are globally disabled upon entering this function. + */ +void LP_EnterLP0(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _LP_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.c new file mode 100644 index 00000000000..7c381c8ef44 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.c @@ -0,0 +1,236 @@ +/** + * @file + * @brief Modular Arithmetic Accelerator (MAA) API Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "maa.h" + +/** + * @ingroup maa + * @{ + */ + +///@cond +#define maa_is_running() (MXC_MAA->ctrl & MXC_F_MAA_CTRL_START ? 1 : 0) + +/** + * Macro that translates from #mxc_maa_reg_select_t to a pointer for MAA memory operations. + */ +#define UMAA_REGFILE_TO_ADDR(base, x) ((base + (MXC_MAA_HALF_SIZE * x))) + +/** + * Macro that adjusts the pointer so that it is pointing to the last 32-bit word in the maa (sub-)segment + */ +#define UMAA_ADDR_INDEX_LAST_32BIT(x) ((uint8_t *)x + (MXC_MAA_HALF_SIZE-4)) +///@endcond + + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_Init(void) +{ + SYS_MAA_Init(); + + return MXC_E_MAA_OK; +} + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_WipeRAM(void) +{ + /* Check for running MAA */ + if (maa_is_running()) { + return MXC_E_MAA_ERR; + } + + /* Clear register files */ + memset((void *)MXC_MAA_MEM->seg0, 0, sizeof(MXC_MAA_MEM->seg0)); + memset((void *)MXC_MAA_MEM->seg1, 0, sizeof(MXC_MAA_MEM->seg1)); + memset((void *)MXC_MAA_MEM->seg2, 0, sizeof(MXC_MAA_MEM->seg2)); + memset((void *)MXC_MAA_MEM->seg3, 0, sizeof(MXC_MAA_MEM->seg3)); + memset((void *)MXC_MAA_MEM->seg4, 0, sizeof(MXC_MAA_MEM->seg4)); + memset((void *)MXC_MAA_MEM->seg5, 0, sizeof(MXC_MAA_MEM->seg5)); + + return MXC_E_MAA_OK; +} + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_Load(mxc_maa_reg_select_t regfile, const uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag) +{ + uint32_t *maaptr; + uint32_t fill; + unsigned int zerotmp; + + if ((regfile > MXC_E_REG_51) || (size > MXC_MAA_REG_SIZE)) { + /* Out of range */ + return MXC_E_MAA_ERR; + } + + if (flag == MXC_MAA_F_MEM_REVERSE) { + /* This is not currently implemented */ + return MXC_E_MAA_ERR; + } + + maaptr = (uint32_t *)UMAA_REGFILE_TO_ADDR(MXC_BASE_MAA_MEM, regfile); + + /* + * MAA (sub-)segments must be loaded with zero pad to a 64-bit boundary, or the "garbage bits" + * will case erroneous results. + */ + /* Find the ceiling for the closest 64-bit boundary based on the selected MAWS */ + zerotmp = (((MXC_MAA->maws & MXC_F_MAA_MAWS_MODLEN) >> MXC_F_MAA_MAWS_MODLEN_POS) + 63) & 0xfc0; + /* Convert to bytes */ + zerotmp /= 8; + + /* Fill uMAA memory in long word sized chunks */ + while (size > 3) { + *maaptr++ = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0]; + data += 4; + size -= 4; + zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0; + } + + /* Remainder */ + if (size) { + fill = data[0]; + fill |= ((size > 1) ? (data[1] << 8) : 0); + fill |= ((size > 2) ? (data[2] << 16) : 0); + *maaptr++ = fill; + + /* We just filled 4 bytes in this section */ + zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0; + } + + /* Wipe the remaining "garbage bits" */ + while (zerotmp) { + *maaptr++ = 0; + zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0; + } + + return MXC_E_MAA_OK; +} + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_Unload(mxc_maa_reg_select_t regfile, uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag) +{ + uint32_t *maaptr; + uint32_t fill; + + if ((regfile > MXC_E_REG_51) || (size > MXC_MAA_REG_SIZE)) { + /* Out of range */ + return MXC_E_MAA_ERR; + } + + if (flag == MXC_MAA_F_MEM_REVERSE) { + /* This is not currently implemented */ + return MXC_E_MAA_ERR; + } + + maaptr = (uint32_t *)UMAA_REGFILE_TO_ADDR(MXC_BASE_MAA_MEM, regfile); + + /* Unload uMAA memory in long word sized chunks */ + while (size > 3) { + fill = *maaptr++; + data[0] = fill & 0xff; + data[1] = (fill >> 8) & 0xff; + data[2] = (fill >> 16) & 0xff; + data[3] = (fill >> 24) & 0xff; + data += 4; + size -= 4; + } + + /* Remainder */ + if (size) { + fill = *maaptr; + data[0] = fill & 0xff; + if (size > 1) { + data[1] = (fill >> 8) & 0xff; + } + if (size > 2) { + data[2] = (fill >> 16) & 0xff; + } + } + + return MXC_E_MAA_OK; +} + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_Run(mxc_maa_operation_t op, + mxc_maa_reg_select_t al, mxc_maa_reg_select_t bl, + mxc_maa_reg_select_t rl, mxc_maa_reg_select_t tl) +{ + if (maa_is_running()) { + /* Attempt to start the MAA while already running */ + return MXC_E_MAA_ERR; + } + + /* Clear out any previous flags */ + MXC_MAA->ctrl = 0x00000020; + + /* Construct memory segment selections, select operation, and start the uMAA */ + MXC_MAA->ctrl = (((al << MXC_F_MAA_CTRL_SEG_A_POS) & MXC_F_MAA_CTRL_SEG_A) | + ((bl << MXC_F_MAA_CTRL_SEG_B_POS) & MXC_F_MAA_CTRL_SEG_B) | + ((rl << MXC_F_MAA_CTRL_SEG_RES_POS) & MXC_F_MAA_CTRL_SEG_RES) | + ((tl << MXC_F_MAA_CTRL_SEG_TMP_POS) & MXC_F_MAA_CTRL_SEG_TMP) | + ((op << MXC_F_MAA_CTRL_OPSEL_POS) & MXC_F_MAA_CTRL_OPSEL) | + MXC_F_MAA_CTRL_START); + + /* Blocking wait for uMAA to complete. */ + while ((MXC_MAA->ctrl & MXC_F_MAA_CTRL_IF_DONE) == 0); + + if (MXC_MAA->ctrl & MXC_F_MAA_CTRL_IF_ERROR) { + /* MAA signaled error */ + return MXC_E_MAA_ERR; + } + + return MXC_E_MAA_OK; +} + +/* ************************************************************************* */ +mxc_maa_ret_t MAA_SetWordSize(unsigned int len) +{ + if ((len > MXC_MAA_REG_SIZE_BITS) || maa_is_running()) { + return MXC_E_MAA_ERR; + } + + /* Set bit length for calculation, and disable endian swap */ + MXC_MAA->maws = ((len << MXC_F_MAA_MAWS_MODLEN_POS) & MXC_F_MAA_MAWS_MODLEN); + + return MXC_E_MAA_OK; +} +/**@} end of ingroup maa */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.h new file mode 100644 index 00000000000..24a64b24d62 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.h @@ -0,0 +1,224 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the Modular Math + * Accelerator (MAA) module. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24665 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MAA_H +#define _MAA_H + +/* **** Includes **** */ +#include + +#include "maa_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup maa MAA + * @details The API only supports synchronous operations due to the sensitive + * nature of the input and output data. + * @{ + */ + +/* **** Definitions **** */ + +/** + * Definition for the maximum MAA register size on this device in bytes, 128. + */ +#define MXC_MAA_REG_SIZE 0x80 +/** + * Definition for the maximum MAA register size on this device in bits, 1024. + */ +#define MXC_MAA_REG_SIZE_BITS (MXC_MAA_REG_SIZE << 3) + +/** + * @def Sub-register ("half size"), allowing 2x more operands in MAA at a time when MAWS <= MAX_SIZE/2 + */ +#define MXC_MAA_HALF_SIZE (MXC_MAA_REG_SIZE/2) + +/** Flags for MAA_Load() and MAA_Unload() */ +#define MXC_MAA_F_MEM_VERBATIM 0 +/** Flags for MAA_Load() and MAA_Unload() */ +#define MXC_MAA_F_MEM_REVERSE 1 + +/** + * Enumeration type for Segment and Sub-segment selection + */ +/* Warning: Do not change the assigned numbers/ordering without associated changes to UMAA_REGFILE_TO_ADDR(x) */ +typedef enum { + /* Register names when MAWS > 512 */ + MXC_E_REG_0 = 0, /**< Register MXC_E_REG_0: If MAA_MAWS > 512 use this register name. */ + MXC_E_REG_1 = 2, /**< Register MXC_E_REG_1: If MAA_MAWS > 512 use this register name. */ + MXC_E_REG_2 = 4, /**< Register MXC_E_REG_2: If MAA_MAWS > 512 use this register name. */ + MXC_E_REG_3 = 6, /**< Register MXC_E_REG_3: If MAA_MAWS > 512 use this register name. */ + MXC_E_REG_4 = 8, /**< Register MXC_E_REG_4: If MAA_MAWS > 512 use this register name. */ + MXC_E_REG_5 = 10, /**< Register MXC_E_REG_5: If MAA_MAWS > 512 use this register name. */ + /* Register names when MAWS < 512 */ + MXC_E_REG_00 = 0, /**< Register MXC_E_REG_00: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_01 = 1, /**< Register MXC_E_REG_01: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_10 = 2, /**< Register MXC_E_REG_10: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_11 = 3, /**< Register MXC_E_REG_11: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_20 = 4, /**< Register MXC_E_REG_20: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_21 = 5, /**< Register MXC_E_REG_21: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_30 = 6, /**< Register MXC_E_REG_30: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_31 = 7, /**< Register MXC_E_REG_31: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_40 = 8, /**< Register MXC_E_REG_40: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_41 = 9, /**< Register MXC_E_REG_41: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_50 = 10, /**< Register MXC_E_REG_50: If MAA_MAWS < 512 this is the register name. */ + MXC_E_REG_51 = 11 /**< Register MXC_E_REG_51: If MAA_MAWS < 512 this is the register name. */ +} mxc_maa_reg_select_t; + +/** + * Enumeration type for MAA operation selection. + */ +typedef enum { + MXC_E_MAA_EXP = 0, /**< Exponentiate */ + MXC_E_MAA_SQR = 1, /**< Square */ + MXC_E_MAA_MUL = 2, /**< Multiply */ + MXC_E_MAA_SQRMUL = 3, /**< Square followed by Multiply */ + MXC_E_MAA_ADD = 4, /**< Addition */ + MXC_E_MAA_SUB = 5 /**< Subtraction */ +} mxc_maa_operation_t; + +/** + * Enumeration type to set special flags for loading & unloading data. + */ +typedef enum { + + MXC_E_MAA_VERBATIM = 0, /**< Copy bytes without reversal and right-justification */ + MXC_E_MAA_REVERSE /**< Reverse bytes and right-justify (bytes are loaded at the highest address, then descending) */ +} mxc_maa_endian_select_t; + +/** + * Enumeration type for MAA module specific return codes. + */ +typedef enum { + MXC_E_MAA_ERR = -1, /**< Error */ + MXC_E_MAA_OK = 0, /**< No Error */ + MXC_E_MAA_BUSY /**< MAA engine busy, try again later */ +} mxc_maa_ret_t; + +/** + * @brief Initialize the required clocks and enable the MAA peripheral + * module. + * @retval #MXC_E_MAA_ERR on error. + * @retval #MXC_E_MAA_BUSY if the MAA is busy. + * @retval #MXC_E_MAA_OK if the MAA is initialized successfully. + */ +mxc_maa_ret_t MAA_Init(void); + +/** + * @brief Erase all MAA register RAM + * @retval #MXC_E_MAA_ERR on error. + * @retval #MXC_E_MAA_BUSY if the MAA is busy. + * @retval #MXC_E_MAA_OK if the MAA is initialized successfully. + */ +mxc_maa_ret_t MAA_WipeRAM(void); + + +/** + * @brief Load the selected MAA register. + * + * @param regfile Selects the register to load. + * @param data Pointer to a data buffer to load into the register. + * @param size Size of the data to load. + * @param flag Reverse the data so that it will unload properly on + * little endian machines, see #mxc_maa_endian_select_t. + * + * @return #MXC_E_MAA_ERR if any parameter out of range. + * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible. + * @return #MXC_E_MAA_OK if the selected register is loaded correctly. + */ +mxc_maa_ret_t MAA_Load(mxc_maa_reg_select_t regfile, const uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag); + +/** + * @brief Unload (copy from) the selected MAA register + * + * @param regfile Selects the register to unload. + * @param data Pointer to a buffer to store the unloaded data. + * @param size Maximum size of the data to unload. + * @param flag Reverse the data so that it will unload properly on + * little endian machines, see #mxc_maa_endian_select_t. + * @return #MXC_E_MAA_ERR if any parameter out of range. + * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible. + * @return #MXC_E_MAA_OK if the requested register data is copied correctly + * to @p data. + */ +mxc_maa_ret_t MAA_Unload(mxc_maa_reg_select_t regfile, uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag); + +/** + * @brief Execute an MAA operation specified. + * + * @param op Operation to perform, see #mxc_maa_operation_t. + * @param al Segment to use for operand A, see #mxc_maa_reg_select_t. + * @param bl Segment to use for operand B. + * @param rl Segment which will hold result R after the operation is + * complete. + * @param tl Segment to use for temporary storage T. + * + * @return #MXC_E_MAA_ERR if any parameter out of range. + * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible. + * @return #MXC_E_MAA_OK if the operation completed. + */ +mxc_maa_ret_t MAA_Run(mxc_maa_operation_t op, \ + mxc_maa_reg_select_t al, mxc_maa_reg_select_t bl, \ + mxc_maa_reg_select_t rl, mxc_maa_reg_select_t tl); + +/** + * @brief Set the bit length of the modulus. + * + * @param len Modulus size in bits (ie. \f$ ln_2(modulus) \f$ ) + * + * @return #MXC_E_MAA_ERR if any parameter out of range. + * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible. + * @return #MXC_E_MAA_OK if the length is set as requested. + */ +mxc_maa_ret_t MAA_SetWordSize(unsigned int len); + +/**@} end of group maa*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.c new file mode 100644 index 00000000000..aa7df477407 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.c @@ -0,0 +1,60 @@ +/** + * @file + * @brief Debug Assertion source file. + */ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:40:22 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24671 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" + +/** + * @ingroup MXC_Assertions + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals *****/ + +/* **** Functions **** */ + +/* ************************************************************************** */ +__weak void mxc_assert(const char *expr, const char *file, int line) +{ + while(1) {} +} +/**@} end of ingroup MXC_Assertions*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.h new file mode 100644 index 00000000000..162df183e63 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.h @@ -0,0 +1,108 @@ +/** + * @file + * @brief Assertion checks for debugging. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24663 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ASSERT_H_ +#define _MXC_ASSERT_H_ + +/* **** Includes **** */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup sysconfig + * @defgroup MXC_Assertions Assertion Checks for Debugging + * @brief Assertion checks for debugging. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + * @{ + */ +/* **** Definitions **** */ + +#ifdef MXC_ASSERT_ENABLE +/** + * Macro that checks the expression for true and generate an assertion. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT(expr) \ +if (!(expr)) \ +{ \ + mxc_assert(#expr, __FILE__, __LINE__); \ +} +/** + * Macro that generates an assertion with the message "FAIL". + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__); +#else +#define MXC_ASSERT(expr) +#define MXC_ASSERT_FAIL() +#endif + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Assert an error when the given expression fails during debugging. + * @param expr String with the expression that failed the assertion. + * @param file File containing the failed assertion. + * @param line Line number for the failed assertion. + * @note This is defined as a weak function and can be overridden at the + * application layer to print the debugging information. + * @code + * printf("%s, file: %s, line %d\n", expr, file, line); + * @endcode + */ +void mxc_assert(const char *expr, const char *file, int line); + +/**@} end of group MXC_Assertions*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_ASSERT_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_config.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_config.h new file mode 100644 index 00000000000..d0c00caf518 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_config.h @@ -0,0 +1,43 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_CONFIG_H +#define _MXC_CONFIG_H + +#include "mxc_device.h" +#include "mxc_errors.h" + +#endif /* _CONFIG_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_errors.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_errors.h new file mode 100644 index 00000000000..47b7127d90d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_errors.h @@ -0,0 +1,96 @@ +/** + * @file + * @brief List of common error return codes for Maxim Integrated libraries. +*/ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24663 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _ERRORS_H_ +#define _ERRORS_H_ + +/** + * @ingroup sysconfig + * @defgroup MXC_Error_Codes Common Error Codes + * @brief A list of common error codes used by the API. + * @note A Negative Error Convention is used to avoid conflict with + * positive Non-Error returns. + * @{ + */ + +/** + * No Error + */ +#define E_NO_ERROR 0 +/** No Error, success */ +#define E_SUCCESS 0 +/** Pointer is NULL */ +#define E_NULL_PTR -1 +/** No such device */ +#define E_NO_DEVICE -2 +/** Parameter not acceptable */ +#define E_BAD_PARAM -3 +/** Value not valid or allowed */ +#define E_INVALID -4 +/** Module not initialized */ +#define E_UNINITIALIZED -5 +/** Busy now, try again later */ +#define E_BUSY -6 +/** Operation not allowed in current state */ +#define E_BAD_STATE -7 +/** Generic error */ +#define E_UNKNOWN -8 +/** General communications error */ +#define E_COMM_ERR -9 +/** Operation timed out */ +#define E_TIME_OUT -10 +/** Expected response did not occur */ +#define E_NO_RESPONSE -11 +/** Operations resulted in unexpected overflow */ +#define E_OVERFLOW -12 +/** Operations resulted in unexpected underflow */ +#define E_UNDERFLOW -13 +/** Data or resource not available at this time */ +#define E_NONE_AVAIL -14 +/** Event was shutdown */ +#define E_SHUTDOWN -15 +/** Event was aborted */ +#define E_ABORT -16 +/** The requested operation is not supported */ +#define E_NOT_SUPPORTED -17 +/**@} end of MXC_Error_Codes group */ + +#endif /* _ERRORS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h new file mode 100644 index 00000000000..3c17a9298e7 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h @@ -0,0 +1,114 @@ +/** + * @file + * @brief Exclusive access lock utility functions. +*/ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24663 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_LOCK_H_ +#define _MXC_LOCK_H_ + +/***** Includes *****/ +#include "mxc_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup sysconfig + * @defgroup mxc_lock_utilities Lock functions for Exclusive Access + * @brief Lock functions to obtain and release a variable for exclusive + * access. These functions are marked interrupt safe if they are + * interrupt safe. + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Attempts to acquire the lock. + * @details This in an interrupt safe function that can be used as a mutex. + * The lock variable must remain in scope until the lock is + * released. Will not block if another thread has already acquired + * the lock. + * @param lock Pointer to variable that is used for the lock. + * @param value Value to be place in the lock. Can not be 0. + * + * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. + */ +__STATIC_INLINE int mxc_get_lock(uint32_t *lock, uint32_t value) +{ + do { + + // Return if the lock is taken by a different thread + if(__LDREXW((volatile unsigned long *)lock) != 0) { + return E_BUSY; + } + + // Attempt to take the lock + } while(__STREXW(value, (volatile unsigned long *)lock) != 0); + + // Do not start any other memory access until memory barrier is complete + __DMB(); + + return E_NO_ERROR; +} + +/** + * @brief Free the given lock. + * @param[in,out] lock Pointer to the variable used for the lock. When the lock + * is free, the value pointed to by @p lock is set to zero. + */ +__STATIC_INLINE void mxc_free_lock(uint32_t *lock) +{ + // Ensure memory operations complete before releasing lock + __DMB(); + *lock = 0; +} + +/**@} end of group mxc_lock_utilities */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_LOCK_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c new file mode 100644 index 00000000000..c0c27353d13 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c @@ -0,0 +1,832 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-06-17 12:59:44 -0500 (Fri, 17 Jun 2016) $ + * $Revision: 23365 $ + * + ******************************************************************************/ + +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "ioman.h" +#include "clkman.h" +#include "pwrseq_regs.h" +#include "pwrman_regs.h" +#include "spix_regs.h" +#include "trim_regs.h" + +/***** Definitions *****/ +#define SYS_RTC_CLK 32768UL + +/******************************************************************************/ +uint32_t SYS_GetFreq(uint32_t clk_scale) +{ + uint32_t freq; + unsigned int clkdiv; + + if (clk_scale == MXC_V_CLKMAN_CLK_SCALE_DISABLED) { + freq = 0; + } else { + clkdiv = 1 << (clk_scale - 1); + freq = SystemCoreClock / clkdiv; + } + + return freq; +} + +/******************************************************************************/ +uint32_t SYS_CPU_GetFreq(void) +{ + return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_CPU)); +} + +/******************************************************************************/ +int SYS_ADC_Init(void) +{ + /* Power up the ADC AFE, enable clocks */ + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE; + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_AES_Init(void) +{ + /* Set up clocks for AES block */ + /* Enable crypto ring oscillator, which is used by all TPU components (AES, uMAA, etc.) */ + CLKMAN_CryptoClockEnable(1); + + /* Change prescaler to /1 */ + CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_AES, CLKMAN_SCALE_DIV_1); + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_GPIO_Init(void) +{ + if (CLKMAN_GetClkScale(CLKMAN_CLK_GPIO) == CLKMAN_SCALE_DISABLED) { + CLKMAN_SetClkScale(CLKMAN_CLK_GPIO, CLKMAN_SCALE_DIV_1); + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg) +{ + static int subsequent_call = 0; + int err, idx; + clkman_scale_t clk_scale; + uint32_t min_baud; + + if(sys_cfg == NULL) + return E_NULL_PTR; + + if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { + CLKMAN_SetClkScale(CLKMAN_CLK_UART, sys_cfg->clk_scale); + } else if (!subsequent_call) { + /* This clock divider is shared amongst all UARTs. Only change it if it + * hasn't already been configured. UART_Init() will check for validity + * for this baudrate. + */ + subsequent_call = 1; + + /* Setup the clock divider for the given baud rate */ + clk_scale = CLKMAN_SCALE_DISABLED; + do { + min_baud = ((SystemCoreClock >> clk_scale++) / (16 * (MXC_F_UART_BAUD_BAUD_DIVISOR >> MXC_F_UART_BAUD_BAUD_DIVISOR_POS))); + } while (uart_cfg->baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO); + + /* check if baud rate cannot be reached */ + if(uart_cfg->baud < min_baud) + return E_BAD_STATE; + + CLKMAN_SetClkScale(CLKMAN_CLK_UART, clk_scale); + } + + if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + /* Reset the peripheral */ + idx = MXC_UART_GET_IDX(uart); + MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx); + MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx)); + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_UART_Shutdown(mxc_uart_regs_t *uart) +{ + int err; + int idx = MXC_UART_GET_IDX(uart); + ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_UART(idx, 0, 0, 0, 0, 0, 0); + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart) +{ + return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_UART)); +} + +/******************************************************************************/ +int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg) +{ + int err; + + if(cfg == NULL) + return E_NULL_PTR; + + CLKMAN_SetClkScale(CLKMAN_CLK_I2CM, cfg->clk_scale); + MXC_CLKMAN->i2c_timer_ctrl = 1; + + if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm) +{ + int err; + int idx = MXC_I2CM_GET_IDX(i2cm); + ioman_cfg_t io_cfg; + + switch(idx) + { + case 0: + io_cfg = (ioman_cfg_t)IOMAN_I2CM0(0, 0); + break; + case 1: + io_cfg = (ioman_cfg_t)IOMAN_I2CM1(0, 0); + break; + case 2: + io_cfg = (ioman_cfg_t)IOMAN_I2CM2(0, 0); + break; + default: + return E_BAD_PARAM; + } + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm) +{ + return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_I2CM)); +} + +/******************************************************************************/ +int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg) +{ + int err; + + if(cfg == NULL) + return E_NULL_PTR; + + CLKMAN_SetClkScale(CLKMAN_CLK_I2CS, cfg->clk_scale); + MXC_CLKMAN->i2c_timer_ctrl = 1; + + if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs) +{ + int err; + ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_I2CS(0, 0); + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs) +{ + uint32_t freq, clkdiv; + + if (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) == MXC_V_CLKMAN_CLK_SCALE_DISABLED) { + freq = 0; + } else { + clkdiv = 1 << (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) - 1); + freq = (SystemCoreClock / clkdiv); + } + + return freq; +} + +/******************************************************************************/ +int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg) +{ + int err, idx; + clkman_scale_t clk_scale; + uint32_t max_baud; + + if(sys_cfg == NULL) + return E_NULL_PTR; + + idx = MXC_SPIM_GET_IDX(spim); + + if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { + if(spim_cfg->baud > ((SystemCoreClock >> (sys_cfg->clk_scale - 1))/2)) { + return E_BAD_PARAM; + } + CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), sys_cfg->clk_scale); + } else { + + if(spim_cfg->baud > (SystemCoreClock/2)) { + return E_BAD_PARAM; + } + + /* Setup the clock divider for the given baud rate */ + clk_scale = CLKMAN_SCALE_DISABLED; + do { + max_baud = ((SystemCoreClock >> clk_scale++) / 2); + } while (spim_cfg->baud < max_baud && clk_scale < CLKMAN_SCALE_AUTO); + + if(clk_scale == CLKMAN_SCALE_AUTO) { + clk_scale--; + } + + CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), clk_scale); + } + + if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim) +{ + int err; + int idx = MXC_SPIM_GET_IDX(spim); + ioman_cfg_t io_cfg; + + switch(idx) + { + case 0: + io_cfg = (ioman_cfg_t)IOMAN_SPIM0(0, 0, 0, 0, 0, 0, 0, 0); + break; + case 1: + io_cfg = (ioman_cfg_t)IOMAN_SPIM1(0, 0, 0, 0, 0, 0); + break; + case 2: + io_cfg = (ioman_cfg_t)IOMAN_SPIM2(0, 0, 0, 0, 0, 0, 0, 0, 0); + break; + default: + return E_BAD_PARAM; + } + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim) +{ + int idx = MXC_SPIM_GET_IDX(spim); + return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx))); +} + +/******************************************************************************/ +int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud) +{ + int err; + clkman_scale_t clk_scale; + uint32_t min_baud; + + if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { + CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), sys_cfg->clk_scale); + } else { + /* Setup the clock divider for the given baud rate */ + clk_scale = CLKMAN_SCALE_DISABLED; + do { + min_baud = ((SystemCoreClock >> clk_scale++) / (2 * + (MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK >> MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS))); + } while (baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO); + + /* check if baud rate cannot be reached */ + if(baud < min_baud) + return E_BAD_STATE; + + CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), clk_scale); + } + + if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_SPIX_Shutdown() +{ + int err; + ioman_cfg_t io_cfg = IOMAN_SPIX(0, 0, 0, 0, 0, 0); + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_SPIX_GetFreq() +{ + return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX))); +} + +/******************************************************************************/ +int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg) +{ + int err; + + if(sys_cfg == NULL) + return E_NULL_PTR; + + if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) + { + CLKMAN_SetClkScale(CLKMAN_CLK_OWM, sys_cfg->clk_scale); + } + else + { + CLKMAN_SetClkScale(CLKMAN_CLK_OWM, CLKMAN_SCALE_DIV_1); + } + + if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int SYS_OWM_Shutdown(mxc_owm_regs_t *owm) +{ + int err; + + ioman_cfg_t io_cfg = IOMAN_OWM(0, 0); + + if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm) +{ + return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_OWM)); +} + +/******************************************************************************/ +uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr) +{ + return SystemCoreClock; +} + +/******************************************************************************/ +int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg) +{ + int pin, gpio_index, tmr_index; + + if (cfg != NULL) + { + /* Make sure the given GPIO mapps to the given TMR */ + for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) + { + if(cfg->mask & (1 << pin)) + { + gpio_index = (MXC_GPIO_MAX_PINS_PER_PORT * cfg->port) + pin; + tmr_index = gpio_index % MXC_CFG_TMR_INSTANCES; + + if(tmr_index == MXC_TMR_GET_IDX(tmr)) + return GPIO_Config(cfg); + else + return E_BAD_PARAM; + } + } + + return E_BAD_PARAM; + + } else { + return E_NO_ERROR; + } +} + +/******************************************************************************/ +uint32_t SYS_SysTick_GetFreq(void) +{ + /* Determine is using internal (SystemCoreClock) or external (32768) clock */ + if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + return SystemCoreClock; + } else { + return SYS_RTC_CLK; + } +} + +/******************************************************************************/ +uint32_t SYS_PT_GetFreq(void) +{ + return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_PT)); +} + +/******************************************************************************/ +void SYS_PT_Init(sys_pt_clk_scale clk_scale) +{ + /* setup clock divider for pulse train clock */ + CLKMAN_SetClkScale(CLKMAN_CLK_PT, clk_scale); +} + +/******************************************************************************/ +int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg) +{ + int pt_index; + + /* Make sure the given GPIO mapps to the given PT */ + pt_index = MXC_PT_GET_IDX(pt); + if(pt_index < 0) { + return E_NOT_SUPPORTED; + } + + /* Even number port */ + if(cfg->port%2 == 0) { + /* Pin number should match PT number */ + if(!(cfg->mask & (0x1 << pt_index))) { + return E_NOT_SUPPORTED; + } + } else { + /* Pin number+8 should match PT */ + if(!((cfg->mask << 8) & (0x1 << pt_index))) { + return E_NOT_SUPPORTED; + } + } + + return GPIO_Config(cfg); +} + +/******************************************************************************/ +void SYS_USB_Enable(uint8_t enable) +{ + /* Enable USB clock */ + CLKMAN_ClockGate(CLKMAN_USB_CLOCK, enable); + + if(enable) { + /* Enable USB Power */ + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED; + } else { + /* Disable USB Power */ + MXC_PWRMAN->pwr_rst_ctrl &= ~MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED; + } +} + +/******************************************************************************/ +int SYS_SysTick_Config(uint32_t ticks, int clk_src) +{ + + if(ticks == 0) + return E_BAD_PARAM; + + /* If SystemClock, call default CMSIS config and return */ + if (clk_src) { + return SysTick_Config(ticks); + } else { /* External clock source requested + enable RTC clock in run mode*/ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN); + + /* Disable SysTick Timer */ + SysTick->CTRL = 0; + /* Check reload value for valid */ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) { + /* Reload value impossible */ + return E_BAD_PARAM; + } + /* set reload register */ + SysTick->LOAD = ticks - 1; + + /* set Priority for Systick Interrupt */ + NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); + + /* Load the SysTick Counter Value */ + SysTick->VAL = 0; + + /* Enable SysTick IRQ and SysTick Timer leaving clock source as external */ + SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Function successful */ + return E_NO_ERROR; + } +} + +/******************************************************************************/ +int SYS_SysTick_Delay(uint32_t ticks) +{ + uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i; + uint32_t reload, value, ctrl; /* save/restore variables */ + + if(ticks == 0) + return E_BAD_PARAM; + + /* If SysTick is not enabled we can take it for our delay */ + if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + + /* Save current state in case it's disabled but already configured, restore at return.*/ + reload = SysTick->LOAD; + value = SysTick->VAL; + ctrl = SysTick->CTRL; + + /* get the number of ticks less than max RELOAD. */ + num_remain = ticks % SysTick_LOAD_RELOAD_Msk; + + /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will + give us the number of max SysTicks cycles required */ + num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk; + + /* Do the required full systick countdowns */ + if (num_full) { + /* load the max count value into systick */ + SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; + /* load the starting value */ + SysTick->VAL = 0; + /*enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + /* CountFlag will get set when VAL reaches zero */ + for (i = num_full; i > 0; i--) { + do { + cur_ticks = SysTick->CTRL; + } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); + } + /* Disable systick */ + SysTick->CTRL = 0; + } + /* Now handle the remainder of ticks */ + if (num_remain) { + SysTick->LOAD = num_remain; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + /* wait for countflag to get set */ + do { + cur_ticks = SysTick->CTRL; + } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); + /* Disable systick */ + SysTick->CTRL = 0; + } + + /* restore original state of SysTick and return */ + SysTick->LOAD = reload; + SysTick->VAL = value; + SysTick->CTRL = ctrl; + + return E_NO_ERROR; + + } else { /* SysTick is enabled + When SysTick is enabled count flag can not be used + and the reload can not be changed. + Do not read the CTRL register -> clears count flag */ + + /* Get the reload value for wrap/reload case */ + reload = SysTick->LOAD; + + /* Read the starting systick value */ + previous_ticks = SysTick->VAL; + + do { + /* get current SysTick value */ + cur_ticks = SysTick->VAL; + /* Check for wrap/reload of timer countval */ + if (cur_ticks > previous_ticks) { + /* subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks) */ + num_subtract = (previous_ticks + (reload - cur_ticks)); + } else { /* standard case (no wrap) + subtract off the number of ticks since last pass */ + num_subtract = (previous_ticks - cur_ticks); + } + /* check to see if we are done. */ + if (num_subtract >= ticks) + return E_NO_ERROR; + else + ticks -= num_subtract; + /* cur_ticks becomes previous_ticks for next timer read. */ + previous_ticks = cur_ticks; + } while (ticks > 0); + /* Should not ever be reached */ + return E_NO_ERROR; + } +} + +/******************************************************************************/ +int SYS_RTC_Init(void) +{ + /* Enable power for RTC for all LPx states */ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | + MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); + + /* Enable clock to synchronizers */ + CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1); + + return E_NO_ERROR; +} + +/******************************************************************************/ +void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg) +{ + unsigned int startbit = (cfg->port * 8); + volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32); + *use_vddioh_reg &= ~cfg->mask << (startbit % 32); +} + +/******************************************************************************/ +void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg) +{ + unsigned int startbit = (cfg->port * 8); + volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32); + *use_vddioh_reg |= cfg->mask << (startbit % 32); +} + +/******************************************************************************/ +void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg) +{ + + if(cfg->clk == CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR) + { + /*enable nanoring in run mode */ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN); + } + else if(cfg->clk == CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR) + { + /*enabled RTC in run mode */ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN); + } + + if(wdt == MXC_WDT0) { + /*select clock source */ + CLKMAN_WdtClkSelect(0, cfg->clk); + + /*Set scale of clock (only used for system clock as source) */ + CLKMAN_SetClkScale(CLKMAN_CLK_WDT0, cfg->clk_scale); + + /*Enable clock */ + CLKMAN_ClockGate(CLKMAN_WDT0_CLOCK, 1); + } else if (wdt == MXC_WDT1) { + /*select clock source */ + CLKMAN_WdtClkSelect(1, cfg->clk); + + /*Set scale of clock (only used for system clock as source) */ + CLKMAN_SetClkScale(CLKMAN_CLK_WDT1, cfg->clk_scale); + + /*Enable clock */ + CLKMAN_ClockGate(CLKMAN_WDT1_CLOCK, 1); + } +} + +/******************************************************************************/ +void SYS_PRNG_Init(void) +{ + /* Start crypto ring, unconditionally */ + CLKMAN_CryptoClockEnable(1); + + /* If we find the dividers in anything other than off, don't touch them */ + if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_PRNG) == CLKMAN_SCALE_DISABLED) { + /* Div 1 mode */ + CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_PRNG, CLKMAN_SCALE_DIV_1); + } + + if (CLKMAN_GetClkScale(CLKMAN_CLK_PRNG) == CLKMAN_SCALE_DISABLED) { + /* Div 1 mode */ + CLKMAN_SetClkScale(CLKMAN_CLK_PRNG, CLKMAN_SCALE_DIV_1); + } +} + +/******************************************************************************/ +void SYS_MAA_Init(void) +{ + /* Start crypto ring, unconditionally */ + CLKMAN_CryptoClockEnable(1); + + /* If we find the dividers in anything other than off, don't touch them */ + if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_MAA) == CLKMAN_SCALE_DISABLED) { + /* Div 1 mode */ + CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_MAA, CLKMAN_SCALE_DIV_1); + } +} + +/******************************************************************************/ +uint32_t SYS_SRAM_GetSize(void) +{ + uint32_t memSize; + + /* Read TRIM value*/ + int SRAMtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_SRAM) >> MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS; + + /* Decode trim value into memory size in bytes */ + switch(SRAMtrim) + { + case MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE: + memSize = (MXC_SRAM_FULL_MEM_SIZE >> 2) * 3; + break; + + case MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE: + memSize = MXC_SRAM_FULL_MEM_SIZE >> 1; + break; + + default: /* other values are FULL size */ + memSize = MXC_SRAM_FULL_MEM_SIZE; + break; + } + + /* Returns size in bytes */ + return memSize; +} + +/******************************************************************************/ +uint32_t SYS_FLASH_GetSize(void) +{ + uint32_t memSize; + + /* Read TRIM value */ + int FLASHtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_FLASH) >> MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS; + + /* Decode trim value into memory size in bytes*/ + switch(FLASHtrim) + { + case MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE: + memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2) * 3; + break; + case MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE: + memSize = (MXC_FLASH_FULL_MEM_SIZE >> 1); + break; + case MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE: + memSize = (MXC_FLASH_FULL_MEM_SIZE >> 3) * 3; + break; + case MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE: + memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2); + break; + default: /* other values are FULL size */ + memSize = MXC_FLASH_FULL_MEM_SIZE; + break; + } + + /* Returns size in bytes */ + return memSize; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h new file mode 100644 index 00000000000..05babf66c9c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h @@ -0,0 +1,496 @@ +/** + * @file mxc_sys.h + * @brief Registers, Bit Masks and Bit Positions for the System Clock Management module. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-08-24 18:33:23 -0500 (Wed, 24 Aug 2016) $ + * $Revision: 24159 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_SYS_H_ +#define _MXC_SYS_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "clkman.h" +#include "ioman.h" +#include "gpio.h" +#include "i2cm_regs.h" +#include "i2cs_regs.h" +#include "tmr_regs.h" +#include "pt_regs.h" +#include "wdt_regs.h" +#include "owm_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sys_cfg System Configuration + * @ingroup sysconfig + * @brief Configuration objects and functions for configuration of the system and peripherals. + * @{ + */ + +/* **** Definitions **** */ + +/** + * Structure type for System Configuration. + */ +typedef struct { + clkman_scale_t clk_scale; /**< Desired clock scale value for the peripheral */ + ioman_cfg_t io_cfg; /**< IOMAN configuration object */ +} sys_cfg_t; + +/** + * Structure type for Watchdog System Configuration. + * @ingroup wdt + * @{ + */ +typedef struct { + clkman_wdt_clk_select_t clk; /**< Select the clock source for the watchdog */ + clkman_scale_t clk_scale; /**< Desired clock scale value for the peripheral. @note clk_scale is only applied if the system clock is used as the clk. */ +} sys_cfg_wdt_t; +/**@}*/ + +/** + * Structure type for UART System Configuration. + * @ingroup uart + */ +typedef sys_cfg_t sys_cfg_uart_t; + +/** + * Structure type for I2CM System Configuration. + * @ingroup i2cm + */ +typedef sys_cfg_t sys_cfg_i2cm_t; + +/** + * Structure type for I2CS System Configuration. + * @ingroup i2cs + */ +typedef sys_cfg_t sys_cfg_i2cs_t; + +/** + * Structure type for SPIM System Configuration. + * @ingroup spim + */ +typedef sys_cfg_t sys_cfg_spim_t; + +/** + * Structure type for SPIX System Configuration. + * @ingroup spix + */ +typedef sys_cfg_t sys_cfg_spix_t; + +/** + * Structure type for OWM System Configuration. + * @ingroup owm + */ +typedef sys_cfg_t sys_cfg_owm_t; + +/** + * Structure type for Timer System Configuration. + * @ingroup timer + */ +typedef gpio_cfg_t sys_cfg_tmr_t; + +/** + * Structure type for Pulse Train System Configuration. + * @ingroup pulsetrain + */ +typedef gpio_cfg_t sys_cfg_pt_t; + +/** + * Structure type for Pulse Train Clock Scale Configuration. + * @ingroup clkman + * @ingroup pulsetrain + */ +typedef clkman_scale_t sys_pt_clk_scale; + +/* **** Include Files **** */ +/* These includes require the above types to be defined first */ +#include "uart.h" +#include "spim.h" + + +/* **** Function Prototypes **** */ + +/** + * @brief Get the frequency of a clock scaler + * @param clk_scale value of SYSTEM_SOURCE_SELECT field of \ref clkman_clk_ctrl register + * @return frequency in Hz + */ +uint32_t SYS_GetFreq(uint32_t clk_scale); + +/** + * @brief Get the frequency of the CPU + * @return frequency in Hz + */ +uint32_t SYS_CPU_GetFreq(void); + +/** + * @brief System level initialization for the ADC module. + * @return #E_NO_ERROR if everything is successful + * @ingroup adc + */ +int SYS_ADC_Init(void); + +/** + * @brief System level initialization for the AES module. + * @return #E_NO_ERROR if everything is successful + * @ingroup aes + */ +int SYS_AES_Init(void); + +/** + * @brief System level initialization for the GPIO module. + * @return #E_NO_ERROR if everything is successful + * @ingroup gpio + */ +int SYS_GPIO_Init(void); + +/** + * @brief System level initialization for the UART module. + * @param uart Pointer to UART module registers + * @param uart_cfg UART configuration object + * @param sys_cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup uart + */ +int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg); + +/** + * @brief System level shutdown for UART module + * @param uart Pointer to UART module registers + * @return #E_NO_ERROR if everything is successful + * @ingroup uart + */ +int SYS_UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief Get the frequency of the UART module source clock + * @param uart Pointer to UART module registers + * @return frequency in Hz + * @ingroup uart + */ +uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart); + +/** + * @brief System level initialization for I2CM module. + * @param i2cm Pointer to I2CM module registers + * @param cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup i2cm + */ +int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg); + +/** + * @brief System level shutdown for I2CM module + * @param i2cm Pointer to I2CM module registers + * @return #E_NO_ERROR if everything is successful + * @ingroup i2cm + */ +int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm); + +/** + * @brief Get the frequency of the I2CM module source clock + * @param i2cm Pointer to I2CM module registers + * @return frequency in Hz + * @ingroup i2cm + */ +uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm); + +/** + * @brief System level initialization for I2CS module. + * @param i2cs Pointer to I2CS module registers + * @param cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup i2cs + */ +int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg); + +/** + * @brief System level shutdown for I2CS module + * @param i2cs Pointer to I2CS module registers + * @return #E_NO_ERROR if everything is successful + * @ingroup i2cs + */ +int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs); + +/** + * @brief Get the frequency of the I2CS module source clock + * @param i2cs Pointer to I2CS module registers + * @return frequency in Hz + * @ingroup i2cs + */ +uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs); + +/** + * @brief System level initialization for SPIM module. + * @param spim Pointer to SPIM module registers + * @param spim_cfg SPIM configuration object + * @param sys_cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup spim + */ +int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg); + +/** + * @brief System level shutdown for SPIM module + * @param spim Pointer to SPIM module registers + * @return #E_NO_ERROR if everything is successful + * @ingroup spim + */ +int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim); + +/** + * @brief Get the frequency of the SPIM module source clock + * @param spim Pointer to SPIM module registers + * @return frequency in Hz + * @ingroup spim + */ +uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim); + +/** + * @brief System level initialization for SPIX module. + * @param sys_cfg System configuration object + * @param baud Baud rate for clock divider configuration + * @return #E_NO_ERROR if everything is successful + * @ingroup spix + */ +int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud); + +/** + * @brief System level shutdown for SPIX module + * @return #E_NO_ERROR if everything is successful + * @ingroup spix + */ +int SYS_SPIX_Shutdown(); + +/** + * @brief Get the frequency of the SPIX module source clock + * @return frequency in Hz + * @ingroup spix + */ +uint32_t SYS_SPIX_GetFreq(); + +/** + * @brief System level initialization for OWM module. + * @param owm Pointer to OWM module registers + * @param sys_cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup owm + */ +int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg); + +/** + * @brief System level shutdown for OWM module + * @param owm Pointer to OWM module registers + * @return #E_NO_ERROR if everything is successful + * @ingroup owm + */ +int SYS_OWM_Shutdown(mxc_owm_regs_t *owm); + +/** + * @brief Get the frequency of the OWM module source clock + * @param owm Pointer to OWM module registers + * @return frequency in Hz + * @ingroup owm + */ +uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm); + +/** + * @brief System level initialization for TMR module. + * @param tmr Pointer to TMR module registers + * @param cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup timer + */ +int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg); + +/** + * @brief Get the frequency of the TMR module source clock + * @param tmr Pointer to TMR module registers + * @return frequency in Hz + * @ingroup timer + */ +uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the frequency of the Pulse Train module source clock + * @return frequency in Hz + * @ingroup pulsetrain + */ +uint32_t SYS_PT_GetFreq(void); + +/** + * @brief Initialize the global pulse train clock scale + * @param clk_scale scale the system clock for the PT clock + * @ingroup pulsetrain + */ +void SYS_PT_Init(sys_pt_clk_scale clk_scale); + +/** + * @brief System level initialization for Pulse Train module. + * @param pt Pointer to PT module registers + * @param cfg System configuration object + * @return #E_NO_ERROR if everything is successful + * @ingroup pulsetrain + */ +int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg); + +/** + * @brief System level initialization for USB device. + * @param enable 1 to enable the peripheral, 0 to disable. + * @ingroup usb + */ +void SYS_USB_Enable(uint8_t enable); + +/** + * @brief System Tick Configuration Helper + * + * The function enables selection of the external clock source for + * the System Tick Timer. It initializes the System Timer and its + * interrupt, and starts the System Tick Timer. Counter is in free + * running mode to generate periodic interrupts. + * + * @param ticks Number of ticks between two interrupts. + * @param clk_src Selects between default SystemClock or External Clock. + * - 0 Use external clock source + * - 1 SystemClock + * @return #E_NO_ERROR Function succeeded. + * @return #E_INVALID Invalid reload value requested. + * + * See CLKMAN_SetRTOSMode(uint8_t enable) if using the external + * clock source to drive the System Tick Timer + */ +int SYS_SysTick_Config(uint32_t ticks, int clk_src); + +/** + * @brief Disable System Tick timer + */ +__STATIC_INLINE void SYS_SysTick_Disable(void) +{ + SysTick->CTRL = 0; +} + +/** + * @brief Delay a requested number of SysTick Timer Ticks. + * @param ticks Number of System Ticks to delay. + * @note This delay function is based on the clock used for the SysTick + * timer if the SysTick timer is enabled. If the SysTick timer is + * not enabled, the current SysTick registers are saved and the + * timer will use the SystemClock as the source for the delay. The + * delay is measured in clock ticks and is not based on the SysTick + * interval. + * @return #E_NO_ERROR if everything is successful + */ +int SYS_SysTick_Delay(uint32_t ticks); + +/** + * @brief Get the frequency of the SysTick Timer + * @return frequency in Hz + */ +uint32_t SYS_SysTick_GetFreq(void); + +/** + * @brief Delay a requested number of microseconds. + * @param us Number of microseconds to delay. + * @note Calls SYS_SysTick_Delay(). + */ +__STATIC_INLINE void SYS_SysTick_DelayUs(uint32_t us) +{ + SYS_SysTick_Delay((uint32_t)(((uint64_t)SYS_SysTick_GetFreq() * us) / 1000000)); +} + +/** + * @brief System level initialization for RTC module. + * @return #E_NO_ERROR if everything is successful + */ +int SYS_RTC_Init(void); + +/** + * @brief Select VDDIO for the specified GPIO pin. + * @ingroup gpio + */ +void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg); + +/** + * @brief Select VDDIOH for the specified GPIO pin. + */ +void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg); + +/** + * @brief System level initialization for Watchdog module. + * @param wdt Pointer to Watchdog module registers + * @param cfg Watchdog System configuration object + * @ingroup wdt + */ +void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg); + +/** + * @brief System level initialization for PRNG module. Enable crypto clock + * and set divisors to 1 if disabled + */ +void SYS_PRNG_Init(void); + +/** + * @brief System level initialization for MAA module. Enable crypto clock + * and set divisors to 1 if disabled + * @ingroup maa + */ +void SYS_MAA_Init(void); + +/** + * @brief Gets the size of the SRAM + * @return size of SRAM in bytes + */ +uint32_t SYS_SRAM_GetSize(void); + +/** + * @brief Gets the size of the Flash + * @return size of Flash in bytes + */ +uint32_t SYS_FLASH_GetSize(void); + +/**@} end of group sys_cfg */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SYS_H_*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c new file mode 100644 index 00000000000..098e953b54e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c @@ -0,0 +1,93 @@ +/** + * @file + * @brief This file contains the implementations of the vendor + * defined NVIC function. + * + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-28 10:27:00 -0500 (Wed, 28 Sep 2016) $ + * $Revision: 24512 $ + * + *************************************************************************** */ + +/** + * @ingroup mxc_nvic + * @{ + */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include +#include "nvic_table.h" + +/* RAM vector_table needs to be aligned with the size of the vector table */ +/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */ +/* Vector Table Offset which requires the next-power-of-two alignment. This */ +/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */ +#if defined ( __ICCARM__ ) +#pragma data_alignment = 512 +#define __isr_vector __vector_table +#else +__attribute__ ((aligned (512))) +#endif +static void (*ramVectorTable[MXC_IRQ_COUNT])(void); + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************* */ +void NVIC_SetRAM(void) +{ + memcpy(&ramVectorTable, (uint32_t*)SCB->VTOR, sizeof(ramVectorTable)); + SCB->VTOR = (uint32_t)&ramVectorTable; +} + +/* ************************************************************************* */ +int NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void)) +{ + int index = irqn + 16; /* offset for externals */ + + /* If not copied, do copy */ + if(SCB->VTOR != (uint32_t)&ramVectorTable) { + NVIC_SetRAM(); + } + + ramVectorTable[index] = irq_handler; + NVIC_EnableIRQ(irqn); + + return 0; +} +/**@} end of group mxc_nvic */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h new file mode 100644 index 00000000000..5e7daa9c207 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h @@ -0,0 +1,88 @@ +/** + * @file + * @brief NVIC utility function and type declarations. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-09 12:24:40 -0500 (Fri, 09 Sep 2016) $ + * $Revision: 24344 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _NVIC_TABLE_H +#define _NVIC_TABLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mxc_nvic NVIC Functions + * @ingroup sysconfig + * @brief Utility function for setting an IRQ handler dynamically + * @{ + */ + +/** + * @brief Type alias for an IRQ handler. + * @details Type alias for an IRQ handler function with prototype:. + * @code + * void irq_handler(void); + * @endcode + * + */ +typedef void (*irq_fn)(void); + +/** + * @brief Set an IRQ hander function for an IRQ specified by @p irqn. + * @details If the IRQ table is in flash, this function will copy the IRQ table to RAM. + * + * @param irqn ARM external IRQ number, see #IRQn_Type + * @param irq_handler Function to be called at IRQ context + */ +int NVIC_SetVector(IRQn_Type irqn, irq_fn irq_handler); + +/** + * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. + * + */ +void NVIC_SetRAM(void); + +/**@} end of group mxc_nvic */ + +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_TABLE_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.c new file mode 100644 index 00000000000..13de401c726 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.c @@ -0,0 +1,639 @@ +/** + * @file + * @brief 1-Wire Master (OWM) API Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-14 10:08:53 -0500 (Mon, 14 Mar 2016) $ + * $Revision: 21855 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "owm.h" + +/** + * @ingroup owm + * @{ + */ +///@cond +/* **** Definitions **** */ +#define OWM_CLK_FREQ 1000000 //1-Wire requires 1MHz clock + +/* **** Globals **** */ +int LastDiscrepancy; +int LastDeviceFlag; + +/* **** Functions **** */ +static uint8_t CalculateCRC8(uint8_t* data, int len); +static uint8_t update_crc8(uint8_t crc, uint8_t value); +///@endcond + + +/* ************************************************************************* */ +int OWM_Init(mxc_owm_regs_t *owm, const owm_cfg_t *cfg, const sys_cfg_owm_t *sys_cfg) +{ + int err = 0; + uint32_t owm_clk, clk_div = 0; + uint32_t ext_pu_mode = 0; + uint32_t ext_pu_polarity = 0; + + // Check the OWM register pointer is valid + MXC_ASSERT(MXC_OWM_GET_IDX(owm) >= 0); + + if(cfg == NULL) { + return E_NULL_PTR; + } + + // Set system level configurations + if ((err = SYS_OWM_Init(owm, sys_cfg)) != E_NO_ERROR) { + return err; + } + + // Configure clk divisor to get 1MHz OWM clk + owm_clk = SYS_OWM_GetFreq(owm); + + if(owm_clk == 0) { + return E_UNINITIALIZED; + } + + // Return error if clk doesn't divide evenly to 1MHz + if(owm_clk % OWM_CLK_FREQ) { + return E_NOT_SUPPORTED; + } + + clk_div = (owm_clk / (OWM_CLK_FREQ)); + + // Can not support lower frequencies + if(clk_div == 0) { + return E_NOT_SUPPORTED; + } + + // Select the PU mode and polarity based on cfg input + switch(cfg->ext_pu_mode) + { + case OWM_EXT_PU_ACT_HIGH: + ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED; + ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH; + break; + case OWM_EXT_PU_ACT_LOW: + ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED; + ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW; + break; + case OWM_EXT_PU_UNUSED: + ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED; + ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH; + break; + default: + return E_BAD_PARAM; + } + + // Set clk divisor + owm->clk_div_1us = (clk_div << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS) & MXC_F_OWM_CLK_DIV_1US_DIVISOR; + + // Set configuration + owm->cfg = (((cfg->int_pu_en << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS) & MXC_F_OWM_CFG_INT_PULLUP_ENABLE) | + ((ext_pu_mode << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS) & MXC_F_OWM_CFG_EXT_PULLUP_MODE) | + ((cfg->long_line_mode << MXC_F_OWM_CFG_LONG_LINE_MODE) & MXC_F_OWM_CFG_LONG_LINE_MODE_POS)); + + owm->ctrl_stat = (((ext_pu_polarity << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS) & MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL) | + ((cfg->overdrive_spec << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS) & MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE)); + + // Clear all interrupt flags + owm->intfl = owm->intfl; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int OWM_Shutdown(mxc_owm_regs_t *owm) +{ + int err; + + // Disable and clear interrupts + owm->inten = 0; + owm->intfl = owm->intfl; + + // Release IO pins and disable clk + if ((err = SYS_OWM_Shutdown(owm)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int OWM_Reset(mxc_owm_regs_t *owm) +{ + owm->intfl = MXC_F_OWM_INTFL_OW_RESET_DONE; // Clear the reset flag + owm->ctrl_stat |= MXC_F_OWM_CTRL_STAT_START_OW_RESET; // Generate a reset pulse + while((owm->intfl & MXC_F_OWM_INTFL_OW_RESET_DONE) == 0); // Wait for reset time slot to complete + + return (!!(owm->ctrl_stat & MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT)); // Return presence pulse detect status +} + +/* ************************************************************************* */ +int OWM_TouchByte(mxc_owm_regs_t *owm, uint8_t data) +{ + owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode + owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY); // Clear the flags + owm->data = (data << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data + while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent + while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read + + return (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & 0xFF; // Return the data read +} + +/* ************************************************************************* */ +int OWM_WriteByte(mxc_owm_regs_t *owm, uint8_t data) +{ + // Send one byte of data and verify the data sent = data parameter + return (OWM_TouchByte(owm, data) == data) ? E_NO_ERROR : E_COMM_ERR; +} + +/* ************************************************************************* */ +int OWM_ReadByte(mxc_owm_regs_t *owm) +{ + // Read one byte of data + return OWM_TouchByte(owm, 0xFF); +} + +/* ************************************************************************* */ +int OWM_TouchBit(mxc_owm_regs_t *owm, uint8_t bit) +{ + MXC_OWM->cfg |= MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 1 bit mode + owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY); // Clear the flags + owm->data = (bit << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data + while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent + while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read + + return (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & 0x1; // Return the bit read +} + +/* ************************************************************************* */ +int OWM_WriteBit(mxc_owm_regs_t *owm, uint8_t bit) +{ + // Send a bit and verify the bit sent = bit parameter + return (OWM_TouchBit(owm, bit) == bit) ? E_NO_ERROR : E_COMM_ERR; +} + +/* ************************************************************************* */ +int OWM_ReadBit(mxc_owm_regs_t *owm) +{ + // Read a bit + return OWM_TouchBit(owm, 1); +} + +/* ************************************************************************* */ +int OWM_Write(mxc_owm_regs_t *owm, uint8_t* data, int len) +{ + int num = 0; + + owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode + + while(num < len) // Loop for number of bytes to write + { + owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY | MXC_F_OWM_INTEN_LINE_SHORT); // Clear the flags + owm->data = (data[num] << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data + while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent + while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read + + // Verify data sent is correct + if(owm->data != data[num]) { + return E_COMM_ERR; + } + + // Check error flag + if(owm->intfl & MXC_F_OWM_INTEN_LINE_SHORT) { + return E_COMM_ERR; // Wire was low before transaction + } + + num++; // Keep track of how many bytes written + } + + return num; // Return number of bytes written +} + +/* ************************************************************************* */ +int OWM_Read(mxc_owm_regs_t *owm, uint8_t* data, int len) +{ + int num = 0; + + owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode + + while(num < len) // Loop for number of bytes to read + { + owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY | MXC_F_OWM_INTEN_LINE_SHORT); // Clear the flags + owm->data = 0xFF; // Write 0xFF for a read + while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent + while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read + + // Check error flag + if(owm->intfl & MXC_F_OWM_INTEN_LINE_SHORT) { + return E_COMM_ERR; // Wire was low before transaction + } + + // Store read data into buffer + data[num] = (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; + + num++; // Keep track of how many bytes read + } + + return num; // Return number of bytes read +} + +/* ************************************************************************* */ +int OWM_ReadROM(mxc_owm_regs_t *owm, uint8_t* ROMCode) +{ + int num_read = 0; + + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send Read ROM command code + if(OWM_WriteByte(owm, READ_ROM_COMMAND) == E_NO_ERROR) + { + // Read 8 bytes and store in buffer + num_read = OWM_Read(owm, ROMCode, 8); + + // Check the number of bytes read + if(num_read != 8) { + return E_COMM_ERR; + } + } + else + { + // Write failed + return E_COMM_ERR; + } + } + else + { + // No presence pulse + return E_COMM_ERR; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int OWM_MatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode) +{ + int num_wrote = 0; + + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send match ROM command code + if(OWM_WriteByte(owm, MATCH_ROM_COMMAND) == E_NO_ERROR) + { + // Write 8 bytes in ROMCode buffer + num_wrote = OWM_Write(owm, ROMCode, 8); + + // Check the number of bytes written + if(num_wrote != 8) { + return E_COMM_ERR; + } + } + else + { + // Write failed + return E_COMM_ERR; + } + } + else + { + // No presence pulse + return E_COMM_ERR; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int OWM_ODMatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode) +{ + int num_wrote = 0; + + // Set to standard speed + owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE); + + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send Overdrive match ROM command code + if(OWM_WriteByte(owm, OD_MATCH_ROM_COMMAND) == E_NO_ERROR) + { + // Set overdrive + owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE; + + // Write 8 bytes in ROMCode buffer + num_wrote = OWM_Write(owm, ROMCode, 8); + + // Check the number of bytes written + if(num_wrote != 8) { + return E_COMM_ERR; + } + } + else + { + // Write failed + return E_COMM_ERR; + } + } + else + { + // No presence pulse + return E_COMM_ERR; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int OWM_SkipROM(mxc_owm_regs_t *owm) +{ + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send skip ROM command code + return OWM_WriteByte(owm, SKIP_ROM_COMMAND); + } + else + { + // No presence pulse + return E_COMM_ERR; + } +} + +/* ************************************************************************* */ +int OWM_ODSkipROM(mxc_owm_regs_t *owm) +{ + // Set to standard speed + owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE); + + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send Overdrive skip ROM command code + if(OWM_WriteByte(owm, OD_SKIP_ROM_COMMAND) == E_NO_ERROR) + { + // Set overdrive speed + owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE; + + return E_NO_ERROR; + } + else + { + // Write failed + return E_COMM_ERR; + } + } + else + { + // No presence pulse + return E_COMM_ERR; + } +} + +/* ************************************************************************* */ +int OWM_Resume(mxc_owm_regs_t *owm) +{ + // Send reset and wait for presence pulse + if(OWM_Reset(owm)) + { + // Send resume command code + return OWM_WriteByte(owm, RESUME_COMMAND); + } + else + { + // No presence pulse + return E_COMM_ERR; + } +} + +/* ************************************************************************* */ +int OWM_SearchROM(mxc_owm_regs_t *owm, int newSearch, uint8_t* ROMCode) +{ + int nibble_start_bit = 1; + int rom_byte_number = 0; + uint8_t rom_nibble_mask = 0x0F; + uint8_t search_direction = 0; + int readValue = 0; + int sentBits = 0; + int discrepancy = 0; + int bit_position = 0; + int discrepancy_mask = 0; + int last_zero = 0; + uint8_t crc8 = 0; + int search_result = 0; + + // Clear ROM array + memset(ROMCode, 0x0, 8); + + if(newSearch) + { + // Reset all global variables to start search from begining + LastDiscrepancy = 0; + LastDeviceFlag = 0; + } + + // Check if the last call was the last device + if(LastDeviceFlag) + { + // Reset the search + LastDiscrepancy = 0; + LastDeviceFlag = 0; + return 0; + } + + // Send reset and wait for presence pulse + if (OWM_Reset(owm)) + { + // Send the search command + OWM_WriteByte(owm, SEARCH_ROM_COMMAND); + + // Set search ROM accelerator bit + owm->ctrl_stat |= MXC_F_OWM_CTRL_STAT_SRA_MODE; + + // Loop until through all ROM bytes 0-7 (this loops 2 times per byte) + while(rom_byte_number < 8) + { + // Each loop finds the discrepancy bits and finds 4 bits (nibble) of the ROM + + // Set the search direction the same as last time for the nibble masked + search_direction = ROMCode[rom_byte_number] & rom_nibble_mask; + + // If the upper nibble is the mask then shift bits to lower nibble + if(rom_nibble_mask > 0x0F) { + search_direction = search_direction >> 4; + } + + // Get the last discrepancy bit position relative to the nibble start bit + bit_position = LastDiscrepancy - nibble_start_bit; + + // Check if last discrepancy is witin this nibble + if( (bit_position >= 0) && (bit_position < 4) ) + { + // Last discrepancy is within this nibble + // Set the bit of the last discrepancy bit + search_direction |= (1 << (bit_position)); + } + + // Performs two read bits and a write bit for 4 bits of the ROM + readValue = OWM_TouchByte(owm, search_direction); + // Get discrepancy flags + discrepancy = readValue & 0xF; + // Get the 4 bits sent to select the ROM + sentBits = (readValue >> 4) & 0xF; + + // Store the bit location of the MSB discrepancy with sentbit = 0 + if(discrepancy) + { + // Initialize bit_position to MSB of nibble + bit_position = 3; + + while(bit_position >= 0) + { + // Get discrepancy flag of the current bit position + discrepancy_mask = discrepancy & (1 << bit_position); + + // If there is a discrepancy and the sent bit is 0 save this bit position + if( (discrepancy_mask) && !(sentBits & discrepancy_mask)) + { + last_zero = nibble_start_bit + bit_position; + break; + } + + bit_position--; + } + } + + // Clear the nibble + ROMCode[rom_byte_number] &= ~rom_nibble_mask; + + // Store the sentBits in the ROMCode + if(rom_nibble_mask > 0x0F) { + ROMCode[rom_byte_number] |= (sentBits << 4); + } + else { + ROMCode[rom_byte_number] |= sentBits; + } + + // Increment the nibble start bit and shift mask + nibble_start_bit += 4; + rom_nibble_mask <<= 4; + + // If the mask is 0 then go to new ROM byte rom_byte_number and reset mask + if (rom_nibble_mask == 0) + { + rom_byte_number++; + rom_nibble_mask = 0x0F; + } + + } // End while(rom_byte_number < 8) + + // Clear search ROM accelerator + owm->ctrl_stat &= ~(MXC_F_OWM_CTRL_STAT_SRA_MODE); + + // Calculate CRC to verify ROM code is correct + crc8 = CalculateCRC8(ROMCode, 7); + + // If the search was successful then + if ((nibble_start_bit >= 65) && (crc8 == ROMCode[7])) + { + // Search successful so set LastDiscrepancy,LastDeviceFlag,search_result + LastDiscrepancy = last_zero; + + // Check for last device + if (LastDiscrepancy == 0) { + LastDeviceFlag = 1; + } + + search_result = 1; + } + } // End if (OWM_Reset) + + // If no device found then reset counters so next 'search' will be like a first + if (!search_result || !ROMCode[0]) + { + LastDiscrepancy = 0; + LastDeviceFlag = 0; + search_result = 0; + } + + return search_result; +} + +/* + * Calcualate CRC8 of the buffer of data provided + */ +uint8_t CalculateCRC8(uint8_t* data, int len) +{ + int i; + uint8_t crc = 0; + + for(i = 0; i < len; i++) + { + crc = update_crc8(crc, data[i]); + } + + return crc; +} + +/* + * Calculate the CRC8 of the byte value provided with the current crc value + * provided Returns updated crc value + */ +uint8_t update_crc8(uint8_t crc, uint8_t val) +{ + uint8_t inc, tmp; + + for (inc = 0; inc < 8; inc++) + { + tmp = (uint8_t)(crc << 7); // Save X7 bit value + crc >>= 1; // Shift crc + if (((tmp >> 7) ^ (val & 0x01)) == 1) // If X7 xor X8 (input data) + { + crc ^= 0x8c; // XOR crc with X4 and X5, X1 = X7^X8 + crc |= 0x80; // Carry + } + val >>= 1; + } + + return crc; +} + +/**@} end of group owm */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.h new file mode 100644 index 00000000000..d6845e3b5fc --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.h @@ -0,0 +1,320 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the 1-Wire Master + * peripheral module. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-14 10:08:53 -0500 (Mon, 14 Mar 2016) $ + * $Revision: 21855 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _OWM_H_ +#define _OWM_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "owm_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup owm 1-Wire Master (OWM) + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type for 1-Wire Overdrive Speed Options. + */ +typedef enum { + OWM_OVERDRIVE_UNUSED = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US, /**< 12us Overdrive Speed Select. */ + OWM_OVERDRIVE_12US = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US, /**< 12us Overdrive Speed Select. */ + OWM_OVERDRIVE_10US = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US /**< 10us Overdrive Speed Select. */ +} owm_overdrive_t; + +/** + * Enumeration type for specifying options for 1-Wire external pullup mode. + */ +typedef enum { + OWM_EXT_PU_ACT_HIGH = 0, /**< Pullup pin is active high when enabled. */ + OWM_EXT_PU_ACT_LOW = 1, /**< Pullup pin is active low when enabled. */ + OWM_EXT_PU_UNUSED = 2, /**< Pullup pin is not used for an external pullup. */ +} owm_ext_pu_t; + +/** + * Structure type for 1-Wire Master configuration. + */ +typedef struct { + uint8_t int_pu_en; /**< 1 = internal pullup on. */ + owm_ext_pu_t ext_pu_mode; /**< See #owm_ext_pu_t. */ + uint8_t long_line_mode; /**< 1 = long line mode enable. */ + owm_overdrive_t overdrive_spec; /**< 0 = timeslot is 12us, 1 = timeslot is 10us. */ +} owm_cfg_t; + + +#define READ_ROM_COMMAND 0x33 /**< Read ROM Command */ +#define MATCH_ROM_COMMAND 0x55 /**< Match ROM Command */ +#define SEARCH_ROM_COMMAND 0xF0 /**< Search ROM Command */ +#define SKIP_ROM_COMMAND 0xCC /**< Skip ROM Command */ +#define OD_SKIP_ROM_COMMAND 0x3C /**< Overdrive Skip ROM Command */ +#define OD_MATCH_ROM_COMMAND 0x69 /**< Overdrive Match ROM Command */ +#define RESUME_COMMAND 0xA5 /**< Resume Command */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize and enable OWM module. + * @param owm Pointer to OWM regs. + * @param cfg Pointer to OWM configuration. + * @param sys_cfg Pointer to system configuration object + * + * @retval #E_NO_ERROR if everything is successful + * @retval #E_NULL_PTR if parameter is a null pointer + * @retval #E_BUSY if IOMAN was not configured correctly + * @retval #E_UNINITIALIZED if OWM CLK disabled + * @retval #E_NOT_SUPPORTED if 1MHz CLK cannot be created with given system and owm CLK + * @retval #E_BAD_PARAM if bad cfg parameter passed in + */ +int OWM_Init(mxc_owm_regs_t *owm, const owm_cfg_t *cfg, const sys_cfg_owm_t *sys_cfg); + +/** + * @brief Shutdown OWM module. + * @param owm Pointer to OWM regs. + * @retval #E_NO_ERROR if everything is successful + * @retval #E_BUSY if IOMAN was not released + */ +int OWM_Shutdown(mxc_owm_regs_t *owm); + +/** + * @brief Send 1-Wire reset pulse. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @retval (0) = no presence pulse detected, (1) = presence pulse detected + */ +int OWM_Reset(mxc_owm_regs_t *owm); + +/** + * @brief Send and receive one byte of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param data data to send + * @retval data read (1 byte) + */ +int OWM_TouchByte(mxc_owm_regs_t *owm, uint8_t data); + +/** + * @brief Write one byte of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param data data to send + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if data written != data parameter + */ +int OWM_WriteByte(mxc_owm_regs_t *owm, uint8_t data); + +/** + * @brief Read one byte of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @retval data read (1 byte) + */ +int OWM_ReadByte(mxc_owm_regs_t *owm); + +/** + * @brief Send and receive one bit of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param bit bit to send + * @retval bit read + */ +int OWM_TouchBit(mxc_owm_regs_t *owm, uint8_t bit); + +/** + * @brief Write one bit of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param bit bit to send + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if bit written != bit parameter + */ +int OWM_WriteBit(mxc_owm_regs_t *owm, uint8_t bit); + +/** + * @brief Read one bit of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @retval bit read + */ +int OWM_ReadBit(mxc_owm_regs_t *owm); + +/** + * @brief Write multiple bytes of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param data Pointer to buffer for write data. + * @param len Number of bytes to write. + * + * @retval Number of bytes written if successful + * @retval #E_COMM_ERR if line short detected before transaction + */ +int OWM_Write(mxc_owm_regs_t *owm, uint8_t* data, int len); + +/** + * @brief Read multiple bytes of data. Will block until transaction is complete. + * @param owm Pointer to OWM regs. + * @param data Pointer to buffer for read data. + * @param len Number of bytes to read. + * + * @retval Number of bytes read if successful + * @retval #E_COMM_ERR if line short detected before transaction + */ +int OWM_Read(mxc_owm_regs_t *owm, uint8_t* data, int len); + +/** + * @brief Starts 1-Wire communication with Read ROM command + * @note Only use the Read ROM command with one slave on the bus + * @param owm Pointer to OWM regs. + * @param ROMCode Pointer to buffer for ROM code read + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset, read or write fails + */ +int OWM_ReadROM(mxc_owm_regs_t *owm, uint8_t* ROMCode); + +/** + * @brief Starts 1-Wire communication with Match ROM command + * @param owm Pointer to OWM regs. + * @param ROMCode Pointer to buffer with ROM code to match + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset or write fails + */ +int OWM_MatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode); + +/** + * @brief Starts 1-Wire communication with Overdrive Match ROM command + * @note After Overdrive Match ROM command is sent, the OWM is set to + * overdrive speed. To set back to standard speed use OWM_SetOverdrive. + * @param owm Pointer to OWM regs. + * @param ROMCode Pointer to buffer with ROM code to match + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset or write fails + */ +int OWM_ODMatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode); + +/** + * @brief Starts 1-Wire communication with Skip ROM command + * @param owm Pointer to OWM regs. + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset or write fails + */ +int OWM_SkipROM(mxc_owm_regs_t *owm); + +/** + * @brief Starts 1-Wire communication with Overdrive Skip ROM command + * @note After Overdrive Skip ROM command is sent, the OWM is set to + * overdrive speed. To set back to standard speed use OWM_SetOverdrive + * @param owm Pointer to OWM regs. + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset or write fails + */ +int OWM_ODSkipROM(mxc_owm_regs_t *owm); + +/** + * @brief Starts 1-Wire communication with Resume command + * @param owm Pointer to OWM regs. + * @retval #E_NO_ERROR if everything is successful + * @retval #E_COMM_ERR if reset or write fails + */ +int OWM_Resume(mxc_owm_regs_t *owm); + +/** + * @brief Starts 1-Wire communication with Search ROM command + * @param owm Pointer to OWM regs. + * @param newSearch (1) = start new search, (0) = continue search for next ROM + * @param ROMCode Pointer to buffer with ROM code found + * @retval (1) = ROM found, (0) = no new ROM found, end of search + */ +int OWM_SearchROM(mxc_owm_regs_t *owm, int newSearch, uint8_t* ROMCode); + +/** + * @brief Clear interrupt flags. + * @param owm Pointer to OWM regs. + * @param mask Mask of interrupts to clear. + */ +__STATIC_INLINE void OWM_ClearFlags(mxc_owm_regs_t *owm, uint32_t mask) +{ + owm->intfl = mask; +} + +/** + * @brief Get interrupt flags. + * @param owm Pointer to OWM regs. + * @retval Mask of active flags. + */ +__STATIC_INLINE unsigned OWM_GetFlags(mxc_owm_regs_t *owm) +{ + return (owm->intfl); +} + +/** + * @brief Enables/Disables the External pullup + * @param owm Pointer to OWM regs. + * @param enable (1) = enable, (0) = disable + */ +__STATIC_INLINE void OWM_SetExtPullup(mxc_owm_regs_t *owm, int enable) +{ + if(enable) + owm->cfg |= MXC_F_OWM_CFG_EXT_PULLUP_ENABLE; + else + owm->cfg &= ~(MXC_F_OWM_CFG_EXT_PULLUP_ENABLE); +} + +/** + * @brief Enables/Disables Overdrive speed + * @param owm Pointer to OWM regs. + * @param enable (1) = overdrive, (0) = standard + */ +__STATIC_INLINE void OWM_SetOverdrive(mxc_owm_regs_t *owm, int enable) +{ + if(enable) + owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE; + else + owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE); +} + +/**@} end of group owm */ +#ifdef __cplusplus +} +#endif + +#endif /* _OWM_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c new file mode 100644 index 00000000000..48ade2a3bc5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c @@ -0,0 +1,246 @@ +/** + * @file + * @brief Peripheral Management Unit (PMU) Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:44:03 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24328 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "pmu.h" +/** + * @ingroup pmuGroup + * @{ + */ + +#if (MXC_PMU_REV == 0) +/* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */ +#include "clkman_regs.h" +/* Channel 5 infinite loop program */ +static const uint32_t pmu_0[] = { + PMU_JUMP(0, 0, (uint32_t)pmu_0) +}; +#endif + +/* **** Local Function Prototypes **** */ +static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int); + + +/* ************************************************************************* */ +void PMU_Handler(void) +{ + int channel; + uint32_t cfg1, cfg2; + mxc_pmu_regs_t *MXC_PMUn; + + for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) { + MXC_PMUn = &MXC_PMU0[channel]; + + if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) { + cfg1 = MXC_PMUn->cfg; + /* Since any set flags will be cleared by the write-back below, mask them off */ + cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT); + + /* Clear the interrupt flag */ + MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT; + + if (callbacks[channel]) { + callbacks[channel](cfg1); + } + } + } +} + +/* ************************************************************************* */ +int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback) +{ + if(channel >= MXC_CFG_PMU_CHANNELS) + return E_BAD_PARAM; + + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + uint32_t cfg = MXC_PMUn->cfg; + + /* is this channel already running? */ + if (cfg & MXC_F_PMU_CFG_ENABLE) { + return E_BUSY; + } + +#if (MXC_PMU_REV == 0) + /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */ + if (channel == 5) { + /* Channel 5 is used for the work-around */ + return E_BUSY; + } + /* Select always-ON clock for PMU */ + MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER; + /* Start channel 5 with infinite-loop program */ + MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */ + MXC_PMU5->dscadr = (uint32_t)pmu_0; + MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS); +#endif + /* Set callback */ + callbacks[channel] = callback; + + /* Set start op-code */ + MXC_PMUn->dscadr = (uint32_t)program_address; + + /* Configure the channel */ + cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS); + + /* Enable if necessary */ + if (callback) { + cfg |= MXC_F_PMU_CFG_INT_EN; + } else { + cfg &= ~MXC_F_PMU_CFG_INT_EN; + } + + /* Start the channel */ + cfg |= MXC_F_PMU_CFG_ENABLE; + + /*If any W1C flags are set, this write will clear them */ + MXC_PMUn->cfg = cfg; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void PMU_Stop(unsigned int channel) +{ + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + uint32_t cfg = MXC_PMUn->cfg; + + /* Since any set flags will be cleared by the write-back below, mask them off */ + cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); + + /* Clear the enable bit to stop the channel */ + cfg &= ~MXC_F_PMU_CFG_ENABLE; + + MXC_PMUn->cfg = cfg; + + /* Remove callback */ + callbacks[channel] = NULL; + +#if (MXC_PMU_REV == 0) + /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */ + /* Check channels 0-4 for any running channels. If none found, stop channel 5 */ + if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && + (MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && + (MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && + (MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && + (MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) { + MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; + } +#endif + +} + +/* ************************************************************************* */ +int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value) +{ + if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1) + return E_BAD_PARAM; + + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + + if (counter == 0) { + MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS); + } else { + MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS); + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks) +{ + if(channel >= MXC_CFG_PMU_CHANNELS) + return E_BAD_PARAM; + + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + uint32_t cfg = MXC_PMUn->cfg; + + /* Since any set flags will be cleared by the write-back below, mask them off */ + cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); + + /* Adjust timeout settings */ + cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL); + cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) | + ((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL); + + MXC_PMUn->cfg = cfg; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +uint32_t PMU_GetFlags(unsigned int channel) +{ + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + uint32_t cfg = MXC_PMUn->cfg; + + /* Mask off configuration bits leaving only flag bits */ + cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL | + MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE); + + return cfg; +} + +/* ************************************************************************* */ +void PMU_ClearFlags(unsigned int channel, unsigned int mask) +{ + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + uint32_t cfg = MXC_PMUn->cfg; + + /* Since any set flags will be cleared by the write-back below, mask them off */ + cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); + + /* Now, apply the caller-supplied bits to clear */ + cfg |= mask; + + MXC_PMUn->cfg = cfg; +} + +/* ************************************************************************* */ +uint32_t PMU_IsActive(unsigned int channel) +{ + mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; + return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE); +} +/**@} end of ingroup pmuGroup */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h new file mode 100644 index 00000000000..f034aa8113d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h @@ -0,0 +1,299 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the PMU module. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24667 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _PMU_H_ +#define _PMU_H_ + +/* **** Includes **** */ +#include "pmu_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup pmuGroup Peripheral Management Unit + * @brief Peripheral Management Unit (PMU) Interface. + * @{ + */ + +/** + * Enum type for the clock scale used for the PMU timeout clock. + */ +typedef enum { + PMU_PS_SEL_DISABLE = MXC_V_PMU_CFG_PS_SEL_DISABLE, /**< Timeout disabled */ + PMU_PS_SEL_DIV_2_8 = MXC_V_PMU_CFG_PS_SEL_DIV_2_8, /**< Timeout clk = PMU clock / 2^8 = 256 */ + PMU_PS_SEL_DIV_2_16 = MXC_V_PMU_CFG_PS_SEL_DIV_2_16, /**< Timeout clk = PMU clock / 2^16 = 65536 */ + PMU_PS_SEL_DIV_2_24 = MXC_V_PMU_CFG_PS_SEL_DIV_2_24 /**< Timeout clk = PMU clock / 2^24 = 16777216 */ +}pmu_ps_sel_t; + +/** + * Enumeration type for the number of clk ticks for the timeout duration. + */ +typedef enum { + PMU_TO_SEL_TICKS_4 = MXC_V_PMU_CFG_TO_SEL_TICKS_4, /**< timeout = 4 * Timeout clk period */ + PMU_TO_SEL_TICKS_8 = MXC_V_PMU_CFG_TO_SEL_TICKS_8, /**< timeout = 8 * Timeout clk period */ + PMU_TO_SEL_TICKS_16 = MXC_V_PMU_CFG_TO_SEL_TICKS_16, /**< timeout = 16 * Timeout clk period */ + PMU_TO_SEL_TICKS_32 = MXC_V_PMU_CFG_TO_SEL_TICKS_32, /**< timeout = 32 * Timeout clk period */ + PMU_TO_SEL_TICKS_64 = MXC_V_PMU_CFG_TO_SEL_TICKS_64, /**< timeout = 64 * Timeout clk period */ + PMU_TO_SEL_TICKS_128 = MXC_V_PMU_CFG_TO_SEL_TICKS_128, /**< timeout = 128 * Timeout clk period */ + PMU_TO_SEL_TICKS_256 = MXC_V_PMU_CFG_TO_SEL_TICKS_256, /**< timeout = 256 * Timeout clk period */ + PMU_TO_SEL_TICKS_512 = MXC_V_PMU_CFG_TO_SEL_TICKS_512 /**< timeout = 512 * Timeout clk period */ +}pmu_to_sel_t; + +/* + * The macros like the one below are designed to help build static PMU programs + * as arrays of 32bit words. + */ +#define PMU_IS(interrupt, stop) ((!!interrupt) << PMU_INT_POS) | ((!!stop) << PMU_STOP_POS) +/* + * Structure type to build a PMU Move Op Code. + */ +typedef struct pmu_move_des_t { + uint32_t op_code : 3; /* 0x0 */ + uint32_t interrupt : 1; + uint32_t stop : 1; + uint32_t read_size : 2; + uint32_t read_inc : 1; + uint32_t write_size : 2; + uint32_t write_inc : 1; + uint32_t cont : 1; + uint32_t length : 20; + + uint32_t write_address; + uint32_t read_address; +} pmu_move_des_t; +#define PMU_MOVE(i, s, rs, ri, ws, wi, c, length, wa, ra) \ + (PMU_MOVE_OP | PMU_IS(i,s) | ((rs & 3) << PMU_MOVE_READS_POS) | ((!!ri) << PMU_MOVE_READI_POS) | \ + ((ws & 3) << PMU_MOVE_WRITES_POS) | ((!!wi) << PMU_MOVE_WRITEI_POS) | ((!!c) << PMU_MOVE_CONT_POS) | ((length & 0xFFFFF) << PMU_MOVE_LEN_POS)), wa, ra + +/* new_value = value | (old_value & ~ mask) */ +typedef struct pmu_write_des_t { + uint32_t op_code : 3; /* 0x1 */ + uint32_t interrupt : 1; + uint32_t stop : 1; + uint32_t : 3; + uint32_t write_method : 4; + uint32_t : 20; + + uint32_t write_address; + uint32_t value; + uint32_t mask; +} pmu_write_des_t; +#define PMU_WRITE(i, s, wm, a, v, m) (PMU_WRITE_OP | PMU_IS(i,s) | ((wm & 0xF) << PMU_WRITE_METHOD_POS)), a, v, m + +typedef struct pmu_wait_des_t { + uint32_t op_code : 3; /* 0x2 */ + uint32_t interrupt : 1; + uint32_t stop : 1; + uint32_t wait : 1; + uint32_t sel : 1; + uint32_t : 25; + + uint32_t mask1; + uint32_t mask2; + uint32_t wait_count; +} pmu_wait_des_t; +#define PMU_WAIT(i, s, sel, m1, m2, cnt) (PMU_WAIT_OP | PMU_IS(i,s) | ((cnt>0)?(1<user_entropy & MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY); +} + +/** + * @brief Retrieve a seed value from the PRNG. + * @note The PRNG hardware does not produce true random numbers. The + * output should be used as a seed to an approved random-number + * algorithm, per a certifying authority such as NIST or PCI. The + * approved algorithm will output random numbers which are cerfitied + * for use in encryption and authentication algorithms. + * + * @return 16-bit seed value + */ +__STATIC_INLINE uint16_t PRNG_GetSeed(void) +{ + return MXC_PRNG->rnd_num; +} + +/** + * @brief Add user entropy to the PRNG entropy source. + * + * @param entropy A value to be mixed into the PRNG entropy source. + */ +__STATIC_INLINE void PRNG_AddUserEntropy(uint8_t entropy) +{ + MXC_PRNG->user_entropy = (uint32_t)entropy; +} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _PRNG_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c new file mode 100644 index 00000000000..bb87dc6f523 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c @@ -0,0 +1,145 @@ +/** + * @file + * @brief Pulse Train Engine Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:43:36 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24327 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "pt.h" + +/** + * @ingroup pulsetrain + * @{ + */ + +/* ************************************************************************* */ +void PT_Init(sys_pt_clk_scale clk_scale) +{ + //disable all pulse trains + MXC_PTG->enable = 0; + + //clear all interrupts + MXC_PTG->intfl = MXC_PTG->intfl; + + SYS_PT_Init(clk_scale); +} + +/* ************************************************************************* */ +int PT_PTConfig(mxc_pt_regs_t *pt, pt_pt_cfg_t *cfg, const sys_cfg_pt_t *sysCfg) +{ + int err; + uint32_t ptClock; + uint32_t rate; + + //check for valid base pointer + MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0); + + if(cfg == NULL) + return E_NULL_PTR; + + if(cfg->bps == 0) + return E_BAD_PARAM; + + //disable pulse train + PT_Stop(pt); + + //setup system GPIO configuration + if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR) + return err; + + //get PT clock frequency from SYS level + ptClock = SYS_PT_GetFreq(); + + if(ptClock == 0) + return E_UNINITIALIZED; + + if(ptClock < (cfg->bps)) + return E_BAD_STATE; + + rate = (ptClock / (cfg->bps)); + + pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS) + & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) | + ((cfg->ptLength << MXC_F_PT_RATE_LENGTH_MODE_POS) + & MXC_F_PT_RATE_LENGTH_MODE); + + pt->train = cfg->pattern; + pt->loop = ((cfg->loop << MXC_F_PT_LOOP_COUNT_POS) & MXC_F_PT_LOOP_COUNT) | + ((cfg->loopDelay << MXC_F_PT_LOOP_DELAY_POS) & MXC_F_PT_LOOP_DELAY); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int PT_SqrWaveConfig(mxc_pt_regs_t *pt, uint32_t freq, const sys_cfg_pt_t *sysCfg) +{ + int err; + uint32_t ptClock; + uint32_t rate; + + //check for valid base pointer + MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0); + + if(freq == 0) + return E_BAD_PARAM; + + //disable pulse train + PT_Stop(pt); + + //setup system GPIO configuration + if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR) + return err; + + //get PT clock frequency from SYS level + ptClock = SYS_PT_GetFreq(); + + if(ptClock == 0) + return E_UNINITIALIZED; + + if(ptClock < (2*freq)) + return E_BAD_STATE; + + rate = (ptClock / (2*freq)) + 1; + + pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS) + & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) | + (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS); + + return E_NO_ERROR; +} +/**@} end of ingroup pulsetrain*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h new file mode 100644 index 00000000000..7857caee0b5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h @@ -0,0 +1,331 @@ +/** + * @file + * @brief Pulse Train data types, definitions and function prototypes. + */ + +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24669 $ + * + ***************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _PT_H_ +#define _PT_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "pt_regs.h" +#include "mxc_assert.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup pulsetrain Pulse Train Engine + * @brief This is the high level API for the pulse train engine. + * @{ + */ + +/** + * Structure type for pulse train mode configuration. + * @note Do not use for square wave + */ +typedef struct { + uint32_t bps; /**< pulse train bit rate */ + uint32_t pattern; /**< Output pattern to shift out, starts at LSB */ + uint8_t ptLength; /**< Number of bits in pulse train, 0 = 32bits, 1 = non valid , 2 = 2 bits, ... */ + uint16_t loop; /**< Number of times to repeat the train, 0 = continuous */ + uint16_t loopDelay; /**< Delay between loops specified in bits Example: loopDelay = 4, delays time = time it takes to shift out 4 bits */ +} pt_pt_cfg_t; + +/** + * @brief This function initializes the pulse trains to a known stopped + * state and sets the global PT clock scale. + * @param clk_scale Scale the system clock for the global PT clock. + */ +void PT_Init(sys_pt_clk_scale clk_scale); + +/** + * @brief Configures the pulse train in the specified mode. + * @details The parameters in the config structure must be set before calling + * this function. This function should be used for configuring pulse + * train mode only. + * @note The pulse train cannot be running when this function is called. + * + * @param pt Pulse train to operate on. + * @param cfg Pointer to pulse train configuration. + * @param sysCfg Pointer to pulse train system GPIO configuration. + * + * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes + * "error" if unsuccessful. + */ +int PT_PTConfig(mxc_pt_regs_t *pt, pt_pt_cfg_t *cfg, const sys_cfg_pt_t *sysCfg); + +/** + * @brief Configures the pulse train in the square wave mode. + * @details This function should be used for configuring square wave mode only. + * @note The pulse train cannot be running when this function is called + * + * @param pt pulse train to operate on + * @param freq square wave output frequency in Hz + * @param sysCfg pointer to pulse train system GPIO configuration + * + * @returns #E_NO_ERROR if everything is successful, \ref MXC_Error_Codes "error" if unsuccessful. + */ +int PT_SqrWaveConfig(mxc_pt_regs_t *pt, uint32_t freq, const sys_cfg_pt_t *sysCfg); + +/** + * @brief Starts the pulse train specified. + * + * @param pt Pulse train to operate on. + */ +__STATIC_INLINE void PT_Start(mxc_pt_regs_t *pt) +{ + int ptIndex = MXC_PT_GET_IDX(pt); + + MXC_PTG->enable |= (1 << ptIndex); + + //wait for PT to start + while( (MXC_PTG->enable & (1 << ptIndex)) == 0 ); +} + +/** + * @brief Start multiple pulse train modules together. + * + * @param pts Set the bits of pulse trains to start + * Bit0-\>pt0, Bit1-\>pt1... etc. + */ +__STATIC_INLINE void PT_StartMulti(uint32_t pts) +{ + MXC_PTG->enable |= pts; + + //wait for PTs to start + while( (MXC_PTG->enable & pts) != pts ); +} + +/** + * @brief Stops a pulse train. + * + * @param pt Pulse train to operate on. + */ +__STATIC_INLINE void PT_Stop(mxc_pt_regs_t *pt) +{ + int ptIndex = MXC_PT_GET_IDX(pt); + + MXC_PTG->enable &= ~(1 << ptIndex); +} + +/** + * @brief Stop multiple pulse trains together + * + * @param pts Set the bits of pulse trains to stop + * Bit0-\>pt0, Bit1-\>pt1... etc. + */ +__STATIC_INLINE void PT_StopMulti(uint32_t pts) +{ + MXC_PTG->enable &= ~(pts); +} + +/** + * @brief Determines if the pulse train is running. + * + * @param pt Pulse train to operate on. + * + * @return 0 Pulse train is off. + * @return \>0 Pulse train is on. + */ +__STATIC_INLINE uint32_t PT_IsActive(mxc_pt_regs_t *pt) +{ + int ptIndex = MXC_PT_GET_IDX(pt); + + return (!!(MXC_PTG->enable & (1 << ptIndex))); +} + +/** + * @brief Determines if the pulse trains selected are running + * + * @param pts Set the bits of pulse trains to check Bit0-\>pt0, + * Bit1-\>pt1... etc. + * + * @return 0 All pulse trains are off. + * @return \>0 At least one pulse train is on. + */ +__STATIC_INLINE uint32_t PT_IsActiveMulti(uint32_t pts) +{ + return (MXC_PTG->enable & pts); +} + +/** + * @brief Sets the pattern of the pulse train + * + * @param pt Pointer to pulse train to operate on + * @param pattern Output pattern. + * + */ +__STATIC_INLINE void PT_SetPattern(mxc_pt_regs_t *pt, uint32_t pattern) +{ + pt->train = pattern; +} + +/** + * @brief Enable pulse train interrupt. + * + * @param pt Pointer to pulse train to operate on. + */ +__STATIC_INLINE void PT_EnableINT(mxc_pt_regs_t *pt) +{ + int ptIndex = MXC_PT_GET_IDX(pt); + + MXC_PTG->inten |= (1 << ptIndex); +} + +/** + * @brief Enable interrupts for the pulse trains selected. + * + * @param pts Bit mask of which pulse trains to enable. Set the bit + * position of each pulse train to enable it. Bit0-\>pt0, + * Bit1-\>pt1... etc, 1 will enable the interrupt, 0 to leave + * a PT channel in its current state. + */ +__STATIC_INLINE void PT_EnableINTMulti(uint32_t pts) +{ + MXC_PTG->inten |= pts; +} + +/** + * @brief Disable pulse train interrupt. + * + * @param pt pulse train to operate on. + */ +__STATIC_INLINE void PT_DisableINT(mxc_pt_regs_t *pt) +{ + int ptIndex = MXC_PT_GET_IDX(pt); + + MXC_PTG->inten &= ~(1 << ptIndex); +} + +/** + * @brief Disable interrupts for the pulse trains selected. + * + * @param pts Bit mask of what pulse trains to disable. Set the bit + * position of each pulse train to disable it. Bit0-\>pt0, + * Bit1-\>pt1... etc, 1 will disable the interrupt, 0 to leave + * a PT channel in its current state. + */ +__STATIC_INLINE void PT_DisableINTMulti(uint32_t pts) +{ + MXC_PTG->inten &= ~pts; +} +/** + * @brief Gets the pulse trains's interrupt flags. + * + * @return The Pulse Train Interrupt Flags, \ref PT_INTFL_Register Register + * for details. + */ +__STATIC_INLINE uint32_t PT_GetFlags(void) +{ + return MXC_PTG->intfl; +} + +/** + * @brief Clears the pulse train's interrupt flag. + * + * @param mask bits to clear, see \ref PT_INTFL_Register Register for details. + */ +__STATIC_INLINE void PT_ClearFlags(uint32_t mask) +{ + MXC_PTG->intfl = mask; +} + +/** + * @brief Setup and enables a pulse train to restart after another pulse + * train has exited its loop. Each pulse train can have up to two + * restart triggers. + * + * @param ptToRestart pulse train to restart after @c ptStop ends. + * @param ptStop pulse train that stops and triggers @p ptToRestart + * to begin. + * @param restartIndex selects which restart trigger to set (0 or 1). + */ +__STATIC_INLINE void PT_SetRestart(mxc_pt_regs_t *ptToRestart, mxc_pt_regs_t *ptStop, uint8_t restartIndex) +{ + int ptStopIndex = MXC_PT_GET_IDX(ptStop); + + MXC_ASSERT(ptStopIndex >= 0); + + if(restartIndex) { + ptToRestart->restart |= (ptStopIndex << MXC_F_PT_RESTART_PT_Y_SELECT_POS) | + MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT; + } else { + ptToRestart->restart |= (ptStopIndex << MXC_F_PT_RESTART_PT_X_SELECT_POS) | + MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT; + } +} + +/** + * @brief Disable the restart for the specified pulse train + * + * @param ptToRestart pulse train to disable the restart + * @param restartIndex selects which restart trigger to disable (0 or 1) + */ +__STATIC_INLINE void PT_RestartDisable(mxc_pt_regs_t *ptToRestart, uint8_t restartIndex) +{ + if(restartIndex) + ptToRestart->restart &= ~MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT; + else + ptToRestart->restart &= ~MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT; +} + +/** + * @brief Resynchronize individual pulse trains together. Resync will stop + * those resync_pts; others will be still running + * + * @param resyncPts pulse train modules that need to be re-synced by bit + * number. Bit0-\>pt0, Bit1-\>pt1... etc. + */ +__STATIC_INLINE void PT_Resync(uint32_t resyncPts) +{ + MXC_PTG->resync = resyncPts; + while(MXC_PTG->resync); +} +/**@} end of group pulsetrains*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _PT_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c new file mode 100644 index 00000000000..dd0475fb046 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c @@ -0,0 +1,197 @@ +/** + * @file + * @brief Real-Time Clock Function Implementations. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:43:13 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24326 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include + +#include "rtc.h" +#include "mxc_assert.h" +#include "mxc_sys.h" + + /** + * @ingroup rtc + * @{ + */ +/* ************************************************************************* */ +int RTC_Init(const rtc_cfg_t *cfg) +{ + int err; + int i = 0; + + //init function -> validate configuration pointer is not NULL + if (cfg == NULL) + return E_NULL_PTR; + //check to make sure that the passed in parameters, prescaler mask and snooze, are valid + if ((cfg->prescalerMask > ((rtc_prescale_t)cfg->prescaler)) || (cfg->snoozeCount > MXC_F_RTC_SNZ_VAL_VALUE)) + return E_INVALID; + + // Set system level configurations + if ((err = SYS_RTC_Init()) != E_NO_ERROR) { + return err; + } + + //disable rtc + MXC_RTCTMR->ctrl &= ~(MXC_F_RTC_CTRL_ENABLE); + + //disable all interrupts + MXC_RTCTMR->inten = 0; + + //clear all interrupts + MXC_RTCTMR->flags = RTC_FLAGS_CLEAR_ALL; + + //reset starting count + MXC_RTCTMR->timer = 0; + + //set the compare registers to the values passed in + for(i = 0; i < RTC_NUM_COMPARE; i++) + MXC_RTCTMR->comp[i] = cfg->compareCount[i]; + + // set the prescaler + MXC_RTCTMR->prescale = cfg->prescaler; + // set the prescale mask, checked it for validity on entry + MXC_RTCTMR->prescale_mask = cfg->prescalerMask; + + //set snooze mode (rtc_snooze_t) + MXC_RTCTMR->ctrl &= (~MXC_F_RTC_CTRL_SNOOZE_ENABLE); + MXC_RTCTMR->ctrl |= (cfg->snoozeMode << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS); + + //set the snooze count. Checked for validity on entry. + MXC_RTCTMR->snz_val = (cfg->snoozeCount << MXC_F_RTC_SNZ_VAL_VALUE_POS) & MXC_F_RTC_SNZ_VAL_VALUE; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + //reset trim to defaults, trim disabled, trim faster override disabled + MXC_RTCTMR->trim_ctrl &= ~(MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R | MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R); + + //set trim slower control bit to 0, which is trim faster by default + MXC_RTCTMR->trim_value &= ~(MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int RTC_SetCompare(uint8_t compareIndex, uint32_t counts) +{ + //check for invalid index + if (compareIndex >= RTC_NUM_COMPARE) + return E_INVALID; + + MXC_RTCTMR->comp[compareIndex] = counts; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +uint32_t RTC_GetCompare(uint8_t compareIndex) +{ + //Debug Assert for Invalid Index + MXC_ASSERT(compareIndex < RTC_NUM_COMPARE); + //check for invalid index + if (compareIndex >= RTC_NUM_COMPARE) + return (uint32_t)(E_BAD_PARAM); /* Unsigned int, so if out of bounds we return 0xFFFFFFFD (-3) */ + + return MXC_RTCTMR->comp[compareIndex]; +} + +/* ************************************************************************* */ +int RTC_SetTrim(uint32_t trim, uint8_t trimSlow) +{ + // make sure rtc is disabled + if(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) + return E_BAD_STATE; // RTC is active, bad state + + // Can check against this because it starts at bit 0 in the register + // Need to check because too large of a value messes with the upper bits in + // the trim register. + if (trim > MXC_F_RTC_TRIM_VALUE_TRIM_VALUE) + return E_INVALID; + + // write the trim to the hardware trim_value register + MXC_RTCTMR->trim_value = (trim << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS) & MXC_F_RTC_TRIM_VALUE_TRIM_VALUE; + + if(trimSlow) + MXC_RTCTMR->trim_value |= MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL; + else + MXC_RTCTMR->trim_value &= ~MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +uint32_t RTC_GetTrim() +{ + return MXC_RTCTMR->trim_value; // return the register value for trim +} + +/* ************************************************************************* */ +int RTC_TrimEnable(void) +{ + // make sure rtc is disabled + if(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) + return E_BAD_STATE; // RTC is active, bad state + + MXC_RTCTMR->trim_ctrl = MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void RTC_TrimDisable(void) +{ + // clear the trim enable bit + MXC_RTCTMR->trim_ctrl &= ~MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + return; +} + +/**@} end of ingroup rtc*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h new file mode 100644 index 00000000000..e173948fb3c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h @@ -0,0 +1,476 @@ +/** + * @file + * @brief Real-Time Clock data types, definitions and function prototypes. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24670 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _RTC_H_ +#define _RTC_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "rtc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup rtc Real-Time Clock (RTC) + * @brief Functions, types, and registers for the Real-Time Clock Peripheral. + * @{ + */ + +/* **** Definitions **** */ +/** + * Enumeration type for scaling down the 4096Hz input clock to the RTC. + */ +typedef enum { + RTC_PRESCALE_DIV_2_0 = MXC_V_RTC_PRESCALE_DIV_2_0, /**< \f$ f_{RTC} = \frac {4096} {2^{0}} = 4096Hz \f$ */ + RTC_PRESCALE_DIV_2_1 = MXC_V_RTC_PRESCALE_DIV_2_1, /**< \f$ f_{RTC} = \frac {4096} {2^{1}} = 2048Hz \f$ */ + RTC_PRESCALE_DIV_2_2 = MXC_V_RTC_PRESCALE_DIV_2_2, /**< \f$ f_{RTC} = \frac {4096} {2^{2}} = 1024Hz \f$ */ + RTC_PRESCALE_DIV_2_3 = MXC_V_RTC_PRESCALE_DIV_2_3, /**< \f$ f_{RTC} = \frac {4096} {2^{3}} = 512Hz \f$ */ + RTC_PRESCALE_DIV_2_4 = MXC_V_RTC_PRESCALE_DIV_2_4, /**< \f$ f_{RTC} = \frac {4096} {2^{4}} = 256Hz \f$ */ + RTC_PRESCALE_DIV_2_5 = MXC_V_RTC_PRESCALE_DIV_2_5, /**< \f$ f_{RTC} = \frac {4096} {2^{5}} = 128Hz \f$ */ + RTC_PRESCALE_DIV_2_6 = MXC_V_RTC_PRESCALE_DIV_2_6, /**< \f$ f_{RTC} = \frac {4096} {2^{6}} = 64Hz \f$ */ + RTC_PRESCALE_DIV_2_7 = MXC_V_RTC_PRESCALE_DIV_2_7, /**< \f$ f_{RTC} = \frac {4096} {2^{7}} = 32Hz \f$ */ + RTC_PRESCALE_DIV_2_8 = MXC_V_RTC_PRESCALE_DIV_2_8, /**< \f$ f_{RTC} = \frac {4096} {2^{8}} = 16Hz \f$ */ + RTC_PRESCALE_DIV_2_9 = MXC_V_RTC_PRESCALE_DIV_2_9, /**< \f$ f_{RTC} = \frac {4096} {2^{9}} = 8Hz \f$ */ + RTC_PRESCALE_DIV_2_10 = MXC_V_RTC_PRESCALE_DIV_2_10, /**< \f$ f_{RTC} = \frac {4096} {2^{10}} = 4Hz \f$ */ + RTC_PRESCALE_DIV_2_11 = MXC_V_RTC_PRESCALE_DIV_2_11, /**< \f$ f_{RTC} = \frac {4096} {2^{11}} = 2Hz \f$ */ + RTC_PRESCALE_DIV_2_12 = MXC_V_RTC_PRESCALE_DIV_2_12, /**< \f$ f_{RTC} = \frac {4096} {2^{12}} = 1Hz \f$ */ +} rtc_prescale_t; + +/** + * Mask of the RTC Flags for the Active Transaction. + */ +#define RTC_CTRL_ACTIVE_TRANS (MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE | \ + MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE | \ + MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE | \ + MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE | \ + MXC_F_RTC_CTRL_RTC_SET_ACTIVE | \ + MXC_F_RTC_CTRL_RTC_CLR_ACTIVE | \ + MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE | \ + MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE | \ + MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE | \ + MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE | \ + MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE | \ + MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE | \ + MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE | \ + MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE | \ + MXC_F_RTC_CTRL_ACTIVE_TRANS_0) + +/** + * Mask used to clear all RTC interrupt flags, see \ref RTC_FLAGS_Register Register. + */ +#define RTC_FLAGS_CLEAR_ALL (MXC_F_RTC_FLAGS_COMP0 | \ + MXC_F_RTC_FLAGS_COMP1| \ + MXC_F_RTC_FLAGS_PRESCALE_COMP | \ + MXC_F_RTC_FLAGS_OVERFLOW | \ + MXC_F_RTC_FLAGS_TRIM) +/** + * Enumeration type to select the type of RTC Snooze Mode for an alarm condition. + */ +typedef enum { + RTC_SNOOZE_DISABLE = MXC_V_RTC_CTRL_SNOOZE_DISABLE, /**< Snooze Mode Disabled */ + RTC_SNOOZE_MODE_A = MXC_V_RTC_CTRL_SNOOZE_MODE_A, /**< \f$ COMP1 = COMP1 + RTC\_SNZ\_VALUE \f$ when snooze flag is set */ + RTC_SNOOZE_MODE_B = MXC_V_RTC_CTRL_SNOOZE_MODE_B, /**< \f$ COMP1 = RTC\_TIMER + RTC\_SNZ\_VALUE \f$ when snooze flag is set */ +} rtc_snooze_t; + +/** + * Number of RTC Compare registers for this peripheral instance. + */ +#define RTC_NUM_COMPARE 2 + +/** + * Structure type that represents the current configuration of the RTC. + */ + +typedef struct { + rtc_prescale_t prescaler; /**< prescale value for the input 4096Hz clock. */ + rtc_prescale_t prescalerMask; /**< Mask value used to compare to the rtc prescale value, when the \f$ (Count_{prescaler}\,\&\,Prescale\,Mask) == 0 \f$, the prescale compare flag will be set. */ + uint32_t compareCount[RTC_NUM_COMPARE]; /**< Values used for setting the RTC alarms. See RTC_SetCompare() and RTC_GetCompare(). */ + uint32_t snoozeCount; /**< The number of RTC ticks to snooze if enabled. */ + rtc_snooze_t snoozeMode; /**< The desired snooze mode, see #rtc_snooze_t. */ +} rtc_cfg_t; + +/** + * @brief Initializes the RTC + * @note Must setup clocking and power prior to this function. + * + * @param cfg RTC configuration object. + * + * @retval #E_NO_ERROR RTC initialized successfully. + * @retval #E_NULL_PTR \p cfg pointer is NULL. + * @retval #E_INVALID if comparison index, prescaler mask or snooze mask + * are out of bounds, see #rtc_cfg_t. + */ +int RTC_Init(const rtc_cfg_t *cfg); + +/** + * @brief Enable and start the real-time clock continuing from its current value. + */ +__STATIC_INLINE void RTC_Start(void) +{ + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Disable and stop the real-time clock counting. + */ +__STATIC_INLINE void RTC_Stop(void) +{ + MXC_RTCTMR->ctrl &= ~(MXC_F_RTC_CTRL_ENABLE); + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Returns the state (running or disabled) for the RTC. + * + * @retval 0 Disabled. + * @retval Non-zero Active. + */ +__STATIC_INLINE uint32_t RTC_IsActive(void) +{ + return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE); +} + +/** + * @brief Set the current count of the RTC + * + * @param count The desired count value to set for the RTC count. + */ +__STATIC_INLINE void RTC_SetCount(uint32_t count) +{ + MXC_RTCTMR->timer = count; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Get the current count value of the RTC. + * + * @retval The value of the RTC counter. + */ +__STATIC_INLINE uint32_t RTC_GetCount(void) +{ + return (MXC_RTCTMR->timer); +} + +/** + * @brief Sets the compare value for the RTC. + * + * @param compareIndex Index of comparator to set, see #RTC_NUM_COMPARE + * for the total number of compare registers + * available. + * @param counts The value to set for the compare. + * @retval #E_NO_ERROR Compare count register set successfully for + * requested comparator. + * @retval #E_INVALID compareIndex is @>= RTC_NUM_COMPARE. + */ +int RTC_SetCompare(uint8_t compareIndex, uint32_t counts); + +/** + * @brief Gets the compare value for the RTC. + * + * @param compareIndex Index of the compare value to return. See #RTC_NUM_COMPARE + * for the total number of compare registers available. + * + * @returns The current value of the specified compare register for the RTC. + */ +uint32_t RTC_GetCompare(uint8_t compareIndex); + +/** + * @brief Set the prescale reload value for the real-time clock. + * @details The prescale reload value determines the number of 4kHz ticks + * that will occur before the timer is incremented. + * + * + *
Prescaler Settings and Corresponding RTC Resolutions
PRESCALE Prescale Reload 4kHz ticks in LSB Min Timer Value (sec) Max Timer Value (sec) Max Timer Value (Days) Max Timer Value (Years) + *
0hRTC_PRESCALE_DIV_2_010.000241048576120.0 + *
1hRTC_PRESCALE_DIV_2_120.000492097152240.1 + *
2hRTC_PRESCALE_DIV_2_240.000984194304490.1 + *
3hRTC_PRESCALE_DIV_2_380.001958388608970.3 + *
4hRTC_PRESCALE_DIV_2_4160.0039116777216194 0.5 + *
5hRTC_PRESCALE_DIV_2_5320.0078133554432388 1.1 + *
6hRTC_PRESCALE_DIV_2_6640.0156367108864777 2.2 + *
7hRTC_PRESCALE_DIV_2_71280.031251342177281553 4.4 + *
8hRTC_PRESCALE_DIV_2_82560.062502684354563107 8.7 + *
9hRTC_PRESCALE_DIV_2_95120.125005368709126214 17.5 + *
AhRTC_PRESCALE_DIV_2_101024 0.2500010737418241242834.9 + *
BhRTC_PRESCALE_DIV_2_112048 0.5000021474836482485569.8 + *
ChRTC_PRESCALE_DIV_2_124096 1.00000429496729649710139.6 + *
+ * + * @param prescaler Prescale value to set, see #rtc_prescale_t. + */ +__STATIC_INLINE void RTC_SetPrescaler(rtc_prescale_t prescaler) +{ + MXC_RTCTMR->prescale = prescaler; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Get the current value of the real-time clock prescaler. + * + * @retval rtc_prescale_t Returns the current RTC prescaler setting, + * See #rtc_prescale_t for values of the prescaler. + */ +__STATIC_INLINE rtc_prescale_t RTC_GetPrescaler(void) +{ + return (rtc_prescale_t)(MXC_RTCTMR->prescale); +} + +/** + * @brief Set the prescaler mask, which is used to set the RTC prescale counter + * compare flag when the prescaler timer matches the bits indicated + * by the mask. + * @param mask A bit mask that is used to set the prescale compare flag if the + * prescale timer has the corresponding bits set. @note This mask must + * be less than or equal to the prescaler reload value. + * See RTC_SetPrescaler() + * @details When \f$ Count_{prescaler}\,\&\,Prescale\,Mask = 0 \f$, the prescale compare flag is set + * @retval int Returns #E_NO_ERROR if prescale value is valid and is set. + * @retval int Returns #E_INVALID if mask is \> than prescaler value + */ +__STATIC_INLINE int RTC_SetPrescalerMask(rtc_prescale_t mask) +{ + if (mask > ((rtc_prescale_t)(MXC_RTCTMR->prescale))) + { + return E_INVALID; + } + MXC_RTCTMR->prescale_mask = mask; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + return E_NO_ERROR; +} + +/** + * @brief Set the count for snooze mode. See RTC_Snooze(). + * @details This value is used to set the snooze count. The meaning of this value is dependant on the snooze mode. p + * See RTC_SetSnoozeMode() for details of calculating the snooze time period based on the mode and snooze count. + * @param count Sets the count used for snooze when snooze mode is + * enabled and the snooze flag is set. + * @retval #E_NO_ERROR Snooze value is set correctly and value is valid. + * @retval #E_INVALID SnoozeCount exceeds maximum supported, see + * MXC_F_RTC_SNZ_VAL_VALUE + */ +__STATIC_INLINE int RTC_SetSnoozeCount(uint32_t count) +{ + // Check to make sure max value is not being exceeded + if (count > MXC_F_RTC_SNZ_VAL_VALUE) + return E_INVALID; + + MXC_RTCTMR->snz_val = count; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + return E_NO_ERROR; +} + +/** + * @brief Gets the current Snooze Count value. + * @details Returns the current value for the Snooze Count. This value is + * used as part of the snooze calculation depending on the snooze + * mode. See RTC_SetSnoozeMode() for details of calculating the + * snooze time period based on the mode and count. + * @return Value of the snooze register. + */ +__STATIC_INLINE uint32_t RTC_GetSnoozeCount(void) +{ + return MXC_RTCTMR->snz_val; +} + +/** + * @brief Activates snooze mode. + * @details Begins a snooze of the RTC. When this function is called + * the snooze time period is determined based on the snooze mode and the count. + * See RTC_GetCount() and RTC_SetSnoozeMode() + */ +__STATIC_INLINE void RTC_Snooze(void) +{ + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_SNOOZE_A | MXC_F_RTC_FLAGS_SNOOZE_B; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Sets the Snooze Mode. + * @details + *
Snooze Modes
ModeSnooze Time Calculation + *
RTC_SNOOZE_DISABLESnooze Disabled + *
RTC_SNOOZE_MODE_A\f$ compare1 = compare1 + snoozeCount \f$ + *
RTC_SNOOZE_MODE_B\f$ compare1 = count + snoozeCount \f$ + *
+ * @note @a count is the value of the RTC counter when RTC_Snooze() + * is called to start a snooze cycle and @a snoozeCount is the value set by the RTC_SetSnoozeCount(uint32_t count) function. + * + * @param mode Specifies the desired snooze mode, see #rtc_snooze_t. + * + */ +__STATIC_INLINE void RTC_SetSnoozeMode(rtc_snooze_t mode) +{ + uint32_t ctrl; + // Get the control register and mask off the non-snooze bits + ctrl = (MXC_RTCTMR->ctrl & ~(MXC_F_RTC_CTRL_SNOOZE_ENABLE)); + // set the requested snooze mode bits and save the settings + MXC_RTCTMR->ctrl = (ctrl | (mode << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)); + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Enables the interrupts specified for the RTC. + * @details + * + *
RTC Interrupts
InterruptMask + *
Compare 0#MXC_F_RTC_INTEN_COMP0 + *
Compare 1 and Snooze#MXC_F_RTC_INTEN_COMP1 + *
Prescale Comp#MXC_F_RTC_INTEN_PRESCALE_COMP + *
RTC Count Overflow#MXC_F_RTC_INTEN_OVERFLOW + *
Trim#MXC_F_RTC_INTEN_TRIM + *
+ * @param mask A mask of the RTC interrupts to enable, 1 = Enable. See + * @ref RTC_FLAGS_Register Register for the RTC interrupt enable bit masks and positions. + */ +__STATIC_INLINE void RTC_EnableINT(uint32_t mask) +{ + MXC_RTCTMR->inten |= mask; +} + +/** + * @brief Disable the interrupts specified for the RTC. See the + * @ref RTC_INTEN_Register Register for the RTC interrupt enable bit masks and positions. + * + * @param mask A mask of the RTC interrupts to disable, 1 = Disable. + */ +__STATIC_INLINE void RTC_DisableINT(uint32_t mask) +{ + MXC_RTCTMR->inten &= ~mask; +} + +/** + * @brief Returns the current interrupt flags that are set. + * + * @return A mask of the current interrupt flags, see the + * @ref RTC_FLAGS_Register Register for the details of the RTC interrupt + * flags. + */ +__STATIC_INLINE uint32_t RTC_GetFlags(void) +{ + return (MXC_RTCTMR->flags); +} + +/** + * @brief Clears the interrupt flags specified. + * + * @param mask A mask of interrupts to clear, see the @ref RTC_FLAGS_Register + * Register for the interrupt flag bit masks and positions. + */ +__STATIC_INLINE void RTC_ClearFlags(uint32_t mask) +{ + MXC_RTCTMR->flags = mask; + + //wait for pending actions to complete + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +/** + * @brief Gets the active transaction flags, see @ref RTC_CTRL_Register Register for the list of ACTIVE flags. + * + * @retval 0 No active transactions. + * @retval nonzero A mask of active transaction bits. + */ +__STATIC_INLINE uint32_t RTC_GetActiveTrans(void) +{ + return (MXC_RTCTMR->ctrl & RTC_CTRL_ACTIVE_TRANS); +} + +/** + * @brief Sets the trim value and trim slow/fast option. + * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC. + * + * @param trim The desired trim value. @note The maximum trim value setting is 0x03FFFF. + * @param trimSlow 1 = trim slow, 0 = trim fast + * + * @return #E_NO_ERROR Trim value is valid and set. + * @return #E_INVALID Trim value exceeds max trim. + * @return #E_BAD_STATE RTC is active. + */ +int RTC_SetTrim(uint32_t trim, uint8_t trimSlow); + +/** + * @brief Gets the current trim value. + * @note Ensure RTC is disabled prior to calling this function, see RTC_Stop(void). + * + * @retval uint32_t Current trim value of RTC. + */ +uint32_t RTC_GetTrim(void); + +/** + * @brief Enable the trim. + * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC. + * @retval #E_NO_ERROR Trim is enabled. + * @retval #E_INVALID RTC is active, see RTC_Stop(void). + */ +int RTC_TrimEnable(void); + +/** + * @brief Disable the trim. + */ +void RTC_TrimDisable(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.c new file mode 100644 index 00000000000..629b62a7eab --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.c @@ -0,0 +1,725 @@ +/** + * @file + * @brief Serial Peripheral Interface Master (SPIM) Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:32:38 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24324 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "mxc_lock.h" +#include "spim.h" + +/** + * @ingroup spim + * @{ + */ +/* **** Definitions **** */ +#define SPIM_MAX_BYTE_LEN 32 +#define SPIM_MAX_PAGE_LEN 32 + +/* **** Globals **** */ + +// Saves the state of the non-blocking requests +typedef struct { + spim_req_t *req; + unsigned head_rem; +} spim_req_head_t; + +static spim_req_head_t states[MXC_CFG_SPIM_INSTANCES]; + +/* **** Local Function Prototypes **** */ + +static unsigned SPIM_ReadRXFIFO(mxc_spim_regs_t *spim, mxc_spim_fifo_regs_t *fifo, + uint8_t *data, unsigned len); + +static uint32_t SPIM_TransHandler(mxc_spim_regs_t *spim, spim_req_t *req, int spim_num); + +/* ************************************************************************* */ +int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg) +{ + int err, spim_num; + uint32_t spim_clk, clocks; + + spim_num = MXC_SPIM_GET_IDX(spim); + MXC_ASSERT(spim_num >= 0); + + // Check the input parameters + if(cfg == NULL) + return E_NULL_PTR; + + if(cfg->baud == 0) + return E_BAD_PARAM; + + // Set system level configurations + if ((err = SYS_SPIM_Init(spim, cfg, sys_cfg)) != E_NO_ERROR) { + return err; + } + + /* Configure the baud, make sure the SPIM clk is enabled and the baud + is less than the maximum */ + spim_clk = SYS_SPIM_GetFreq(spim); + if((spim_clk == 0) || ((spim_clk == SystemCoreClock) && ((spim_clk/2) < cfg->baud))) { + return E_BAD_PARAM; + } + + // Initialize state pointers + states[spim_num].req = NULL; + states[spim_num].head_rem = 0; + + // Drain the FIFOs, enable SPIM, enable SCK Feedback + spim->gen_ctrl = 0; + spim->gen_ctrl = (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN | MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | + MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE); + + // Set mode and page size + spim->mstr_cfg = (((cfg->mode << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS) & MXC_F_SPIM_MSTR_CFG_SPI_MODE) | + MXC_S_SPIM_MSTR_CFG_PAGE_32B | (0x2 << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS)); + + // Configure the SSEL polarity + spim->ss_sr_polarity = ((cfg->ssel_pol << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS) & + MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY); + +#if(MXC_SPIM_REV == 0) + // Disable the feedback clock in modes 1 and 2 + if((cfg->mode == 1) || (cfg->mode == 2)) { + spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE; + spim->mstr_cfg |= (0x1 << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS); + } +#else + // Increase the RX FIFO margin + MXC_SPIM1->spcl_ctrl = ((MXC_SPIM1->spcl_ctrl & ~(MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN)) | + (0x3 << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS)); +#endif + + // Calculate the hi/lo clock setting + if(spim_clk/2 > cfg->baud) { + + /* Disable the feedback mode and use the sample mode with an appropriate hi/lo clk + to achieve the lower baud rate */ + spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE; + + clocks = (spim_clk / (2*cfg->baud)); + + if(clocks == 0 || clocks > 0x10) { + return E_BAD_PARAM; + } + + // 0 => 16 in the 4 bit field for HI_CLK and LO_CLK + if(clocks == 0x10) { + clocks = 0; + } + + } else { + // Continue to use feedback mode and set hi/lo clk to 1 + clocks = 1; + } + + spim->mstr_cfg |= (((clocks << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS) & MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK) | + ((clocks << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS) & MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK)); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int SPIM_Shutdown(mxc_spim_regs_t *spim) +{ + int spim_num, err; + spim_req_t *temp_req; + + // Disable and clear interrupts + spim->inten = 0; + spim->intfl = spim->intfl; + + // Disable SPIM and FIFOS + spim->gen_ctrl &= ~(MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN | MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | + MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN); + + // Call all of the pending callbacks for this SPIM + spim_num = MXC_SPIM_GET_IDX(spim); + if(states[spim_num].req != NULL) { + + // Save the request + temp_req = states[spim_num].req; + + // Unlock this SPIM + mxc_free_lock((uint32_t*)&states[spim_num].req); + + // Callback if not NULL + if(temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + // Clear system level configurations + if ((err = SYS_SPIM_Shutdown(spim)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass) +{ + int spim_num; + mxc_spim_fifo_regs_t *fifo; + uint16_t header = 0x1; + uint32_t num = len; + + // Make sure the SPIM has been initialized + if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0) + return E_UNINITIALIZED; + + if(!(len > 0)) { + return E_NO_ERROR; + } + + // Check the previous transaction if we're switching the slave select + if((ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >> + MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) { + + // Return E_BUSY if the slave select is still asserted + return E_BUSY; + } + + // Attempt to lock this SPIM + spim_num = MXC_SPIM_GET_IDX(spim); + if(mxc_get_lock((uint32_t*)&states[spim_num].req, 1) != E_NO_ERROR) { + return E_BUSY; + } + + // Set which slave select we are using + spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) | + ((ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL)); + + //force deass to a 1 or 0 + deass = !!deass; + +#if(MXC_SPIM_REV == 0) + // Wait for all of the data to transmit + while(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) {} + + // Disable the feedback clock, save state + uint32_t gen_ctrl = spim->gen_ctrl; + spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE; +#endif + + // Get the TX and RX FIFO for this SPIM + fifo = MXC_SPIM_GET_SPIM_FIFO(spim_num); + + // Send the headers to transmit the clocks + while(len > 32) { + fifo->trans_16[0] = header; + fifo->trans_16[0] = 0xF000; + fifo->trans_16[0] = 0xF000; + len -= 32; + } + + if(len) { + if(len < 32) { + header |= (len << 4); + } + header |= (deass << 13); + + fifo->trans_16[0] = header; + + if(len > 16) { + fifo->trans_16[0] = 0xF000; + } + fifo->trans_16[0] = 0xF000; + } + +#if(MXC_SPIM_REV == 0) + // Wait for all of the data to transmit + while(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) {} + + // Restore feedback clock setting + spim->gen_ctrl |= (gen_ctrl & MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE); +#endif + + // Unlock this SPIM + mxc_free_lock((uint32_t*)&states[spim_num].req); + + return num; +} + + +/* ************************************************************************* */ +int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req) +{ + int spim_num; + + // Make sure the SPIM has been initialized + if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0) + return E_UNINITIALIZED; + + // Check the input parameters + if(req == NULL) + return E_NULL_PTR; + + if((req->rx_data == NULL) && (req->tx_data == NULL)) + return E_NULL_PTR; + + if(!(req->len > 0)) { + return E_NO_ERROR; + } + + // Check the previous transaction if we're switching the slave select + if((req->ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >> + MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) { + + // Return E_BUSY if the slave select is still asserted + return E_BUSY; + } + + // Attempt to register this write request + spim_num = MXC_SPIM_GET_IDX(spim); + if(mxc_get_lock((uint32_t*)&states[spim_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Set which slave select we are using + spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) | + ((req->ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL)); + + //force deass to a 1 or 0 + req->deass = !!req->deass; + + // Clear the number of bytes counter + req->read_num = 0; + req->write_num = 0; + req->callback = NULL; + states[spim_num].head_rem = 0; + + // Start the transaction, keep calling the handler until complete + while(SPIM_TransHandler(spim, req, spim_num) != 0); + + if(req->tx_data == NULL) { + return req->read_num; + } + return req->write_num; +} + +/* ************************************************************************* */ +int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req) +{ + int spim_num; + + // Make sure the SPIM has been initialized + if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0) + return E_UNINITIALIZED; + + // Check the input parameters + if(req == NULL) + return E_NULL_PTR; + + if((req->rx_data == NULL) && (req->tx_data == NULL)) + return E_NULL_PTR; + + if(!(req->len > 0)) { + return E_NO_ERROR; + } + + + // Check the previous transaction if we're switching the slave select + if((req->ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >> + MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) { + + // Return E_BUSY if the slave select is still asserted + return E_BUSY; + } + + // Attempt to register this write request + spim_num = MXC_SPIM_GET_IDX(spim); + if(mxc_get_lock((uint32_t*)&states[spim_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Set which slave select we are using + spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) | + ((req->ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL)); + + //force deass to a 1 or 0 + req->deass = !!req->deass; + + // Clear the number of bytes counter + req->read_num = 0; + req->write_num = 0; + states[spim_num].head_rem = 0; + + // Start the transaction, enable the interrupts + spim->inten = SPIM_TransHandler(spim, req, spim_num); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int SPIM_AbortAsync(spim_req_t *req) +{ + int spim_num; + mxc_spim_regs_t *spim; + + // Check the input parameters + if(req == NULL) { + return E_BAD_PARAM; + } + + // Find the request, set to NULL + for(spim_num = 0; spim_num < MXC_CFG_SPIM_INSTANCES; spim_num++) { + if(req == states[spim_num].req) { + + spim = MXC_SPIM_GET_SPIM(spim_num); + + // Disable interrupts, clear the flags + spim->inten = 0; + spim->intfl = spim->intfl; + + // Reset the SPIM to cancel the on ongoing transaction + spim->gen_ctrl &= ~(MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN); + spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN); + + // Unlock this SPIM + mxc_free_lock((uint32_t*)&states[spim_num].req); + + // Callback if not NULL + if(req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +/* ************************************************************************* */ +void SPIM_Handler(mxc_spim_regs_t *spim) +{ + int spim_num; + uint32_t flags; + + // Clear the interrupt flags + spim->inten = 0; + flags = spim->intfl; + spim->intfl = flags; + + spim_num = MXC_SPIM_GET_IDX(spim); + + // Figure out if this SPIM has an active request + if((states[spim_num].req != NULL) && (flags)) { + spim->inten = SPIM_TransHandler(spim, states[spim_num].req, spim_num); + } +} + +/* ************************************************************************* */ +int SPIM_Busy(mxc_spim_regs_t *spim) +{ + // Check to see if there are any ongoing transactions + if((states[MXC_SPIM_GET_IDX(spim)].req == NULL) && + !(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED)) { + + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************* */ +int SPIM_PrepForSleep(mxc_spim_regs_t *spim) +{ + if(SPIM_Busy(spim) != E_NO_ERROR) { + return E_BUSY; + } + + // Disable interrupts + spim->inten = 0; + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static unsigned SPIM_ReadRXFIFO(mxc_spim_regs_t *spim, mxc_spim_fifo_regs_t *fifo, + uint8_t *data, unsigned len) +{ + unsigned num = 0; + unsigned avail = ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> + MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); + + // Get data from the RXFIFO + while(avail && (len - num)) { + + if((avail >= 4) && ((len-num) >= 4)) { + // Save data from the RXFIFO + uint32_t temp = fifo->rslts_32[0]; + data[num+0] = ((temp & 0x000000FF) >> 0); + data[num+1] = ((temp & 0x0000FF00) >> 8); + data[num+2] = ((temp & 0x00FF0000) >> 16); + data[num+3] = ((temp & 0xFF000000) >> 24); + num+=4; + avail-=4; + } else if ((avail >= 2) && ((len-num) >= 2)) { + // Save data from the RXFIFO + uint16_t temp = fifo->rslts_16[0]; + data[num+0] = ((temp & 0x00FF) >> 0); + data[num+1] = ((temp & 0xFF00) >> 8); + num+=2; + avail-=2; + } else { + // Save data from the RXFIFO + data[num] = fifo->rslts_8[0]; + num+=1; + avail-=1; + } + + // Check to see if there is more data in the FIFO + if(avail == 0) { + avail = ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> + MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); + } + } + + return num; +} + +uint16_t header_save; + + +/* ************************************************************************* */ +static uint32_t SPIM_TransHandler(mxc_spim_regs_t *spim, spim_req_t *req, int spim_num) +{ + uint8_t read, write; + uint16_t header; + uint32_t pages, bytes, inten; + unsigned remain, bytes_read, head_rem_temp, avail; + mxc_spim_fifo_regs_t *fifo; + + inten = 0; + + // Get the FIFOS for this UART + fifo = MXC_SPIM_GET_SPIM_FIFO(spim_num); + + // Figure out if we're reading + if(req->rx_data != NULL) { + read = 1; + } else { + read = 0; + } + + // Figure out if we're writing + if(req->tx_data != NULL) { + write = 1; + } else { + write = 0; + } + + // Read byte from the FIFO if we are reading + if(read) { + + // Read all of the data in the RXFIFO, or until we don't need anymore + bytes_read = SPIM_ReadRXFIFO(spim, fifo, &req->rx_data[req->read_num], + (req->len - req->read_num)); + + req->read_num += bytes_read; + + // Adjust head_rem if we are only reading + if(!write && (states[spim_num].head_rem > 0)) { + states[spim_num].head_rem -= bytes_read; + } + + // Figure out how many byte we have left to read + if(states[spim_num].head_rem > 0) { + remain = states[spim_num].head_rem; + } else { + remain = req->len - req->read_num; + } + + if(remain) { + + // Set the RX interrupts + if (remain > MXC_CFG_SPIM_FIFO_DEPTH) { + spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL) | + ((MXC_CFG_SPIM_FIFO_DEPTH - 2) << + MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)); + + } else { + spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL) | + ((remain - 1) << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)); + } + + inten |= MXC_F_SPIM_INTEN_RX_FIFO_AF; + } + } + + // Figure out how many bytes we have left to send headers for + if(write) { + remain = req->len - req->write_num; + } else { + remain = req->len - req->read_num; + } + + // See if we need to send a new header + if(states[spim_num].head_rem <= 0 && remain) { + + // Set the transaction configuration in the header + header = ((write << 0) | (read << 1) | (req->width << 9)); + + if(remain >= SPIM_MAX_BYTE_LEN) { + + // Send a 32 byte header + if(remain == SPIM_MAX_BYTE_LEN) { + + header |= ((0x1 << 2) | (req->deass << 13)); + + // Save the number of bytes we need to write to the FIFO + bytes = SPIM_MAX_BYTE_LEN; + + } else { + // Send in increments of 32 byte pages + header |= (0x2 << 2); + pages = remain / SPIM_MAX_PAGE_LEN; + + if(pages >= 32) { + // 0 maps to 32 in the header + bytes = 32 * SPIM_MAX_PAGE_LEN; + } else { + header |= (pages << 4); + bytes = pages * SPIM_MAX_PAGE_LEN; + } + + // Check if this is the last header we will send + if((remain - bytes) == 0) { + header |= (req->deass << 13); + } + } + + header_save = header; + fifo->trans_16[0] = header; + + // Save the number of bytes we need to write to the FIFO + states[spim_num].head_rem = bytes; + + } else { + + // Send final header with the number of bytes remaining and if + // we want to de-assert the SS at the end of the transaction + header |= ((0x1 << 2) | (remain << 4) | (req->deass << 13)); + fifo->trans_16[0] = header; + states[spim_num].head_rem = remain; + } + } + + // Put data into the FIFO if we are writing + remain = req->len - req->write_num; + head_rem_temp = states[spim_num].head_rem; + if(write && head_rem_temp) { + + // Fill the FIFO + avail = (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> + MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)); + + // Use memcpy for everything except the last byte in odd length transactions + while((avail >= 2) && (head_rem_temp >= 2)) { + + unsigned length; + if(head_rem_temp < avail) { + length = head_rem_temp; + } else { + length = avail; + } + + // Only memcpy even numbers + length = ((length / 2) * 2); + + memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length); + + head_rem_temp -= length; + req->write_num += length; + + avail = (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> + MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)); + } + + // Copy the last byte and pad with 0xF0 to not get confused as header + if((avail >= 1) && (head_rem_temp == 1)) { + + // Write the last byte + fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]); + + avail -= 1; + req->write_num += 1; + head_rem_temp -= 1; + } + + states[spim_num].head_rem = head_rem_temp; + remain = req->len - req->write_num; + + // Set the TX interrupts + if(remain) { + + // Set the TX FIFO almost empty interrupt if we have to refill + spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL) | + ((MXC_CFG_SPIM_FIFO_DEPTH - 2) << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS)); + + inten |= MXC_F_SPIM_INTEN_TX_FIFO_AE; + + } + } + + // Check to see if we've finished reading and writing + if(((read && (req->read_num == req->len)) || !read) && + ((req->write_num == req->len) || !write)) { + + // Disable interrupts + spim->inten = 0; + + // Unlock this SPIM + mxc_free_lock((uint32_t*)&states[spim_num].req); + + // Callback if not NULL + if(req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + + // Enable the SPIM interrupts + return inten; +} +/**@} end of ingroup spim */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h new file mode 100644 index 00000000000..887c51e5d1b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h @@ -0,0 +1,347 @@ +/** + * @file + * @brief Registers, Bit Masks and Bit Positions for the SPI Master module. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24672 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "spim_regs.h" + +/* Define to prevent redundant inclusion */ +#ifndef _SPIM_H_ +#define _SPIM_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @ingroup commperipherals + * @defgroup spi_comm SPI + * @brief SPI Master and Slave Communication Peripherals + */ + +/** + * @ingroup spi_comm + * @defgroup spim SPI Master + * @brief Serial Peripheral Interface Master (SPIM) Communications + * Interface. + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type for selecting the active levels for the SPI Master Slave Select (SS) lines. + */ +typedef enum { + SPIM_SSEL0_HIGH = (0x1 << 0), /**< Slave Select 0 High. */ + SPIM_SSEL0_LOW = 0, /**< Slave Select 0 Low. */ + SPIM_SSEL1_HIGH = (0x1 << 1), /**< Slave Select 1 High. */ + SPIM_SSEL1_LOW = 0, /**< Slave Select 1 Low. */ + SPIM_SSEL2_HIGH = (0x1 << 2), /**< Slave Select 2 High. */ + SPIM_SSEL2_LOW = 0, /**< Slave Select 2 Low. */ + SPIM_SSEL3_HIGH = (0x1 << 3), /**< Slave Select 3 High. */ + SPIM_SSEL3_LOW = 0, /**< Slave Select 3 Low. */ + SPIM_SSEL4_HIGH = (0x1 << 4), /**< Slave Select 4 High. */ + SPIM_SSEL4_LOW = 0 /**< Slave Select 4 Low. */ +} +spim_ssel_t; + +/** + * Enumeration type for setting the number data lines to use for communication. + */ +typedef enum { + SPIM_WIDTH_1 = 0, /**< 1 Data Line. */ + SPIM_WIDTH_2 = 1, /**< 2 Data Lines (x2). */ + SPIM_WIDTH_4 = 2 /**< 4 Data Lines (x4). */ +} spim_width_t; + +/** + * Structure type for configuring a SPIM port. + */ +typedef struct { + uint8_t mode; /**< SPIM mode selection, 0 to 3. */ + uint32_t ssel_pol; /**< Mask of active levels for the slave select signals, see #spim_ssel_t. */ + uint32_t baud; /**< Baud rate in Hz. */ +} spim_cfg_t; + +/** + * Structure type representing a SPI Master Transaction request. + */ +typedef struct spim_req spim_req_t; + +/** + * @brief Callback function type used in asynchromous SPIM communications requests. + * @details The function declaration for the SPIM callback is: + * @code + * void callback(spim_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spim_req object representing the active SPIM active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @addtogroup spim_async + */ +typedef void (*spim_callback_fn)(spim_req_t * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup spim_async + */ +struct spim_req { + uint8_t ssel; /**< Number of the Slave Select to use. */ + uint8_t deass; /**< Set to de-assert slave select at the completions of the transaction.*/ + const uint8_t *tx_data; /**< Pointer to a buffer to transmit data from. */ + uint8_t *rx_data; /**< Pointer to a buffer to store data received. */ + spim_width_t width; /**< Number of data lines to use, see #spim_width_t. */ + unsigned len; /**< Number of bytes to send from the \p tx_data buffer. */ + unsigned read_num; /**< Number of bytes read and stored in \p rx_data buffer. */ + unsigned write_num; /**< Number of bytes sent from the \p tx_data buffer, this will be filled by the driver after up to \p len bytes have been transmitted. */ + spim_callback_fn callback; /**< Function pointer to a callback function if desired, NULL otherwise */ +}; + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the SPIM peripheral module. + * + * @param spim Pointer to the SPIM register structure. + * @param cfg Pointer to an SPIM configuration object. + * @param sys_cfg Pointer to a system configuration object to select the + * peripheral clock rate and assign the requested GPIO. + * + * @return #E_NO_ERROR if the SPIM port is initialized successfully, @ref MXC_Error_Codes + * "error" if unsuccessful. + */ +int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg); + +/** + * @brief Shutdown the SPIM peripheral module instance represented by the + * @p spim parameter. + * + * @param spim Pointer to the SPIM register structure. + * + * @return #E_NO_ERROR if the SPIM is shutdown successfully, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIM_Shutdown(mxc_spim_regs_t *spim); + +/** + * @brief Send Clock cycles on SCK without reading or writing. + * + * @param spim Pointer to the SPIM register structure. + * @param len Number of clock cycles to send. + * @param ssel Slave select number. + * @param deass De-assert slave select at the end of the transaction. + * + * @return Cycles transacted if everything is successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass); + +/** + * @brief Read/write SPIM data. This function will block until the + * transaction is complete. + * + * @param spim Pointer to the SPIM register structure. + * @param req Request for a SPIM transaction. + * @note If a callback function is registered it will not be called when using a blocking function. + * + * @return Bytes transacted if everything is successful, error if + * unsuccessful. + */ +int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req); +/** + * @defgroup spim_async SPIM Asynchrous Functions + * @{ + */ +/** + * @brief Asynchronously read/write SPIM data. + * + * @param spim Pointer to the SPIM register structure. + * @param req Request for a SPIM transaction. + * @note Request struct must remain allocated until callback. + * + * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes + * "error" if unsuccessful. + */ +int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req); + +/** + * @brief Abort asynchronous request. + * + * @param req Pointer to a request structure for a SPIM transaction. + * + * @return #E_NO_ERROR if request aborted, , @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int SPIM_AbortAsync(spim_req_t *req); + +/** + * @brief SPIM interrupt handler. + * @details This function should be called by the application from the + * interrupt handler if SPIM interrupts are enabled. Alternately, + * this function can be periodically polled by the application if + * SPIM interrupts are disabled. + * + * @param spim Base address of the SPIM module. + */ +void SPIM_Handler(mxc_spim_regs_t *spim); + +/** + * @brief Check the SPIM to see if it's busy. + * + * @param spim Pointer to the SPIM register structure. + * + * @retval #E_NO_ERROR if idle. + * @retval #E_BUSY if in use. + */ +int SPIM_Busy(mxc_spim_regs_t *spim); +/**@} end of spim_async define group */ + +/** + * @brief Attempts to prepare the SPIM for Low Power Sleep Modes. + * @details Checks for any ongoing transactions. Disables interrupts if the + * SPIM is idle. + * + * @param spim The spim + * + * @return #E_NO_ERROR if ready to sleep. + * @return #E_BUSY if not able to sleep at this time. + */ +int SPIM_PrepForSleep(mxc_spim_regs_t *spim); + +/** + * @brief Enables the SPIM without overwriting the existing configuration. + * + * @param spim Pointer to the SPIM register structure. + */ +__STATIC_INLINE void SPIM_Enable(mxc_spim_regs_t *spim) +{ + spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN | + MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN); +} + +/** + * @brief Drains/empties the data in the RX FIFO. + * + * @param spim Pointer to the SPIM register structure. + */ +__STATIC_INLINE void SPIM_DrainRX(mxc_spim_regs_t *spim) +{ + uint32_t ctrl_save = spim->gen_ctrl; + spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN); + spim->gen_ctrl = ctrl_save; +} + +/** + * @brief Drains/empties the data in the TX FIFO. + * + * @param spim Pointer to the SPIM register structure. + */ +__STATIC_INLINE void SPIM_DrainTX(mxc_spim_regs_t *spim) +{ + uint32_t ctrl_save = spim->gen_ctrl; + spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN); + spim->gen_ctrl = ctrl_save; +} + +/** + * @brief Returns the number of bytes free in the TX FIFO. + * + * @param spim Pointer to the SPIM register structure. + * + * @return Number of bytes free in Transmit FIFO. + */ +__STATIC_INLINE unsigned SPIM_NumWriteAvail(mxc_spim_regs_t *spim) +{ + return (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl & + MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)); +} + +/** + * @brief Returns the number of bytes available to read in the RX FIFO. + * + * @param spim Pointer to the SPIM register structure. + * + * @return Number of bytes in RX FIFO. + */ +__STATIC_INLINE unsigned SPIM_NumReadAvail(mxc_spim_regs_t *spim) +{ + return ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> + MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); +} + +/** + * @brief Clear the SPIM interrupt flags. + * + * @param spim Pointer to the SPIM register structure. + * @param mask Mask of the SPIM interrupt flags to clear, see @ref + * SPIM_INTFL_Register Register for the SPIM interrupt flag + * bit masks. + */ +__STATIC_INLINE void SPIM_ClearFlags(mxc_spim_regs_t *spim, uint32_t mask) +{ + spim->intfl = mask; +} + +/** + * @brief Read the current SPIM interrupt flags. + * + * @param spim Pointer to the SPIM register structure. + * + * @return Mask of currently set SPIM interrupt flags, see @ref + * SPIM_INTFL_Register Register for the SPIM interrupt flag bit + * masks. + */ +__STATIC_INLINE unsigned SPIM_GetFlags(mxc_spim_regs_t *spim) +{ + return (spim->intfl); +} + +/**@} end of group spim_comm */ +#ifdef __cplusplus +} +#endif + +#endif /* _SPIM_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c new file mode 100644 index 00000000000..684a4719b8f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c @@ -0,0 +1,297 @@ +/** + * @file + * @brief SPI execute in place driver. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:31:41 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24323 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "spix.h" +#include "spix_regs.h" + +/** + * @ingroup spix + * @{ + */ + +/* **** Definitions **** */ +#define CMD_CLOCKS 8 +#define ADDR_3BYTE_CLOCKS 24 +#define ADDR_4BYTE_CLOCKS 32 + +/***** Globals *****/ + +/***** Functions *****/ + +/******************************************************************************/ +#if defined ( __GNUC__ ) +#undef IAR_SPIX_PRAGMA //Make sure this is not defined for GCC +#endif + +#if IAR_SPIX_PRAGMA +// IAR memory section declaration for the SPIX functions to be loaded in RAM. +#pragma section=".spix_config" +#endif + +#if(MXC_SPIX_REV == 0) + +#if defined ( __GNUC__ ) +__attribute__ ((section(".spix_config"), noinline)) +#endif /* __GNUC */ + +#if IAR_SPIX_PRAGMA +#pragma location=".spix_config" // IAR locate function in RAM section .spix_config +#pragma optimize=no_inline // IAR no inline optimization on this function +#endif /* IAR_PRAGMA */ + +static void SPIX_UpdateFBIgnore() +{ + // Update the feedback ignore clocks + uint8_t clocks = 0; + uint8_t no_cmd_clocks = 0; + + // Adjust the clocks for the command + if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) == + MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO) { + + clocks += CMD_CLOCKS/4; + } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) == + MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO) { + + clocks += CMD_CLOCKS/2; + } else { + + clocks += CMD_CLOCKS; + } + + // Adjust the clocks for the address + if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) == + MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO) { + + if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) { + clocks += ADDR_4BYTE_CLOCKS/4; + no_cmd_clocks += ADDR_4BYTE_CLOCKS/4; + } else { + clocks += ADDR_3BYTE_CLOCKS/4; + no_cmd_clocks += ADDR_3BYTE_CLOCKS/4; + } + + } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) == + MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO) { + + if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) { + clocks += ADDR_4BYTE_CLOCKS/2; + no_cmd_clocks += ADDR_4BYTE_CLOCKS/2; + } else { + clocks += ADDR_3BYTE_CLOCKS/2; + no_cmd_clocks += ADDR_3BYTE_CLOCKS/2; + } + } else { + + if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) { + clocks += ADDR_4BYTE_CLOCKS; + no_cmd_clocks += ADDR_4BYTE_CLOCKS; + } else { + clocks += ADDR_3BYTE_CLOCKS; + no_cmd_clocks += ADDR_3BYTE_CLOCKS; + } + } + + // Adjust for the mode clocks + clocks += ((MXC_SPIX->mode_ctrl & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) >> + MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS); + + // Set the FB Ignore clocks + MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS) | + (clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)); + + MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD) | + (no_cmd_clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)); +} +#endif /* MXC_SPIX_REV==0 */ + +/******************************************************************************/ +#if defined ( __GNUC__ ) +__attribute__ ((section(".spix_config"), noinline)) +#endif /* __GNUC */ + +#if IAR_SPIX_PRAGMA +#pragma location=".spix_config" // IAR locate function in RAM section .spix_config +#pragma optimize=no_inline // IAR no inline optimization on this function +#endif /* IAR_SPIX_PRAGMA */ +int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample) +{ + int err; + uint32_t spix_clk, clocks; + + // Check the input parameters + if(sys_cfg == NULL) { + return E_NULL_PTR; + } + + // Set system level configurations + if ((err = SYS_SPIX_Init(sys_cfg, baud)) != E_NO_ERROR) { + return err; + } + + // Configure the mode and baud + spix_clk = SYS_SPIX_GetFreq(); + if(spix_clk <= 0) { + return E_UNINITIALIZED; + } + + // Make sure that we can generate this frequency + clocks = (spix_clk / (2*baud)); + if((clocks <= 0) || (clocks >= 0x10)) { + return E_BAD_PARAM; + } + + // Set the baud + MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & + ~(MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK | MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK)) | + (clocks << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS) | + (clocks << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)); + + if(sample != 0) { + // Use sample mode + MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT) | + (sample << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)); + + MXC_SPIX->sck_fb_ctrl &= ~(MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE | + MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK); + } else { + // Use Feedback mode + MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT); + + MXC_SPIX->sck_fb_ctrl |= (MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE | + MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK); + + +#if(MXC_SPIX_REV == 0) + SPIX_UpdateFBIgnore(); +#endif + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +#if defined ( __GNUC__ ) +__attribute__ ((section(".spix_config"), noinline)) +#endif /* __GNUC */ + +#if IAR_SPIX_PRAGMA +#pragma location=".spix_config" // IAR locate function in RAM section .spix_config +#pragma optimize=no_inline // IAR no inline optimization on this function +#endif /* IAR_SPIX_PRAGMA */ + +void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay) +{ + + // Set the slave select + MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SLAVE_SEL) | + (ssel << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)); + + if(pol != 0) { + // Active high + MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SS_ACT_LO); + } else { + // Active low + MXC_SPIX->master_cfg |= MXC_F_SPIX_MASTER_CFG_SS_ACT_LO; + } + + // Set the delays + MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~(MXC_F_SPIX_MASTER_CFG_ACT_DELAY | + MXC_F_SPIX_MASTER_CFG_INACT_DELAY)) | + (act_delay << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS) | + (inact_delay << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)); +} + +/******************************************************************************/ +#if defined ( __GNUC__ ) +__attribute__ ((section(".spix_config"), noinline)) +#endif /* __GNUC */ + +#if IAR_SPIX_PRAGMA +#pragma location=".spix_config" // IAR locate function in RAM section .spix_config +#pragma optimize=no_inline // IAR no inline optimization on this function +#endif /* IAR_SPIX_PRAGMA */ + +void SPIX_ConfigFetch(const spix_fetch_t *fetch) +{ + // Configure how the SPIX fetches data + MXC_SPIX->fetch_ctrl = (((fetch->cmd << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_VALUE) | + ((fetch->cmd_width << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) | + ((fetch->addr_width << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) | + ((fetch->data_width << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH) | + ((fetch->addr_size << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS) & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR)); + + // Set the command mode and clocks + MXC_SPIX->mode_ctrl = (((fetch->mode_clocks << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS) & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) | + (!!fetch->no_cmd_mode << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)); + + MXC_SPIX->mode_data = (((fetch->mode_data << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS) & MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS) | + MXC_F_SPIX_MODE_DATA_MODE_DATA_OE); + +#if(MXC_SPIX_REV == 0) + SPIX_UpdateFBIgnore(); +#endif +} + +/******************************************************************************/ +#if defined ( __GNUC__ ) +__attribute__ ((section(".spix_config"), noinline)) +#endif /* __GNUC */ + +#if IAR_SPIX_PRAGMA +#pragma location=".spix_config" // IAR locate function in RAM section .spix_config +#pragma optimize=no_inline // IAR no inline optimization on this function +#endif /* IAR_SPIX_PRAGMA */ + +int SPIX_Shutdown(mxc_spix_regs_t *spix) +{ + int err; + + // Clear system level configurations + if ((err = SYS_SPIX_Shutdown()) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.h new file mode 100644 index 00000000000..e13fb87456b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.h @@ -0,0 +1,140 @@ +/** + * @file + * @brief This is the high level API for the SPI Execute in Place (SPIX) + * module. + * @note If using this SPIX with IAR Embedded Workbench for ARM, it is + * required to define IAR_SPIX_PRAGMA=1. This should be + * done under Project->Options-> C/C++ Compiler->Preprocessor in the + * Defined Symbols input box. See the IAR documentation for + * additional information on how to set a preprocessor define in a + * project. + */ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:45:55 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24674 $ + * + **************************************************************************** */ + + + +#include "mxc_sys.h" +#include "spix_regs.h" + +/* Define to prevent redundant inclusion */ +#ifndef _SPIX_H_ +#define _SPIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup spix SPIX + * @brief SPI Execute In Place. + * @{ + */ + +/* **** Definitions **** */ +/// @brief Options for number of I/O pins to use during for each fetch stage +typedef enum { + SPIX_SINGLE_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE, + SPIX_DUAL_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO, + SPIX_QUAD_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO +} spix_width_t; + +/// @brief Options for number of address bytes to use during fetch +typedef enum { + SPIX_3BYTE_FETCH_ADDR = 0, + SPIX_4BYTE_FETCH_ADDR = 1 +} spix_addr_size_t; + +/// @brief SPIX fetch configuration. +typedef struct { + spix_width_t cmd_width; ///< Number of I/O lines used for command SPI transaction. + spix_width_t addr_width; ///< Number of I/O lines used for address SPI transaction. + spix_width_t data_width; ///< Number of I/O lines used for data SPI transaction. + spix_addr_size_t addr_size; ///< Use 3 or 4 byte addresses for fetches. + uint8_t cmd; ///< Command value to initiate fetch. + uint8_t mode_clocks; ///< Number of SPI clocks required during mode phase of fetch. + uint8_t no_cmd_mode; ///< Read command sent only once. + uint16_t mode_data; ///< Data sent with mode clocks. +} spix_fetch_t; + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + + /** + * @brief Configure SPI execute in place clocking. + * @param sys_cfg Pointer to system level configuration structure. + * @param baud Frequency in hertz to set the clock to. May not be able + * to achieve with the given clock divider. + * @param sample Number of SPIX clocks to delay the sampling of the SDIO + * lines. Will use feedback mode if set to 0. + * @return #E_NO_ERROR if everything is successful + */ +int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample); + +/** + * @brief Configure SPI execute in place slave select. + * @param ssel Index of which slave select line to use. + * @param pol Polarity of slave select (0 for active low, 1 for + * active high). + * @param act_delay SPIX clocks between slave select assert and active + * SPI clock. + * @param inact_delay SPIX clocks between active SPI clock and slave + * select deassert. + */ +void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay); + +/** + * @brief Configure how the SPIX fetches data. + * @param fetch Pointer to configuration struct that describes how to + * fetch data. + */ +void SPIX_ConfigFetch(const spix_fetch_t *fetch); + +/** + * @brief Shutdown SPIX module. + * @param spix Pointer to SPIX regs. + * @return #E_NO_ERROR if everything is successful + */ +int SPIX_Shutdown(mxc_spix_regs_t *spix); + +/**@} end of group spix */ +#ifdef __cplusplus +} +#endif + +#endif /* _SPIX_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c new file mode 100644 index 00000000000..957ac264084 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c @@ -0,0 +1,399 @@ +/** + * @file + * @brief Timer Peripheral Driver Source. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:30:35 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24322 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" + +/** + * @ingroup tmr + * @{ + */ +static tmr_prescale_t prescaler[MXC_CFG_TMR_INSTANCES]; + +/* ************************************************************************* */ +int TMR_Init(mxc_tmr_regs_t *tmr, tmr_prescale_t prescale, const sys_cfg_tmr_t *sysCfg) +{ + int err; + int tmrNum; + + //get the timer number + tmrNum = MXC_TMR_GET_IDX(tmr); + + //check for valid pointer + MXC_ASSERT(tmrNum >= 0); + + //steup system GPIO config + if((err = SYS_TMR_Init(tmr, sysCfg)) != E_NO_ERROR) + return err; + + //save the prescale value for this timer + prescaler[tmrNum] = prescale; + + //Disable timer and clear settings + tmr->ctrl = 0; + + //reset all counts to 0 + tmr->count32 = 0; + tmr->count16_0 = 0; + tmr->count16_1 = 0; + + // Clear interrupt flag + tmr->intfl = MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void TMR32_Config(mxc_tmr_regs_t *tmr, const tmr32_cfg_t *config) +{ + //stop timer + TMR32_Stop(tmr); + + //setup timer configuration register + //clear tmr2x16 (32bit mode), mode and polarity bits + tmr->ctrl &= ~(MXC_F_TMR_CTRL_TMR2X16 | MXC_F_TMR_CTRL_MODE | + MXC_F_TMR_CTRL_POLARITY); + + //set mode and polarity + tmr->ctrl |= ((config->mode << MXC_F_TMR_CTRL_MODE_POS) | + (config->polarity << MXC_F_TMR_CTRL_POLARITY_POS)); + + //setup timer Tick registers + tmr->term_cnt32 = config->compareCount; + + return; +} + +/* ************************************************************************* */ +void TMR32_PWMConfig(mxc_tmr_regs_t *tmr, const tmr32_cfg_pwm_t *config) +{ + //stop timer + TMR32_Stop(tmr); + + //setup timer configuration register + //clear tmr2x16 (32bit mode), mode and polarity bits + tmr->ctrl &= ~(MXC_F_TMR_CTRL_TMR2X16 | MXC_F_TMR_CTRL_MODE | + MXC_F_TMR_CTRL_POLARITY); + + //set mode and polarity + tmr->ctrl |= ((TMR32_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) | + (config->polarity << MXC_F_TMR_CTRL_POLARITY_POS)); + + tmr->pwm_cap32 = config->dutyCount; + + //setup timer Tick registers + tmr->count32 = 0; + tmr->term_cnt32 = config->periodCount; + + return; +} + +/* ************************************************************************* */ +void TMR16_Config(mxc_tmr_regs_t *tmr, uint8_t index, const tmr16_cfg_t *config) +{ + //stop timer + TMR16_Stop(tmr, index); + + if(index > 0) { //configure timer 16_1 + + //setup timer configuration register + tmr->ctrl |= MXC_F_TMR_CTRL_TMR2X16; //1 = 16bit mode + + //set mode + if(config->mode) + tmr->ctrl |= MXC_F_TMR_CTRL_MODE_16_1; + else + tmr->ctrl &= ~MXC_F_TMR_CTRL_MODE_16_1; + + //setup timer Ticks registers + tmr->term_cnt16_1 = config->compareCount; + } else { //configure timer 16_0 + + //setup timer configuration register + tmr->ctrl |= MXC_F_TMR_CTRL_TMR2X16; //1 = 16bit mode + + //set mode + if(config->mode) + tmr->ctrl |= MXC_F_TMR_CTRL_MODE_16_0; + else + tmr->ctrl &= ~MXC_F_TMR_CTRL_MODE_16_0; + + //setup timer Ticks registers + tmr->term_cnt16_0 = config->compareCount; + } + + return; +} + +/* ************************************************************************* */ +void TMR32_Start(mxc_tmr_regs_t *tmr) +{ + int tmrNum; + uint32_t ctrl; + + //get the timer number + tmrNum = MXC_TMR_GET_IDX(tmr); + + //prescaler gets reset to 0 when timer is disabled + //set the prescale to the saved value for this timer + ctrl = tmr->ctrl; + ctrl &= ~(MXC_F_TMR_CTRL_PRESCALE); //clear prescaler bits + ctrl |= prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS; //set prescaler + ctrl |= MXC_F_TMR_CTRL_ENABLE0; //set enable to start the timer + + tmr->ctrl = ctrl; + + return; +} + +/* ************************************************************************* */ +void TMR16_Start(mxc_tmr_regs_t *tmr, uint8_t index) +{ + int tmrNum; + uint32_t ctrl; + + //get the timer number + tmrNum = MXC_TMR_GET_IDX(tmr); + + ctrl = tmr->ctrl; + + //prescaler gets reset to 0 when both 16 bit timers are disabled + //set the prescale to the saved value for this timer if is is not already set + if((ctrl & MXC_F_TMR_CTRL_PRESCALE) != (uint32_t)(prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS)) { + ctrl &= ~(MXC_F_TMR_CTRL_PRESCALE); //clear prescaler bits + ctrl |= prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS; //set prescaler + } + + if(index > 0) + ctrl |= MXC_F_TMR_CTRL_ENABLE1; //start timer 16_1 + else + ctrl |= MXC_F_TMR_CTRL_ENABLE0; //start timer 16_0 + + tmr->ctrl = ctrl; + + return; +} + +/* ************************************************************************* */ +uint32_t TMR_GetPrescaler(mxc_tmr_regs_t *tmr) +{ + int tmrNum; + + //get the timer number + tmrNum = MXC_TMR_GET_IDX(tmr); + + return ((uint32_t)prescaler[tmrNum]); +} + + +/* ************************************************************************* */ +int TMR32_GetPWMTicks(mxc_tmr_regs_t *tmr, uint8_t dutyPercent, uint32_t freq, uint32_t *dutyTicks, uint32_t *periodTicks) +{ + uint32_t timerClock; + uint32_t prescale; + uint64_t ticks; + + if(dutyPercent > 100) + return E_BAD_PARAM; + + if(freq == 0) + return E_BAD_PARAM; + + timerClock = SYS_TMR_GetFreq(tmr); + prescale = TMR_GetPrescaler(tmr); + + if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12) + return E_UNINITIALIZED; + + ticks = timerClock / (1 << (prescale & 0xF)) / freq; + + //make sure ticks is within a 32 bit value + if (!(ticks & 0xffffffff00000000) && (ticks & 0xffffffff)) { + *periodTicks = ticks; + + *dutyTicks = ((uint64_t)*periodTicks * dutyPercent) / 100; + + return E_NO_ERROR; + } + + return E_INVALID; +} + +/* ************************************************************************* */ +int TMR32_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks) +{ + uint32_t unit_div0, unit_div1; + uint32_t timerClock; + uint32_t prescale; + uint64_t temp_ticks; + + timerClock = SYS_TMR_GetFreq(tmr); + prescale = TMR_GetPrescaler(tmr); + + if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12) + return E_UNINITIALIZED; + + switch (units) { + case TMR_UNIT_NANOSEC: + unit_div0 = 1000000; + unit_div1 = 1000; + break; + case TMR_UNIT_MICROSEC: + unit_div0 = 1000; + unit_div1 = 1000; + break; + case TMR_UNIT_MILLISEC: + unit_div0 = 1; + unit_div1 = 1000; + break; + case TMR_UNIT_SEC: + unit_div0 = 1; + unit_div1 = 1; + break; + default: + return E_BAD_PARAM; + } + + temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF))); + + //make sure ticks is within a 32 bit value + if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) { + *ticks = temp_ticks; + return E_NO_ERROR; + } + + return E_INVALID; +} + +/* ************************************************************************* */ +int TMR16_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint16_t *ticks) +{ + uint32_t unit_div0, unit_div1; + uint32_t timerClock; + uint32_t prescale; + uint64_t temp_ticks; + + timerClock = SYS_TMR_GetFreq(tmr); + prescale = TMR_GetPrescaler(tmr); + + if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12) + return E_UNINITIALIZED; + + switch (units) { + case TMR_UNIT_NANOSEC: + unit_div0 = 1000000; + unit_div1 = 1000; + break; + case TMR_UNIT_MICROSEC: + unit_div0 = 1000; + unit_div1 = 1000; + break; + case TMR_UNIT_MILLISEC: + unit_div0 = 1; + unit_div1 = 1000; + break; + case TMR_UNIT_SEC: + unit_div0 = 1; + unit_div1 = 1; + break; + default: + return E_BAD_PARAM; + } + + temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF))); + + //make sure ticks is within a 32 bit value + if (!(temp_ticks & 0xffffffffffff0000) && (temp_ticks & 0xffff)) { + *ticks = temp_ticks; + return E_NO_ERROR; + } + + return E_INVALID; +} + + +/* ************************************************************************* */ +int TMR_TicksToTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units) +{ + uint64_t temp_time = 0; + + uint32_t timerClock = SYS_TMR_GetFreq(tmr); + uint32_t prescale = TMR_GetPrescaler(tmr); + + if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12) + return E_UNINITIALIZED; + + tmr_unit_t temp_unit = TMR_UNIT_NANOSEC; + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000); + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = temp_unit; + return E_NO_ERROR; + } + + temp_unit = TMR_UNIT_MICROSEC; + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000); + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = temp_unit; + return E_NO_ERROR; + } + + temp_unit = TMR_UNIT_MILLISEC; + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock; + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = temp_unit; + return E_NO_ERROR; + } + + temp_unit = TMR_UNIT_SEC; + temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock; + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = temp_unit; + return E_NO_ERROR; + } + + return E_INVALID; +} +/**@} end of ingroup tmr */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h new file mode 100644 index 00000000000..a9b15fe7038 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h @@ -0,0 +1,611 @@ +/** + * @file + * @brief Timer0 & Timer1 32/16-Bit Peripheral Driver. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24675 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _TIMER_H +#define _TIMER_H + +/* **** Includes **** */ +#include "mxc_config.h" +#include "tmr_regs.h" +#include "mxc_sys.h" + +/* **** Extern CPP **** */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup periphlibs + * @defgroup tmr Timers + * @brief 32/16-bit Timers + * @{ + */ + +/** + * Enumeration type for units of time. + */ +typedef enum { + TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */ + TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */ + TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */ + TMR_UNIT_SEC, /**< Second Unit Indicator. */ +} tmr_unit_t; + +/** + * Enumeration type to select the 32-bit Timer Mode. + */ +typedef enum { + TMR32_MODE_ONE_SHOT = MXC_V_TMR_CTRL_MODE_ONE_SHOT, /**< One-shot Mode */ + TMR32_MODE_CONTINUOUS = MXC_V_TMR_CTRL_MODE_CONTINUOUS, /**< Continuous Mode */ + TMR32_MODE_COUNTER = MXC_V_TMR_CTRL_MODE_COUNTER, /**< Counter Mode */ + TMR32_MODE_PWM = MXC_V_TMR_CTRL_MODE_PWM, /**< Pulse Width Modulation Mode */ + TMR32_MODE_CAPTURE = MXC_V_TMR_CTRL_MODE_CAPTURE, /**< Capture Mode */ + TMR32_MODE_COMPARE = MXC_V_TMR_CTRL_MODE_COMPARE, /**< Compare Mode */ + TMR32_MODE_GATED = MXC_V_TMR_CTRL_MODE_GATED, /**< Gated Mode */ + TMR32_MODE_MEASURE = MXC_V_TMR_CTRL_MODE_MEASURE /**< Measure Mode */ +} tmr32_mode_t; + +/** + * Enumeration type to select a 16-bit Timer Mode. + * @note 16-bit times only support One Shot and Continuous timers. + */ +typedef enum { + TMR16_MODE_ONE_SHOT = MXC_V_TMR_CTRL_MODE_ONE_SHOT, /**< One-Shot Mode. */ + TMR16_MODE_CONTINUOUS = MXC_V_TMR_CTRL_MODE_CONTINUOUS /**< Continuous Mode. */ +} tmr16_mode_t; + +/** + * Enumeration type to select the Prescale Divider for the timer module. The prescaler + * divides the peripheral input clock to the timer by a selectable divisor. + */ +typedef enum { + TMR_PRESCALE_DIV_2_0 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0} = 1 \f$ */ + TMR_PRESCALE_DIV_2_1 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1} = 2 \f$ */ + TMR_PRESCALE_DIV_2_2 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2} = 4 \f$ */ + TMR_PRESCALE_DIV_2_3 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3} = 8 \f$ */ + TMR_PRESCALE_DIV_2_4 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4} = 16 \f$ */ + TMR_PRESCALE_DIV_2_5 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5} = 32 \f$ */ + TMR_PRESCALE_DIV_2_6 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6} = 64 \f$ */ + TMR_PRESCALE_DIV_2_7 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7} = 128 \f$ */ + TMR_PRESCALE_DIV_2_8 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8} = 256 \f$ */ + TMR_PRESCALE_DIV_2_9 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9} = 512 \f$ */ + TMR_PRESCALE_DIV_2_10 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */ + TMR_PRESCALE_DIV_2_11 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */ + TMR_PRESCALE_DIV_2_12 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */ +} tmr_prescale_t; + +/** + * Enumeration type to set the polarity bit for pwm timer. + */ +typedef enum { + TMR_POLARITY_UNUSED = 0, /**< @internal Unused polarity @endinternal */ + + TMR_POLARITY_INIT_LOW = 0, /**< GPIO initial output level = low */ + TMR_POLARITY_INIT_HIGH = 1, /**< GPIO initial output level = high */ + + TMR_POLARITY_RISING_EDGE = 0, /**< timer trigger on GPIO rising edge */ + TMR_POLARITY_FALLING_EDGE = 1, /**< timer trigger on GPIO falling edge */ +} tmr_polarity_t; + +/** + * Enumeration type to set the polarity bit for pwm timer. + */ +typedef enum { + TMR_PWM_INVERTED = 0, /**< duty cycle = low pulse */ + TMR_PWM_NONINVERTED, /**< duty cycle = high pulse */ +} tmr_pwm_polarity_t; + +/** + * Structure type for Configuring a 32-bit timer in all modes except PWM. + */ +typedef struct { + tmr32_mode_t mode; /**< Desired timer mode, see #tmr32_mode_t for valid modes. @note If PWM mode is desired, setting the mode to TMR32_MODE_PWM is valid. To configure PWM Mode, see #tmr32_cfg_pwm_t. */ + tmr_polarity_t polarity; /**< Polarity for GPIO */ + uint32_t compareCount; /**< Ticks to stop, reset back to 1, or compare timer */ +} tmr32_cfg_t; + +/** + * Structure type for Configuring PWM Mode for a 32-bit timer. + */ +typedef struct { + tmr_pwm_polarity_t polarity; /**< PWM polarity selection, see #tmr_pwm_polarity_t. */ + uint32_t periodCount; /**< PWM period in number of timer ticks. */ + uint32_t dutyCount; /**< PWM duty cycle in number of timer ticks. */ +} tmr32_cfg_pwm_t; + +/** + * Structure type for Configuring a 16-bit Timer. + */ +typedef struct { + tmr16_mode_t mode; /**< 16-bit timer mode, see #tmr16_mode_t for supported modes. */ + uint16_t compareCount; /**< Number of timer ticks to either stop or reset the timer. */ +} tmr16_cfg_t; + + + +/** + * @brief Initializes the timer to a known state. + * @details This function initializes the timer to a known state and saves + * the prescaler. The timer will be left disabled. TMR_Init should + * be called before TMR_Config. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param prescale clock divider for the timer clock + * @param sysCfg Pointer to the timer system GPIO configuration. If not + * using GPIO for the timer instance, set this parameter + * to NULL. + * + * @retval #E_NO_ERROR Timer initialized successfully. + * @retval Error Code Timer was not initialized, see @ref MXC_Error_Codes. + */ +int TMR_Init(mxc_tmr_regs_t *tmr, tmr_prescale_t prescale, const sys_cfg_tmr_t *sysCfg); + +/** + * @brief Configures the timer in the specified mode. + * @details The parameters in config structure must be set before calling + * this function. This function should be used for configuring the + * timer in all 32 bit modes other than PWM. + * @note The timer cannot be running when this function is called + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param config pointer to timer configuration + */ +void TMR32_Config(mxc_tmr_regs_t *tmr, const tmr32_cfg_t *config); + +/** + * @brief Configures the timer in PWM mode. + * @details The parameters in config structure must be set before calling + * this function. This function should be used for configuring the + * timer in PWM mode only. + * @note The timer cannot be running when this function is called + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param config pointer to timer configuration + */ +void TMR32_PWMConfig(mxc_tmr_regs_t *tmr, const tmr32_cfg_pwm_t *config); + +/** + * @brief Configures the timer in the specified mode. + * @details The parameters in config structure must be set before calling + * this function. This function should be used for configuring the + * timer in all 16 bit modes. + * @note The timer cannot be running when this function is called + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * @param config pointer to timer configuration + */ +void TMR16_Config(mxc_tmr_regs_t *tmr, uint8_t index, const tmr16_cfg_t *config); + +/** + * @brief Starts the specified timer. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + */ +void TMR32_Start(mxc_tmr_regs_t *tmr); + +/** + * @brief Starts the specified timer. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + */ +void TMR16_Start(mxc_tmr_regs_t *tmr, uint8_t index); + +/** + * @brief Stops the specified 32 bit timer. + * @details All other timer states are left unchanged. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + */ +__STATIC_INLINE void TMR32_Stop(mxc_tmr_regs_t *tmr) +{ + tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; +} + +/** + * @brief Stop the specified 16 bit timer. + * @details All other timer states are left unchanged. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + */ +__STATIC_INLINE void TMR16_Stop(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE1; + else + tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; +} + +/** + * @brief Determines if the timer is running + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * + * @return 0 = timer is off, non-zero = timer is on + */ +__STATIC_INLINE uint32_t TMR32_IsActive(mxc_tmr_regs_t *tmr) +{ + return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE0); +} + +/** + * @brief Determines if the timer is running + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * + * @return 0 Timer is off. + * @return Non-zero Timer is on. + */ +__STATIC_INLINE uint32_t TMR16_IsActive(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE1); + else + return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE0); +} + +/** + * @brief Enables the timer's interrupt + * + * @param tmr Pointer to timer registers for the timer instance to modify. + */ +__STATIC_INLINE void TMR32_EnableINT(mxc_tmr_regs_t *tmr) +{ + tmr->inten |= MXC_F_TMR_INTEN_TIMER0; +} + +/** + * @brief Enables the timer's interrupt + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + */ +__STATIC_INLINE void TMR16_EnableINT(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + tmr->inten |= MXC_F_TMR_INTEN_TIMER1; + else + tmr->inten |= MXC_F_TMR_INTEN_TIMER0; +} + +/** + * @brief Disables the timer's interrupt + * + * @param tmr Pointer to timer registers for the timer instance to modify. + */ +__STATIC_INLINE void TMR32_DisableINT(mxc_tmr_regs_t *tmr) +{ + tmr->inten &= ~MXC_F_TMR_INTEN_TIMER0; +} + +/** + * @brief Disables the timer's interrupt + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + */ +__STATIC_INLINE void TMR16_DisableINT(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + tmr->inten &= ~MXC_F_TMR_INTEN_TIMER1; + else + tmr->inten &= ~MXC_F_TMR_INTEN_TIMER0; +} + +/** + * @brief Gets the timer's interrupt flag + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * + * @return 0 = flag not set, non-zero = flag is set + */ +__STATIC_INLINE uint32_t TMR32_GetFlag(mxc_tmr_regs_t *tmr) +{ + return (tmr->intfl & MXC_F_TMR_INTFL_TIMER0); +} + +/** + * @brief Gets the timer's interrupt flag + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * + * @return 0 = flag not set, non-zero = flag is set + */ +__STATIC_INLINE uint32_t TMR16_GetFlag(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + return (tmr->intfl & MXC_F_TMR_INTFL_TIMER1); + else + return (tmr->intfl & MXC_F_TMR_INTFL_TIMER0); +} + +/** + * @brief Clears the timer interrupt flag + * + * @param tmr Pointer to timer registers for the timer instance to modify. + */ +__STATIC_INLINE void TMR32_ClearFlag(mxc_tmr_regs_t *tmr) +{ + tmr->intfl = MXC_F_TMR_INTFL_TIMER0; +} + +/** + * @brief Clears the timer interrupt flag for the specified index + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + */ +__STATIC_INLINE void TMR16_ClearFlag(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + tmr->intfl = MXC_F_TMR_INTFL_TIMER1; + else + tmr->intfl = MXC_F_TMR_INTFL_TIMER0; +} + +/** + * @brief Set the current tick value to start counting from. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param count value to set the current ticks + */ +__STATIC_INLINE void TMR32_SetCount(mxc_tmr_regs_t *tmr, uint32_t count) +{ + tmr->count32 = count; +} + +/** + * @brief Set the current tick value to start counting from. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * @param count value to set the current ticks + */ +__STATIC_INLINE void TMR16_SetCount(mxc_tmr_regs_t *tmr, uint8_t index, uint16_t count) +{ + if (index) + tmr->count16_1 = count; + else + tmr->count16_0 = count; +} + +/** + * @brief Gets the most current count value. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * + * @return current count value in ticks + */ +__STATIC_INLINE uint32_t TMR32_GetCount(mxc_tmr_regs_t *tmr) +{ + return (tmr->count32); +} + +/** + * @brief Gets the most current count value. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer(0 = 16_0 or 1 = 16_1) + * + * @return current count value in ticks + */ +__STATIC_INLINE uint32_t TMR16_GetCount(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if(index) + return tmr->count16_1; + else + return tmr->count16_0; +} + +/** + * @brief Gets the most recent capture value. + * @details Used in Capture or Measure timer modes + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * + * @return capture value in ticks + */ +__STATIC_INLINE uint32_t TMR32_GetCapture(mxc_tmr_regs_t *tmr) +{ + return (tmr->pwm_cap32); +} + +/** + * @brief Set a new compare tick value for timer + * @details Depending on the timer mode this is the tick value to stop the + * timer, reset ticks to 1, or compare the timer + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param count new terminal/compare value in timer counts + */ +__STATIC_INLINE void TMR32_SetCompare(mxc_tmr_regs_t *tmr, uint32_t count) +{ + tmr->term_cnt32 = count; +} + +/** + * @brief Get compare tick value for timer + * @param tmr Pointer to timer registers for the timer instance to modify. + * @return compare value in ticks + */ +__STATIC_INLINE uint32_t TMR32_GetCompare(mxc_tmr_regs_t *tmr) +{ + return tmr->term_cnt32; +} + +/** + * @brief Set a new compare tick value for timer + * @details Depending on the timer mode this is the tick value to stop the + * timer, reset ticks to 1, or compare the timer + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * @param count new terminal/compare value in timer counts + */ +__STATIC_INLINE void TMR16_SetCompare(mxc_tmr_regs_t *tmr, uint8_t index, uint16_t count) +{ + if (index) + tmr->term_cnt16_1 = count; + else + tmr->term_cnt16_0 = count; +} + +/** + * @brief Get compare tick value for timer + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1) + * @return compare value in ticks + */ +__STATIC_INLINE uint32_t TMR16_GetCompare(mxc_tmr_regs_t *tmr, uint8_t index) +{ + if (index) + return tmr->term_cnt16_1; + return tmr->term_cnt16_0; +} + +/** + * @brief Returns the prescale value used by the timer + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * + * @return prescaler + */ +uint32_t TMR_GetPrescaler(mxc_tmr_regs_t *tmr); + +/** + * @brief Set a new duty cycle when the timer is used in PWM mode. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param dutyCount duty cycle value in timer counts + */ +__STATIC_INLINE void TMR32_SetDuty(mxc_tmr_regs_t *tmr, uint32_t dutyCount) +{ + tmr->pwm_cap32 = dutyCount; +} + +/** + * @brief Set a new duty cycle when the timer is used in PWM mode. + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param dutyPercent duty cycle value in percent (0 to 100%) + */ +__STATIC_INLINE void TMR32_SetDutyPer(mxc_tmr_regs_t *tmr, uint32_t dutyPercent) +{ + uint32_t periodCount = tmr->term_cnt32; + tmr->pwm_cap32 = ((uint64_t)periodCount * dutyPercent) / 100; +} + +/** + * @brief Set a new period value for PWM timer + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param period new period value in timer counts + */ +__STATIC_INLINE void TMR32_SetPeriod(mxc_tmr_regs_t *tmr, uint32_t period) +{ + tmr->term_cnt32 = period; +} + +/** + * @brief Converts frequency and duty cycle % to period and duty ticks + * @note TMR_Init should be called before this function to set the prescaler + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param dutyPercent duty cycle in percent (0 to 100%) + * @param freq frequency of pwm signal in Hz + * @param dutyTicks calculated duty cycle in ticks + * @param periodTicks calculated period in ticks + * + * @returns #E_NO_ERROR if everything is successful, error if unsuccessful. + * + */ +int TMR32_GetPWMTicks(mxc_tmr_regs_t *tmr, uint8_t dutyPercent, uint32_t freq, uint32_t *dutyTicks, uint32_t *periodTicks); + +/** + * @brief Converts a time and units to a number of ticks for the 32-bit timer. + * @note TMR_Init should be called before this function to set the prescaler + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param time time value. + * @param units time units. + * @param ticks calculated number of ticks. + * + * @returns #E_NO_ERROR if everything is successful, error if unsuccessful. + */ +int TMR32_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks); + +/** + * @brief Converts a time and units to a number of ticks for the 16-bit timer. + * @note TMR_Init should be called before this function to set the prescaler + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param time time value. + * @param units time units. + * @param ticks calculated number of ticks. + * + * @returns #E_NO_ERROR if everything is successful, error if unsuccessful. + */ +int TMR16_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint16_t *ticks); + +/** + * @brief Converts a number of ticks to a time and units for the timer. + * @note TMR_Init should be called before this function to set the prescaler + * + * @param tmr Pointer to timer registers for the timer instance to modify. + * @param ticks number of ticks. + * @param time calculated time value. + * @param units calculated time units. + * + * @returns #E_NO_ERROR if everything is successful, error if unsuccessful. + */ +int TMR_TicksToTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TIMER_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.c new file mode 100644 index 00000000000..fe109ac9e64 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.c @@ -0,0 +1,174 @@ +/** + * @file + * @brief Timer utility functions. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:30:35 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24322 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" +#include "tmr_utils.h" + + +/** + * @ingroup tmr_utilities + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************** */ +void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us) +{ + TMR_TO_Start(tmr, us); + + while(TMR_TO_Check(tmr) != E_TIME_OUT) {} +} + +/* ************************************************************************** */ +void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us) +{ + unsigned clk_shift = 0; + uint64_t max_us; + uint32_t ticks; + + // Adjust the clk shift amout by how long the timeout is + // Start with the fastest clock to give the greatest accuracy + do { + max_us = (uint64_t)((0xFFFFFFFFUL / ((uint64_t)SystemCoreClock >> clk_shift++)) * 1000000UL); + } while(us > max_us); + + // Calculate the number of timer ticks we need to wait + TMR_Init(tmr, (tmr_prescale_t)clk_shift, NULL); + TMR32_TimeToTicks(tmr, us, TMR_UNIT_MICROSEC, &ticks); + + // Initialize the timer in one-shot mode + tmr32_cfg_t cfg; + cfg.mode = TMR32_MODE_ONE_SHOT; + cfg.compareCount = ticks; + TMR32_Stop(tmr); + TMR32_Config(tmr, &cfg); + + TMR32_ClearFlag(tmr); + TMR32_Start(tmr); +} + +/* ************************************************************************** */ +int TMR_TO_Check(mxc_tmr_regs_t* tmr) +{ + if(TMR32_GetFlag(tmr)) { + return E_TIME_OUT; + } + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void TMR_TO_Stop(mxc_tmr_regs_t* tmr) +{ + TMR32_Stop(tmr); + TMR32_SetCount(tmr, 0x0); +} + +/* ************************************************************************** */ +void TMR_TO_Clear(mxc_tmr_regs_t* tmr) +{ + TMR32_ClearFlag(tmr); + TMR32_SetCount(tmr, 0x0); +} + +/* ************************************************************************** */ +unsigned TMR_TO_Elapsed(mxc_tmr_regs_t* tmr) +{ + uint32_t elapsed; + tmr_unit_t units; + + TMR_TicksToTime(tmr, TMR32_GetCount(tmr), &elapsed, &units); + + switch(units) { + case TMR_UNIT_NANOSEC: + default: + return (elapsed / 1000); + case TMR_UNIT_MICROSEC: + return (elapsed); + case TMR_UNIT_MILLISEC: + return (elapsed * 1000); + case TMR_UNIT_SEC: + return (elapsed * 1000000); + } +} + +/* ************************************************************************** */ +unsigned TMR_TO_Remaining(mxc_tmr_regs_t* tmr) +{ + uint32_t remaining_ticks, remaining_time; + tmr_unit_t units; + + remaining_ticks = TMR32_GetCompare(tmr) - TMR32_GetCount(tmr); + TMR_TicksToTime(tmr, remaining_ticks, &remaining_time, &units); + + switch(units) { + case TMR_UNIT_NANOSEC: + default: + return (remaining_time / 1000); + case TMR_UNIT_MICROSEC: + return (remaining_time); + case TMR_UNIT_MILLISEC: + return (remaining_time * 1000); + case TMR_UNIT_SEC: + return (remaining_time * 1000000); + } +} + +/* ************************************************************************** */ +void TMR_SW_Start(mxc_tmr_regs_t* tmr) +{ + TMR_TO_Start(tmr, 0xFFFFFFFF); +} + +/* ************************************************************************** */ +unsigned TMR_SW_Stop(mxc_tmr_regs_t* tmr) +{ + unsigned elapsed = TMR_TO_Elapsed(tmr); + TMR_TO_Stop(tmr); + return elapsed; +} +/** @} end of ingroup tmr_utilities */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h new file mode 100644 index 00000000000..c401ff04ed8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h @@ -0,0 +1,136 @@ +/** + * @file + * @brief Timer utility functions. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24675 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _TMR_UTILS_H +#define _TMR_UTILS_H + +/***** Includes *****/ +#include "mxc_config.h" +#include "tmr_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup tmr + * @defgroup tmr_utils Timer Utility Functions + * @{ + */ +/* **** Definitions **** */ +/** Macro to convert the parameter \p s from seconds to micro-seconds. */ +#define SEC(s) (((unsigned long)s) * 1000000UL) +/** Macro to convert the parameter \p ms from milli-seconds to micro-seconds. */ +#define MSEC(ms) (ms * 1000UL) +/** Macro to convert the parameter \p us to micro-seconds. */ +#define USEC(us) (us) + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Delays for the specified number of microseconds. + * @param tmr TMR module to operate on + * @param us Number of microseconds to delay. + */ +void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us); + +/** + * @brief Start the timeout time for the specified number of microseconds. + * @param tmr TMR module to operate on + * @param us Number of microseconds in the timeout. + */ +void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); + +/** + * @brief Check if the timeout has occured. + * @param tmr TMR module to operate on + * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has. + */ +int TMR_TO_Check(mxc_tmr_regs_t* tmr); + +/** + * @brief Stops the timer for the timeout. + * @param tmr TMR module to operate on + */ +void TMR_TO_Stop(mxc_tmr_regs_t* tmr); + +/** + * @brief Clears the timeout flag. + * @param tmr TMR module to operate on + */ +void TMR_TO_Clear(mxc_tmr_regs_t* tmr); + +/** + * @brief Get the number of microseconds elapsed since TMR_TO_Start(). + * @param tmr TMR module to operate on + * @return Number of microseconds since TMR_TO_Start(). + */ +unsigned TMR_TO_Elapsed(mxc_tmr_regs_t* tmr); + +/** + * @brief Get the number of microseconds remaining in the timeout. + * @param tmr TMR module to operate on + * @return Number of microseconds since TMR_TO_Start(). + */ +unsigned TMR_TO_Remaining(mxc_tmr_regs_t* tmr); + +/** + * @brief Start the stopwatch. + * @param tmr TMR module to operate on + */ +void TMR_SW_Start(mxc_tmr_regs_t* tmr); + +/** + * @brief Stop the stopwatch and return the number of microseconds that + * have elapsed. + * @param tmr TMR module to operate on + * @return Number of microseconds since TMR_TO_Start(). + */ +unsigned TMR_SW_Stop(mxc_tmr_regs_t* tmr); +/**@} end of defgroup tmr_utils*/ +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_UTILS_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c new file mode 100644 index 00000000000..9298a04bebb --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c @@ -0,0 +1,661 @@ +/** + * @file + * @brief This file contains the function implementations for the UART + * serial communications peripheral module. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:00:36 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24319 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "uart.h" + +/** + * @ingroup uart_comm + * @{ + */ +/* **** Definitions **** */ +///@cond +#define UART_ERRORS (MXC_F_UART_INTEN_RX_FIFO_OVERFLOW | \ + MXC_F_UART_INTEN_RX_FRAMING_ERR | \ + MXC_F_UART_INTEN_RX_PARITY_ERR) + +#define UART_READ_INTS (MXC_F_UART_INTEN_RX_FIFO_AF | \ + MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | \ + MXC_F_UART_INTEN_RX_STALLED | \ + UART_ERRORS) + +#define UART_WRITE_INTS (MXC_F_UART_INTEN_TX_UNSTALLED | \ + MXC_F_UART_INTEN_TX_FIFO_AE) + +#define UART_RXFIFO_USABLE (MXC_UART_FIFO_DEPTH-3) +///@endcond +// +/* **** Globals **** */ + +// Saves the state of the non-blocking read requests +static uart_req_t *rx_states[MXC_CFG_UART_INSTANCES]; + +// Saves the state of the non-blocking write requests +static uart_req_t *tx_states[MXC_CFG_UART_INSTANCES]; + +/* **** Functions **** */ +static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num); +static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num, + uint32_t flags); + +/* ************************************************************************* */ +int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg) +{ + int err; + int uart_num; + uint32_t uart_clk; + uint8_t baud_shift; + uint16_t baud_div; + uint32_t baud, diff_baud; + uint32_t baud_1, diff_baud_1; + + // Check the input parameters + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + // Set system level configurations + if(sys_cfg != NULL) { + if ((err = SYS_UART_Init(uart, cfg, sys_cfg)) != E_NO_ERROR) { + return err; + } + } + + // Initialize state pointers + rx_states[uart_num] = NULL; + tx_states[uart_num] = NULL; + + // Drain FIFOs and enable UART + uart->ctrl = 0; + uart->ctrl = (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN | + MXC_F_UART_CTRL_RX_FIFO_EN | + (UART_RXFIFO_USABLE << MXC_F_UART_CTRL_RTS_LEVEL_POS)); + + // Configure data size, stop bit, parity, cts, and rts + uart->ctrl |= ((cfg->size << MXC_F_UART_CTRL_DATA_SIZE_POS) | + (cfg->extra_stop << MXC_F_UART_CTRL_EXTRA_STOP_POS) | + (cfg->parity << MXC_F_UART_CTRL_PARITY_POS) | + (cfg->cts << MXC_F_UART_CTRL_CTS_EN_POS) | + (cfg->rts << MXC_F_UART_CTRL_RTS_EN_POS)); + + // Configure the baud rate and divisor + uart_clk = SYS_UART_GetFreq(uart); + MXC_ASSERT(uart_clk > 0); + + baud_shift = 2; + baud_div = (uart_clk / (cfg->baud * 4)); + + // Can not support higher frequencies + if(!baud_div) { + return E_NOT_SUPPORTED; + } + + // Decrease the divisor if baud_div is overflowing + while(baud_div > 0xFF) { + if(baud_shift == 0) { + return E_NOT_SUPPORTED; + } + baud_shift--; + baud_div = (uart_clk / (cfg->baud * (16 >> baud_shift))); + } + + // Adjust baud_div so we don't overflow with the calculations below + if(baud_div == 0xFF) { + baud_div = 0xFE; + } + if(baud_div == 0) { + baud_div = 1; + } + + // Figure out if the truncation increased the error + baud = (uart_clk / (baud_div * (16 >> baud_shift))); + baud_1 = (uart_clk / ((baud_div+1) * (16 >> baud_shift))); + + if(cfg->baud > baud) { + diff_baud = cfg->baud - baud; + } else { + diff_baud = baud - cfg->baud; + } + + if(cfg->baud > baud_1) { + diff_baud_1 = cfg->baud - baud_1; + } else { + diff_baud_1 = baud_1 - cfg->baud; + } + + if(diff_baud < diff_baud_1) { + uart->baud = ((baud_div & MXC_F_UART_BAUD_BAUD_DIVISOR) | + (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS)); + } else { + uart->baud = (((baud_div+1) & MXC_F_UART_BAUD_BAUD_DIVISOR) | + (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS)); + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_Shutdown(mxc_uart_regs_t *uart) +{ + int uart_num, err; + uart_req_t *temp_req; + + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + // Disable and clear interrupts + uart->inten = 0; + uart->intfl = uart->intfl; + + // Disable UART and FIFOS + uart->ctrl &= ~(MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN | + MXC_F_UART_CTRL_RX_FIFO_EN); + + // Call all of the pending callbacks for this UART + if(rx_states[uart_num] != NULL) { + + // Save the request + temp_req = rx_states[uart_num]; + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + // Callback if not NULL + if(temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + if(tx_states[uart_num] != NULL) { + + // Save the request + temp_req = tx_states[uart_num]; + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + // Callback if not NULL + if(temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + // Clears system level configurations + if ((err = SYS_UART_Shutdown(uart)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len) +{ + int num, uart_num; + mxc_uart_fifo_regs_t *fifo; + + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + if(data == NULL) { + return E_NULL_PTR; + } + + // Make sure the UART has been initialized + if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) { + return E_UNINITIALIZED; + } + + if(!(len > 0)) { + return E_NO_ERROR; + } + + // Lock this UART from writing + while(mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {} + + // Get the FIFO for this UART + fifo = MXC_UART_GET_FIFO(uart_num); + + num = 0; + + while(num < len) { + + // Wait for TXFIFO to not be full + while((uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) == + MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) {} + + // Write the data to the FIFO +#if(MXC_UART_REV == 0) + uart->intfl = MXC_F_UART_INTFL_TX_DONE; +#endif + fifo->tx = data[num++]; + } + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + return num; +} + +/* ************************************************************************* */ +int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num) +{ + int num_local, remain, uart_num; + mxc_uart_fifo_regs_t *fifo; + + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + if(data == NULL) { + return E_NULL_PTR; + } + + // Make sure the UART has been initialized + if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) { + return E_UNINITIALIZED; + } + + if(!(len > 0)) { + return E_NO_ERROR; + } + + // Lock this UART from reading + while(mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {} + + // Get the FIFO for this UART + fifo = MXC_UART_GET_FIFO(uart_num); + + num_local = 0; + remain = len; + while(remain) { + + // Save the data in the FIFO + while((uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) && remain) { + data[num_local] = fifo->rx; + num_local++; + remain--; + } + + // Break if there is an error + if(uart->intfl & UART_ERRORS) { + break; + } + } + + // Save the number of bytes read if pointer is valid + if(num != NULL) { + *num = num_local; + } + + // Check for errors + if(uart->intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) { + + // Clear errors and return error code + uart->intfl = UART_ERRORS; + + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + return E_OVERFLOW; + + } else if(uart->intfl & (MXC_F_UART_INTFL_RX_FRAMING_ERR | + MXC_F_UART_INTFL_RX_PARITY_ERR)) { + + // Clear errors and return error code + uart->intfl = UART_ERRORS; + + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + return E_COMM_ERR; + } + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + return num_local; +} + +/* ************************************************************************* */ +int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req) +{ + int uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + // Check the input parameters + if(req->data == NULL) { + return E_NULL_PTR; + } + + // Make sure the UART has been initialized + if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) { + return E_UNINITIALIZED; + } + + if(!(req->len > 0)) { + return E_NO_ERROR; + } + + // Attempt to register this write request + if(mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Clear the number of bytes counter + req->num = 0; + + // Start the write + UART_WriteHandler(uart, req, uart_num); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req) +{ + int uart_num; + uint32_t flags; + + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + if(req->data == NULL) { + return E_NULL_PTR; + } + + // Make sure the UART has been initialized + if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) { + return E_UNINITIALIZED; + } + + if(!(req->len > 0)) { + return E_NO_ERROR; + } + + // Attempt to register this write request + if(mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Clear the number of bytes counter + req->num = 0; + + // Start the read + flags = uart->intfl; + uart->intfl = flags; + UART_ReadHandler(uart, req, uart_num, flags); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_AbortAsync(uart_req_t *req) +{ + int uart_num; + + // Figure out if this was a read or write request, find the request, set to NULL + for(uart_num = 0; uart_num < MXC_CFG_UART_INSTANCES; uart_num++) { + if(req == rx_states[uart_num]) { + + // Disable read interrupts, clear flags. + MXC_UART_GET_UART(uart_num)->inten &= ~UART_READ_INTS; + MXC_UART_GET_UART(uart_num)->intfl = UART_READ_INTS; + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + // Callback if not NULL + if(req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + + if(req == tx_states[uart_num]) { + + // Disable write interrupts, clear flags. + MXC_UART_GET_UART(uart_num)->inten &= ~(UART_WRITE_INTS); + MXC_UART_GET_UART(uart_num)->intfl = UART_WRITE_INTS; + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + // Callback if not NULL + if(req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +/* ************************************************************************* */ +void UART_Handler(mxc_uart_regs_t *uart) +{ + int uart_num; + uint32_t flags; + + uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + flags = uart->intfl; + uart->intfl = flags; + + // Figure out if this UART has an active Read request + if((rx_states[uart_num] != NULL) && (flags & UART_READ_INTS)) { + UART_ReadHandler(uart, rx_states[uart_num], uart_num, flags); + } + + // Figure out if this UART has an active Write request + if((tx_states[uart_num] != NULL) && (flags & (UART_WRITE_INTS))) { + + UART_WriteHandler(uart, tx_states[uart_num], uart_num); + } +} +/* ************************************************************************* */ +int UART_Busy(mxc_uart_regs_t *uart) +{ + int uart_num = MXC_UART_GET_IDX(uart); + MXC_ASSERT(uart_num >= 0); + + // Check to see if there are any ongoing transactions or if the UART is disabled + if(((tx_states[uart_num] == NULL) && + !(uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) && +#if(MXC_UART_REV == 0) + (uart->intfl & MXC_F_UART_INTFL_TX_DONE)) || +#else + (uart->idle & MXC_F_UART_IDLE_TX_RX_IDLE)) || +#endif + !(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) { + + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************* */ +int UART_PrepForSleep(mxc_uart_regs_t *uart) +{ + if(UART_Busy(uart) != E_NO_ERROR) { + return E_BUSY; + } + + // Leave read interrupts enabled, if already enabled + uart->inten &= UART_READ_INTS; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num) +{ + int avail, remain; + mxc_uart_fifo_regs_t *fifo; + + // Disable write interrupts + uart->inten &= ~(UART_WRITE_INTS); + + // Get the FIFO for this UART + fifo = MXC_UART_GET_FIFO(uart_num); + + // Refill the TX FIFO + avail = UART_NumWriteAvail(uart); + remain = req->len - req->num; + + while(avail && remain) { + + // Write the data to the FIFO +#if(MXC_UART_REV == 0) + uart->intfl = MXC_F_UART_INTFL_TX_DONE; +#endif + fifo->tx = req->data[req->num++]; + remain--; + avail--; + } + + // All of the bytes have been written to the FIFO + if(!remain) { + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + if(req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + + } else { + + // Interrupt when there is one byte left in the TXFIFO + uart->tx_fifo_ctrl = ((MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS); + + // Enable almost empty interrupt + uart->inten |= (MXC_F_UART_INTEN_TX_FIFO_AE); + } +} + +/* ************************************************************************* */ +static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num, + uint32_t flags) +{ + int avail, remain; + mxc_uart_fifo_regs_t *fifo; + + // Disable interrupts + uart->inten &= ~UART_READ_INTS; + + // Get the FIFO for this UART, uart_num + fifo = MXC_UART_GET_FIFO(uart_num); + + // Save the data in the FIFO while we still need data + avail = UART_NumReadAvail(uart); + remain = req->len - req->num; + while(avail && remain) { + req->data[req->num++] = fifo->rx; + remain--; + avail--; + } + + // Check for errors + if(flags & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) { + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + if(req->callback != NULL) { + req->callback(req, E_OVERFLOW); + } + + return; + } + + if(flags & (MXC_F_UART_INTFL_RX_FRAMING_ERR | + MXC_F_UART_INTFL_RX_PARITY_ERR)) { + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + if(req->callback != NULL) { + req->callback(req, E_COMM_ERR); + } + + return; + } + + // Check to see if we're done receiving + if(remain == 0) { + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + if(req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + + return; + } + + if(remain == 1) { + uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | UART_ERRORS); + + } else { + // Set the RX FIFO AF threshold + if(remain < UART_RXFIFO_USABLE) { + uart->rx_fifo_ctrl = ((remain - 1) << + MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS); + } else { + uart->rx_fifo_ctrl = (UART_RXFIFO_USABLE << + MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS); + } + uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_AF | UART_ERRORS); + } +} +/**@} end of ingroup uart_comm */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.h new file mode 100644 index 00000000000..0904f0b92ac --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.h @@ -0,0 +1,347 @@ +/** + * @file + * @brief UART data types, definitions and function prototypes. + */ + /* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:51:14 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24676 $ + * + **************************************************************************** */ + + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "uart_regs.h" + +/* Define to prevent redundant inclusion */ +#ifndef _UART_H_ +#define _UART_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup commperipherals + * @defgroup uart_comm UART + * @brief UART serial communications peripheral. + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type for defining the number of bits per character. + */ +typedef enum { + UART_DATA_SIZE_5_BITS = MXC_V_UART_CTRL_DATA_SIZE_5_BITS, + UART_DATA_SIZE_6_BITS = MXC_V_UART_CTRL_DATA_SIZE_6_BITS, + UART_DATA_SIZE_7_BITS = MXC_V_UART_CTRL_DATA_SIZE_7_BITS, + UART_DATA_SIZE_8_BITS = MXC_V_UART_CTRL_DATA_SIZE_8_BITS +} +uart_data_size_t; + +/** + * Enumeration type for selecting Parity and type. + */ +typedef enum { + UART_PARITY_DISABLE = MXC_V_UART_CTRL_PARITY_DISABLE, + UART_PARITY_ODD = MXC_V_UART_CTRL_PARITY_ODD, + UART_PARITY_EVEN = MXC_V_UART_CTRL_PARITY_EVEN, + UART_PARITY_MARK = MXC_V_UART_CTRL_PARITY_MARK +} uart_parity_t; + +/** + * Configuration structure type for a UART port. + */ +typedef struct { + uint8_t extra_stop; /**< Number of stop bits. + * @li 0 for one stop bit + * @li 1 for two stop bits + */ + uint8_t cts; /**< CTS Enable/Disable. + * @li 1 to enable CTS + * @li 0 to disable CTS + */ + uint8_t rts; /**< RTS Enable/Disable. + * @li 1 to enable RTS + * @li 0 to disable RTS + */ + uint32_t baud; /**< Baud rate in Hz. */ + uart_data_size_t size; /**< Set the number of bits per character, see #uart_data_size_t. */ + uart_parity_t parity; /**< Set the parity, see #uart_parity_t for supported parity types. */ +} uart_cfg_t; + +/** + * Structure type for a UART asynchronous transaction request. + */ +typedef struct uart_req uart_req_t; + +/** + * @brief Type alias \c uart_async_callback for a callback function with signature of: \code void callback)(uart_req_t* , int error_code) \endcode + * @param uart_req_t* Pointer to the transaction request. + * @param error_code Return code for the UART request. @see mxc_errors.h. + * @addtogroup uart_async + */ +typedef void (*uart_async_callback)(uart_req_t*, int); + +/** + * Structure for a UART asynchronous transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup uart_async + */ +struct uart_req { + uint8_t *data; /**< Data buffer for characters. */ + unsigned len; /**< Length of characters in data to send or receive. */ + unsigned num; /**< Number of characters actually sent or received. */ + uart_async_callback callback; /**< Pointer to a callback function of type uart_async_callback(). */ +}; + + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize and enable UART module. + * @param uart Pointer to the UART registers. + * @param cfg Pointer to UART configuration. + * @param sys_cfg Pointer to system configuration object + * @returns #E_NO_ERROR UART initialized successfully, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg); + +/** + * @brief Shutdown UART module. + * @param uart Pointer to the UART registers. + * @returns #E_NO_ERROR UART shutdown successfully, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief Write UART data. This function blocks until the write transaction + * is complete. + * @param uart Pointer to the UART registers. + * @param data Pointer to buffer for write data. + * @param len Number of bytes to write. + * @note Will return once data has been put into FIFO, not necessarily + * transmitted. + * @return Number of bytes written if successful, error if unsuccessful. + */ +int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len); + +/** + * @brief Read UART data, blocking until transaction is complete. + * + * @param uart Pointer to the UART registers. + * @param data Pointer to buffer to save the data read. + * @param len Number of bytes to read. + * @param num Pointer to store the number of bytes actually read, pass NULL if not needed. + * + * @return Number of bytes read, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num); + +/** + * @ingroup uart_comm + * @defgroup uart_async UART Asynchronous Functions + */ + +/** + * @brief Asynchronously write/transmit data to the UART. + * + * @param uart Pointer to the UART registers. + * @param req Request for a UART transaction. + * @note Request struct must remain allocated until callback. + * + * @return #E_NO_ERROR Asynchronous write successfully started, @ref + * MXC_Error_Codes "error" if unsuccessful. + * @addtogroup uart_async + */ +int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req); + +/** + * @brief Asynchronously Read UART data. + * + * @param uart Pointer to the UART registers. + * @param req Pointer to request for a UART transaction. + * @note Request struct must remain allocated until callback function is called. + * + * @return #E_NO_ERROR Asynchronous read successfully started, @ref + * MXC_Error_Codes "error" if unsuccessful. + * @addtogroup uart_async + */ +int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req); + +/** + * @brief Abort asynchronous request. + * + * @param req Pointer to a request for a UART transaction, see #uart_req. + * + * @return #E_NO_ERROR Asynchronous request aborted successfully, error if unsuccessful. + * @addtogroup uart_async + */ +int UART_AbortAsync(uart_req_t *req); + +/** + * @brief UART interrupt handler. + * @details This function should be called by the application from the + * interrupt handler if UART interrupts are enabled. Alternately, + * this function can be periodically called by the application if + * UART interrupts are disabled. Only necessary to call this when + * using asynchronous functions. + * + * @param uart Pointer to the UART registers. + * @addtogroup uart_async + */ +void UART_Handler(mxc_uart_regs_t *uart); + +/** + * @brief Check to see if the UART is busy. + * + * @param uart Pointer to the UART registers. + * + * @return #E_NO_ERROR UART is idle. + * @return #E_BUSY UART is in use. + */ +int UART_Busy(mxc_uart_regs_t *uart); + +/** + * @brief Prepare the UART for entry into a Low-Power mode (LP0/LP1). + * @details Checks for any ongoing transactions. Disables interrupts if the + * UART is idle. + * + * @param uart Pointer to the UART registers. + * @return #E_NO_ERROR UART is ready to enter Low-Power modes (LP0/LP1). + * @return #E_BUSY UART is active and busy and not ready to enter a + * Low-Power mode (LP0/LP1). + * + */ +int UART_PrepForSleep(mxc_uart_regs_t *uart); + +/** + * @brief Enables the UART. + * @note This function does not change the existing UART configuration. + * + * @param uart Pointer to the UART registers. + */ +__STATIC_INLINE void UART_Enable(mxc_uart_regs_t *uart) +{ + uart->ctrl |= (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN | + MXC_F_UART_CTRL_RX_FIFO_EN); +} + +/** + * @brief Drains/empties and data in the RX FIFO. + * + * @param uart Pointer to the UART registers. + */ +__STATIC_INLINE void UART_DrainRX(mxc_uart_regs_t *uart) +{ + uint32_t ctrl_save = uart->ctrl; + uart->ctrl = (ctrl_save & ~MXC_F_UART_CTRL_RX_FIFO_EN); + uart->ctrl = ctrl_save; +} + +/** + * @brief Drains/empties any data in the TX FIFO. + * + * @param uart Pointer to the UART registers. + */ +__STATIC_INLINE void UART_DrainTX(mxc_uart_regs_t *uart) +{ + uint32_t ctrl_save = uart->ctrl; + uart->ctrl = (ctrl_save & ~MXC_F_UART_CTRL_TX_FIFO_EN); + uart->ctrl = ctrl_save; +} + +/** + * @brief Returns the number of unused bytes available in the UART TX FIFO. + * + * @param uart Pointer to the UART registers. + * + * @return Number of unused bytes in the TX FIFO. + */ +__STATIC_INLINE unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart) +{ + return (MXC_UART_FIFO_DEPTH - (uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)); +} + +/** + * @brief Returns the number of bytes available to be read from the RX + * FIFO. + * + * @param uart Pointer to the UART registers. + * + * @return The number of bytes available to read in the RX FIFO. + */ +__STATIC_INLINE unsigned UART_NumReadAvail(mxc_uart_regs_t *uart) +{ + return (uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY); +} + +/** + * @brief Clear interrupt flags. + * + * @param uart Pointer to the UART registers. + * @param mask Mask of the UART interrupts to clear, see + * @ref UART_INTFL_Register Register. + */ +__STATIC_INLINE void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask) +{ + uart->intfl = mask; +} + +/** + * @brief Get interrupt flags. + * + * @param uart Pointer to the UART registers. + * + * @return Mask of active flags. + */ +__STATIC_INLINE unsigned UART_GetFlags(mxc_uart_regs_t *uart) +{ + return (uart->intfl); +} + +/**@} end of group uart_comm */ +#ifdef __cplusplus +} +#endif + +#endif /* _UART_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c new file mode 100644 index 00000000000..a53b5a5a2ea --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c @@ -0,0 +1,290 @@ +/** + * @file + * @brief Watchdog driver source. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:27:05 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24321 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "wdt.h" +/** + * @ingroup wdt + * @{ + */ +static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function + +/* ************************************************************************* */ +int WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg, uint8_t unlock_key) +{ + if ((wdt == NULL) || (cfg == NULL)) + return E_NULL_PTR; + + //setup watchdog clock + SYS_WDT_Init(wdt, cfg); + + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable all interrupts + interruptEnable = 0; + wdt->enable = interruptEnable; + + //enable the watchdog clock and clear all other settings + wdt->ctrl = MXC_F_WDT_CTRL_EN_CLOCK; + + //clear all interrupt flags + wdt->flags = WDT_FLAGS_CLEAR_ALL; + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_EnableInt(mxc_wdt_regs_t *wdt, wdt_period_t int_period, uint8_t unlock_key) +{ + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //stop timer and clear interval period + wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_PERIOD | MXC_F_WDT_CTRL_EN_TIMER); + + //set interval period + wdt->ctrl |= (int_period << MXC_F_WDT_CTRL_INT_PERIOD_POS); + + //enable timeout interrupt + interruptEnable |= MXC_F_WDT_ENABLE_TIMEOUT; + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_DisableInt(mxc_wdt_regs_t *wdt, uint8_t unlock_key) +{ + //unlock register to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable timeout interrupt + interruptEnable &= ~MXC_F_WDT_ENABLE_TIMEOUT; + wdt->enable = interruptEnable; + + //lock register to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_EnableWait(mxc_wdt_regs_t *wdt, wdt_period_t wait_period, uint8_t unlock_key) +{ + // Make sure wait_period is valid + if (wait_period >= WDT_PERIOD_MAX) + return E_INVALID; + + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //stop timer and clear wait period + wdt->ctrl &= ~(MXC_F_WDT_CTRL_WAIT_PERIOD | MXC_F_WDT_CTRL_EN_TIMER); + + //set wait period + wdt->ctrl |= (wait_period << MXC_F_WDT_CTRL_WAIT_PERIOD_POS); + + //enable wait interrupt + interruptEnable |= MXC_F_WDT_ENABLE_PRE_WIN; + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_DisableWait(mxc_wdt_regs_t *wdt, uint8_t unlock_key) +{ + //unlock register to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable wait interrupt + interruptEnable &= ~MXC_F_WDT_ENABLE_PRE_WIN; + wdt->enable = interruptEnable; + + //lock register to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_EnableReset(mxc_wdt_regs_t *wdt, wdt_period_t rst_period, uint8_t unlock_key) +{ + // Make sure wait_period is valid + if (rst_period >= WDT_PERIOD_MAX) + return E_INVALID; + + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //stop timer and clear reset period + wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_PERIOD | MXC_F_WDT_CTRL_EN_TIMER); + + //set reset period + wdt->ctrl |= (rst_period << MXC_F_WDT_CTRL_RST_PERIOD_POS); + + //enable reset0 + interruptEnable |= MXC_F_WDT_ENABLE_RESET_OUT; + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_DisableReset(mxc_wdt_regs_t *wdt, uint8_t unlock_key) +{ + //unlock register to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable reset0 + interruptEnable &= ~MXC_F_WDT_ENABLE_RESET_OUT; + wdt->enable = interruptEnable; + + //lock register to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT_Start(mxc_wdt_regs_t *wdt, uint8_t unlock_key) +{ + //check if watchdog is already running + if(WDT_IsActive(wdt)) + return E_BAD_STATE; + + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + WDT_Reset(wdt); + + //enable interrupts + wdt->enable = interruptEnable; + + //start timer + wdt->ctrl |= MXC_F_WDT_CTRL_EN_TIMER; + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void WDT_Reset(mxc_wdt_regs_t *wdt) +{ + //reset the watchdog counter + wdt->clear = MXC_V_WDT_RESET_KEY_0; + wdt->clear = MXC_V_WDT_RESET_KEY_1; + + //clear all interrupt flags + wdt->flags = WDT_FLAGS_CLEAR_ALL; + + //wait for all interrupts to clear + while(wdt->flags != 0) { + wdt->flags = WDT_FLAGS_CLEAR_ALL; + } + + return; +} + +/* ************************************************************************* */ +int WDT_Stop(mxc_wdt_regs_t *wdt, uint8_t unlock_key) +{ + //unlock ctrl to be writable + wdt->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (wdt->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disabled the timer and interrupts + wdt->enable = 0; + wdt->ctrl &= ~(MXC_F_WDT_CTRL_EN_TIMER); + + //lock ctrl to read-only + wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY; + + return E_NO_ERROR; +} +/**@} end of ingroup wdt */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h new file mode 100644 index 00000000000..0ce237bd413 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h @@ -0,0 +1,254 @@ +/** + * @file + * @brief This is the high level API for the watchdog timer interface module + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24677 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _WDT_H +#define _WDT_H + +/* **** Includes **** */ +#include "mxc_config.h" +#include "wdt_regs.h" +#include "mxc_assert.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @ingroup periphlibs + * @defgroup wdttimers Watch Dog Timers + * @brief Watch Dog Timer High Level APIs. + */ +/** + * @ingroup wdttimers + * @defgroup wdt0 Watch Dog Timer 0/1 + * @brief WDT0/WDT1 configuration and control API. + * @{ + */ + +/** + * Definition used for clearing all of the WDT instances flags for Timeout, Pre-Window and Reset Out. + */ +#define WDT_FLAGS_CLEAR_ALL (MXC_F_WDT_FLAGS_TIMEOUT| MXC_F_WDT_FLAGS_PRE_WIN | MXC_F_WDT_FLAGS_RESET_OUT) +/** + * Enumeration type to define the Watchdog Timer's Period + */ +typedef enum { + WDT_PERIOD_2_31_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS, /**< \f$ 2^{31} \f$ WDT clocks. */ + WDT_PERIOD_2_30_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS, /**< \f$ 2^{30} \f$ WDT clocks. */ + WDT_PERIOD_2_29_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS, /**< \f$ 2^{29} \f$ WDT clocks. */ + WDT_PERIOD_2_28_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS, /**< \f$ 2^{28} \f$ WDT clocks. */ + WDT_PERIOD_2_27_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS, /**< \f$ 2^{27} \f$ WDT clocks. */ + WDT_PERIOD_2_26_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS, /**< \f$ 2^{26} \f$ WDT clocks. */ + WDT_PERIOD_2_25_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS, /**< \f$ 2^{25} \f$ WDT clocks. */ + WDT_PERIOD_2_24_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS, /**< \f$ 2^{24} \f$ WDT clocks. */ + WDT_PERIOD_2_23_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS, /**< \f$ 2^{23} \f$ WDT clocks. */ + WDT_PERIOD_2_22_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS, /**< \f$ 2^{22} \f$ WDT clocks. */ + WDT_PERIOD_2_21_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS, /**< \f$ 2^{21} \f$ WDT clocks. */ + WDT_PERIOD_2_20_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS, /**< \f$ 2^{20} \f$ WDT clocks. */ + WDT_PERIOD_2_19_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS, /**< \f$ 2^{19} \f$ WDT clocks. */ + WDT_PERIOD_2_18_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS, /**< \f$ 2^{18} \f$ WDT clocks. */ + WDT_PERIOD_2_17_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS, /**< \f$ 2^{17} \f$ WDT clocks. */ + WDT_PERIOD_2_16_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS, /**< \f$ 2^{16} \f$ WDT clocks. */ + WDT_PERIOD_MAX /**< Maximum Period is Max - 1 */ +} wdt_period_t; + +/** + * @brief Initializes system level clocks and sets watchdog in a known disabled state + * @note The clk_scale in cfg is only used if the system clock is selected for clk. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param cfg Watchdog system configuration, see sys_cfg_wdt_t. + * @param unlock_key Watchdog unlock key + * + * @retval #E_NO_ERROR Watchdog Timer initialized as requested + * @retval #E_NULL_PTR NULL pointer for Watchdog Timer Instance or Configuration parameters. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg, uint8_t unlock_key); + +/** + * @brief Configures and enables the interrupt timeout for the watchdog specified. + * + * @param wdt Watchdog module to operate on + * @param int_period Interrupt period as defined by wdt_period_t. + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Interrupt enabled + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_EnableInt(mxc_wdt_regs_t *wdt, wdt_period_t int_period, uint8_t unlock_key); + +/** + * @brief Disables the interrupt timeout for the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Interrupt disabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_DisableInt(mxc_wdt_regs_t *wdt, uint8_t unlock_key); + +/** + * @brief Configures and enables the pre-window timeout for the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param wait_period Pre-window period, see wdt_period_t for accepted values. + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Pre-window timeout set to wait_period + * @retval #E_BAD_STATE WDT unable to be unlocked + * @retval #E_INVALID Requested Period is greater than the maximum supported + */ +int WDT_EnableWait(mxc_wdt_regs_t *wdt, wdt_period_t wait_period, uint8_t unlock_key); + +/** + * @brief Disables the pre-window timeout for the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Wait disabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_DisableWait(mxc_wdt_regs_t *wdt, uint8_t unlock_key); + +/** + * @brief Configures and enables the reset timeout for the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param rst_period Reset period, see wdt_period_t for accepted values. + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Watchdog Timer Reset enabled with the rst_period time. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + * @retval #E_INVALID Requested Period is greater than the maximum supported + */ +int WDT_EnableReset(mxc_wdt_regs_t *wdt, wdt_period_t rst_period, uint8_t unlock_key); + +/** + * @brief Disables the reset timeout for the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY. + * + * @retval #E_NO_ERROR Reset disabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_DisableReset(mxc_wdt_regs_t *wdt, uint8_t unlock_key); + +/** + * @brief Gets the watchdog interrupt flags + * + * @param wdt Pointer to the Watchdog Timer Instance. + * + * @retval uint32_t Value of the Watchdog Timer Flags. + * + */ +__STATIC_INLINE uint32_t WDT_GetFlags(mxc_wdt_regs_t *wdt) +{ + return (wdt->flags); +} + +/** + * @brief Clears the watchdog interrupt flags based on the mask + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param mask Watchdog Flags to clear + * + */ +__STATIC_INLINE void WDT_ClearFlags(mxc_wdt_regs_t *wdt, uint32_t mask) +{ + wdt->flags = mask; +} + +/** + * @brief Starts the specified Watchdog Timer instance. + * + * @param wdt Pointer to the Watchdog Timer instance + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR Interrupt enabled. + * @retval #E_BAD_STATE WDT1 Already Running + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + * + */ +int WDT_Start(mxc_wdt_regs_t *wdt, uint8_t unlock_key); + +/** + * @brief Feeds the watchdog specified. + * + * @param wdt Watchdog module to operate on + * + */ +void WDT_Reset(mxc_wdt_regs_t *wdt); + +/** + * @brief Stops the watchdog specified. + * + * @param wdt Pointer to the Watchdog Timer Instance + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR Interrupt enabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock. + */ +int WDT_Stop(mxc_wdt_regs_t *wdt, uint8_t unlock_key); + +/** + * @brief Determines if the watchdog is running + * + * @param wdt Pointer to the Watchdog Timer Instance + * + * @retval 0 Watchdog timer is Disabled. + * @retval non-zero Watchdog timer is Active + */ +__STATIC_INLINE int WDT_IsActive(mxc_wdt_regs_t *wdt) +{ + return (!!(wdt->ctrl & MXC_F_WDT_CTRL_EN_TIMER)); +} + +/**@} end of group wdt*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c new file mode 100644 index 00000000000..fee58cb37d1 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c @@ -0,0 +1,275 @@ +/** + * @file + * @brief Watchdog Timer 2 Function Implementations. + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-09-08 17:06:34 -0500 (Thu, 08 Sep 2016) $ + * $Revision: 24320 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "wdt2.h" +#include "pwrseq_regs.h" + +/** + * @ingroup wdt2 + * @{ + */ +static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function + +/* ************************************************************************* */ +int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key) +{ + //enable nanoring in run and sleep mode + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN); + + //unlock ctrl to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable all interrupts + interruptEnable = 0; + MXC_WDT2->enable = interruptEnable; + + //enable the watchdog clock and clear all other settings + MXC_WDT2->ctrl = (MXC_F_WDT2_CTRL_EN_CLOCK); + + //clear all interrupt flags + MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL; + + if(runInSleep) { + // turn on nanoring during sleep + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_SLP); + //turn on timer during sleep + MXC_WDT2->ctrl |= MXC_F_WDT2_CTRL_EN_TIMER_SLP; + } else { + // turn off nanoring during sleep + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_NREN_SLP); + //turn off timer during sleep + MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER_SLP); + } + + //lock ctrl to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key) +{ + // Make sure interrupt period is valid + if (int_period >= WDT2_PERIOD_MAX) + return E_INVALID; + + //unlock ctrl to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //stop timer and clear interval period + MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_INT_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER); + + //set interval period + MXC_WDT2->ctrl |= (int_period << MXC_F_WDT2_CTRL_INT_PERIOD_POS); + + //enable timeout wake-up + interruptEnable |= MXC_F_WDT2_ENABLE_TIMEOUT; + + //lock ctrl to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + // Enable wake-up + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT2_DisableWakeUp(uint8_t unlock_key) +{ + //unlock register to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable timeout wake-up + interruptEnable &= ~MXC_F_WDT2_ENABLE_TIMEOUT; + MXC_WDT2->enable = interruptEnable; + + //lock register to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + // disable wake-up + MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key) +{ + // Make sure reset period is valid + if (rst_period >= WDT2_PERIOD_MAX) + return E_INVALID; + + //unlock ctrl to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //stop timer and clear reset period + MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_RST_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER); + + //set reset period + MXC_WDT2->ctrl |= (rst_period << MXC_F_WDT2_CTRL_RST_PERIOD_POS); + + //int flag has to be clear before interrupt enable can be written + MXC_WDT2->flags = MXC_F_WDT2_FLAGS_RESET_OUT; + + //enable reset0 + interruptEnable |= MXC_F_WDT2_ENABLE_RESET_OUT; + + //lock ctrl to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + //enable RSTN on WDT2 reset + MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT2_DisableReset(uint8_t unlock_key) +{ + //unlock register to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disable reset + interruptEnable &= ~MXC_F_WDT2_ENABLE_RESET_OUT; + MXC_WDT2->enable = interruptEnable; + + //lock register to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + //disable RSTN on WDT2 reset + MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int WDT2_Start(uint8_t unlock_key) +{ + //check if watchdog is already running + if(WDT2_IsActive()) + return E_BAD_STATE; + + //unlock ctrl to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + WDT2_Reset(); + + //enable interrupts + MXC_WDT2->enable = interruptEnable; + + //start timer + MXC_WDT2->ctrl |= (MXC_F_WDT2_CTRL_EN_TIMER); + + //lock ctrl to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void WDT2_Reset(void) +{ + //reset the watchdog counter + MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_0; + MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_1; + + //clear all interrupt flags + MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL; + + //wait for all interrupts to clear + while(MXC_WDT2->flags != 0) { + MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL; + } + + return; +} + +/* ************************************************************************* */ +int WDT2_Stop(uint8_t unlock_key) +{ + //check if watchdog is not running + if(!WDT2_IsActive()) + return E_BAD_STATE; + + //unlock ctrl to be writable + MXC_WDT2->lock_ctrl = unlock_key; + + //check to make sure it unlocked + if (MXC_WDT2->lock_ctrl & 0x01) + return E_BAD_STATE; + + //disabled the timer and interrupts + MXC_WDT2->enable = 0; + MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER); + + //lock ctrl to read-only + MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY; + + return E_NO_ERROR; +} +/**@} end of group wdt2*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h new file mode 100644 index 00000000000..8c6b7b171f8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h @@ -0,0 +1,218 @@ +/** + * @file + * @brief WDT2 peripheral module API. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $ + * $Revision: 24678 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _WDT2_H +#define _WDT2_H + +/* **** Includes **** */ +#include "mxc_config.h" +#include "wdt2_regs.h" +#include "mxc_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup wdttimers + * @defgroup wdt2 Watch Dog Timer 2 + * @brief WDT2 configuration and control API. + * @{ + */ + +/** + * @def Definition to clear all WDT2 flags + */ +#define WDT2_FLAGS_CLEAR_ALL (MXC_F_WDT2_FLAGS_TIMEOUT | MXC_F_WDT2_FLAGS_RESET_OUT) +/** + * Enumeration type to select the Watchdog Timer's Period + */ +typedef enum { + WDT2_PERIOD_2_25_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS, /**< \f$ 2^{25}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_24_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS, /**< \f$ 2^{24}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_23_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS, /**< \f$ 2^{23}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_22_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS, /**< \f$ 2^{22}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_21_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS, /**< \f$ 2^{21}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_20_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS, /**< \f$ 2^{20}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_19_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS, /**< \f$ 2^{19}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_18_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS, /**< \f$ 2^{18}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_17_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS, /**< \f$ 2^{17}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_16_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS, /**< \f$ 2^{16}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_15_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS, /**< \f$ 2^{15}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_14_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS, /**< \f$ 2^{14}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_13_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS, /**< \f$ 2^{13}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_12_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS, /**< \f$ 2^{12}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_11_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS, /**< \f$ 2^{11}\f$ Nano Ring clocks. */ + WDT2_PERIOD_2_10_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS, /**< \f$ 2^{10}\f$ Nano Ring clocks. */ + WDT2_PERIOD_MAX /**< Maximum Period is Max - 1 */ +} wdt2_period_t; + + +/** + * @brief Initializes the NanoRing for the watchdog clock and sets watchdog + * in a known disabled state + * @param runInSleep If non-zero, the WDT2 operates in Sleep Modes for + * the device, 0 disables the WDT2 during Sleep Modes. + * @param unlock_key The WDT2 unlock key value, use + * #MXC_V_WDT2_UNLOCK_KEY + * + * @retval #E_NO_ERROR Watchdog Timer initialized as requested + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key); + +/** + * @brief Configures and enables the wake-up timeout for the watchdog + * specified. + * + * @param int_period Interrupt period. + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR WDT2 Interrupt period enabled with the int_period + * time. + * @retval #E_INVALID Requested Period is greater than the maximum + * supported + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key); + +/** + * @brief Disables the interrupt timeout for the watchdog specified. + * + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR Wakeup disabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_DisableWakeUp(uint8_t unlock_key); + +/** + * @brief Configures and enables the reset timeout for the watchdog + * specified. + * + * @param rst_period Reset period. + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR Reset timeout enabled with the rst_period time. + * @retval #E_INVALID Requested Period is greater than the maximum + * supported + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key); + +/** + * @brief Disables the reset timeout for the watchdog specified. + * + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR Reset disabled. + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_DisableReset(uint8_t unlock_key); + +/** + * @brief Gets the watchdog flags + * + * @retval 0 No flags set. + * @retval non-zero The WDT2 interrupt flags that are + * set, see @ref WDT2_FLAGS_Register "WDT2_FLAGS + * register". + */ +__STATIC_INLINE uint32_t WDT2_GetFlags(void) +{ + return (MXC_WDT2->flags); +} + +/** + * @brief Clears the watchdog flags based on the @p mask. + * + * @param mask bits to clear + */ +__STATIC_INLINE void WDT2_ClearFlags(uint32_t mask) +{ + MXC_WDT2->flags = mask; +} + +/** + * @brief Starts the watchdog specified. + * + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR WDT2 started. + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_Start(uint8_t unlock_key); + +/** + * @brief Feeds the watchdog specified. + * + * @retval #E_NO_ERROR WDT2 reset successfully. + */ +void WDT2_Reset(void); + +/** + * @brief Stops the WatchDog Timer 2. + * + * @param unlock_key Key to unlock watchdog. + * + * @retval #E_NO_ERROR WDT2 stopped. + * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock. + */ +int WDT2_Stop(uint8_t unlock_key); + +/** + * @brief Determines if the watchdog is running + * + * @retval 0 Inactive + * @retval non-zero Active + */ +__STATIC_INLINE int WDT2_IsActive(void) +{ + return (!!(MXC_WDT2->ctrl & MXC_F_WDT2_CTRL_EN_TIMER)); +} + +/**@} end of group wdt2*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/objects.h b/targets/TARGET_Maxim/TARGET_MAX32630/objects.h new file mode 100644 index 00000000000..32ae81c294b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/objects.h @@ -0,0 +1,116 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "gpio_regs.h" +#include "uart_regs.h" +#include "i2cm_regs.h" +#include "spim_regs.h" +#include "pt_regs.h" +#include "adc_regs.h" +#include "uart.h" +#include "adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + PortName port; + uint32_t mask; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PinMode mode; +}; + +struct gpio_irq_s { + uint8_t port; + uint8_t pin; + uint8_t rise_en; + uint8_t fall_en; + uint32_t id; +}; + +struct serial_s { + int index; + mxc_uart_regs_t *uart; + mxc_uart_fifo_regs_t *fifo; + uint32_t id; + uart_cfg_t cfg; + sys_cfg_uart_t sys_cfg; + PinName tx; + PinName rx; +}; + +struct i2c_s { + mxc_i2cm_regs_t *i2c; + mxc_i2cm_fifo_regs_t *fifo; + int start_pending; + sys_cfg_i2cm_t sys_cfg; +}; + +struct spi_s { + int index; + mxc_spim_regs_t *spi; +}; + +struct pwmout_s { + mxc_pt_regs_t *pwm; + int period; + int pulse_width; +}; + +struct analogin_s { + mxc_adc_regs_t *adc; + mxc_adc_chsel_t channel; +}; + +typedef struct { + volatile uint32_t *reg_req; + volatile uint32_t *reg_ack; + uint32_t req_val; + uint32_t ack_mask; +} pin_function_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c b/targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c new file mode 100644 index 00000000000..79ce793b552 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c @@ -0,0 +1,81 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "objects.h" +#include "gpio_regs.h" + +void pin_function(PinName name, int function) +{ + MBED_ASSERT(name != (PinName)NC); + + if ((function >= 0) && (function <= 0xF)) { + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4)); + MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4)); + } else { + /* Assume this is a pointer to a pin function object */ + pin_function_t *obj = (pin_function_t*)function; + + if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) { + /* Request pin mapping */ + *obj->reg_req |= obj->req_val; + + /* Check for acknowledgment */ + MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val); + } + } +} + +void pin_mode(PinName name, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Must set mode while retaining direction */ + + /* Get the current direction */ + uint32_t curr_mode = (MXC_GPIO->out_mode[port] >> (pin * 4)) & 0xF; + PinDirection direction = PIN_OUTPUT; + if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || + (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) || + (curr_mode == MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z)) { + direction = PIN_INPUT; + } + + /* Set mode based on current direction */ + pin_dir_mode(name, direction, mode); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/port_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/port_api.c new file mode 100644 index 00000000000..adce69af0da --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/port_api.c @@ -0,0 +1,98 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection direction) +{ + obj->port = port; + obj->mask = mask; + obj->reg_out = &MXC_GPIO->out_val[port]; + obj->reg_in = &MXC_GPIO->in_val[port]; + obj->mode = PullDefault; + + /* Ensure that the GPIO clock is enabled */ + MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(obj->port, i)); + pin_dir_mode(port_pin(obj->port, i), direction, obj->mode); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + obj->mode = mode; + // The mode is set per pin: reuse pinmap logic + for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection direction) +{ + uint32_t i; + // The mode is set per pin: reuse gpio logic + for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) { + if (obj->mask & (1 << i)) { + pin_dir_mode(port_pin(obj->port, i), direction, obj->mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + return (*obj->reg_in & obj->mask); +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/pwmout_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/pwmout_api.c new file mode 100644 index 00000000000..ec8a3cfca4d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/pwmout_api.c @@ -0,0 +1,221 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "cmsis.h" +#include "pwmout_api.h" +#include "pinmap.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +#define MXC_GPIO_OUT_MODE_FIELD_WIDTH 4 +#define MXC_GPIO_OUT_MODE_FIELD_MASK ((uint32_t)0xFFFFFFFF >> (32 - MXC_GPIO_OUT_MODE_FIELD_WIDTH)) +#define MXC_GPIO_FUNC_SEL_FIELD_WIDTH 4 +#define MXC_GPIO_FUNC_SEL_FIELD_MASK ((uint32_t)0xFFFFFFFF >> (32 - MXC_GPIO_FUNC_SEL_FIELD_WIDTH)) + + +//****************************************************************************** +void pwmout_init(pwmout_t* obj, PinName pin) +{ + // Make sure the pin is free for GPIO use + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT); + MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin)); + + int i = 0; + PinMap pwm = PinMap_PWM[0]; + + // Check if there is a pulse train already active on this port + int pin_func = (MXC_GPIO->func_sel[port] & (MXC_GPIO_FUNC_SEL_FIELD_MASK << (port_pin * MXC_GPIO_FUNC_SEL_FIELD_WIDTH))) >> + (port_pin * MXC_GPIO_FUNC_SEL_FIELD_WIDTH); + MBED_ASSERT((pin_func < 1) || (pin_func > 3)); + + // Search through PinMap_PWM to find the pin + while (pwm.pin != pin) { + pwm = PinMap_PWM[++i]; + } + + // Find a free PT instance on this pin + while (pwm.pin == pin) { + + // Check to see if this PT instance is free + if (((mxc_pt_regs_t*)pwm.peripheral)->rate_length & MXC_F_PT_RATE_LENGTH_MODE) { + break; + } + + pwm = PinMap_PWM[++i]; + + // Raise an assertion if we can not allocate another PT instance. + MBED_ASSERT(pwm.pin == pin); + } + + // Enable the clock + MXC_CLKMAN->sys_clk_ctrl_7_pt = MXC_S_CLKMAN_CLK_SCALE_DIV_1; + + // Set the obj pointer to the propper PWM instance + obj->pwm = (mxc_pt_regs_t*)pwm.peripheral; + + // Initialize object period and pulse width + obj->period = -1; + obj->pulse_width = -1; + + // Disable the output + obj->pwm->train = 0x0; + obj->pwm->rate_length = 0x0; + + // Configure the pin + pin_mode(pin, (PinMode)PullNone); + pin_function(pin, pwm.function); + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_us(obj, 20000); + pwmout_write (obj, 0); + + // Set the drive mode to normal + MXC_SET_FIELD(&MXC_GPIO->out_mode[port], + (MXC_GPIO_OUT_MODE_FIELD_MASK << (port_pin * MXC_GPIO_OUT_MODE_FIELD_WIDTH)), + (MXC_V_GPIO_OUT_MODE_NORMAL << (port_pin * MXC_GPIO_OUT_MODE_FIELD_WIDTH))); + + // Enable this PWM channel + MXC_PTG->enable |= (1 << MXC_PT_GET_IDX(obj->pwm)); +} + +//****************************************************************************** +void pwmout_free(pwmout_t* obj) +{ + // Set the registers to the reset value + obj->pwm->train = 0; + obj->pwm->rate_length = 0x08000000; +} + +//****************************************************************************** +static void pwmout_update(pwmout_t* obj) +{ + // Calculate and set the divider ratio + int div = (obj->period * (SystemCoreClock / 1000000))/32; + if (div < 2) { + div = 2; + } + MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); + + // Change the duty cycle to adjust the pulse width + obj->pwm->train = (0xFFFFFFFF << (32 - ((32 * obj->pulse_width) / obj->period))); +} + + +//****************************************************************************** +void pwmout_write(pwmout_t* obj, float percent) +{ + // Saturate percent if outside of range + if(percent < 0.0f) { + percent = 0.0f; + } else if(percent > 1.0f) { + percent = 1.0f; + } + + // Resize the pulse width to set the duty cycle + pwmout_pulsewidth_us(obj, (int)(percent*obj->period)); +} + +//****************************************************************************** +float pwmout_read(pwmout_t* obj) +{ + // Check for when pulsewidth or period equals 0 + if((obj->pulse_width == 0) || (obj->period == 0)) { + return 0; + } + + // Return the duty cycle + return ((float)obj->pulse_width / (float)obj->period); +} + +//****************************************************************************** +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +//****************************************************************************** +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +//****************************************************************************** +void pwmout_period_us(pwmout_t* obj, int us) +{ + // Check the range of the period + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32))); + + // Set pulse width to half the period if uninitialized + if (obj->pulse_width == -1) { + obj->pulse_width = us / 2; + } + + // Save the period + obj->period = us; + + // Update the registers + pwmout_update(obj); +} + +//****************************************************************************** +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f)); +} + +//****************************************************************************** +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +//****************************************************************************** +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + // Check the range of the pulsewidth + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32))); + + // Initialize period to double the pulsewidth if uninitialized + if (obj->period == -1) { + obj->period = 2 * us; + } + + // Save the pulsewidth + obj->pulse_width = us; + + // Update the register + pwmout_update(obj); +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c new file mode 100644 index 00000000000..2b411c26c31 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c @@ -0,0 +1,253 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "rtc_api.h" +#include "lp_ticker_api.h" +#include "rtc.h" +#include "lp.h" + +#define PRESCALE_VAL RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock +#define SHIFT_AMT (RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL) + +#define WINDOW 1000 + +static int rtc_inited = 0; +static volatile uint32_t overflow_cnt = 0; + +static uint64_t rtc_read64(void); + +//****************************************************************************** +static void overflow_handler(void) +{ + overflow_cnt++; + RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS); +} + +//****************************************************************************** +void rtc_init(void) +{ + if (rtc_inited) { + return; + } + rtc_inited = 1; + + overflow_cnt = 0; + + /* Enable power for RTC for all LPx states */ + MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | + MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); + + /* Enable clock to synchronizers */ + CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1); + + // Prepare interrupt handlers + NVIC_SetVector(RTC0_IRQn, lp_ticker_irq_handler); + NVIC_EnableIRQ(RTC0_IRQn); + NVIC_SetVector(RTC3_IRQn, overflow_handler); + NVIC_EnableIRQ(RTC3_IRQn); + + // Enable wakeup on RTC rollover + LP_ConfigRTCWakeUp(0, 0, 0, 1); + + /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC + * if it is already running. + */ + if (!RTC_IsActive()) { + rtc_cfg_t cfg = {0}; + cfg.prescaler = PRESCALE_VAL; + cfg.snoozeMode = RTC_SNOOZE_DISABLE; + + int retval = RTC_Init(&cfg); + MBED_ASSERT(retval == E_NO_ERROR); + + RTC_EnableINT(MXC_F_RTC_FLAGS_OVERFLOW); + RTC_Start(); + } +} + +//****************************************************************************** +void lp_ticker_init(void) +{ + rtc_init(); +} + +//****************************************************************************** +void rtc_free(void) +{ + if (RTC_IsActive()) { + // Clear and disable RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR; + RTC_Stop(); + } +} + +//****************************************************************************** +int rtc_isenabled(void) +{ + return RTC_IsActive(); +} + +//****************************************************************************** +time_t rtc_read(void) +{ + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + uint32_t ovf1, ovf2; + + // Make sure RTC is setup before trying to read + if (!rtc_inited) { + rtc_init(); + } + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW; + timer_cnt = RTC_GetCount(); + ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW; + ovf_cnt_2 = overflow_cnt; + } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2)); + + // Account for an unserviced interrupt + if (ovf1) { + ovf_cnt_1++; + } + + return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT)); +} + +//****************************************************************************** +static uint64_t rtc_read64(void) +{ + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + uint32_t ovf1, ovf2; + uint64_t current_us; + + // Make sure RTC is setup before trying to read + if (!rtc_inited) { + rtc_init(); + } + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW; + timer_cnt = RTC_GetCount(); + ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW; + ovf_cnt_2 = overflow_cnt; + } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2)); + + // Account for an unserviced interrupt + if (ovf1) { + ovf_cnt_1++; + } + + current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT)); + + return current_us; +} + +//****************************************************************************** +void rtc_write(time_t t) +{ + // Make sure RTC is setup before accessing + if (!rtc_inited) { + rtc_init(); + } + + RTC_Stop(); + RTC_SetCount(t << SHIFT_AMT); + overflow_cnt = t >> (32 - SHIFT_AMT); + RTC_Start(); +} + +//****************************************************************************** +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + uint32_t comp_value; + uint64_t curr_ts64; + uint64_t ts64; + + // Note: interrupts are disabled before this function is called. + + // Disable the alarm while it is prepared + RTC_DisableINT(MXC_F_RTC_INTEN_COMP0); + + curr_ts64 = rtc_read64(); + ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL); + + // If this event is older than a recent window, it must be in the future + if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) { + ts64 += 0x100000000ULL; + } + + uint32_t timer = RTC_GetCount(); + if (ts64 <= curr_ts64) { + // This event has already occurred. Set the alarm to expire immediately. + comp_value = timer + 1; + } else { + comp_value = (ts64 << SHIFT_AMT) / 1000000; + } + + // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs. + if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) { + comp_value = timer + 2; + } + + MXC_RTCTMR->comp[0] = comp_value; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; + RTC_EnableINT(MXC_F_RTC_INTEN_COMP0); + + // Enable wakeup from RTC + LP_ConfigRTCWakeUp(1, 0, 0, 1); + + // Wait for pending transactions + while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); +} + +//****************************************************************************** +inline void lp_ticker_disable_interrupt(void) +{ + RTC_DisableINT(MXC_F_RTC_INTEN_COMP0); +} + +//****************************************************************************** +inline void lp_ticker_clear_interrupt(void) +{ + RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS); +} + +//****************************************************************************** +inline uint32_t lp_ticker_read(void) +{ + return rtc_read64(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c new file mode 100644 index 00000000000..a84df5a297c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c @@ -0,0 +1,381 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "serial_api.h" +#include "gpio_api.h" +#include "uart.h" +#include "uart_regs.h" +#include "ioman_regs.h" +#include "PeripheralPins.h" + +#define DEFAULT_BAUD 9600 + +#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \ + MXC_F_UART_INTFL_RX_PARITY_ERR | \ + MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) + +// Variables for managing the stdio UART +int stdio_uart_inited = 0; +serial_t stdio_uart = {0}; + +// Variables for interrupt driven +static uart_irq_handler irq_handler; +static serial_t *objs[MXC_CFG_UART_INSTANCES]; + +static void usurp_pin(PinName, int); + +//****************************************************************************** +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine which uart is associated with each pin + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + // Make sure that both pins are pointing to the same uart + MBED_ASSERT(uart != (UARTName)NC); + + // Set the obj pointer to the proper uart + obj->uart = (mxc_uart_regs_t*)uart; + + // Set the uart index + obj->index = MXC_UART_GET_IDX(obj->uart); + obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index); + + // Record the pins requested + obj->tx = tx; + obj->rx = rx; + + // Merge pin function requests for use with CMSIS init func + ioman_req_t io_req = {0}; + pin_function_t *pin_func = NULL; + if (tx != NC) { + pin_func = (pin_function_t *)pinmap_find_function(tx, PinMap_UART_TX); + io_req.value = pin_func->req_val; + } + if (rx != NC) { + pin_func = (pin_function_t *)pinmap_find_function(rx, PinMap_UART_RX); + io_req.value |= pin_func->req_val; + } + + // Using req and ack pointers of last pin function lookup + obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req; + obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack; + obj->sys_cfg.io_cfg.req_val = io_req; + obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_8; + + // Configure the UART with default parameters + obj->cfg.extra_stop = 0; + obj->cfg.cts = 0; + obj->cfg.rts = 0; + obj->cfg.baud = DEFAULT_BAUD; + obj->cfg.size = UART_DATA_SIZE_8_BITS; + obj->cfg.parity = UART_PARITY_DISABLE; + + // Manage stdio UART + if (uart == STDIO_UART) { + stdio_uart_inited = 1; + stdio_uart = *obj; + } + + int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg); + MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +void serial_baud(serial_t *obj, int baudrate) +{ + obj->cfg.baud = baudrate; + int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg); + MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + switch (data_bits) { + case 5: + obj->cfg.size = UART_DATA_SIZE_5_BITS; + break; + case 6: + obj->cfg.size = UART_DATA_SIZE_6_BITS; + break; + case 7: + obj->cfg.size = UART_DATA_SIZE_7_BITS; + break; + case 8: + obj->cfg.size = UART_DATA_SIZE_8_BITS; + break; + default: + MBED_ASSERT(0); + break; + } + + switch (parity) { + case ParityNone: + obj->cfg.parity = UART_PARITY_DISABLE; + break; + case ParityOdd : + obj->cfg.parity = UART_PARITY_ODD; + break; + case ParityEven: + obj->cfg.parity = UART_PARITY_EVEN; + break; + case ParityForced1: + case ParityForced0: + default: + MBED_ASSERT(0); + break; + } + + switch (stop_bits) { + case 1: + obj->cfg.extra_stop = 0; + break; + case 2: + obj->cfg.extra_stop = 1; + break; + default: + MBED_ASSERT(0); + break; + } + + int retval = UART_Init(obj->uart, &obj->cfg, NULL); + MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +void uart_handler(serial_t *obj) +{ + if (obj && obj->id) { + irq_handler(obj->id, RxIrq); + } +} + +void uart0_handler(void) { uart_handler(objs[0]); } +void uart1_handler(void) { uart_handler(objs[1]); } +void uart2_handler(void) { uart_handler(objs[2]); } +void uart3_handler(void) { uart_handler(objs[3]); } + +//****************************************************************************** +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + obj->id = id; +} + +//****************************************************************************** +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + switch (obj->index) { + case 0: + NVIC_SetVector(UART0_IRQn, uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + break; + case 1: + NVIC_SetVector(UART1_IRQn, uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + break; + case 2: + NVIC_SetVector(UART2_IRQn, uart2_handler); + NVIC_EnableIRQ(UART2_IRQn); + break; + case 3: + NVIC_SetVector(UART3_IRQn, uart3_handler); + NVIC_EnableIRQ(UART3_IRQn); + break; + default: + MBED_ASSERT(0); + } + + if (irq == RxIrq) { + // Enable RX FIFO Threshold Interrupt + if (enable) { + // Clear pending interrupts + obj->uart->intfl = obj->uart->intfl; + obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); + } else { + // Clear pending interrupts + obj->uart->intfl = obj->uart->intfl; + obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); + } + } else if (irq == TxIrq) { + // Set TX Almost Empty level to interrupt when empty + MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL, + (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS); + + // Enable TX Almost Empty Interrupt + if (enable) { + // Clear pending interrupts + obj->uart->intfl = obj->uart->intfl; + obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE; + } else { + // Clear pending interrupts + obj->uart->intfl = obj->uart->intfl; + obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE; + } + } else { + MBED_ASSERT(0); + } +} + +//****************************************************************************** +int serial_getc(serial_t *obj) +{ + int c = -1; + + if (obj->rx != NC) { + // Wait for data to be available + while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0); + + c = obj->fifo->rx; + } + + return c; +} + +//****************************************************************************** +void serial_putc(serial_t *obj, int c) +{ + if (obj->tx != NC) { + // Wait for room in the FIFO without blocking interrupts. + while (UART_NumWriteAvail(obj->uart) == 0); + + // Must clear before every write to the buffer to know that the FIFO + // is empty when the TX DONE bit is set + obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE; + obj->fifo->tx = (uint8_t)c; + } +} + +//****************************************************************************** +int serial_readable(serial_t *obj) +{ + return UART_NumReadAvail(obj->uart); +} + +//****************************************************************************** +int serial_writable(serial_t *obj) +{ + return UART_NumWriteAvail(obj->uart); +} + +//****************************************************************************** +void serial_clear(serial_t *obj) +{ + // Clear the RX and TX FIFOs + UART_DrainRX(obj->uart); + UART_DrainTX(obj->uart); +} + +//****************************************************************************** +void serial_break_set(serial_t *obj) +{ + // Make sure that nothing is being sent + while (((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) + >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0); + while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE)); + + // Configure TX to output 0 + usurp_pin(obj->tx, 0); + + // GPIO is setup now, but we need to unmap UART from the pin + pin_function_t *pin_func = (pin_function_t *)pinmap_find_function(obj->tx, PinMap_UART_TX); + *pin_func->reg_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ; + MBED_ASSERT((*pin_func->reg_ack & MXC_F_IOMAN_UART_ACK_IO_ACK) == 0); +} + +//****************************************************************************** +void serial_break_clear(serial_t *obj) +{ + // Configure TX to output 1 + usurp_pin(obj->tx, 1); + // Return TX to UART control + serial_pinout_tx(obj->tx); +} + +//****************************************************************************** +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +//****************************************************************************** +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + pin_function_t rtscts_pin_func = {0}; + + obj->cfg.cts = 0; + obj->cfg.rts = 0; + + if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) { + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart = (UARTName)pinmap_merge(uart_cts, (UARTName)obj->uart); + // Assert pin is usable with existing uart + MBED_ASSERT(uart != (UARTName)NC); + + pin_function_t *pin_func; + pin_func = (pin_function_t *)pinmap_find_function(txflow, PinMap_UART_CTS); + rtscts_pin_func.req_val |= pin_func->req_val; + + obj->cfg.cts = 1; + } + + if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) { + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart = (UARTName)pinmap_merge(uart_rts, (UARTName)obj->uart); + MBED_ASSERT(uart != (UARTName)NC); + + pin_function_t *pin_func; + pin_func = (pin_function_t *)pinmap_find_function(rxflow, PinMap_UART_RTS); + rtscts_pin_func.req_val |= pin_func->req_val; + + obj->cfg.rts = 1; + } + + obj->sys_cfg.io_cfg.req_val.value |= rtscts_pin_func.req_val; + + int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg); + MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +static void usurp_pin(PinName pin, int state) +{ + gpio_t gpio; + gpio_init_out(&gpio, pin); + gpio_write(&gpio, state); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c new file mode 100644 index 00000000000..560a4409293 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "sleep_api.h" +#include "lp.h" + +void sleep(void) +{ + LP_EnterLP2(); +} + +// Low-power stop mode +void deepsleep(void) +{ + sleep(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c new file mode 100644 index 00000000000..e8bb11a3021 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c @@ -0,0 +1,181 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "spi_api.h" // mbed HAL +#include "spim_regs.h" // bare metal +#include "spim.h" // Maxim CMSIS driver +#include "pinmap.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Make sure pins are pointing to the same SPI instance + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl; + + // Control is SCK and optionaly SS + if ((SPIName)spi_ssel != (SPIName)NC) { + spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + } else { + spi_cntl = spi_sclk; + } + + SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((SPIName)spi != (SPIName)NC); + + obj->spi = (mxc_spim_regs_t *)spi; + + // Merge pin function requests for use with CMSIS init func + ioman_req_t io_req; + pin_function_t *pin_func; + pin_func = (pin_function_t *)pinmap_find_function(mosi, PinMap_SPI_MOSI); + io_req.value = pin_func->req_val; + pin_func = (pin_function_t *)pinmap_find_function(miso, PinMap_SPI_MISO); + io_req.value |= pin_func->req_val; + pin_func = (pin_function_t *)pinmap_find_function(sclk, PinMap_SPI_SCLK); + io_req.value |= pin_func->req_val; + if ((SPIName)spi_ssel != (SPIName)NC) { + pin_func = (pin_function_t *)pinmap_find_function(ssel, PinMap_SPI_SSEL); + io_req.value |= pin_func->req_val; + } + + // Using req and ack pointers of last pin function lookup + sys_cfg_spim_t sys_cfg; + sys_cfg.io_cfg.req_reg = pin_func->reg_req; + sys_cfg.io_cfg.ack_reg = pin_func->reg_ack; + sys_cfg.io_cfg.req_val = io_req; + sys_cfg.clk_scale = CLKMAN_SCALE_AUTO; + + // Defaults + spim_cfg_t spim_cfg; + spim_cfg.mode = 0; + spim_cfg.ssel_pol = 0; + spim_cfg.baud = 1000000; + + SPIM_Init(obj->spi, &spim_cfg, &sys_cfg); + + obj->index = MXC_SPIM_GET_IDX(obj->spi); +} + +//****************************************************************************** +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Check the validity of the inputs + MBED_ASSERT(bits == 8); + + // Only supports master mode + MBED_ASSERT(!slave); + + // Set the mode + obj->spi->mstr_cfg &= ~(MXC_F_SPIM_MSTR_CFG_SPI_MODE); + obj->spi->mstr_cfg |= (mode << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS); +} + +//****************************************************************************** +void spi_frequency(spi_t *obj, int hz) +{ + // Maximum frequency is half the system frequency + MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2)); + unsigned clocks = ((SystemCoreClock / 2) / hz); + + // Figure out the divider ratio + int clk_div = 1; + while(clk_div < 10) { + if(clocks < 0x10) { + break; + } + clk_div++; + clocks = clocks >> 1; + } + + // Turn on the SPI clock + if(obj->index == 0) { + MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div; + } else if(obj->index == 1) { + MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div; + } else if(obj->index == 2) { + MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div; + } else { + MBED_ASSERT(0); + } + + // Set the number of clocks to hold sclk high and low + MXC_SET_FIELD(&obj->spi->mstr_cfg, + (MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK | MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK), + ((clocks << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS))); +} + +//****************************************************************************** +int spi_master_write(spi_t *obj, int value) +{ + spim_req_t req; + uint8_t out; + uint8_t in; + + out = value; + + req.ssel = 0; + req.deass = 0; + req.tx_data = &out; + req.rx_data = ∈ + req.width = SPIM_WIDTH_1; + req.len = 1; + req.ssel = 0; + req.deass = 1; + req.callback = NULL; + + SPIM_Trans(obj->spi, &req); + + return *req.rx_data; +} + +//****************************************************************************** +int spi_busy(spi_t *obj) +{ + return SPIM_Busy(obj->spi); +} + +//****************************************************************************** +uint8_t spi_get_module(spi_t *obj) +{ + return obj->index; +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c new file mode 100644 index 00000000000..dad1ce2339f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c @@ -0,0 +1,257 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_error.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "tmr.h" + +#define US_TIMER MXC_TMR0 +#define US_TIMER_IRQn TMR0_0_IRQn + +static int us_ticker_inited = 0; +static uint32_t ticks_per_us; +static uint32_t tick_win; +static volatile uint64_t current_cnt; // Hold the current ticks +static volatile uint64_t event_cnt; // Holds the value of the next event + +#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) + +//****************************************************************************** +static inline void inc_current_cnt(uint32_t inc) +{ + // Overflow the ticker when the us ticker overflows + current_cnt += inc; + if (current_cnt > MAX_TICK_VAL) { + current_cnt -= (MAX_TICK_VAL + 1); + } +} + +//****************************************************************************** +static inline int event_passed(uint64_t current, uint64_t event) +{ + // Determine if the event has already happened. + // If the event is behind the current ticker, within a window, + // then the event has already happened. + if (((current < tick_win) && ((event < current) || + (event > (MAX_TICK_VAL - (tick_win - current))))) || + ((event < current) && (event > (current - tick_win)))) { + return 1; + } + + return 0; +} + +//****************************************************************************** +static inline uint64_t event_diff(uint64_t current, uint64_t event) +{ + // Check to see if the ticker will overflow before the event + if(current <= event) { + return (event - current); + } + + return ((MAX_TICK_VAL - current) + event); +} + +//****************************************************************************** +static void tmr_handler(void) +{ + uint32_t cmp = TMR32_GetCompare(US_TIMER); + TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts + TMR32_ClearFlag(US_TIMER); + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + + inc_current_cnt(cmp); + + if (event_passed(current_cnt + TMR32_GetCount(US_TIMER), event_cnt)) { + // the timestamp has expired + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value + us_ticker_irq_handler(); + } else { + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + TMR32_SetCompare(US_TIMER, diff); + + // Since the timer keeps counting after the terminal value is reached, it is possible that the new + // terminal value is in the past. + if (TMR32_GetCompare(US_TIMER) < TMR32_GetCount(US_TIMER)) { + // the timestamp has expired + TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts + TMR32_ClearFlag(US_TIMER); + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value + us_ticker_irq_handler(); + } + } + } +} + +//****************************************************************************** +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + + us_ticker_inited = 1; + current_cnt = 0; + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value + ticks_per_us = SystemCoreClock / 1000000; + tick_win = SystemCoreClock / 100; // Set the tick window to 10ms + + int retval = TMR_Init(US_TIMER, TMR_PRESCALE_DIV_2_0, NULL); + MBED_ASSERT(retval == E_NO_ERROR); + + tmr32_cfg_t cfg; + cfg.mode = TMR32_MODE_CONTINUOUS; + cfg.polarity = TMR_POLARITY_UNUSED; + cfg.compareCount = 0xFFFFFFFF; + TMR32_Config(US_TIMER, &cfg); + + NVIC_SetVector(US_TIMER_IRQn, tmr_handler); + NVIC_EnableIRQ(US_TIMER_IRQn); + TMR32_EnableINT(US_TIMER); + + TMR32_Start(US_TIMER); +} + +//****************************************************************************** +void us_ticker_deinit(void) +{ + TMR32_Stop(US_TIMER); + TMR32_DisableINT(US_TIMER); + TMR32_ClearFlag(US_TIMER); + us_ticker_inited = 0; +} + +//****************************************************************************** +uint32_t us_ticker_read(void) +{ + uint64_t current_cnt1, current_cnt2; + uint32_t cmp, cnt; + uint32_t flag1, flag2; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + // Ensure coherency between current_cnt and TMR32_GetCount() + do { + current_cnt1 = current_cnt; + flag1 = TMR32_GetFlag(US_TIMER); + cmp = TMR32_GetCompare(US_TIMER); + cnt = TMR32_GetCount(US_TIMER); + flag2 = TMR32_GetFlag(US_TIMER); + current_cnt2 = current_cnt; + } while ((current_cnt1 != current_cnt2) || (flag1 != flag2)); + + // Account for an unserviced interrupt + if (flag1) { + current_cnt1 += cmp; + } + + current_cnt1 += cnt; + + return (current_cnt1 / ticks_per_us); +} + +//****************************************************************************** +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Note: interrupts are disabled before this function is called. + + TMR32_Stop(US_TIMER); + + if (TMR32_GetFlag(US_TIMER)) { + TMR32_ClearFlag(US_TIMER); + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + inc_current_cnt(TMR32_GetCompare(US_TIMER)); + } + + // add and reset the current count value + inc_current_cnt(TMR32_GetCount(US_TIMER)); + TMR32_SetCount(US_TIMER, 0); + + // add the number of cycles that the timer is disabled here for + inc_current_cnt(200); + + event_cnt = (uint64_t)timestamp * ticks_per_us; + + // Check to see if the event has already passed + if (!event_passed(current_cnt, event_cnt)) { + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + TMR32_SetCompare(US_TIMER, diff); + } else { + // the event occurs after the next overflow + TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // set to max + } + } else { + // the requested timestamp occurs in the past + // set the timer up to immediately expire + TMR32_SetCompare(US_TIMER, 1); + } + + TMR32_Start(US_TIMER); +} + +//****************************************************************************** +void us_ticker_disable_interrupt(void) +{ + // There are no more events, set timer overflow to the max + TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); +} + +//****************************************************************************** +void us_ticker_clear_interrupt(void) +{ + // cleared in the local handler +} + +//****************************************************************************** +void us_ticker_set(timestamp_t timestamp) +{ + TMR32_Stop(US_TIMER); + current_cnt = (uint64_t)timestamp * ticks_per_us; + TMR32_SetCount(US_TIMER, 0); + TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); + TMR32_Start(US_TIMER); + + if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) { + // The next timestamp has elapsed. Trigger the interrupt to handle it. + NVIC_SetPendingIRQ(US_TIMER_IRQn); + } +} diff --git a/targets/TARGET_Maxim/mbed_rtx.h b/targets/TARGET_Maxim/mbed_rtx.h index 1099d4a501d..07e635d40b4 100644 --- a/targets/TARGET_Maxim/mbed_rtx.h +++ b/targets/TARGET_Maxim/mbed_rtx.h @@ -77,6 +77,21 @@ #define OS_CLOCK 96000000 #endif +#elif defined(TARGET_MAX32630) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20080000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 96000000 +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index ae2ff703fc6..bad4e0c2495 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1880,6 +1880,15 @@ "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"], "release_versions": ["2", "5"] }, + "MAX32630FTHR": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132"], + "extra_labels": ["Maxim", "MAX32630"], + "supported_toolchains": ["GCC_ARM", "IAR", "ARM"], + "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"], + "release_versions": ["2", "5"] + }, "EFM32": { "inherits": ["Target"], "extra_labels": ["Silicon_Labs", "EFM32"],