diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt index 24d9f345c3d..2a3d39f2790 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt @@ -15,6 +15,8 @@ function(_mbed_get_cortex_m_exception_handlers toolchain_dir) set(STARTUP_RTX_FILE TARGET_M3/irq_cm3.S) elseif(${key} STREQUAL M33) set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) + elseif(${key} STREQUAL M55) + set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) elseif(${key} STREQUAL RTOS_M4_M7) set(STARTUP_RTX_FILE TARGET_RTOS_M4_M7/irq_cm4f.S) endif() diff --git a/tools/cmake/cores/Cortex-M55.cmake b/tools/cmake/cores/Cortex-M55.cmake new file mode 100644 index 00000000000..88bb9b99495 --- /dev/null +++ b/tools/cmake/cores/Cortex-M55.cmake @@ -0,0 +1,28 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Sets cpu core options +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + list(APPEND common_options + "-mthumb" + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=softfp" + "-mcpu=cortex-m55" + ) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + list(APPEND common_options + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=hard" + "-mcpu=cortex-m55" + ) +endif() + +function(mbed_set_cpu_core_definitions target) + target_compile_definitions(${target} + INTERFACE + __CORTEX_M55 + __FPU_PRESENT=1 + __CMSIS_RTOS + __MBED_CMSIS_RTOS_CM + ) +endfunction() diff --git a/tools/cmake/toolchain.cmake b/tools/cmake/toolchain.cmake index ff64de55e20..8d151ecc08f 100644 --- a/tools/cmake/toolchain.cmake +++ b/tools/cmake/toolchain.cmake @@ -53,6 +53,8 @@ elseif (MBED_CPU_CORE STREQUAL Cortex-M4) set(CMAKE_SYSTEM_PROCESSOR cortex-m4) elseif (MBED_CPU_CORE STREQUAL Cortex-M4F) set(CMAKE_SYSTEM_PROCESSOR cortex-m4) +elseif (MBED_CPU_CORE STREQUAL Cortex-M55) + set(CMAKE_SYSTEM_PROCESSOR cortex-m55) elseif (MBED_CPU_CORE STREQUAL Cortex-M7) set(CMAKE_SYSTEM_PROCESSOR cortex-m7) elseif (MBED_CPU_CORE STREQUAL Cortex-M7F)