From e600c577ee14881f8c4b05c747b2754168dcd715 Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Thu, 19 Nov 2020 19:14:53 +0800 Subject: [PATCH] targets:evkbimxrt1050: Adjust the SEMC re-order rules Update the BMCR0, BMCR1 registers to adjust the SEMC re-order rules. This can improve the SDRAM stability under multiple AXI masters system. Signed-off-by: Gavin Liu --- .../TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c index 50ba9a82145..a2c02676993 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -239,9 +239,9 @@ const uint8_t dcd_data[] = { /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */