From 8858a87071debf4bbb2e5f987ce9b03eb1836ba6 Mon Sep 17 00:00:00 2001 From: MarceloSalazar Date: Tue, 7 Apr 2020 22:49:59 +0100 Subject: [PATCH 01/15] Remove Thundersoft targets --- .../TARGET_TT_M3HQ/PeripheralNames.h | 163 - targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h | 139 - targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h | 49 - .../TARGET_TT/TARGET_TT_M3HQ/analogin_api.c | 119 - .../TARGET_TT/TARGET_TT_M3HQ/analogout_api.c | 109 - targets/TARGET_TT/TARGET_TT_M3HQ/device.h | 23 - .../TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h | 4539 ------------ .../TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S | 614 -- .../device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct | 39 - .../TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S | 582 -- .../device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld | 166 - .../device/TOOLCHAIN_IAR/startup_TMPM3HQ.S | 1107 --- .../device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf | 43 - .../TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h | 12 - .../TARGET_TT_M3HQ/device/cmsis_nvic.h | 13 - .../TARGET_TT_M3HQ/device/system_TMPM3HQ.c | 342 - .../TARGET_TT_M3HQ/device/system_TMPM3HQ.h | 52 - targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c | 116 - .../TARGET_TT/TARGET_TT_M3HQ/gpio_include.h | 355 - .../TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c | 466 -- .../TARGET_TT/TARGET_TT_M3HQ/gpio_object.h | 98 - targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c | 400 -- targets/TARGET_TT/TARGET_TT_M3HQ/objects.h | 113 - targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c | 215 - targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c | 150 - targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c | 200 - targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c | 471 -- targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c | 75 - targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c | 329 - targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c | 101 - .../TARGET_TT_M4G9/Periph_Driver/inc/adc.h | 499 -- .../TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h | 135 - .../Periph_Driver/inc/adc_include.h | 349 - .../Periph_Driver/inc/tmpm4g9_fc.h | 137 - .../Periph_Driver/inc/tmpm4g9_rtc.h | 386 -- .../TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h | 113 - .../Periph_Driver/inc/txz_driver_def.h | 96 - .../Periph_Driver/inc/txz_fuart.h | 552 -- .../Periph_Driver/inc/txz_fuart_ex.h | 110 - .../Periph_Driver/inc/txz_fuart_include.h | 390 -- .../Periph_Driver/inc/txz_gpio.h | 2406 ------- .../Periph_Driver/inc/txz_hal.h | 126 - .../Periph_Driver/inc/txz_i2c.h | 843 --- .../Periph_Driver/inc/txz_i2c_api.h | 311 - .../Periph_Driver/inc/txz_sample_def.h | 30 - .../Periph_Driver/inc/txz_t32a.h | 1024 --- .../Periph_Driver/inc/txz_tspi.h | 1322 ---- .../Periph_Driver/inc/txz_uart.h | 812 --- .../Periph_Driver/inc/txz_uart_include.h | 476 -- .../TARGET_TT_M4G9/Periph_Driver/src/adc.c | 1200 ---- .../TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c | 351 - .../Periph_Driver/src/tmpm4g9_fc.c | 646 -- .../TARGET_TT_M4G9/Periph_Driver/src/txz_cg.c | 492 -- .../Periph_Driver/src/txz_fuart.c | 1438 ---- .../Periph_Driver/src/txz_fuart_ex.c | 206 - .../Periph_Driver/src/txz_gpio.c | 4751 ------------- .../Periph_Driver/src/txz_hal.c | 175 - .../Periph_Driver/src/txz_i2c.c | 415 -- .../Periph_Driver/src/txz_i2c_api.c | 1865 ----- .../Periph_Driver/src/txz_t32a.c | 2034 ------ .../Periph_Driver/src/txz_tspi.c | 2830 -------- .../Periph_Driver/src/txz_uart.c | 1910 ----- .../TARGET_TT_M4G9/PeripheralNames.h | 187 - targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h | 139 - targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h | 50 - .../TARGET_TT/TARGET_TT_M4G9/analogin_api.c | 138 - .../TARGET_TT/TARGET_TT_M4G9/analogout_api.c | 127 - targets/TARGET_TT/TARGET_TT_M4G9/device.h | 24 - .../TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h | 6129 ----------------- .../TOOLCHAIN_ARM_STD/startup_TMPM4G9.S | 533 -- .../device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct | 50 - .../TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S | 532 -- .../device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld | 214 - .../device/TOOLCHAIN_IAR/startup_TMPM4G9.S | 952 --- .../device/TOOLCHAIN_IAR/tmpm4g9f15.icf | 45 - .../TARGET_TT/TARGET_TT_M4G9/device/cmsis.h | 12 - .../TARGET_TT_M4G9/device/cmsis_nvic.h | 28 - .../TARGET_TT_M4G9/device/system_TMPM4G9.c | 338 - .../TARGET_TT_M4G9/device/system_TMPM4G9.h | 54 - targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c | 130 - targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c | 125 - .../TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c | 281 - .../TARGET_TT/TARGET_TT_M4G9/gpio_object.h | 70 - targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c | 216 - targets/TARGET_TT/TARGET_TT_M4G9/objects.h | 105 - targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c | 98 - targets/TARGET_TT/TARGET_TT_M4G9/port_api.c | 140 - targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c | 225 - targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c | 420 -- targets/TARGET_TT/TARGET_TT_M4G9/sleep.c | 125 - targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c | 341 - targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c | 106 - targets/TARGET_TT/mbed_rtx.h | 38 - targets/targets.json | 86 - 94 files changed, 51688 deletions(-) delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/objects.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_cg.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/objects.h delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/port_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/sleep.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c delete mode 100644 targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c delete mode 100644 targets/TARGET_TT/mbed_rtx.h diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h deleted file mode 100644 index f9c8c5377a1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h +++ /dev/null @@ -1,163 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - SERIAL_3, - SERIAL_4, - SERIAL_5, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - ADC_AINA00 = 0, - ADC_AINA01, - ADC_AINA02, - ADC_AINA03, - ADC_AINA04, - ADC_AINA05, - ADC_AINA06, - ADC_AINA07, - ADC_AINA08, - ADC_AINA09, - ADC_AINA10, - ADC_AINA11, - ADC_AINA12, - ADC_AINA13, - ADC_AINA14, - ADC_AINA15, - ADC_AINA16, - ADC_AINA17, - ADC_AINA18, - ADC_AINA19, - ADC_AINA20, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - DAC_A0 = 0, - DAC_A1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - GPIO_IRQ_00 = 0, - GPIO_IRQ_01, - GPIO_IRQ_02, - GPIO_IRQ_03, - GPIO_IRQ_04, - GPIO_IRQ_05, - GPIO_IRQ_06, - GPIO_IRQ_07, - GPIO_IRQ_08, - GPIO_IRQ_09, - GPIO_IRQ_10, - GPIO_IRQ_11, - GPIO_IRQ_12, - GPIO_IRQ_13, - GPIO_IRQ_14, - GPIO_IRQ_15, - GPIO_IRQ_16, - GPIO_IRQ_17_18, - GPIO_IRQ_19_22, - GPIO_IRQ_23_26, - GPIO_IRQ_27_28, - GPIO_IRQ_29, - GPIO_IRQ_30_31, - INVALID_GPIO_IRQ = (int)NC -} gpio_irqname; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART SERIAL_1 - -#define MBED_SPI0 PA1, PA2, PA0, PA4 -#define MBED_SPI1 PB3, PB4, PB2, PB5 -#define MBED_SPI2 PT3, PT4, PT2, PT1 -#define MBED_SPI3 PP4, PP3, PP5, PP6 -#define MBED_SPI4 PH5, PH6, PH4, PH0 - -#define MBED_UART0 PA1, PA2 -#define MBED_UART1 PJ1, PJ2 -#define MBED_UART2 PB2, PB3 -#define MBED_UART3 PA7, PA6 -#define MBED_UART4 PC4, PC5 -#define MBED_UART5 PN2, PN3 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PC1, PC0 -#define MBED_I2C1 PA5, PA4 -#define MBED_I2C2 PL1, PL0 -#define MBED_I2C3 PT0, PT1 - -#define MBED_ANALOGIN0 A0 -#define MBED_ANALOGIN1 A1 -#define MBED_ANALOGIN2 A2 -#define MBED_ANALOGIN3 A3 -#define MBED_ANALOGIN4 A4 -#define MBED_ANALOGIN5 A5 - -#define MBED_PWMOUT0 PB0 -#define MBED_PWMOUT1 PC0 -#define MBED_PWMOUT2 PJ0 -#define MBED_PWMOUT3 PK2 -#define MBED_PWMOUT4 PN0 -#define MBED_PWMOUT5 PL5 -#define MBED_PWMOUT6 PG2 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h deleted file mode 100644 index e966a4f5fd7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0x1F) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) - -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) -#define PIN_DIR(X) ((X) & 0xffff) - -#define GPIO_NUM (15U) // total number of gpio -#define FRMAX (7U) -#define RESER (8U - (FRMAX)) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM3HQ Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, - PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, - PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, - PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, - PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, - PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7, - PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, - PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, - - // Other mbed Pin Names - LED0 = PK4, - LED1 = PK5, - LED2 = PK6, - LED3 = PK7, - - // External data bus Pin Names - D0 = PG3, - D1 = PG4, - D2 = PG5, - D3 = PG2, - D4 = PG6, - D5 = PA0, - D6 = PL5, - D7 = PL6, - D8 = PT0, - D9 = PP0, - D10 = PT1, - D11 = PT3, - D12 = PT4, - D13 = PT2, - D14 = PA5, - D15 = PA4, - - DAC0 = PG0, - DAC1 = PG1, - // Analogue out pins - A0 = PF7, - A1 = PF6, - A2 = PF5, - A3 = PF4, - A4 = PF3, - A5 = PF2, - - // DAP_UART - USBTX = PJ1, - USBRX = PJ2, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - // Switches - SW1 = PP6, //DIP switch J7_1 - SW2 = PP7, //DIP switch J7_2 - SW3 = (int)0xFFFFFFFF, //Reset Button - SW4 = PV3, //Push button S2 - USER_BUTTON = PV3, - - // I2C pins - SDA = D14, - SCL = D15, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault -} PinMode; - -typedef enum { - DISABLE = 0, - ENABLE -} FunctionalState; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h deleted file mode 100644 index 84bcf0b3da8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, - PortT, - PortU, - PortV -} PortName; - -#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c deleted file mode 100644 index e043e2611f0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c +++ /dev/null @@ -1,119 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_ADC[] = { - {PD0, ADC_AINA00, PIN_DATA(0, 0)}, - {PD1, ADC_AINA01, PIN_DATA(0, 0)}, - {PD2, ADC_AINA02, PIN_DATA(0, 0)}, - {PD3, ADC_AINA03, PIN_DATA(0, 0)}, - {PE0, ADC_AINA04, PIN_DATA(0, 0)}, - {PE1, ADC_AINA05, PIN_DATA(0, 0)}, - {PE2, ADC_AINA06, PIN_DATA(0, 0)}, - {PE3, ADC_AINA07, PIN_DATA(0, 0)}, - {PE4, ADC_AINA08, PIN_DATA(0, 0)}, - {PE5, ADC_AINA09, PIN_DATA(0, 0)}, - {PE6, ADC_AINA10, PIN_DATA(0, 0)}, - {PF0, ADC_AINA11, PIN_DATA(0, 0)}, - {PF1, ADC_AINA12, PIN_DATA(0, 0)}, - {PF2, ADC_AINA13, PIN_DATA(0, 0)}, - {PF3, ADC_AINA14, PIN_DATA(0, 0)}, - {PF4, ADC_AINA15, PIN_DATA(0, 0)}, - {PF5, ADC_AINA16, PIN_DATA(0, 0)}, - {PF6, ADC_AINA17, PIN_DATA(0, 0)}, - {PF7, ADC_AINA18, PIN_DATA(0, 0)}, - {PD4, ADC_AINA19, PIN_DATA(0, 0)}, - {PD5, ADC_AINA20, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -/** - * [analogin_init] - * @param obj - * @param pin - * @description Initialize analog input - */ -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - // Assert that ADC channel is valid - MBED_ASSERT(obj->adc != (ADCName)NC); - obj->obj = TSB_ADA; - // ADC CG Fsys Enable - TSB_CG_FSYSENB_IPENB15 = ENABLE; - // ADC Clock Enable - TSB_CG_SPCLKEN_ADCKEN = ENABLE; - // Set pin function as ADC - pinmap_pinout(pin, PinMap_ADC); - // Set sample hold time and pre-scale clock - obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); - obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - obj->obj->MOD1 = ADC_MOD1_AVDD5_3V; - obj->obj->MOD2 = ADC_MOD2_TMPM3Hx; -} - -/** - * [analogin_read_u16] - * @param obj - * @return An unsigned short in the range [0x00, 0x0FFF] - * @description Read the ADC input - */ -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t ADCResultValue = 0; - uint32_t ADCResultStored = 0; - - // Wait at least 3us to ensure the voltage is stable - wait_us(300); - // ADC configuration for data Conversion - obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); - obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE - | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); - // Wait until AD conversion complete - while( (obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE); - // Wait for register to update with convert value - wait_us(30); - // Convert result - ADCResultStored = (obj->obj->REG0 | obj->adc); - if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { - ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); - } - return ADCResultValue; -} - -/** - * [analogin_read] - * @param obj - * @return A float in the range [0.0, 1.0] - * @description Read the ADC input - */ -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return ((float)(value * (1.0f / (float)ADC_12BIT_RANGE))); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c deleted file mode 100644 index dbf4b385b99..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" -#include "PeripheralNames.h" -#include "mbed_wait_api.h" -#include "pinmap.h" - -#define DAC_START ((uint32_t)0x00000001) -#define DAC_STOP ((uint32_t)0x00000000) - -static const PinMap PinMap_DAC[] = { - {DAC0, DAC_A0, PIN_DATA(0, 3)}, - {DAC1, DAC_A1, PIN_DATA(0, 3)}, - {NC, NC, 0} -}; - -static void analogout_start(dac_t *obj) -{ - obj->handler->CTL = DAC_START; // Supply Vref and enable DAC -} - -void analogout_init(dac_t *obj, PinName pin) -{ - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module - MBED_ASSERT(obj->dac != (DACName)NC); - - pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC - TSB_CG_FSYSENA_IPENA06 = ENABLE; - if (obj->dac == DAC_A0) { // Compute handler - obj->handler = TSB_DA0; - TSB_CG_FSYSENB_IPENB17 = ENABLE; - } else { - if (obj->dac == DAC_A1) { - obj->handler = TSB_DA1; - TSB_CG_FSYSENB_IPENB18 = ENABLE; - } else { - obj->handler = NULL; - } - } - obj->handler->CTL = DAC_STOP; -} - -void analogout_free(dac_t *obj) -{ - obj->handler->CTL = DAC_STOP; -} - -void analogout_write(dac_t *obj, float value) -{ - uint8_t outputcode; - - analogout_start(obj); - - if (value < 0.0f) { - value = 0.0f; - } else { - if (value >= 1.0f) { - value = 1.0f; - } - } - outputcode = (uint8_t)(value * 255.0f); - obj->handler->REG = outputcode; - wait_ms(3); -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - analogout_start(obj); - obj->handler->REG = (uint8_t)(value & 0xFF); - wait_ms(3); -} - -float analogout_read(dac_t *obj) -{ - float result; - uint32_t value = 0; - - value = ((obj->handler->REG) & (0xFF)); - result = ((float)value / 255.0f); - - return result; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint16_t value = 0; - - value = (uint16_t)((obj->handler->REG) & (0xFF)); - - return value; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device.h deleted file mode 100644 index ff9910ab575..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h deleted file mode 100644 index 0aaef3e355f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h +++ /dev/null @@ -1,4539 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM3HQ.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V1.0.0.1 - * $Date:: 2017-12-27 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM3HQ - * @{ - */ - -#ifndef __TMPM3HQ_H__ -#define __TMPM3HQ_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** TMPM3HQ Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt Pin 00 */ - INT01_IRQn = 1, /*!< Interrupt Pin 01 */ - INT02_IRQn = 2, /*!< Interrupt Pin 02 */ - INT03_IRQn = 3, /*!< Interrupt Pin 03 */ - INT04_IRQn = 4, /*!< Interrupt Pin 04 */ - INT05_IRQn = 5, /*!< Interrupt Pin 05 */ - INT06_IRQn = 6, /*!< Interrupt Pin 06 */ - INT07_IRQn = 7, /*!< Interrupt Pin 07 */ - INT08_IRQn = 8, /*!< Interrupt Pin 08 */ - INT09_IRQn = 9, /*!< Interrupt Pin 09 */ - INT10_IRQn = 10, /*!< Interrupt Pin 10 */ - INT11_IRQn = 11, /*!< Interrupt Pin 11 */ - INT12_IRQn = 12, /*!< Interrupt Pin 12 */ - INT13_IRQn = 13, /*!< Interrupt Pin 13 */ - INT14_IRQn = 14, /*!< Interrupt Pin 14 */ - INT15_IRQn = 15, /*!< Interrupt Pin 15 */ - INT16_IRQn = 16, /*!< Interrupt Pin 16 */ - INT17_18_IRQn = 17, /*!< Interrupt Pin 17_18 */ - INT19_22_IRQn = 18, /*!< Interrupt Pin 19_22 */ - INT23_26_IRQn = 19, /*!< Interrupt Pin 23_26 */ - INT27_28_IRQn = 20, /*!< Interrupt Pin 27_28 */ - INT29_IRQn = 21, /*!< Interrupt Pin 29 */ - INT30_31_IRQn = 22, /*!< Interrupt Pin 30_31 */ - INTEMG0_IRQn = 23, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 24, /*!< PMD0 OVV interrupt */ - INTPMD0_IRQn = 25, /*!< PMD0 interrupt */ - INTENC00_IRQn = 26, /*!< Encoder 0 interrupt 0 */ - INTENC01_IRQn = 27, /*!< Encoder 0 interrupt 1 */ - INTADAPDA_IRQn = 28, /*!< ADC conversion triggered by PMD is finished A */ - INTADAPDB_IRQn = 29, /*!< ADC conversion triggered by PMD is finished B */ - INTADACP0_IRQn = 30, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 31, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 32, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 33, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 34, /*!< ADC conversion triggered by Continuity program is finished */ - INTT0RX_IRQn = 35, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 36, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 37, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 38, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 39, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 40, /*!< TSPI/SIO error (channel 1) */ - INTT2RX_IRQn = 41, /*!< TSPI/SIO reception (channel 2) */ - INTT2TX_IRQn = 42, /*!< TSPI/SIO transmit (channel 2) */ - INTT2ERR_IRQn = 43, /*!< TSPI/SIO error (channel 2) */ - INTT3RX_IRQn = 44, /*!< TSPI/SIO reception (channel 3) */ - INTT3TX_IRQn = 45, /*!< TSPI/SIO transmit (channel 3) */ - INTT3ERR_IRQn = 46, /*!< TSPI/SIO error (channel 3) */ - INTT4RX_IRQn = 47, /*!< TSPI/SIO reception (channel 4) */ - INTT4TX_IRQn = 48, /*!< TSPI/SIO transmit (channel 4) */ - INTT4ERR_IRQn = 49, /*!< TSPI/SIO error (channel 4) */ - INTI2CWUP_IRQn = 50, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ - INTI2C0_IRQn = 51, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 52, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 53, /*!< I2C0 bus free interrupt */ - INTI2C0NA_IRQn = 54, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 55, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 56, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 57, /*!< I2C1 bus free interrupt */ - INTI2C1NA_IRQn = 58, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 59, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 60, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 61, /*!< I2C2 bus free interrupt */ - INTI2C2NA_IRQn = 62, /*!< I2C2 no ack interrupt */ - INTI2C3_IRQn = 63, /*!< I2C3 transmission and reception interrupt */ - INTI2C3AL_IRQn = 64, /*!< I2C3 arbitration lost interrupt */ - INTI2C3BF_IRQn = 65, /*!< I2C3 bus free interrupt */ - INTI2C3NA_IRQn = 66, /*!< I2C3 no ack interrupt */ - INTUART0RX_IRQn = 67, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 68, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 69, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 70, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 71, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 72, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 73, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 74, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 75, /*!< UART error (channel 2) */ - INTUART3RX_IRQn = 76, /*!< UART reception (channel 3) */ - INTUART3TX_IRQn = 77, /*!< UART transmit (channel 3) */ - INTUART3ERR_IRQn = 78, /*!< UART error (channel 3) */ - INTUART4RX_IRQn = 79, /*!< UART reception (channel 4) */ - INTUART4TX_IRQn = 80, /*!< UART transmit (channel 4) */ - INTUART4ERR_IRQn = 81, /*!< UART error (channel 4) */ - INTUART5RX_IRQn = 82, /*!< UART reception (channel 5) */ - INTUART5TX_IRQn = 83, /*!< UART transmit (channel 5) */ - INTUART5ERR_IRQn = 84, /*!< UART error (channel 5) */ - INTT32A00A_IRQn = 85, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ - INTT32A00ACAP0_IRQn = 86, /*!< 32bit T32A00A input capture 0 */ - INTT32A00ACAP1_IRQn = 87, /*!< 32bit T32A00A input capture 1 */ - INTT32A00B_IRQn = 88, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ - INTT32A00BCAP0_IRQn = 89, /*!< 32bit T32A00B input capture 0 */ - INTT32A00BCAP1_IRQn = 90, /*!< 32bit T32A00B input capture 1 */ - INTT32A00C_IRQn = 91, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ - INTT32A00CCAP0_IRQn = 92, /*!< 32bit T32A00C input capture 0 */ - INTT32A00CCAP1_IRQn = 93, /*!< 32bit T32A00C input capture 1 */ - INTT32A01A_IRQn = 94, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ - INTT32A01ACAP0_IRQn = 95, /*!< 32bit T32A01A input capture 0 */ - INTT32A01ACAP1_IRQn = 96, /*!< 32bit T32A01A input capture 1 */ - INTT32A01B_IRQn = 97, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ - INTT32A01BCAP0_IRQn = 98, /*!< 32bit T32A01B input capture 0 */ - INTT32A01BCAP1_IRQn = 99, /*!< 32bit T32A01B input capture 1 */ - INTT32A01C_IRQn = 100, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ - INTT32A01CCAP0_IRQn = 101, /*!< 32bit T32A01C input capture 0 */ - INTT32A01CCAP1_IRQn = 102, /*!< 32bit T32A01C input capture 1 */ - INTT32A02A_IRQn = 103, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ - INTT32A02ACAP0_IRQn = 104, /*!< 32bit T32A02A input capture 0 */ - INTT32A02ACAP1_IRQn = 105, /*!< 32bit T32A02A input capture 1 */ - INTT32A02B_IRQn = 106, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ - INTT32A02BCAP0_IRQn = 107, /*!< 32bit T32A02B input capture 0 */ - INTT32A02BCAP1_IRQn = 108, /*!< 32bit T32A02B input capture 1 */ - INTT32A02C_IRQn = 109, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ - INTT32A02CCAP0_IRQn = 110, /*!< 32bit T32A02C input capture 0 */ - INTT32A02CCAP1_IRQn = 111, /*!< 32bit T32A02C input capture 1 */ - INTT32A03A_IRQn = 112, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ - INTT32A03ACAP0_IRQn = 113, /*!< 32bit T32A03A input capture 0 */ - INTT32A03ACAP1_IRQn = 114, /*!< 32bit T32A03A input capture 1 */ - INTT32A03B_IRQn = 115, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ - INTT32A03BCAP0_IRQn = 116, /*!< 32bit T32A03B input capture 0 */ - INTT32A03BCAP1_IRQn = 117, /*!< 32bit T32A03B input capture 1 */ - INTT32A03C_IRQn = 118, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ - INTT32A03CCAP0_IRQn = 119, /*!< 32bit T32A03C input capture 0 */ - INTT32A03CCAP1_IRQn = 120, /*!< 32bit T32A03C input capture 1 */ - INTT32A04A_IRQn = 121, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ - INTT32A04ACAP0_IRQn = 122, /*!< 32bit T32A04A input capture 0 */ - INTT32A04ACAP1_IRQn = 123, /*!< 32bit T32A04A input capture 1 */ - INTT32A04B_IRQn = 124, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ - INTT32A04BCAP0_IRQn = 125, /*!< 32bit T32A04B input capture 0 */ - INTT32A04BCAP1_IRQn = 126, /*!< 32bit T32A04B input capture 1 */ - INTT32A04C_IRQn = 127, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ - INTT32A04CCAP0_IRQn = 128, /*!< 32bit T32A04C input capture 0 */ - INTT32A04CCAP1_IRQn = 129, /*!< 32bit T32A04C input capture 1 */ - INTT32A05A_IRQn = 130, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ - INTT32A05ACAP0_IRQn = 131, /*!< 32bit T32A05A input capture 0 */ - INTT32A05ACAP1_IRQn = 132, /*!< 32bit T32A05A input capture 1 */ - INTT32A05B_IRQn = 133, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ - INTT32A05BCAP0_IRQn = 134, /*!< 32bit T32A05B input capture 0 */ - INTT32A05BCAP1_IRQn = 135, /*!< 32bit T32A05B input capture 1 */ - INTT32A05C_IRQn = 136, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ - INTT32A05CCAP0_IRQn = 137, /*!< 32bit T32A05C input capture 0 */ - INTT32A05CCAP1_IRQn = 138, /*!< 32bit T32A05C input capture 1 */ - INTT32A06A_IRQn = 139, /*!< 32bit T32A06A compare match detection 0 / Over flow / under flow*/ - INTT32A06ACAP0_IRQn = 140, /*!< 32bit T32A06A input capture 0 */ - INTT32A06ACAP1_IRQn = 141, /*!< 32bit T32A06A input capture 1 */ - INTT32A06B_IRQn = 142, /*!< 32bit T32A06B compare match detection 0 / Over flow / under flow*/ - INTT32A06BCAP0_IRQn = 143, /*!< 32bit T32A06B input capture 0 */ - INTT32A06BCAP1_IRQn = 144, /*!< 32bit T32A06B input capture 1 */ - INTT32A06C_IRQn = 145, /*!< 32bit T32A06C compare match detection 0 / Over flow / under flow*/ - INTT32A06CCAP0_IRQn = 146, /*!< 32bit T32A06C input capture 0 */ - INTT32A06CCAP1_IRQn = 147, /*!< 32bit T32A06C input capture 1 */ - INTT32A07A_IRQn = 148, /*!< 32bit T32A07A compare match detection 0 / Over flow / under flow*/ - INTT32A07ACAP0_IRQn = 149, /*!< 32bit T32A07A input capture 0 */ - INTT32A07ACAP1_IRQn = 150, /*!< 32bit T32A07A input capture 1 */ - INTT32A07B_IRQn = 151, /*!< 32bit T32A07B compare match detection 0 / Over flow / under flow*/ - INTT32A07BCAP0_IRQn = 152, /*!< 32bit T32A07B input capture 0 */ - INTT32A07BCAP1_IRQn = 153, /*!< 32bit T32A07B input capture 1 */ - INTT32A07C_IRQn = 154, /*!< 32bit T32A07C compare match detection 0 / Over flow / under flow*/ - INTT32A07CCAP0_IRQn = 155, /*!< 32bit T32A07C input capture 0 */ - INTT32A07CCAP1_IRQn = 156, /*!< 32bit T32A07C input capture 1 */ - INTPARI_IRQn = 157, /*!< RAM parity interrupt */ - INTDMAATC_IRQn = 158, /*!< DMAA end of transfer */ - INTDMAAERR_IRQn = 159, /*!< DMAA transfer error */ - INTDMABTC_IRQn = 160, /*!< DMAB end of transfer */ - INTDMABERR_IRQn = 161, /*!< DMAB transfer error */ - INTRTC_IRQn = 162, /*!< Real time clock interrupt */ - INTRMC0_IRQn = 163, /*!< Remote control reception interrupt */ - INTFLCRDY_IRQn = 164, /*!< Code FLASH Ready interrupt */ - INTFLDRDY_IRQn = 165 /*!< Data FLASH Ready interrupt */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_TMPM3HQ.h" /* TMPM3HQ System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ - __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ - __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ - __IO uint8_t IMC03; /*!< Interrupu Mode Control Register(A) 03 */ - uint8_t RESERVED1[12]; - __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ - __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset LOSC Management register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief I2C Wakeup control register - */ -typedef struct -{ - __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ - __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ - __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ - __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ -} TSB_I2CS_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR; /*!< LVD Control register */ -} TSB_LVD_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t STATUS; /*!< DMA Status Register */ - __O uint32_t CFG; /*!< DMA Configuration Register */ - __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ - __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base -Pointer Register*/ - uint32_t RESERVED0; - __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ - __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ - __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ - __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ - __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ - __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ - __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ - __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ - __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ - __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ - __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ - uint32_t RESERVED1[3]; - __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ -} TSB_DMA_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CTL; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< I2C Interrupt Register */ - __IO uint32_t OP; /*!< I2C Optiononal Function register */ - __I uint32_t PM; /*!< I2C Bus Monitor register */ - __IO uint32_t AR2; /*!< I2C Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - uint32_t RESERVED0[3]; - __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ - __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ - __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ - __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ - __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ - __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ - __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ - __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ - __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ - __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ - __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ - __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ - __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ - __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ - __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ - __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ - __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ - __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ - __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ - __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ - __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ - uint32_t RESERVED1[3]; - __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ - __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ - __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ - __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ - __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ - __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ - __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ - __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED2[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief T32A - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ - __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ - __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ - __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ - __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ - __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ - __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ - __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software reset register */ - __IO uint32_t CR0; /*!< UART Control register 0 */ - __IO uint32_t CR1; /*!< UART Control register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control register */ - __IO uint32_t BRD; /*!< UART Baud rate register */ - __IO uint32_t TRANS; /*!< UART Transfer enable register */ - __IO uint32_t DR; /*!< UART Data register */ - __IO uint32_t SR; /*!< UART Status register */ - __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ - __IO uint32_t ERR; /*!< UART Error register */ -} TSB_UART_TypeDef; - -/** - * @brief SIWD - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect register */ - __IO uint32_t EN; /*!< SIWD Enable register */ - __O uint32_t CR; /*!< SIWD Control register */ - __IO uint32_t MOD; /*!< SIWD Mode register */ - __I uint32_t MONI; /*!< SIWD Monitor register */ - __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ -} TSB_SIWD_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ - __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ - __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ - __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ - __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ - __IO uint32_t CR15; /*!< TRGSEL Control register 15 */ -} TSB_TSEL_TypeDef; - -/** - * @brief RAM Parity - */ -typedef struct -{ - __IO uint32_t CTL; /*!< RAMM Parity control register */ - __I uint32_t ST; /*!< RAMM Parity status register */ - __O uint32_t CLR; /*!< RAMM Parity status clear register */ - __I uint32_t EAD0; /*!< RAMM Parity Error address register 0 */ - __I uint32_t EAD1; /*!< RAMM Parity Error address register 1 */ - __I uint32_t EAD2; /*!< RAMM Parity Error address register 2 */ - __I uint32_t EAD3; /*!< RAMM Parity Error address register 3 */ -} TSB_RPAR_TypeDef; - -/** - * @brief CRC - */ -typedef struct -{ - __IO uint32_t DIN; /*!< CRC input data register */ - uint32_t RESERVED0[4]; - __IO uint32_t TYP; /*!< CRC data type register */ - uint32_t RESERVED1[5]; - __IO uint32_t CLC; /*!< CRC calculation result register */ -} TSB_CRC_TypeDef; - -/** - * @brief CMP - */ -typedef struct -{ - __IO uint32_t CTRLA; /*!< CMP control register A */ -} TSB_CMP_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PA Data Register */ - __IO uint32_t CR; /*!< PA Control Register */ - __IO uint32_t FR1; /*!< PA Function Register 1 */ - __IO uint32_t FR2; /*!< PA Function Register 2 */ - __IO uint32_t FR3; /*!< PA Function Register 3 */ - __IO uint32_t FR4; /*!< PA Function Register 4 */ - __IO uint32_t FR5; /*!< PA Function Register 5 */ - __IO uint32_t FR6; /*!< PA Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PA Open Drain Control Register */ - __IO uint32_t PUP; /*!< PA Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PA Input Enable Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PB Data Register */ - __IO uint32_t CR; /*!< PB Control Register */ - __IO uint32_t FR1; /*!< PB Function Register 1 */ - __IO uint32_t FR2; /*!< PB Function Register 2 */ - __IO uint32_t FR3; /*!< PB Function Register 3 */ - __IO uint32_t FR4; /*!< PB Function Register 4 */ - __IO uint32_t FR5; /*!< PB Function Register 5 */ - __IO uint32_t FR6; /*!< PB Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PB Open Drain Control Register */ - __IO uint32_t PUP; /*!< PB Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PB Input Enable Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PC Data Register */ - __IO uint32_t CR; /*!< PC Control Register */ - __IO uint32_t FR1; /*!< PC Function Register 1 */ - __IO uint32_t FR2; /*!< PC Function Register 2 */ - __IO uint32_t FR3; /*!< PC Function Register 3 */ - __IO uint32_t FR4; /*!< PC Function Register 4 */ - __IO uint32_t FR5; /*!< PC Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PC Open Drain Control Register */ - __IO uint32_t PUP; /*!< PC Pull-up Control Register */ - __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PC Input Enable Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PD Data Register */ - __IO uint32_t CR; /*!< PD Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PD Open Drain Control Register */ - __IO uint32_t PUP; /*!< PD Pull-up Control Register */ - __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PD Input Enable Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PE Data Register */ - __IO uint32_t CR; /*!< PE Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PE Open Drain Control Register */ - __IO uint32_t PUP; /*!< PE Pull-up Control Register */ - __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PE Input Enable Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief Port F - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PF Data Register */ - __IO uint32_t CR; /*!< PF Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PF Open Drain Control Register */ - __IO uint32_t PUP; /*!< PF Pull-up Control Register */ - __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PF Input Enable Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief Port G - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PG Data Register */ - __IO uint32_t CR; /*!< PG Control Register */ - __IO uint32_t FR1; /*!< PG Function Register 1 */ - __IO uint32_t FR2; /*!< PG Function Register 2 */ - __IO uint32_t FR3; /*!< PG Function Register 3 */ - __IO uint32_t FR4; /*!< PG Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PG Open Drain Control Register */ - __IO uint32_t PUP; /*!< PG Pull-up Control Register */ - __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PG Input Enable Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief Port H - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PH Data Register */ - __IO uint32_t CR; /*!< PH Control Register */ - __IO uint32_t FR1; /*!< PH Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PH Open Drain Control Register */ - __IO uint32_t PUP; /*!< PH Pull-up Control Register */ - __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PH Input Enable Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief Port J - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PJ Data Register */ - __IO uint32_t CR; /*!< PJ Control Register */ - __IO uint32_t FR1; /*!< PJ Function Register 1 */ - __IO uint32_t FR2; /*!< PJ Function Register 2 */ - __IO uint32_t FR3; /*!< PJ Function Register 3 */ - __IO uint32_t FR4; /*!< PJ Function Register 4 */ - __IO uint32_t FR5; /*!< PJ Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PJ Open Drain Control Register */ - __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ - __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PJ Input Enable Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief Port K - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PK Data Register */ - __IO uint32_t CR; /*!< PK Control Register */ - __IO uint32_t FR1; /*!< PK Function Register 1 */ - __IO uint32_t FR2; /*!< PK Function Register 2 */ - __IO uint32_t FR3; /*!< PK Function Register 3 */ - __IO uint32_t FR4; /*!< PK Function Register 4 */ - __IO uint32_t FR5; /*!< PK Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PK Open Drain Control Register */ - __IO uint32_t PUP; /*!< PK Pull-up Control Register */ - __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PK Input Enable Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief Port L - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PL Data Register */ - __IO uint32_t CR; /*!< PL Control Register */ - __IO uint32_t FR1; /*!< PL Function Register 1 */ - __IO uint32_t FR2; /*!< PL Function Register 2 */ - __IO uint32_t FR3; /*!< PL Function Register 3 */ - __IO uint32_t FR4; /*!< PL Function Register 4 */ - __IO uint32_t FR5; /*!< PL Function Register 4 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PL Open Drain Control Register */ - __IO uint32_t PUP; /*!< PL Pull-up Control Register */ - __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PL Input Enable Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief Port M - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PM Data Register */ - __IO uint32_t CR; /*!< PM Control Register */ - __IO uint32_t FR1; /*!< PM Function Register 1 */ - __IO uint32_t FR2; /*!< PM Function Register 2 */ - __IO uint32_t FR3; /*!< PM Function Register 3 */ - __IO uint32_t FR4; /*!< PM Function Register 4 */ - __IO uint32_t FR5; /*!< PM Function Register 5 */ - __IO uint32_t FR6; /*!< PM Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PM Open Drain Control Register */ - __IO uint32_t PUP; /*!< PM Pull-up Control Register */ - __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PM Input Enable Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief Port N - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PN Data Register */ - __IO uint32_t CR; /*!< PN Control Register */ - __IO uint32_t FR1; /*!< PN Function Register 1 */ - __IO uint32_t FR2; /*!< PN Function Register 2 */ - __IO uint32_t FR3; /*!< PN Function Register 3 */ - __IO uint32_t FR4; /*!< PN Function Register 4 */ - __IO uint32_t FR5; /*!< PN Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PN Open Drain Control Register */ - __IO uint32_t PUP; /*!< PN Pull-up Control Register */ - __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PN Input Enable Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief Port P - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PP Data Register */ - __IO uint32_t CR; /*!< PP Control Register */ - __IO uint32_t FR1; /*!< PP Function Register 1 */ - __IO uint32_t FR2; /*!< PP Function Register 2 */ - __IO uint32_t FR3; /*!< PP Function Register 3 */ - __IO uint32_t FR4; /*!< PP Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PP Open Drain Control Register */ - __IO uint32_t PUP; /*!< PP Pull-up Control Register */ - __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PP Input Enable Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief Port R - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PR Data Register */ - __IO uint32_t CR; /*!< PR Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< PR Function Register 3 */ - __IO uint32_t FR4; /*!< PR Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< PR Open Drain Control Register */ - __IO uint32_t PUP; /*!< PR Pull-up Control Register */ - __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PR Input Enable Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief Port T - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PT Data Register */ - __IO uint32_t CR; /*!< PT Control Register */ - __IO uint32_t FR1; /*!< PT Function Register 1 */ - __IO uint32_t FR2; /*!< PT Function Register 2 */ - __IO uint32_t FR3; /*!< PT Function Register 3 */ - __IO uint32_t FR4; /*!< PT Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PT Open Drain Control Register */ - __IO uint32_t PUP; /*!< PT Pull-up Control Register */ - __IO uint32_t PDN; /*!< PT Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PT Input Enable Control Register */ -} TSB_PT_TypeDef; - -/** - * @brief Port U - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PU Data Register */ - __IO uint32_t CR; /*!< PU Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PU Open Drain Control Register */ - __IO uint32_t PUP; /*!< PU Pull-up Control Register */ - __IO uint32_t PDN; /*!< PU Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PU Input Enable Control Register */ -} TSB_PU_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PV Data Register */ - __IO uint32_t CR; /*!< PV Control Register */ - __IO uint32_t FR1; /*!< PV Function Register 1 */ - __IO uint32_t FR2; /*!< PV Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PV Open Drain Control Register */ - __IO uint32_t PUP; /*!< PV Pull-up Control Register */ - __IO uint32_t PDN; /*!< PV Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PV Input Enable Control Register */ -} TSB_PV_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ - __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ -} TSB_RTC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< CG Protect Register */ - __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< CG System clock control register */ - __IO uint32_t STBYCR; /*!< CG Standby Control Register */ - __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ - __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ - uint32_t RESERVED2[6]; - __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ - __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ - __IO uint32_t FCEN; /*!< CG output control register for fc clock */ - __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ -} TSB_CG_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protect register */ - __IO uint32_t OSCEN; /*!< TRM Enable register */ - __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ - __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ -} TSB_TRM_TypeDef; - -/** - * @brief Interrupt control register B - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ - __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ - __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ - __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ - __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ - __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ - __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ - __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ - __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ - __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ - __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ - __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ - __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ - __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ - __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ - __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ - __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ - __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ - __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ - __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ - __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ - __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ - __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ - __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ - __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ - __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ - __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ - __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ - __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ - __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ - __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ - __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ - __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ - __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ - __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ - __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ - __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ - __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ - __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ - __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ - __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ - __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ - __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ - __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ - __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ - __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ - __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ - __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ - __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ - __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ - __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ - __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ - __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ - __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ - __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ - __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ - __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ - __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ - __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ - __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ - __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ - __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ - __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ - __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ - __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ - __IO uint8_t IMC065; /*!< Interrupt Mode Control Register(B) 065 */ - __IO uint8_t IMC066; /*!< Interrupu Mode Control Register(B) 066 */ - __IO uint8_t IMC067; /*!< Interrupu Mode Control Register(B) 067 */ - __IO uint8_t IMC068; /*!< Interrupu Mode Control Register(B) 068 */ - __IO uint8_t IMC069; /*!< Interrupu Mode Control Register(B) 069 */ - __IO uint8_t IMC070; /*!< Interrupu Mode Control Register(B) 070 */ - __IO uint8_t IMC071; /*!< Interrupu Mode Control Register(B) 071 */ - __IO uint8_t IMC072; /*!< Interrupu Mode Control Register(B) 072 */ - __IO uint8_t IMC073; /*!< Interrupu Mode Control Register(B) 073 */ - __IO uint8_t IMC074; /*!< Interrupu Mode Control Register(B) 074 */ - __IO uint8_t IMC075; /*!< Interrupu Mode Control Register(B) 075 */ - __IO uint8_t IMC076; /*!< Interrupu Mode Control Register(B) 076 */ - __IO uint8_t IMC077; /*!< Interrupu Mode Control Register(B) 077 */ - __IO uint8_t IMC078; /*!< Interrupu Mode Control Register(B) 078 */ - __IO uint8_t IMC079; /*!< Interrupu Mode Control Register(B) 079 */ - __IO uint8_t IMC080; /*!< Interrupu Mode Control Register(B) 080 */ - __IO uint8_t IMC081; /*!< Interrupu Mode Control Register(B) 081 */ - __IO uint8_t IMC082; /*!< Interrupu Mode Control Register(B) 082 */ - __IO uint8_t IMC083; /*!< Interrupu Mode Control Register(B) 083 */ - __IO uint8_t IMC084; /*!< Interrupu Mode Control Register(B) 084 */ - __IO uint8_t IMC085; /*!< Interrupu Mode Control Register(B) 085 */ - __IO uint8_t IMC086; /*!< Interrupu Mode Control Register(B) 086 */ - __IO uint8_t IMC087; /*!< Interrupu Mode Control Register(B) 087 */ - __IO uint8_t IMC088; /*!< Interrupu Mode Control Register(B) 088 */ - __IO uint8_t IMC089; /*!< Interrupu Mode Control Register(B) 089 */ - __IO uint8_t IMC090; /*!< Interrupu Mode Control Register(B) 090 */ - __IO uint8_t IMC091; /*!< Interrupu Mode Control Register(B) 091 */ - __IO uint8_t IMC092; /*!< Interrupu Mode Control Register(B) 092 */ - __IO uint8_t IMC093; /*!< Interrupu Mode Control Register(B) 093 */ - __IO uint8_t IMC094; /*!< Interrupu Mode Control Register(B) 094 */ -} TSB_IB_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ - uint32_t RESERVED0; - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ - __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ - __I uint32_t FLG5; /*!< NMI Interrupt Monitor Flag 5 */ -} TSB_IMN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ - __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ - __IO uint32_t RATE; /*!< PWM Frequency Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - uint32_t RESERVED0; - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ - __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ - __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ - __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ - uint32_t RESERVED1; - __IO uint32_t DBGOUTCR; /*!< Debug output control */ -} TSB_PMD_TypeDef; - -/** - * @brief Encoder Input (ENC) - */ -typedef struct -{ - __IO uint32_t TNCR; /*!< ENC Control Register */ - __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ - __IO uint32_t INT; /*!< ENC INT Compare Register */ - __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ - __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ - __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ - __I uint32_t STS; /*!< ENC Status Register */ - __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ - __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ - __I uint32_t INPMON; /*!< ENC Input Moniter Register */ - __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ - __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ - __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ -} TSB_EN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3[4]; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED4; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED5[4]; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED6[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED7[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED8; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED9; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) -#define TSB_DMAB_BASE (PERI_BASE + 0x004D000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) -#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) -#define TSB_TSPI2_BASE (PERI_BASE + 0x009A000UL) -#define TSB_TSPI3_BASE (PERI_BASE + 0x009B000UL) -#define TSB_TSPI4_BASE (PERI_BASE + 0x009C000UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_I2C3_BASE (PERI_BASE + 0x00A3000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) -#define TSB_T32A6_BASE (PERI_BASE + 0x00BA600UL) -#define TSB_T32A7_BASE (PERI_BASE + 0x00BA700UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) -#define TSB_UART3_BASE (PERI_BASE + 0x00BB300UL) -#define TSB_UART4_BASE (PERI_BASE + 0x00BBD00UL) -#define TSB_UART5_BASE (PERI_BASE + 0x00BBE00UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) -#define TSB_DNFB_BASE (PERI_BASE + 0x00BB700UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) -#define TSB_TSEL1_BASE (PERI_BASE + 0x00BB900UL) -#define TSB_RPAR_BASE (PERI_BASE + 0x00BBB00UL) -#define TSB_CRC_BASE (PERI_BASE + 0x00BBC00UL) -#define TSB_CMP_BASE (PERI_BASE + 0x00BC100UL) -#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) -#define TSB_PT_BASE (PERI_BASE + 0x00C0F00UL) -#define TSB_PU_BASE (PERI_BASE + 0x00C1000UL) -#define TSB_PV_BASE (PERI_BASE + 0x00C1100UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) -#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) -#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) -#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) -#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) -#define TSB_DMAB (( TSB_DMA_TypeDef *) TSB_DMAB_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) -#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) -#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) -#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) -#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) -#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_TSEL1 (( TSB_TSEL_TypeDef *) TSB_TSEL1_BASE) -#define TSB_RPAR (( TSB_RPAR_TypeDef *) TSB_RPAR_BASE) -#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) -#define TSB_CMP (( TSB_CMP_TypeDef *) TSB_CMP_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) -#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) -#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - - - - - -/* DMA Controller */ -#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) -#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) -#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) - -#define TSB_DMAB_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAB->STATUS,0))) -#define TSB_DMAB_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAB->CFG,0))) -#define TSB_DMAB_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAB->ERRCLR,0))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) - -#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - -#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) -#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) -#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) -#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) -#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) -#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) -#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) -#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) -#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) -#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) -#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) -#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) -#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) -#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) -#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) -#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) -#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) -#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) -#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) -#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) -#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) -#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) -#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) -#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) -#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) -#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) -#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) -#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) -#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) -#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) -#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) -#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) -#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) -#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) -#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) -#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) -#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) -#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) - -#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) -#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) -#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) -#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) -#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) -#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) -#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) -#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) -#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) -#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) -#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) -#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) -#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) -#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) -#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) -#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) -#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) -#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) -#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) -#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) -#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) -#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) -#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) -#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) -#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) -#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) -#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) -#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) -#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) -#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) -#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) -#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) -#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) -#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) -#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) -#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) -#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) -#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) - -#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) -#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) -#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) -#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) -#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) -#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) -#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) -#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) -#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) -#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) -#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) -#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) -#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) -#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) -#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) -#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) -#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) -#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) -#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) -#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) -#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) -#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) -#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) -#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) -#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) -#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) -#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) -#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) -#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) -#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) -#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) -#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) -#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) -#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) -#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) -#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) -#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) -#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - -#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) -#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) -#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) -#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) -#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) -#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) -#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) -#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) -#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) -#define TSB_I2C3_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) -#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) -#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) -#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) -#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) -#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) -#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) -#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) -#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) -#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) -#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) -#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) -#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) -#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) -#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) -#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) -#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) -#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) -#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) -#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) -#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) -#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) -#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) -#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) -#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) -#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) -#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) -#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) -#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) -#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) -#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) -#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) -#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) -#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) -#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) -#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) -#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) -#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) -#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) -#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) -#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) -#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) -#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) -#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) -#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) -#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) -#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) -#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) -#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) -#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) -#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) -#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) -#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) -#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) -#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) -#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) -#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) -#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) -#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) -#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) -#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) -#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) -#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) -#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) -#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) -#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) -#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) -#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) -#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) -#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) -#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) -#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* T32A */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - -#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) -#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) -#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) -#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) -#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) -#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) -#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) -#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) -#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) -#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) -#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) -#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) -#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) -#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) -#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) -#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) -#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) -#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) -#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) -#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) -#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) -#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) -#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) -#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) -#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) -#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) -#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) -#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) -#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) -#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) -#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) -#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) -#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) -#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) -#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) -#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) -#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) -#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) -#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) -#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) -#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) -#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) -#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) -#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) -#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) -#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) -#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) -#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) -#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) -#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) -#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) -#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) -#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) -#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) - -#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) -#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) -#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) -#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) -#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) -#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) -#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) -#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) -#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) -#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) -#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) -#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) -#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) -#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) -#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) -#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) -#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) -#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) -#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) -#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) -#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) -#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) -#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) -#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) -#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) -#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) -#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) -#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) -#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) -#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) -#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) -#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) -#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) -#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) -#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) -#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) -#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) -#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) -#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) -#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) -#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) -#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) -#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) -#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) -#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) -#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) -#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) -#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) -#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) -#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) -#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) -#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) -#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) -#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) -#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) -#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) -#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) -#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) -#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) -#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - -#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) -#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) -#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) -#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) -#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) -#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) -#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) -#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) -#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) -#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) -#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) -#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) -#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) -#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) -#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) -#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) -#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) -#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) -#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) -#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) -#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) -#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) -#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) -#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) -#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) -#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) -#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) -#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) -#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) -#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) -#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) -#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) -#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) -#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) -#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) -#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) -#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) -#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) -#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) -#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) -#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) -#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) - -#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) -#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) -#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) -#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) -#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) -#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) -#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) -#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) -#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) -#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) -#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) -#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) -#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) -#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) -#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) -#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) -#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) -#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) -#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) -#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) -#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) -#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) -#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) -#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) -#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) -#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) -#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) -#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) -#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) -#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) -#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) -#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) -#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) -#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) -#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) -#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) -#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) -#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) -#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) -#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) -#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) -#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) - -#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) -#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) -#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) -#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) -#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) -#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) -#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) -#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) -#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) -#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) -#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) -#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) -#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) -#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) -#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) -#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) -#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) -#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) -#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) -#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) -#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) -#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) -#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) -#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) -#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) -#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) -#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) -#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) -#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) -#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) -#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) -#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) -#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) -#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) -#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) -#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) -#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) -#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) -#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) -#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) -#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) -#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) - - -/* SIWD */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) -#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - -#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) -#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) -#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) -#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) -#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) -#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) -#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) -#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) -#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) -#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) -#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) -#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) -#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) -#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) -#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) -#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) -#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) -#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) -#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) -#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) -#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) -#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) -#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) -#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) -#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) -#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) -#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) -#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) -#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) -#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) -#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) -#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) -#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) -#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) -#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) -#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) -#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) -#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) -#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) -#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) -#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) -#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) -#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) -#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) -#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) -#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) -#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) -#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) -#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) -#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) -#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) -#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) -#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) -#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) -#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) -#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) -#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) -#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) -#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) -#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) -#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) -#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) -#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) -#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) -#define TSB_TSEL0_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,8))) -#define TSB_TSEL0_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,9))) -#define TSB_TSEL0_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,10))) -#define TSB_TSEL0_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,16))) -#define TSB_TSEL0_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,17))) -#define TSB_TSEL0_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,18))) -#define TSB_TSEL0_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,24))) -#define TSB_TSEL0_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,25))) -#define TSB_TSEL0_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,26))) -#define TSB_TSEL0_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,0))) -#define TSB_TSEL0_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,1))) -#define TSB_TSEL0_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,2))) -#define TSB_TSEL0_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,8))) -#define TSB_TSEL0_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,9))) -#define TSB_TSEL0_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,10))) -#define TSB_TSEL0_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,16))) -#define TSB_TSEL0_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,17))) -#define TSB_TSEL0_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,18))) -#define TSB_TSEL0_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,24))) -#define TSB_TSEL0_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,25))) -#define TSB_TSEL0_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,26))) - -#define TSB_TSEL1_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,0))) -#define TSB_TSEL1_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,1))) -#define TSB_TSEL1_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,2))) -#define TSB_TSEL1_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,8))) -#define TSB_TSEL1_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,9))) -#define TSB_TSEL1_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,10))) -#define TSB_TSEL1_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,16))) -#define TSB_TSEL1_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,17))) -#define TSB_TSEL1_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,18))) -#define TSB_TSEL1_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,24))) -#define TSB_TSEL1_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,25))) -#define TSB_TSEL1_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,26))) -#define TSB_TSEL1_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,0))) -#define TSB_TSEL1_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,1))) -#define TSB_TSEL1_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,2))) -#define TSB_TSEL1_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,8))) -#define TSB_TSEL1_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,9))) -#define TSB_TSEL1_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,10))) -#define TSB_TSEL1_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,16))) -#define TSB_TSEL1_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,17))) -#define TSB_TSEL1_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,18))) -#define TSB_TSEL1_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,24))) -#define TSB_TSEL1_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,25))) -#define TSB_TSEL1_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,26))) -#define TSB_TSEL1_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,0))) -#define TSB_TSEL1_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,1))) -#define TSB_TSEL1_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,2))) -#define TSB_TSEL1_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,8))) -#define TSB_TSEL1_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,9))) -#define TSB_TSEL1_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,10))) -#define TSB_TSEL1_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,16))) -#define TSB_TSEL1_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,17))) -#define TSB_TSEL1_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,18))) -#define TSB_TSEL1_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,24))) -#define TSB_TSEL1_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,25))) -#define TSB_TSEL1_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,26))) -#define TSB_TSEL1_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,0))) -#define TSB_TSEL1_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,1))) -#define TSB_TSEL1_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,2))) -#define TSB_TSEL1_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,8))) -#define TSB_TSEL1_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,9))) -#define TSB_TSEL1_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,10))) -#define TSB_TSEL1_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,16))) -#define TSB_TSEL1_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,17))) -#define TSB_TSEL1_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,18))) -#define TSB_TSEL1_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,24))) -#define TSB_TSEL1_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,25))) -#define TSB_TSEL1_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,26))) -#define TSB_TSEL1_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,0))) -#define TSB_TSEL1_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,1))) -#define TSB_TSEL1_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,2))) -#define TSB_TSEL1_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,8))) -#define TSB_TSEL1_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,9))) -#define TSB_TSEL1_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,10))) -#define TSB_TSEL1_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,16))) -#define TSB_TSEL1_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,17))) -#define TSB_TSEL1_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,18))) -#define TSB_TSEL1_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,24))) -#define TSB_TSEL1_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,25))) -#define TSB_TSEL1_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,26))) -#define TSB_TSEL1_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,0))) -#define TSB_TSEL1_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,1))) -#define TSB_TSEL1_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,2))) -#define TSB_TSEL1_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,8))) -#define TSB_TSEL1_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,9))) -#define TSB_TSEL1_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,10))) -#define TSB_TSEL1_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,16))) -#define TSB_TSEL1_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,17))) -#define TSB_TSEL1_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,18))) -#define TSB_TSEL1_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,24))) -#define TSB_TSEL1_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,25))) -#define TSB_TSEL1_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,26))) -#define TSB_TSEL1_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,0))) -#define TSB_TSEL1_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,1))) -#define TSB_TSEL1_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,2))) -#define TSB_TSEL1_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,8))) -#define TSB_TSEL1_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,9))) -#define TSB_TSEL1_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,10))) -#define TSB_TSEL1_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,16))) -#define TSB_TSEL1_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,17))) -#define TSB_TSEL1_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,18))) -#define TSB_TSEL1_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,24))) -#define TSB_TSEL1_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,25))) -#define TSB_TSEL1_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,26))) -#define TSB_TSEL1_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,0))) -#define TSB_TSEL1_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,1))) -#define TSB_TSEL1_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,2))) -#define TSB_TSEL1_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,8))) -#define TSB_TSEL1_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,9))) -#define TSB_TSEL1_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,10))) -#define TSB_TSEL1_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,16))) -#define TSB_TSEL1_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,17))) -#define TSB_TSEL1_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,18))) -#define TSB_TSEL1_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,24))) -#define TSB_TSEL1_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,25))) -#define TSB_TSEL1_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,26))) -#define TSB_TSEL1_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,0))) -#define TSB_TSEL1_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,1))) -#define TSB_TSEL1_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,2))) -#define TSB_TSEL1_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,8))) -#define TSB_TSEL1_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,9))) -#define TSB_TSEL1_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,10))) -#define TSB_TSEL1_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,16))) -#define TSB_TSEL1_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,17))) -#define TSB_TSEL1_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,18))) -#define TSB_TSEL1_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,24))) -#define TSB_TSEL1_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,25))) -#define TSB_TSEL1_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,26))) -#define TSB_TSEL1_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,0))) -#define TSB_TSEL1_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,1))) -#define TSB_TSEL1_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,2))) -#define TSB_TSEL1_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,8))) -#define TSB_TSEL1_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,9))) -#define TSB_TSEL1_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,10))) -#define TSB_TSEL1_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,16))) -#define TSB_TSEL1_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,17))) -#define TSB_TSEL1_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,18))) -#define TSB_TSEL1_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,24))) -#define TSB_TSEL1_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,25))) -#define TSB_TSEL1_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,26))) -#define TSB_TSEL1_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,0))) -#define TSB_TSEL1_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,1))) -#define TSB_TSEL1_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,2))) -#define TSB_TSEL1_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,8))) -#define TSB_TSEL1_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,9))) -#define TSB_TSEL1_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,10))) -#define TSB_TSEL1_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,16))) -#define TSB_TSEL1_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,17))) -#define TSB_TSEL1_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,18))) -#define TSB_TSEL1_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,24))) -#define TSB_TSEL1_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,25))) -#define TSB_TSEL1_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,26))) -#define TSB_TSEL1_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,0))) -#define TSB_TSEL1_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,1))) -#define TSB_TSEL1_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,2))) -#define TSB_TSEL1_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,8))) -#define TSB_TSEL1_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,9))) -#define TSB_TSEL1_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,10))) -#define TSB_TSEL1_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,16))) -#define TSB_TSEL1_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,17))) -#define TSB_TSEL1_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,18))) -#define TSB_TSEL1_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,24))) -#define TSB_TSEL1_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,25))) -#define TSB_TSEL1_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,26))) -#define TSB_TSEL1_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,0))) -#define TSB_TSEL1_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,1))) -#define TSB_TSEL1_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,2))) -#define TSB_TSEL1_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,8))) -#define TSB_TSEL1_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,9))) -#define TSB_TSEL1_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,10))) -#define TSB_TSEL1_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,16))) -#define TSB_TSEL1_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,17))) -#define TSB_TSEL1_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,18))) -#define TSB_TSEL1_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,24))) -#define TSB_TSEL1_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,25))) -#define TSB_TSEL1_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,26))) -#define TSB_TSEL1_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,0))) -#define TSB_TSEL1_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,1))) -#define TSB_TSEL1_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,2))) -#define TSB_TSEL1_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,8))) -#define TSB_TSEL1_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,9))) -#define TSB_TSEL1_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,10))) -#define TSB_TSEL1_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,16))) -#define TSB_TSEL1_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,17))) -#define TSB_TSEL1_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,18))) -#define TSB_TSEL1_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,24))) -#define TSB_TSEL1_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,25))) -#define TSB_TSEL1_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,26))) -#define TSB_TSEL1_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,0))) -#define TSB_TSEL1_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,1))) -#define TSB_TSEL1_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,2))) -#define TSB_TSEL1_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,8))) -#define TSB_TSEL1_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,9))) -#define TSB_TSEL1_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,10))) -#define TSB_TSEL1_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,16))) -#define TSB_TSEL1_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,17))) -#define TSB_TSEL1_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,18))) -#define TSB_TSEL1_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,24))) -#define TSB_TSEL1_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,25))) -#define TSB_TSEL1_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,26))) -#define TSB_TSEL1_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,0))) -#define TSB_TSEL1_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,1))) -#define TSB_TSEL1_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,2))) -#define TSB_TSEL1_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,8))) -#define TSB_TSEL1_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,9))) -#define TSB_TSEL1_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,10))) -#define TSB_TSEL1_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,16))) -#define TSB_TSEL1_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,17))) -#define TSB_TSEL1_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,18))) -#define TSB_TSEL1_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,24))) -#define TSB_TSEL1_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,25))) -#define TSB_TSEL1_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,26))) - - -/* RAM Parity */ -#define TSB_RPAR_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,0))) -#define TSB_RPAR_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,1))) -#define TSB_RPAR_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,0))) -#define TSB_RPAR_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,1))) -#define TSB_RPAR_ST_RPARFG2 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,2))) -#define TSB_RPAR_ST_RPARFG3 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,3))) -#define TSB_RPAR_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,0))) -#define TSB_RPAR_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,1))) -#define TSB_RPAR_CLR_RPARCLR2 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,2))) -#define TSB_RPAR_CLR_RPARCLR3 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,3))) - - - -/* CMP */ -#define TSB_CMP_CTRLA_CMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,0))) -#define TSB_CMP_CTRLA_CMPISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,1))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) -#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR2_PA6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,6))) -#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) -#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) -#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) -#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) -#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) -#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) -#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) -#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) -#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) -#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) -#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) -#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) -#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) -#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) -#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) -#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) -#define TSB_PC_FR2_PC3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,3))) -#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) -#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) -#define TSB_PC_FR2_PC6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,6))) -#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) -#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) -#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) -#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) -#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) -#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) -#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) -#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) -#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) -#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) -#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) -#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) -#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) -#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) -#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) -#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) -#define TSB_PG_FR2_PG2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,2))) -#define TSB_PG_FR2_PG3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,3))) -#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) -#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) -#define TSB_PG_FR3_PG4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,4))) -#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) -#define TSB_PG_FR3_PG6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,6))) -#define TSB_PG_FR3_PG7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,7))) -#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) -#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) -#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) -#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) -#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) -#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) -#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) -#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) -#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) -#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) -#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) -#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) -#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) -#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) -#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) -#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) -#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) -#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) -#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) -#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) -#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) -#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) -#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) -#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) -#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) -#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) -#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) -#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) -#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) -#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) -#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) -#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) -#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) -#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) -#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) -#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) -#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) -#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) -#define TSB_PH_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) -#define TSB_PH_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) -#define TSB_PH_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) -#define TSB_PH_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) -#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) -#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) -#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) -#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) -#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) -#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) -#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) -#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) -#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) -#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) -#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) -#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) -#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) -#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) -#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) -#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) - - -/* Port K */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) -#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) -#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) -#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) -#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) -#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) -#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) -#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) -#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* Port L */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) -#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) -#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) -#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) -#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) -#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) -#define TSB_PL_FR3_PL2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,2))) -#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) -#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) -#define TSB_PL_FR3_PL5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,5))) -#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) -#define TSB_PL_FR3_PL7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,7))) -#define TSB_PL_FR4_PL5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,5))) -#define TSB_PL_FR4_PL6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,6))) -#define TSB_PL_FR4_PL7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,7))) -#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) -#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) -#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) -#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) -#define TSB_PL_FR5_PL4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,4))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) -#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) - - -/* Port M */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) -#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) -#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) -#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) -#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) -#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) -#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) -#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) -#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) -#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) - - -/* Port N */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) -#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) -#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) -#define TSB_PN_FR1_PN3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,3))) -#define TSB_PN_FR1_PN4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,4))) -#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) -#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) -#define TSB_PN_FR2_PN2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,2))) -#define TSB_PN_FR2_PN3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,3))) -#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) -#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) -#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) -#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) -#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) -#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) -#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) -#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) -#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) -#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) - - -/* Port P */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) -#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) -#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) -#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) -#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) -#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) -#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) -#define TSB_PP_FR1_PP3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,3))) -#define TSB_PP_FR1_PP4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,4))) -#define TSB_PP_FR1_PP5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,5))) -#define TSB_PP_FR1_PP6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,6))) -#define TSB_PP_FR1_PP7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,7))) -#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) -#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) -#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) -#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) -#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) -#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) -#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) -#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) -#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) -#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) -#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) -#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) -#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) -#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) -#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) -#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) -#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) -#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) -#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) -#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) -#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) - - -/* Port R */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) -#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) -#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) -#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) -#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) -#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) -#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) -#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) -#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) -#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) -#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) -#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) -#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) -#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) -#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) -#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) -#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) -#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) -#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) -#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) -#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) -#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) -#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) - - -/* Port T */ -#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) -#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) -#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) -#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) -#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) -#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) -#define TSB_PT_DATA_PT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,6))) -#define TSB_PT_DATA_PT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,7))) -#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) -#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) -#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) -#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) -#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) -#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) -#define TSB_PT_CR_PT6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,6))) -#define TSB_PT_CR_PT7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,7))) -#define TSB_PT_FR1_PT0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,0))) -#define TSB_PT_FR1_PT1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,1))) -#define TSB_PT_FR1_PT2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,2))) -#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) -#define TSB_PT_FR1_PT4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,4))) -#define TSB_PT_FR2_PT0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,0))) -#define TSB_PT_FR2_PT1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,1))) -#define TSB_PT_FR3_PT1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,1))) -#define TSB_PT_FR3_PT2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,2))) -#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) -#define TSB_PT_FR3_PT4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,4))) -#define TSB_PT_FR3_PT5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,5))) -#define TSB_PT_FR3_PT6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,6))) -#define TSB_PT_FR3_PT7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,7))) -#define TSB_PT_FR4_PT5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,5))) -#define TSB_PT_FR4_PT6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,6))) -#define TSB_PT_FR4_PT7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,7))) -#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) -#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) -#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) -#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) -#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) -#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) -#define TSB_PT_OD_PT6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,6))) -#define TSB_PT_OD_PT7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,7))) -#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) -#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) -#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) -#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) -#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) -#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) -#define TSB_PT_PUP_PT6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,6))) -#define TSB_PT_PUP_PT7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,7))) -#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) -#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) -#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) -#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) -#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) -#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) -#define TSB_PT_PDN_PT6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,6))) -#define TSB_PT_PDN_PT7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,7))) -#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) -#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) -#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) -#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) -#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) -#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) -#define TSB_PT_IE_PT6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,6))) -#define TSB_PT_IE_PT7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,7))) - - -/* Port U */ -#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) -#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) -#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) -#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) -#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) -#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) -#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) -#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) -#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) -#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) -#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) -#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) -#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) -#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) -#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) -#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) -#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) -#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) -#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) -#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) -#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) -#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) -#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) -#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) -#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) -#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) -#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) -#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) -#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) -#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) -#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) -#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) -#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) -#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) -#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) -#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) - - -/* */ -#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) -#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) -#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) -#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) -#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) -#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) -#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) -#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) -#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) -#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) -#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) -#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) -#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) -#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) -#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) -#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) -#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) -#define TSB_PV_FR1_PV6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,6))) -#define TSB_PV_FR1_PV7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,7))) -#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) -#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) -#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) -#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) -#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) -#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) -#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) -#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) -#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) -#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) -#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) -#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) -#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) -#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) -#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) -#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) -#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) -#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) -#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) -#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) -#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) -#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) -#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) -#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) -#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) -#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) -#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) -#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) -#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) -#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) -#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) -#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) -#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) -#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) - - -/* */ -#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) -#define TSB_RTC_ADJSIGN_ADJSIGN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJSIGN,0))) - - -/* */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - - -/* */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - -/* */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) -#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) -#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) -#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) -#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) -#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) -#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) -#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) -#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) -#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) -#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) -#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) -#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) -#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) -#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) -#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) -#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) -#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) -#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) -#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) -#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) -#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) -#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) -#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) -#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) -#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) -#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) -#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) -#define TSB_CG_FSYSENB_IPENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,8))) -#define TSB_CG_FSYSENB_IPENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,9))) -#define TSB_CG_FSYSENB_IPENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,10))) -#define TSB_CG_FSYSENB_IPENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,11))) -#define TSB_CG_FSYSENB_IPENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,12))) -#define TSB_CG_FSYSENB_IPENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,13))) -#define TSB_CG_FSYSENB_IPENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,14))) -#define TSB_CG_FSYSENB_IPENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,15))) -#define TSB_CG_FSYSENB_IPENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,16))) -#define TSB_CG_FSYSENB_IPENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,17))) -#define TSB_CG_FSYSENB_IPENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,18))) -#define TSB_CG_FSYSENB_IPENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,19))) -#define TSB_CG_FSYSENB_IPENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,20))) -#define TSB_CG_FSYSENB_IPENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,21))) -#define TSB_CG_FSYSENB_IPENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,22))) -#define TSB_CG_FSYSENB_IPENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,23))) -#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) -#define TSB_CG_FCEN_FCIPEN07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,7))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) - - -/* */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - - -/* */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) -#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) -#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) -#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) -#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) -#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) -#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) -#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) -#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) -#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) -#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) -#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) -#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) -#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) -#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) -#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) -#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) -#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) -#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) -#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) -#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) -#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) -#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) -#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) -#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) -#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) -#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) -#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) -#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) -#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) -#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) -#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) -#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) -#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) -#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) -#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) -#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) -#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) -#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) -#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) -#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) -#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) -#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) -#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) -#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) -#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) -#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) -#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) -#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) -#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) -#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) -#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) -#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) -#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) -#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) -#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) -#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) -#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) -#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) -#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) -#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) -#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) -#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) -#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) -#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) -#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) -#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) - - -/* Encoder Input (ENC) */ -#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) -#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) -#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) -#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) -#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) -#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) -#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) -#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) -#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) -#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) -#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) -#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) -#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) -#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) -#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) -#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) -#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) -#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) -#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) -#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) -#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) -#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) -#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) -#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) -#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) -#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) -#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) -#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) -#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) -#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) -#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) -#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) -#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) -#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) -#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) -#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) -#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) -#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) -#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM3HQ_H__ */ - -/** @} */ /* End of group TMPM3HQ */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S deleted file mode 100644 index da09c62e25a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S +++ /dev/null @@ -1,614 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INT16_IRQHandler [WEAK] - EXPORT INT17_18_IRQHandler [WEAK] - EXPORT INT19_22_IRQHandler [WEAK] - EXPORT INT23_26_IRQHandler [WEAK] - EXPORT INT27_28_IRQHandler [WEAK] - EXPORT INT29_IRQHandler [WEAK] - EXPORT INT30_31_IRQHandler [WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPMD0_IRQHandler [WEAK] - EXPORT INTENC00_IRQHandler [WEAK] - EXPORT INTENC01_IRQHandler [WEAK] - EXPORT INTADAPDA_IRQHandler [WEAK] - EXPORT INTADAPDB_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTT2RX_IRQHandler [WEAK] - EXPORT INTT2TX_IRQHandler [WEAK] - EXPORT INTT2ERR_IRQHandler [WEAK] - EXPORT INTT3RX_IRQHandler [WEAK] - EXPORT INTT3TX_IRQHandler [WEAK] - EXPORT INTT3ERR_IRQHandler [WEAK] - EXPORT INTT4RX_IRQHandler [WEAK] - EXPORT INTT4TX_IRQHandler [WEAK] - EXPORT INTT4ERR_IRQHandler [WEAK] - EXPORT INTI2CWUP_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NA_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NA_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NA_IRQHandler [WEAK] - EXPORT INTI2C3_IRQHandler [WEAK] - EXPORT INTI2C3AL_IRQHandler [WEAK] - EXPORT INTI2C3BF_IRQHandler [WEAK] - EXPORT INTI2C3NA_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTUART3RX_IRQHandler [WEAK] - EXPORT INTUART3TX_IRQHandler [WEAK] - EXPORT INTUART3ERR_IRQHandler [WEAK] - EXPORT INTUART4RX_IRQHandler [WEAK] - EXPORT INTUART4TX_IRQHandler [WEAK] - EXPORT INTUART4ERR_IRQHandler [WEAK] - EXPORT INTUART5RX_IRQHandler [WEAK] - EXPORT INTUART5TX_IRQHandler [WEAK] - EXPORT INTUART5ERR_IRQHandler [WEAK] - EXPORT INTT32A00A_IRQHandler [WEAK] - EXPORT INTT32A00ACAP0_IRQHandler [WEAK] - EXPORT INTT32A00ACAP1_IRQHandler [WEAK] - EXPORT INTT32A00B_IRQHandler [WEAK] - EXPORT INTT32A00BCAP0_IRQHandler [WEAK] - EXPORT INTT32A00BCAP1_IRQHandler [WEAK] - EXPORT INTT32A00C_IRQHandler [WEAK] - EXPORT INTT32A00CCAP0_IRQHandler [WEAK] - EXPORT INTT32A00CCAP1_IRQHandler [WEAK] - EXPORT INTT32A01A_IRQHandler [WEAK] - EXPORT INTT32A01ACAP0_IRQHandler [WEAK] - EXPORT INTT32A01ACAP1_IRQHandler [WEAK] - EXPORT INTT32A01B_IRQHandler [WEAK] - EXPORT INTT32A01BCAP0_IRQHandler [WEAK] - EXPORT INTT32A01BCAP1_IRQHandler [WEAK] - EXPORT INTT32A01C_IRQHandler [WEAK] - EXPORT INTT32A01CCAP0_IRQHandler [WEAK] - EXPORT INTT32A01CCAP1_IRQHandler [WEAK] - EXPORT INTT32A02A_IRQHandler [WEAK] - EXPORT INTT32A02ACAP0_IRQHandler [WEAK] - EXPORT INTT32A02ACAP1_IRQHandler [WEAK] - EXPORT INTT32A02B_IRQHandler [WEAK] - EXPORT INTT32A02BCAP0_IRQHandler [WEAK] - EXPORT INTT32A02BCAP1_IRQHandler [WEAK] - EXPORT INTT32A02C_IRQHandler [WEAK] - EXPORT INTT32A02CCAP0_IRQHandler [WEAK] - EXPORT INTT32A02CCAP1_IRQHandler [WEAK] - EXPORT INTT32A03A_IRQHandler [WEAK] - EXPORT INTT32A03ACAP0_IRQHandler [WEAK] - EXPORT INTT32A03ACAP1_IRQHandler [WEAK] - EXPORT INTT32A03B_IRQHandler [WEAK] - EXPORT INTT32A03BCAP0_IRQHandler [WEAK] - EXPORT INTT32A03BCAP1_IRQHandler [WEAK] - EXPORT INTT32A03C_IRQHandler [WEAK] - EXPORT INTT32A03CCAP0_IRQHandler [WEAK] - EXPORT INTT32A03CCAP1_IRQHandler [WEAK] - EXPORT INTT32A04A_IRQHandler [WEAK] - EXPORT INTT32A04ACAP0_IRQHandler [WEAK] - EXPORT INTT32A04ACAP1_IRQHandler [WEAK] - EXPORT INTT32A04B_IRQHandler [WEAK] - EXPORT INTT32A04BCAP0_IRQHandler [WEAK] - EXPORT INTT32A04BCAP1_IRQHandler [WEAK] - EXPORT INTT32A04C_IRQHandler [WEAK] - EXPORT INTT32A04CCAP0_IRQHandler [WEAK] - EXPORT INTT32A04CCAP1_IRQHandler [WEAK] - EXPORT INTT32A05A_IRQHandler [WEAK] - EXPORT INTT32A05ACAP0_IRQHandler [WEAK] - EXPORT INTT32A05ACAP1_IRQHandler [WEAK] - EXPORT INTT32A05B_IRQHandler [WEAK] - EXPORT INTT32A05BCAP0_IRQHandler [WEAK] - EXPORT INTT32A05BCAP1_IRQHandler [WEAK] - EXPORT INTT32A05C_IRQHandler [WEAK] - EXPORT INTT32A05CCAP0_IRQHandler [WEAK] - EXPORT INTT32A05CCAP1_IRQHandler [WEAK] - EXPORT INTT32A06A_IRQHandler [WEAK] - EXPORT INTT32A06ACAP0_IRQHandler [WEAK] - EXPORT INTT32A06ACAP1_IRQHandler [WEAK] - EXPORT INTT32A06B_IRQHandler [WEAK] - EXPORT INTT32A06BCAP0_IRQHandler [WEAK] - EXPORT INTT32A06BCAP1_IRQHandler [WEAK] - EXPORT INTT32A06C_IRQHandler [WEAK] - EXPORT INTT32A06CCAP0_IRQHandler [WEAK] - EXPORT INTT32A06CCAP1_IRQHandler [WEAK] - EXPORT INTT32A07A_IRQHandler [WEAK] - EXPORT INTT32A07ACAP0_IRQHandler [WEAK] - EXPORT INTT32A07ACAP1_IRQHandler [WEAK] - EXPORT INTT32A07B_IRQHandler [WEAK] - EXPORT INTT32A07BCAP0_IRQHandler [WEAK] - EXPORT INTT32A07BCAP1_IRQHandler [WEAK] - EXPORT INTT32A07C_IRQHandler [WEAK] - EXPORT INTT32A07CCAP0_IRQHandler [WEAK] - EXPORT INTT32A07CCAP1_IRQHandler [WEAK] - EXPORT INTPARI_IRQHandler [WEAK] - EXPORT INTDMAATC_IRQHandler [WEAK] - EXPORT INTDMAAERR_IRQHandler [WEAK] - EXPORT INTDMABTC_IRQHandler [WEAK] - EXPORT INTDMABERR_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTFLCRDY_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INT16_IRQHandler -INT17_18_IRQHandler -INT19_22_IRQHandler -INT23_26_IRQHandler -INT27_28_IRQHandler -INT29_IRQHandler -INT30_31_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPMD0_IRQHandler -INTENC00_IRQHandler -INTENC01_IRQHandler -INTADAPDA_IRQHandler -INTADAPDB_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTT2RX_IRQHandler -INTT2TX_IRQHandler -INTT2ERR_IRQHandler -INTT3RX_IRQHandler -INTT3TX_IRQHandler -INTT3ERR_IRQHandler -INTT4RX_IRQHandler -INTT4TX_IRQHandler -INTT4ERR_IRQHandler -INTI2CWUP_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NA_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NA_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NA_IRQHandler -INTI2C3_IRQHandler -INTI2C3AL_IRQHandler -INTI2C3BF_IRQHandler -INTI2C3NA_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTUART3RX_IRQHandler -INTUART3TX_IRQHandler -INTUART3ERR_IRQHandler -INTUART4RX_IRQHandler -INTUART4TX_IRQHandler -INTUART4ERR_IRQHandler -INTUART5RX_IRQHandler -INTUART5TX_IRQHandler -INTUART5ERR_IRQHandler -INTT32A00A_IRQHandler -INTT32A00ACAP0_IRQHandler -INTT32A00ACAP1_IRQHandler -INTT32A00B_IRQHandler -INTT32A00BCAP0_IRQHandler -INTT32A00BCAP1_IRQHandler -INTT32A00C_IRQHandler -INTT32A00CCAP0_IRQHandler -INTT32A00CCAP1_IRQHandler -INTT32A01A_IRQHandler -INTT32A01ACAP0_IRQHandler -INTT32A01ACAP1_IRQHandler -INTT32A01B_IRQHandler -INTT32A01BCAP0_IRQHandler -INTT32A01BCAP1_IRQHandler -INTT32A01C_IRQHandler -INTT32A01CCAP0_IRQHandler -INTT32A01CCAP1_IRQHandler -INTT32A02A_IRQHandler -INTT32A02ACAP0_IRQHandler -INTT32A02ACAP1_IRQHandler -INTT32A02B_IRQHandler -INTT32A02BCAP0_IRQHandler -INTT32A02BCAP1_IRQHandler -INTT32A02C_IRQHandler -INTT32A02CCAP0_IRQHandler -INTT32A02CCAP1_IRQHandler -INTT32A03A_IRQHandler -INTT32A03ACAP0_IRQHandler -INTT32A03ACAP1_IRQHandler -INTT32A03B_IRQHandler -INTT32A03BCAP0_IRQHandler -INTT32A03BCAP1_IRQHandler -INTT32A03C_IRQHandler -INTT32A03CCAP0_IRQHandler -INTT32A03CCAP1_IRQHandler -INTT32A04A_IRQHandler -INTT32A04ACAP0_IRQHandler -INTT32A04ACAP1_IRQHandler -INTT32A04B_IRQHandler -INTT32A04BCAP0_IRQHandler -INTT32A04BCAP1_IRQHandler -INTT32A04C_IRQHandler -INTT32A04CCAP0_IRQHandler -INTT32A04CCAP1_IRQHandler -INTT32A05A_IRQHandler -INTT32A05ACAP0_IRQHandler -INTT32A05ACAP1_IRQHandler -INTT32A05B_IRQHandler -INTT32A05BCAP0_IRQHandler -INTT32A05BCAP1_IRQHandler -INTT32A05C_IRQHandler -INTT32A05CCAP0_IRQHandler -INTT32A05CCAP1_IRQHandler -INTT32A06A_IRQHandler -INTT32A06ACAP0_IRQHandler -INTT32A06ACAP1_IRQHandler -INTT32A06B_IRQHandler -INTT32A06BCAP0_IRQHandler -INTT32A06BCAP1_IRQHandler -INTT32A06C_IRQHandler -INTT32A06CCAP0_IRQHandler -INTT32A06CCAP1_IRQHandler -INTT32A07A_IRQHandler -INTT32A07ACAP0_IRQHandler -INTT32A07ACAP1_IRQHandler -INTT32A07B_IRQHandler -INTT32A07BCAP0_IRQHandler -INTT32A07BCAP1_IRQHandler -INTT32A07C_IRQHandler -INTT32A07CCAP0_IRQHandler -INTT32A07CCAP1_IRQHandler -INTPARI_IRQHandler -INTDMAATC_IRQHandler -INTDMAAERR_IRQHandler -INTDMABTC_IRQHandler -INTDMABERR_IRQHandler -INTRTC_IRQHandler -INTRMC0_IRQHandler -INTFLCRDY_IRQHandler -INTFLDRDY_IRQHandler - - B . - - ENDP - - ALIGN - END - diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct deleted file mode 100644 index d0e8c1b2a2b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct +++ /dev/null @@ -1,39 +0,0 @@ -#! armcc -E -;; TMPM3HQFDFG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x80000 -{ - ER_IROM1 0x00000000 0x80000 - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x200002D8 (0x10000 - 0x2D8) - { - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK 0x200002D8+0x10000 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S deleted file mode 100644 index 113531b7715..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S +++ /dev/null @@ -1,582 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM3HQ.s - * @brief CMSIS Cortex-M3 Core Device Startup File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V5.00 - * @date 2016/03/02 - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop // Top of Stack - .long Reset_Handler // Reset Handler - .long NMI_Handler // NMI Handler - .long HardFault_Handler // Hard Fault Handler - .long MemManage_Handler // MPU Fault Handler - .long BusFault_Handler // Bus Fault Handler - .long UsageFault_Handler // Usage Fault Handler - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long SVC_Handler // SVCall Handler - .long DebugMon_Handler // Debug Monitor Handler - .long 0 // Reserved - .long PendSV_Handler // PendSV Handler - .long SysTick_Handler // SysTick Handler - - // External interrupts - .long INT00_IRQHandler // 0: Interrupt Pin0 - .long INT01_IRQHandler // 1: Interrupt Pin1 - .long INT02_IRQHandler // 2: Interrupt Pin2 - .long INT03_IRQHandler // 3: Interrupt Pin3 - .long INT04_IRQHandler // 4: Interrupt Pin4 - .long INT05_IRQHandler // 5: Interrupt Pin5 - .long INT06_IRQHandler // 6: Interrupt Pin6 - .long INT07_IRQHandler // 7: Interrupt Pin7 - .long INT08_IRQHandler // 8: Interrupt Pin8 - .long INT09_IRQHandler // 9: Interrupt Pin9 - .long INT10_IRQHandler // 10: Interrupt Pin10 - .long INT11_IRQHandler // 11: Interrupt Pin11 - .long INT12_IRQHandler // 12: Interrupt Pin12 - .long INT13_IRQHandler // 13: Interrupt Pin13 - .long INT14_IRQHandler // 14: Interrupt Pin14 - .long INT15_IRQHandler // 15: Interrupt Pin15 - .long INT16_IRQHandler // 16: Interrupt Pin 16 - .long INT17_18_IRQHandler // 17: Interrupt Pin 17_18 - .long INT19_22_IRQHandler // 18: Interrupt Pin 19_22 - .long INT23_26_IRQHandler // 19: Interrupt Pin 23_26 - .long INT27_28_IRQHandler // 20: Interrupt Pin 27_28 - .long INT29_IRQHandler // 21: Interrupt Pin 29 - .long INT30_31_IRQHandler // 22: Interrupt Pin 30_31 - .long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt - .long INTPMD0_IRQHandler // 25: PMD0 interrupt - .long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0 - .long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1 - .long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A - .long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B - .long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0 - .long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1 - .long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished - .long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1) - .long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2) - .long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2) - .long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2) - .long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3) - .long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3) - .long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3) - .long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4) - .long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4) - .long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4) - .long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0) - .long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt - .long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt - .long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt - .long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt - .long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt - .long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt - .long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt - .long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt - .long INTUART0RX_IRQHandler // 67: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 68: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 69: UART error (channel 0) - .long INTUART1RX_IRQHandler // 70: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 71: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 72: UART error (channel 1) - .long INTUART2RX_IRQHandler // 73: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 74: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 75: UART error (channel 2) - .long INTUART3RX_IRQHandler // 76: UART reception (channel 3) - .long INTUART3TX_IRQHandler // 77: UART transmit (channel 3) - .long INTUART3ERR_IRQHandler // 78: UART error (channel 3) - .long INTUART4RX_IRQHandler // 79: UART reception (channel 4) - .long INTUART4TX_IRQHandler // 80: UART transmit (channel 4) - .long INTUART4ERR_IRQHandler // 81: UART error (channel 4) - .long INTUART5RX_IRQHandler // 82: UART reception (channel 5) - .long INTUART5TX_IRQHandler // 83: UART transmit (channel 5) - .long INTUART5ERR_IRQHandler // 84: UART error (channel 5) - .long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - .long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0 - .long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1 - .long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - .long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0 - .long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1 - .long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - .long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0 - .long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1 - .long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - .long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0 - .long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1 - .long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - .long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0 - .long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1 - .long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - .long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0 - .long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1 - .long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - .long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0 - .long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1 - .long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - .long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0 - .long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1 - .long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - .long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0 - .long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1 - .long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - .long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0 - .long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1 - .long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - .long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0 - .long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1 - .long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - .long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0 - .long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1 - .long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - .long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0 - .long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1 - .long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - .long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0 - .long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1 - .long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - .long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0 - .long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1 - .long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - .long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0 - .long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1 - .long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - .long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0 - .long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1 - .long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - .long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0 - .long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1 - .long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - .long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0 - .long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1 - .long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - .long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0 - .long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1 - .long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - .long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0 - .long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1 - .long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - .long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0 - .long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1 - .long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - .long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0 - .long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1 - .long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - .long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0 - .long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1 - .long INTPARI_IRQHandler // 157: RAM parity interrupt - .long INTDMAATC_IRQHandler // 158: DMAA end of transfer - .long INTDMAAERR_IRQHandler // 159: DMAA transfer error - .long INTDMABTC_IRQHandler // 160: DMAB end of transfer - .long INTDMABERR_IRQHandler // 161: DMAB transfer error - .long INTRTC_IRQHandler // 162: Real time clock interrupt - .long INTRMC0_IRQHandler // 163: Remote control reception interrupt - .long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt - .long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INT16_IRQHandler - def_irq_handler INT17_18_IRQHandler - def_irq_handler INT19_22_IRQHandler - def_irq_handler INT23_26_IRQHandler - def_irq_handler INT27_28_IRQHandler - def_irq_handler INT29_IRQHandler - def_irq_handler INT30_31_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPMD0_IRQHandler - def_irq_handler INTENC00_IRQHandler - def_irq_handler INTENC01_IRQHandler - def_irq_handler INTADAPDA_IRQHandler - def_irq_handler INTADAPDB_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTT2RX_IRQHandler - def_irq_handler INTT2TX_IRQHandler - def_irq_handler INTT2ERR_IRQHandler - def_irq_handler INTT3RX_IRQHandler - def_irq_handler INTT3TX_IRQHandler - def_irq_handler INTT3ERR_IRQHandler - def_irq_handler INTT4RX_IRQHandler - def_irq_handler INTT4TX_IRQHandler - def_irq_handler INTT4ERR_IRQHandler - def_irq_handler INTI2CWUP_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NA_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NA_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NA_IRQHandler - def_irq_handler INTI2C3_IRQHandler - def_irq_handler INTI2C3AL_IRQHandler - def_irq_handler INTI2C3BF_IRQHandler - def_irq_handler INTI2C3NA_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTUART3RX_IRQHandler - def_irq_handler INTUART3TX_IRQHandler - def_irq_handler INTUART3ERR_IRQHandler - def_irq_handler INTUART4RX_IRQHandler - def_irq_handler INTUART4TX_IRQHandler - def_irq_handler INTUART4ERR_IRQHandler - def_irq_handler INTUART5RX_IRQHandler - def_irq_handler INTUART5TX_IRQHandler - def_irq_handler INTUART5ERR_IRQHandler - def_irq_handler INTT32A00A_IRQHandler - def_irq_handler INTT32A00ACAP0_IRQHandler - def_irq_handler INTT32A00ACAP1_IRQHandler - def_irq_handler INTT32A00B_IRQHandler - def_irq_handler INTT32A00BCAP0_IRQHandler - def_irq_handler INTT32A00BCAP1_IRQHandler - def_irq_handler INTT32A00C_IRQHandler - def_irq_handler INTT32A00CCAP0_IRQHandler - def_irq_handler INTT32A00CCAP1_IRQHandler - def_irq_handler INTT32A01A_IRQHandler - def_irq_handler INTT32A01ACAP0_IRQHandler - def_irq_handler INTT32A01ACAP1_IRQHandler - def_irq_handler INTT32A01B_IRQHandler - def_irq_handler INTT32A01BCAP0_IRQHandler - def_irq_handler INTT32A01BCAP1_IRQHandler - def_irq_handler INTT32A01C_IRQHandler - def_irq_handler INTT32A01CCAP0_IRQHandler - def_irq_handler INTT32A01CCAP1_IRQHandler - def_irq_handler INTT32A02A_IRQHandler - def_irq_handler INTT32A02ACAP0_IRQHandler - def_irq_handler INTT32A02ACAP1_IRQHandler - def_irq_handler INTT32A02B_IRQHandler - def_irq_handler INTT32A02BCAP0_IRQHandler - def_irq_handler INTT32A02BCAP1_IRQHandler - def_irq_handler INTT32A02C_IRQHandler - def_irq_handler INTT32A02CCAP0_IRQHandler - def_irq_handler INTT32A02CCAP1_IRQHandler - def_irq_handler INTT32A03A_IRQHandler - def_irq_handler INTT32A03ACAP0_IRQHandler - def_irq_handler INTT32A03ACAP1_IRQHandler - def_irq_handler INTT32A03B_IRQHandler - def_irq_handler INTT32A03BCAP0_IRQHandler - def_irq_handler INTT32A03BCAP1_IRQHandler - def_irq_handler INTT32A03C_IRQHandler - def_irq_handler INTT32A03CCAP0_IRQHandler - def_irq_handler INTT32A03CCAP1_IRQHandler - def_irq_handler INTT32A04A_IRQHandler - def_irq_handler INTT32A04ACAP0_IRQHandler - def_irq_handler INTT32A04ACAP1_IRQHandler - def_irq_handler INTT32A04B_IRQHandler - def_irq_handler INTT32A04BCAP0_IRQHandler - def_irq_handler INTT32A04BCAP1_IRQHandler - def_irq_handler INTT32A04C_IRQHandler - def_irq_handler INTT32A04CCAP0_IRQHandler - def_irq_handler INTT32A04CCAP1_IRQHandler - def_irq_handler INTT32A05A_IRQHandler - def_irq_handler INTT32A05ACAP0_IRQHandler - def_irq_handler INTT32A05ACAP1_IRQHandler - def_irq_handler INTT32A05B_IRQHandler - def_irq_handler INTT32A05BCAP0_IRQHandler - def_irq_handler INTT32A05BCAP1_IRQHandler - def_irq_handler INTT32A05C_IRQHandler - def_irq_handler INTT32A05CCAP0_IRQHandler - def_irq_handler INTT32A05CCAP1_IRQHandler - def_irq_handler INTT32A06A_IRQHandler - def_irq_handler INTT32A06ACAP0_IRQHandler - def_irq_handler INTT32A06ACAP1_IRQHandler - def_irq_handler INTT32A06B_IRQHandler - def_irq_handler INTT32A06BCAP0_IRQHandler - def_irq_handler INTT32A06BCAP1_IRQHandler - def_irq_handler INTT32A06C_IRQHandler - def_irq_handler INTT32A06CCAP0_IRQHandler - def_irq_handler INTT32A06CCAP1_IRQHandler - def_irq_handler INTT32A07A_IRQHandler - def_irq_handler INTT32A07ACAP0_IRQHandler - def_irq_handler INTT32A07ACAP1_IRQHandler - def_irq_handler INTT32A07B_IRQHandler - def_irq_handler INTT32A07BCAP0_IRQHandler - def_irq_handler INTT32A07BCAP1_IRQHandler - def_irq_handler INTT32A07C_IRQHandler - def_irq_handler INTT32A07CCAP0_IRQHandler - def_irq_handler INTT32A07CCAP1_IRQHandler - def_irq_handler INTPARI_IRQHandler - def_irq_handler INTDMAATC_IRQHandler - def_irq_handler INTDMAAERR_IRQHandler - def_irq_handler INTDMABTC_IRQHandler - def_irq_handler INTDMABERR_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTFLCRDY_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - - .end diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld deleted file mode 100644 index 7c9a2e765b3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld +++ /dev/null @@ -1,166 +0,0 @@ -/* Linker script for Toshiba TMPM3HQ */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K - RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8) -} - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S deleted file mode 100644 index cbed3bdbe30..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S +++ /dev/null @@ -1,1107 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INT16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT16_IRQHandler - B INT16_IRQHandler - - PUBWEAK INT17_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT17_18_IRQHandler - B INT17_18_IRQHandler - - PUBWEAK INT19_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT19_22_IRQHandler - B INT19_22_IRQHandler - - PUBWEAK INT23_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT23_26_IRQHandler - B INT23_26_IRQHandler - - PUBWEAK INT27_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT27_28_IRQHandler - B INT27_28_IRQHandler - - PUBWEAK INT29_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT29_IRQHandler - B INT29_IRQHandler - - PUBWEAK INT30_31_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT30_31_IRQHandler - B INT30_31_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPMD0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPMD0_IRQHandler - B INTPMD0_IRQHandler - - PUBWEAK INTENC00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC00_IRQHandler - B INTENC00_IRQHandler - - PUBWEAK INTENC01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC01_IRQHandler - B INTENC01_IRQHandler - - PUBWEAK INTADAPDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDA_IRQHandler - B INTADAPDA_IRQHandler - - PUBWEAK INTADAPDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDB_IRQHandler - B INTADAPDB_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTT2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2RX_IRQHandler - B INTT2RX_IRQHandler - - PUBWEAK INTT2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2TX_IRQHandler - B INTT2TX_IRQHandler - - PUBWEAK INTT2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2ERR_IRQHandler - B INTT2ERR_IRQHandler - - PUBWEAK INTT3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3RX_IRQHandler - B INTT3RX_IRQHandler - - PUBWEAK INTT3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3TX_IRQHandler - B INTT3TX_IRQHandler - - PUBWEAK INTT3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3ERR_IRQHandler - B INTT3ERR_IRQHandler - - PUBWEAK INTT4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4RX_IRQHandler - B INTT4RX_IRQHandler - - PUBWEAK INTT4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4TX_IRQHandler - B INTT4TX_IRQHandler - - PUBWEAK INTT4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4ERR_IRQHandler - B INTT4ERR_IRQHandler - - PUBWEAK INTI2CWUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2CWUP_IRQHandler - B INTI2CWUP_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NA_IRQHandler - B INTI2C0NA_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NA_IRQHandler - B INTI2C1NA_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NA_IRQHandler - B INTI2C2NA_IRQHandler - - PUBWEAK INTI2C3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3_IRQHandler - B INTI2C3_IRQHandler - - PUBWEAK INTI2C3AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3AL_IRQHandler - B INTI2C3AL_IRQHandler - - PUBWEAK INTI2C3BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3BF_IRQHandler - B INTI2C3BF_IRQHandler - - PUBWEAK INTI2C3NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3NA_IRQHandler - B INTI2C3NA_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTUART3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3RX_IRQHandler - B INTUART3RX_IRQHandler - - PUBWEAK INTUART3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3TX_IRQHandler - B INTUART3TX_IRQHandler - - PUBWEAK INTUART3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3ERR_IRQHandler - B INTUART3ERR_IRQHandler - - PUBWEAK INTUART4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4RX_IRQHandler - B INTUART4RX_IRQHandler - - PUBWEAK INTUART4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4TX_IRQHandler - B INTUART4TX_IRQHandler - - PUBWEAK INTUART4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4ERR_IRQHandler - B INTUART4ERR_IRQHandler - - PUBWEAK INTUART5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5RX_IRQHandler - B INTUART5RX_IRQHandler - - PUBWEAK INTUART5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5TX_IRQHandler - B INTUART5TX_IRQHandler - - PUBWEAK INTUART5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5ERR_IRQHandler - B INTUART5ERR_IRQHandler - - PUBWEAK INTT32A00A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00A_IRQHandler - B INTT32A00A_IRQHandler - - PUBWEAK INTT32A00ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP0_IRQHandler - B INTT32A00ACAP0_IRQHandler - - PUBWEAK INTT32A00ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP1_IRQHandler - B INTT32A00ACAP1_IRQHandler - - PUBWEAK INTT32A00B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00B_IRQHandler - B INTT32A00B_IRQHandler - - PUBWEAK INTT32A00BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP0_IRQHandler - B INTT32A00BCAP0_IRQHandler - - PUBWEAK INTT32A00BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP1_IRQHandler - B INTT32A00BCAP1_IRQHandler - - PUBWEAK INTT32A00C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00C_IRQHandler - B INTT32A00C_IRQHandler - - PUBWEAK INTT32A00CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP0_IRQHandler - B INTT32A00CCAP0_IRQHandler - - PUBWEAK INTT32A00CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP1_IRQHandler - B INTT32A00CCAP1_IRQHandler - - PUBWEAK INTT32A01A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01A_IRQHandler - B INTT32A01A_IRQHandler - - PUBWEAK INTT32A01ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP0_IRQHandler - B INTT32A01ACAP0_IRQHandler - - PUBWEAK INTT32A01ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP1_IRQHandler - B INTT32A01ACAP1_IRQHandler - - PUBWEAK INTT32A01B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01B_IRQHandler - B INTT32A01B_IRQHandler - - PUBWEAK INTT32A01BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP0_IRQHandler - B INTT32A01BCAP0_IRQHandler - - PUBWEAK INTT32A01BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP1_IRQHandler - B INTT32A01BCAP1_IRQHandler - - PUBWEAK INTT32A01C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01C_IRQHandler - B INTT32A01C_IRQHandler - - PUBWEAK INTT32A01CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP0_IRQHandler - B INTT32A01CCAP0_IRQHandler - - PUBWEAK INTT32A01CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP1_IRQHandler - B INTT32A01CCAP1_IRQHandler - - PUBWEAK INTT32A02A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02A_IRQHandler - B INTT32A02A_IRQHandler - - PUBWEAK INTT32A02ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP0_IRQHandler - B INTT32A02ACAP0_IRQHandler - - PUBWEAK INTT32A02ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP1_IRQHandler - B INTT32A02ACAP1_IRQHandler - - PUBWEAK INTT32A02B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02B_IRQHandler - B INTT32A02B_IRQHandler - - PUBWEAK INTT32A02BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP0_IRQHandler - B INTT32A02BCAP0_IRQHandler - - PUBWEAK INTT32A02BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP1_IRQHandler - B INTT32A02BCAP1_IRQHandler - - PUBWEAK INTT32A02C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02C_IRQHandler - B INTT32A02C_IRQHandler - - PUBWEAK INTT32A02CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP0_IRQHandler - B INTT32A02CCAP0_IRQHandler - - PUBWEAK INTT32A02CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP1_IRQHandler - B INTT32A02CCAP1_IRQHandler - - PUBWEAK INTT32A03A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03A_IRQHandler - B INTT32A03A_IRQHandler - - PUBWEAK INTT32A03ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP0_IRQHandler - B INTT32A03ACAP0_IRQHandler - - PUBWEAK INTT32A03ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP1_IRQHandler - B INTT32A03ACAP1_IRQHandler - - PUBWEAK INTT32A03B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03B_IRQHandler - B INTT32A03B_IRQHandler - - PUBWEAK INTT32A03BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP0_IRQHandler - B INTT32A03BCAP0_IRQHandler - - PUBWEAK INTT32A03BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP1_IRQHandler - B INTT32A03BCAP1_IRQHandler - - PUBWEAK INTT32A03C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03C_IRQHandler - B INTT32A03C_IRQHandler - - PUBWEAK INTT32A03CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP0_IRQHandler - B INTT32A03CCAP0_IRQHandler - - PUBWEAK INTT32A03CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP1_IRQHandler - B INTT32A03CCAP1_IRQHandler - - PUBWEAK INTT32A04A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04A_IRQHandler - B INTT32A04A_IRQHandler - - PUBWEAK INTT32A04ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP0_IRQHandler - B INTT32A04ACAP0_IRQHandler - - PUBWEAK INTT32A04ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP1_IRQHandler - B INTT32A04ACAP1_IRQHandler - - PUBWEAK INTT32A04B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04B_IRQHandler - B INTT32A04B_IRQHandler - - PUBWEAK INTT32A04BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP0_IRQHandler - B INTT32A04BCAP0_IRQHandler - - PUBWEAK INTT32A04BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP1_IRQHandler - B INTT32A04BCAP1_IRQHandler - - PUBWEAK INTT32A04C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04C_IRQHandler - B INTT32A04C_IRQHandler - - PUBWEAK INTT32A04CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP0_IRQHandler - B INTT32A04CCAP0_IRQHandler - - PUBWEAK INTT32A04CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP1_IRQHandler - B INTT32A04CCAP1_IRQHandler - - PUBWEAK INTT32A05A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05A_IRQHandler - B INTT32A05A_IRQHandler - - PUBWEAK INTT32A05ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP0_IRQHandler - B INTT32A05ACAP0_IRQHandler - - PUBWEAK INTT32A05ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP1_IRQHandler - B INTT32A05ACAP1_IRQHandler - - PUBWEAK INTT32A05B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05B_IRQHandler - B INTT32A05B_IRQHandler - - PUBWEAK INTT32A05BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP0_IRQHandler - B INTT32A05BCAP0_IRQHandler - - PUBWEAK INTT32A05BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP1_IRQHandler - B INTT32A05BCAP1_IRQHandler - - PUBWEAK INTT32A05C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05C_IRQHandler - B INTT32A05C_IRQHandler - - PUBWEAK INTT32A05CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP0_IRQHandler - B INTT32A05CCAP0_IRQHandler - - PUBWEAK INTT32A05CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP1_IRQHandler - B INTT32A05CCAP1_IRQHandler - - PUBWEAK INTT32A06A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06A_IRQHandler - B INTT32A06A_IRQHandler - - PUBWEAK INTT32A06ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP0_IRQHandler - B INTT32A06ACAP0_IRQHandler - - PUBWEAK INTT32A06ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP1_IRQHandler - B INTT32A06ACAP1_IRQHandler - - PUBWEAK INTT32A06B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06B_IRQHandler - B INTT32A06B_IRQHandler - - PUBWEAK INTT32A06BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP0_IRQHandler - B INTT32A06BCAP0_IRQHandler - - PUBWEAK INTT32A06BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP1_IRQHandler - B INTT32A06BCAP1_IRQHandler - - PUBWEAK INTT32A06C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06C_IRQHandler - B INTT32A06C_IRQHandler - - PUBWEAK INTT32A06CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP0_IRQHandler - B INTT32A06CCAP0_IRQHandler - - PUBWEAK INTT32A06CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP1_IRQHandler - B INTT32A06CCAP1_IRQHandler - - PUBWEAK INTT32A07A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07A_IRQHandler - B INTT32A07A_IRQHandler - - PUBWEAK INTT32A07ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP0_IRQHandler - B INTT32A07ACAP0_IRQHandler - - PUBWEAK INTT32A07ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP1_IRQHandler - B INTT32A07ACAP1_IRQHandler - - PUBWEAK INTT32A07B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07B_IRQHandler - B INTT32A07B_IRQHandler - - PUBWEAK INTT32A07BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP0_IRQHandler - B INTT32A07BCAP0_IRQHandler - - PUBWEAK INTT32A07BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP1_IRQHandler - B INTT32A07BCAP1_IRQHandler - - PUBWEAK INTT32A07C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07C_IRQHandler - B INTT32A07C_IRQHandler - - PUBWEAK INTT32A07CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP0_IRQHandler - B INTT32A07CCAP0_IRQHandler - - PUBWEAK INTT32A07CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP1_IRQHandler - B INTT32A07CCAP1_IRQHandler - - PUBWEAK INTPARI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPARI_IRQHandler - B INTPARI_IRQHandler - - PUBWEAK INTDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAATC_IRQHandler - B INTDMAATC_IRQHandler - - PUBWEAK INTDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAAERR_IRQHandler - B INTDMAAERR_IRQHandler - - PUBWEAK INTDMABTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABTC_IRQHandler - B INTDMABTC_IRQHandler - - PUBWEAK INTDMABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABERR_IRQHandler - B INTDMABERR_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTFLCRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY_IRQHandler - B INTFLCRDY_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - END diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf deleted file mode 100644 index 0d58c53864a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __BRAM_start__ = 0x20010000; -define symbol __BRAM_end__ = 0x200107FF; -define symbol __DFLASH_start__ = 0x30000000; -define symbol __DFLASH_end__ = 0x30007FFF; -define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; -define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in BRAM_region { section .backup_ram }; -place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h deleted file mode 100644 index 441eb0d0ef8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h +++ /dev/null @@ -1,12 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM3HQ - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in TMPM3HQ specifics - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM3HQ.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h deleted file mode 100644 index bb3ccde7a00..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM3HQ - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (182) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c deleted file mode 100644 index 92a628a8563..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c +++ /dev/null @@ -1,342 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM3Hy.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version 0.0.5.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#include "TMPM3HQ.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_Val (0x00000000UL) - -#define STBYCR_Val (0x00000000UL) - -#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */ -#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */ -#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */ -#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */ -#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ -#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ -#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ -#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) - -#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) - -#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) - -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) - #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL -#else - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) - #define PLL0SEL_Ready CG_10M_MUL_8_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_6M (6000000UL) -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ -#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ -#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ -#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ -#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ -#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ -#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ -#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL)) - #define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) - #define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 6MHz */ - #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL)) - #define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) - #define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) - #define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) - #define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t CoreClockInput = 0U; - uint32_t regval = 0U; - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_6M) { /* If input is 6MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) { - CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { - CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) { - CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { - CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) { - CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { - CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - if (CoreClockInput >= EOSC_8M) { - SystemCoreClock = CoreClockInput / 8U; - } else { - SystemCoreClock = 0U; - } - break; - case 4U: /* Gear -> fc/16 */ - if (CoreClockInput > EOSC_12M) { - SystemCoreClock = CoreClockInput / 16U; - } else { - SystemCoreClock = 0U; - } - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - //Enable 32.768khz. - //TSB_RLM->LOSCCR = 0x01; - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h deleted file mode 100644 index 0dd2ddcdb54..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM3Hy.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version V1.0.1.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM3HQ_H -#define __SYSTEM_TMPM3HQ_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c deleted file mode 100644 index a800f57e2ed..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c +++ /dev/null @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" - -extern const PinMap PinMap_GPIO_IRQ[]; -#define GPIO_DATA PIN_DATA(0, 2) - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - // Checking pin name is not interrupt pins - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - // Return pin mask - return (1 << (pin & 0x07)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin != NC) { - obj->mask = gpio_set(pin); - obj->port = (PortName) (pin >> 3); - TSB_CG->FSYSENA |= (1<<(obj->port)); - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - pin_function(obj->pin, PIN_INPUT); - break; - - case PIN_OUTPUT: - pin_function(obj->pin, PIN_OUTPUT); - break; - - case PIN_INOUT: - pin_function(obj->pin, PIN_INOUT); - break; - - default: - error("Invalid direction\n"); - break; - } -} - -// Write gpio object pin data -void gpio_write(gpio_t *obj, int value) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - if(value == GPIO_PIN_SET) - BITBAND_PORT_SET(base, bit); - else if(value == GPIO_PIN_RESET) - BITBAND_PORT_CLR(base, bit); - else - error("Invalid value\n"); -} - -// Read gpio object pin data -int gpio_read (gpio_t *obj) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base; - uint32_t val; - int BitValue; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - BITBAND_PORT_READ(val, base, bit); - if(val == GPIO_PIN_RESET) - BitValue = GPIO_PIN_RESET; - else - BitValue = GPIO_PIN_SET; - return (BitValue); -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h deleted file mode 100644 index 04b381798d4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h +++ /dev/null @@ -1,355 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __GPIO_INCLUDE_H -#define __GPIO_INCLUDE_H - -#include -#include "TMPM3HQ.h" -#include "objects.h" -#include "serial_api.h" - -enum BitMode { - GPIO_PIN_RESET = 0, /* 0: Clear */ - GPIO_PIN_SET, /* 1: Set */ -}; - -enum PortFunction { - GPIO_Mode_DATA = 0x0, /* 0x0: PxDATA */ - GPIO_Mode_CR = 0x04, /* 0x4: PxCR */ - GPIO_Mode_FR1 = 0x08, /* 0x8: PxFR1 */ - GPIO_Mode_FR2 = 0x0C, /* 0xC: PxFR2 */ - GPIO_Mode_FR3 = 0x10, /* 0x10: PxFR3 */ - GPIO_Mode_FR4 = 0x14, /* 0x14: PxFR4 */ - GPIO_Mode_FR5 = 0x18, /* 0x18: PxFR5 */ - GPIO_Mode_FR6 = 0x1C, /* 0x1C: PxFR6 */ - GPIO_Mode_FR7 = 0x20, /* 0x20: PxFR7 */ - GPIO_Mode_OD = 0x28, /* 0x28: PxOD */ - GPIO_Mode_PUP = 0x2C, /* 0x2C: PxPUP */ - GPIO_Mode_PDN = 0x30, /* 0x30: PxPDN */ - GPIO_Mode_IE = 0x38 /* 0x38: PxIE */ -}; - -#define PORT_BASE (0x400C0000UL) /* Port Register Base Adress */ -#define BITBAND_PORT_OFFSET (0x0000100UL) /* Port Register Offset Value */ -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /* Operational target Port Adress */ -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /* Operational target Control Register Adress */ -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /* Target Pin Bit set */ -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /* Target Pin Bit clear */ -#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /* Target Pin Bit read */ - -/* PWM Macros */ -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) -#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) -#define T32A_MODE_16 ((uint32_t)0x00000000) /* 16bit Mode */ -#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /* prescaler */ -#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /* Enable */ -#define T32A_COUNT_UP ((uint32_t)0x00000000) /* count up */ -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /* match up Timer Register */ -#define T32A_STOP_NON ((uint32_t)0x00000000) /* No use trigger */ -#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /* external trigger rising edge */ -#define T32A_OCR_SET ((uint32_t)0x00000001) /* Hi */ -#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /* Hi */ -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /* Hi */ -#define T32A_IMx0_MASK_ALL ((uint32_t)0x0000000F) /* request */ -#define T32A_COUNT_DOWN ((uint32_t)0x00010000) -#define MAX_COUNTER_16B 0xFFFF -#define DEFAULT_CLOCK_DIVISION 32 -#define DEFAULT_PERIOD 0.02f - -/* RTC Configuration Macro */ -#define RTC_24_HOUR_MODE ((uint8_t)0x01) -#define PAGER_PAGE_ONE ((uint8_t)0x01) -#define PAGER_PAGE_ZERO ((uint8_t)0xEE) -#define RTC_CLK_ENABLE ((uint8_t)0x08) -#define RTC_CLK_DISABLE ((uint8_t)0xE7) -#define RTC_INT_ENABLE ((uint8_t)0x80) -#define RTC_CLEAR_ALL ((uint8_t)0x00) -#define RTC_RESET ((uint8_t)0xF7) -#define RTC_INT_SET ((uint8_t)0xFB) -#define RTC_INT_CLR ((uint8_t)0x04) -#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) -#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) -#define ELOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ -#define ELOSC_CFG_CLOCK ((uint32_t)(32768)) /* Clock(hz) */ -#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) /* WUPTL :High Bit Mask */ -#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) /* WULEF :Mask */ -#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) /* WULEF :[R] :Done */ -#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) /* WULON :[W] :Enable */ -#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) /* XTEN :[R/W] :Enable */ -#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro -#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro - -/* Serial Macros */ -#define UART0 TSB_UART0 -#define UART1 TSB_UART1 -#define UART2 TSB_UART2 -#define UART3 TSB_UART3 -#define UART4 TSB_UART4 -#define UART5 TSB_UART5 -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /* SWRSTF :Mask */ -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /* SWRSTF :During "Software Reset */ -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /* SWRST :"10" */ -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /* SWRST :"01" */ -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /* TFCLR :Clear the transmit buff */ -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /* RFCLR :Clear the receive buff */ -#define UART_PLESCALER_1 ((uint32_t)0x00000000) /* Boudrate Generator prescale 1/1 */ -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /* Enable */ -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /* Available */ -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /* Available */ -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) /* 1 stage */ -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /* Minimum Value :K=0 */ -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /* Maximum Value :K=63 */ -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /* Minimum Value :N=1 */ -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /* Maximum Value :N=65535 */ -typedef struct { - uint32_t ken; /* Enable/Disable Division Definition */ - uint32_t brk; /* Division Value K */ - uint32_t brn; /* Division Value N */ -} uart_boudrate_t; -/* Sleep Macros */ -#define CG_STBY_MODE_IDLE 0x00 -#define CG_STBY_MODE_STOP1 0x01 -#define EXTERNEL_OSC_MASK 0xFFFFFFF9 -#define IHOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ -#define IHOSC_CFG_CLOCK ((uint32_t)(10000000)) /* Clock(hz) */ -#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) /* WUPT :High Bit Mask */ -#define CGWUPHCR_WUCLK_MASK ((uint32_t)0x00000100) /* WUCLK :Mask */ -#define CGWUPHCR_WUCLK_RW_IHOSC ((uint32_t)0x00000000) /* WUCLK :[R/W] :IHOSC */ - -/* SPI macros */ -typedef enum { - SPI_MASTER, - SPI_SLAVE -} spi_mode; -#define IS_SPI_MODULE(param) (((param) == SPI_0) || ((param) == SPI_1)) -#define TSPI_INT_ALL (uint32_t)0xF4 /* All above interrupt control */ -#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /* DR :Mask for 8bit */ -/* TSPI_SW_Reset SW Reset */ -#define TSPI_RESET10 ((uint32_t)0x00000010) /* RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000001) /* RESET Pattarn 01 */ -/* TSPI_Enable TSPI Enable/Disable Control */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /* Enable */ -/* TSPI_Triger_Control Triger Control */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /* Enable */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /* TSPI MODE */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /* MASTER MODE */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /* TWO WAY */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /* Single Transfer Frame :0 */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /* Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /* Hi */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 0 */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 8 */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -/* TSPI_Baudrate_Clock */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /* T16 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /* 1/3 */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /* MSB first */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /* 8 bit */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /* 0 */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /* 1st Edge Sampling */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /* IDLE Term TSPII??SCK LOW */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /* 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ -/* Format control1 Register */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /* Odd Parity */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /* Clear */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /* Enable */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /* TX_REACH_FILL_LEVEL_MASK */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /* Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /* Send Data Complete */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /* Disable MASK */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /* Transfer Mode bit MASK */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /* RECEIVE ONLY */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /* Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /* Send Data Complete */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /* TX_REACH_FILL_LEVEL_MASK */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /* Receive Data Complete Flag Clear */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /* Clear */ - -/* Ticker Macros */ -#define T32A_MODE_32 ((uint32_t)0x00000001) -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) -#define T32A_COUNT_STOP ((uint32_t)0x00000004) -#define T32A_COUNT_START ((uint32_t)0x00000002) -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) - -/* I2C Macros */ - -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) -#define I2CxCR2_INIT ((uint32_t)0x00000008) -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) -#define I2CxCR2_TRX ((uint32_t)0x00000040) -#define I2CxST_I2C ((uint32_t)0x00000001) -#define I2CxST_CLEAR ((uint32_t)0x0000000F) -#define I2CxCR1_ACK ((uint32_t)0x00000010) -#define I2CxSR_BB ((uint32_t)0x00000020) -#define I2CxSR_LRB ((uint32_t)0x00000001) -#define I2CxOP_RSTA ((uint32_t)0x00000008) -#define I2CxOP_SREN ((uint32_t)0x00000002) -#define I2CxOP_MFACK ((uint32_t)0x00000001) -#define I2CxOP_INIT ((uint32_t)0x00000084) -#define I2CxIE_CLEAR ((uint32_t)0x00000000) -#define I2CxPRS_PRCK ((uint32_t)0x0000000F) -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) -// Slave Initial Settings. -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) -#define I2CAR_SA_MASK ((uint32_t)0x000000FE) -#define I2CxSR_TRX ((uint32_t)0x00000040) -#define I2CxOP_SAST ((uint32_t)0x00000020) -#define I2CxIE_INTI2C ((uint32_t)0x00000001) -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_GENERAL (2) -#define I2C_WRITE_ADDRESSED (3) -#define I2C_ACK (1) -#define I2C_TIMEOUT (100000) - -/* ADC macros */ -#define ADC_12BIT_RANGE 0xFFF -#define ADC_SCLK_1 ((uint32_t)0x00000000) /* SCLK : ADCLK/1 */ -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /* RCUT : Normal */ -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /* DACON : DAC on */ -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /* ENINT :Disable */ -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) /* TRGS :Single */ -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /* CNTDMEN :Disable */ -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /* SGLDMEN :Disable */ -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /* TRGDMEN :Disable */ -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /* TRGEN :Disable */ -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /* ADEN :Disable */ -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /* ADEN :Enable */ -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /* SGL :Enable */ -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /* CNT :Disable */ -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /* SNGF :Idle */ -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /* SNGF :Running */ -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /* ADRFn :Mask */ -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /* ADRFn :Flag on */ -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /* ADRn :Mask */ -#define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008) -#define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300) -#define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001) - -/* RMC Include */ -#define RMC_LI_ENABLE ((uint32_t)0x80000000) /* Enable */ -#define RMC_EDI_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define RMC_LD_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define RMC_PHM_DISABLE ((uint32_t)0x00000000) /* A remote control signal of the phase system isn't received */ -#define RMC_LL_MAX ((uint32_t)0x00000FF) /* Maximum Value(Disable Receiving End Interrupt) */ -#define RMC_THRESH_HIGH_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_POLARITY_POSITIVE ((uint32_t)0x0000000) /* Positive side */ -#define RMC_NOISE_REDUCTION_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_RX_DATA_BITS_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_CLK_LOW_SPEED ((uint32_t)0x00000000) /* Low speed clock(32.768kHz) */ -#define RMC_CYCLE_MAX_INT_OCCUR ((uint32_t)0x00002000) /* It occurs */ -#define RMC_LEADER_DETECT ((uint32_t)0x00000080) /* It detests */ -#define RMC_RX_BIT_NUM_MASK ((uint32_t)0x0000007F) /* Mask */ -#define RMCxEN_RMCEN_ENABLE ((uint32_t)0x00000001) /* RMCEN : Enable */ - -typedef struct { - uint32_t lcMax; /* Upper limit in a cycle period of leader detection */ - uint32_t lcMin; /* Lower limit in a cycle period of leader detection */ - uint32_t llMax; /* Upper limit in a low period of leader detection */ - uint32_t llMin; /* Lower limit in a low period of leader detection */ -} rmc_control1_t; - -typedef struct { - uint32_t lien; /* Enable a leader detection interrupt */ - uint32_t edien; /* Enable a remote control input falling edge interrupt */ - uint32_t cld; /* Enable a receive mode, that receives both remote control signals without leaders and with leaders */ - uint32_t phim; /* Setting of a remote control reception mode of the phase system */ - uint32_t ll; /* Setting at the timing of a "Receiving End Interrupt" by detection Low */ - uint32_t dmax; /* Setting at the timing of a "Receiving End Interrupt" by the cycle of the data bit */ -} rmc_control2_t; - -/* Receive Control Setting "3" */ -typedef struct { - uint32_t dath; /* Threshold value high setting of 3 price judgement of a Data bit */ - uint32_t datl; /* Threshold value low setting of 3 price judgement of a Data bit */ -} rmc_control3_t; - -/* Receive Control Setting "4" */ -typedef struct { - uint32_t po; /* Polarity choice of a remote control input signal */ - uint32_t nc; /* Setting of noise reduction time */ -} rmc_control4_t; - -/* Num of received end bit "1" */ -typedef struct { - uint32_t end1; /* Num of received data bits */ -} rmc_end1_t; - -/* Num of received end bit "2" */ -typedef struct { - uint32_t end2; /* Num of received data bits */ -} rmc_end2_t; - -/* Num of received end bit "3" */ -typedef struct { - uint32_t end3; /* Num of received data bits */ -} rmc_end3_t; - -/* Select source clock */ -typedef struct { - uint32_t clk; /* Select RMC sampling clock */ -} rmc_fssel_t; - -/* Initial setting structure definition */ -typedef struct { - rmc_control1_t cnt1; /* Receive Control Setting "1" */ - rmc_control2_t cnt2; /* Receive Control Setting "2" */ - rmc_control3_t cnt3; /* Receive Control Setting "3" */ - rmc_control4_t cnt4; /* Control4 setting */ - rmc_end1_t end1; /* Receive End Bit1 setting */ - rmc_end2_t end2; /* Receive End Bit2 setting */ - rmc_end3_t end3; /* Receive End Bit3 setting */ - rmc_fssel_t fssel; /* Select source clock */ -} rmc_initial_setting_t; - -/* RMC handle structure definition */ -typedef struct uart_handle { - TSB_RMC_TypeDef *p_instance; /* Registers base address */ - rmc_initial_setting_t init; /* Initial setting */ -} rmc_t; - -void rmc_init(rmc_t *p_obj); -void rmc_get_data(rmc_t *p_obj, uint32_t data[]); - - -#endif /* __GPIO_INCLUDE_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c deleted file mode 100644 index 890f0b16212..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c +++ /dev/null @@ -1,466 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "mbed_critical.h" - -#define CHANNEL_NUM 32 - -const PinMap PinMap_GPIO_IRQ[] = { - {PC0, GPIO_IRQ_00, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_01, PIN_DATA(0, 0)}, - {PC2, GPIO_IRQ_02, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_03, PIN_DATA(0, 0)}, - {PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_05, PIN_DATA(0, 0)}, - {PH3, GPIO_IRQ_06, PIN_DATA(0, 0)}, - {PA6, GPIO_IRQ_07, PIN_DATA(0, 0)}, - {PL3, GPIO_IRQ_08, PIN_DATA(0, 0)}, - {PM2, GPIO_IRQ_09, PIN_DATA(0, 0)}, - {PN3, GPIO_IRQ_10, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_11, PIN_DATA(0, 0)}, - {PL4, GPIO_IRQ_12, PIN_DATA(0, 0)}, - {PK7, GPIO_IRQ_13, PIN_DATA(0, 0)}, - {PP3, GPIO_IRQ_14, PIN_DATA(0, 0)}, - {PM6, GPIO_IRQ_15, PIN_DATA(0, 0)}, - {PB7, GPIO_IRQ_16, PIN_DATA(0, 0)}, - {PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)}, - {PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)}, - {PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, - {PT1, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, - {PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)}, - {PT7, GPIO_IRQ_29, PIN_DATA(0, 0)}, - {PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState ); -cg_intactivestate CurrentState; -static void INT_IRQHandler(PinName pin, uint32_t index); -static uint32_t CheckPinNameIRQSRC(PinName pin); - -// Initialize gpio IRQ pin -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - - // Disable interrupt by CPU - core_util_critical_section_enter(); - - // Calculate port and pin position - obj->port = (PortName)PIN_PORT(pin); - obj->pin = pin; - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_CLR(port_base, bit); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - - // Get GPIO irq source - switch (obj->irq_id) { - case GPIO_IRQ_00: - obj->irq_src = CG_INT_SRC_01; - break; - case GPIO_IRQ_01: - obj->irq_src = CG_INT_SRC_02; - break; - case GPIO_IRQ_02: - obj->irq_src = CG_INT_SRC_03; - break; - case GPIO_IRQ_03: - obj->irq_src = CG_INT_SRC_04; - break; - case GPIO_IRQ_04: - obj->irq_src = CG_INT_SRC_05; - break; - case GPIO_IRQ_05: - obj->irq_src = CG_INT_SRC_06; - break; - case GPIO_IRQ_06: - obj->irq_src = CG_INT_SRC_07; - break; - case GPIO_IRQ_07: - obj->irq_src = CG_INT_SRC_08; - break; - case GPIO_IRQ_08: - obj->irq_src = CG_INT_SRC_09; - break; - case GPIO_IRQ_09: - obj->irq_src = CG_INT_SRC_0A; - break; - case GPIO_IRQ_10: - obj->irq_src = CG_INT_SRC_0B; - break; - case GPIO_IRQ_11: - obj->irq_src = CG_INT_SRC_0C; - break; - case GPIO_IRQ_12: - obj->irq_src = CG_INT_SRC_0D; - break; - case GPIO_IRQ_13: - obj->irq_src = CG_INT_SRC_0E; - break; - case GPIO_IRQ_14: - obj->irq_src = CG_INT_SRC_0F; - break; - case GPIO_IRQ_15: - obj->irq_src = CG_INT_SRC_10; - break; - case GPIO_IRQ_16: - obj->irq_src = CG_INT_SRC_11; - break; - case GPIO_IRQ_17_18: - obj->irq_src = CG_INT_SRC_12; - break; - case GPIO_IRQ_19_22: - obj->irq_src = CG_INT_SRC_14; - break; - case GPIO_IRQ_23_26: - obj->irq_src = CheckPinNameIRQSRC(pin); - break; - case GPIO_IRQ_27_28: - obj->irq_src = CG_INT_SRC_1C; - break; - case GPIO_IRQ_29: - obj->irq_src = CG_INT_SRC_1E; - break; - case GPIO_IRQ_30_31: - obj->irq_src = CG_INT_SRC_1F; - break; - default: - break; - } - - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - - // Save irq id - channel_ids[obj->irq_src] = id; - - // Initialize interrupt event as both edges detection - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - CurrentState = CG_INT_ACTIVE_STATE_BOTH_EDGES; - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); - - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); - - core_util_critical_section_exit(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -// Set interrupt event of gpio_irq object -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - // Calculate port and pin position - bit = PIN_POS(obj->pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - - if(obj->event != CG_INT_ACTIVE_STATE_INVALID ) { - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); - BITBAND_PORT_CLR(port_base, bit); - } else { - BITBAND_PORT_SET(port_base, bit); - } - //Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -// Enable gpio_irq object -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -// Disable gpio_irq object -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - int port = 0; - uint8_t bit = 0; - uint32_t data = 0; - uint32_t port_base = 0; - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - // Clear interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, DISABLE); - - port_base = BITBAND_PORT_BASE(port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_READ(data, port_base, bit); - - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_01 + index)); - - // Enable interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, ENABLE); -} - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PC0, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PC1, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PC2, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PB1, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PJ4, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PK1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PH3, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PA6, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PL3, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PM2, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PN3, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PA7, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PL4, 12); -} - -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PK7, 13); -} - -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PP3, 14); -} - -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PM6, 15); -} - -void INT16_IRQHandler(void) -{ - INT_IRQHandler(PB7, 16); -} - -void INT17_18_IRQHandler(void) -{ - INT_IRQHandler(PV2, 17); -} - -void INT19_22_IRQHandler(void) -{ - INT_IRQHandler(PH4, 19); -} - -#define BIT22 (0x1 << 22) -#define BIT21 (0x1 << 21) -void INT23_26_IRQHandler(void) -{ - uint32_t int_num = TSB_IMN->FLG5; - if( int_num & BIT22) { - INT_IRQHandler(PT1, 24); - } else if(int_num & BIT21) { - INT_IRQHandler(PT0, 23); - } -} - -void INT27_28_IRQHandler(void) -{ - INT_IRQHandler(PG2, 27); -} - -void INT29_IRQHandler(void) -{ - INT_IRQHandler(PT7, 29); -} - -void INT30_31_IRQHandler(void) -{ - INT_IRQHandler(PU0, 30); -} - -static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) -{ - __IO uint8_t *p_imc; - - if(intsource < 3U || intsource == 13U) { - if(intsource == 13U) { - intsource = (cg_intsrc)3U; - } - p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } else { - if(intsource > 13U) { - intsource -= 4; - } else { - intsource -= 3; - } - p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } - // Dummy read is need - { - __IO uint8_t imc = *p_imc; - } -} - -/** - * @brief Return INTSRC for gpio INT that enable more than one pin. - * @param pin PinName. - * @return GPIO IRQn_Type . - * @note You can expand func CheckPinNameIRQSRC if need to add other GPIO INT. - */ -static uint32_t CheckPinNameIRQSRC(PinName pin) -{ - switch(pin) - { - case PT0: - return CG_INT_SRC_18; - case PT1: - return CG_INT_SRC_19; - default: - break; - } - return -1; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h deleted file mode 100644 index 3569f438046..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) -#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) -#define GPIO_BIT_ALL ((uint8_t)0xFF) - -typedef enum { - CG_INT_SRC_01 = 0U, - CG_INT_SRC_02, - CG_INT_SRC_03, - CG_INT_SRC_04, - CG_INT_SRC_05, - CG_INT_SRC_06, - CG_INT_SRC_07, - CG_INT_SRC_08, - CG_INT_SRC_09, - CG_INT_SRC_0A, - CG_INT_SRC_0B, - CG_INT_SRC_0C, - CG_INT_SRC_0D, - CG_INT_SRC_0E, - CG_INT_SRC_0F, - CG_INT_SRC_10, - CG_INT_SRC_11, - CG_INT_SRC_12, - CG_INT_SRC_13, - CG_INT_SRC_14, - CG_INT_SRC_15, - CG_INT_SRC_16, - CG_INT_SRC_17, - CG_INT_SRC_18, - CG_INT_SRC_19, - CG_INT_SRC_1A, - CG_INT_SRC_1B, - CG_INT_SRC_1C, - CG_INT_SRC_1D, - CG_INT_SRC_1E, - CG_INT_SRC_1F, - CG_INT_SRC_20 -} cg_intsrc; - -typedef enum { - CG_INT_ACTIVE_STATE_L = 0x00U, - CG_INT_ACTIVE_STATE_H = 0x02U, - CG_INT_ACTIVE_STATE_FALLING = 0x04U, - CG_INT_ACTIVE_STATE_RISING = 0x06U, - CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, - CG_INT_ACTIVE_STATE_INVALID = 0x0AU -} cg_intactivestate; - -typedef struct { - PinName pin; - uint32_t mask; - PortName port; -} gpio_t; - -struct gpio_irq_s { - uint32_t mask; - PortName port; - PinName pin; - uint32_t irq_id; - cg_intactivestate event; - cg_intsrc irq_src; -}; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c deleted file mode 100644 index d4f80b1c079..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c +++ /dev/null @@ -1,400 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) -#else -#define I2C_S(obj) (struct i2c_s *) (obj) -#endif - -static const PinMap PinMap_I2C_SDA[] = { - {PC1, I2C_0, PIN_DATA(1, 2)}, - {PA5, I2C_1, PIN_DATA(1, 2)}, - {PL1, I2C_2, PIN_DATA(3, 2)}, - {PT0, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PC0, I2C_0, PIN_DATA(1, 2)}, - {PA4, I2C_1, PIN_DATA(1, 2)}, - {PL0, I2C_2, PIN_DATA(3, 2)}, - {PT1, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -// Clock setting structure definition -typedef struct { - uint32_t sck; - uint32_t prsck; -} I2C_clock_setting_t; - -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { - 20, 24, 32, 48, 80, 144, 272, 528 -}; // SCK Divider value table - -I2C_clock_setting_t clk; -static uint32_t start_flag = 0; - -static int32_t wait_status(i2c_t *p_obj); -static void i2c_start_bit(i2c_t *obj); - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *obj_s = I2C_S(obj); - MBED_ASSERT(obj_s != NULL); - - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch (i2c_name) { - case I2C_0: - TSB_CG_FSYSENB_IPENB11 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - obj_s->i2c = TSB_I2C0; - break; - case I2C_1: - TSB_CG_FSYSENB_IPENB12 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - obj_s->i2c = TSB_I2C1; - break; - case I2C_2: - TSB_CG_FSYSENB_IPENB13 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - obj_s->i2c = TSB_I2C2; - case I2C_3: - TSB_CG_FSYSENB_IPENB14 = ENABLE; - TSB_CG_FSYSENA_IPENA15 = ENABLE; - obj_s->i2c = TSB_I2C3; - break; - default: - error("I2C is not available"); - break; - } - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->IE = I2CxIE_CLEAR; -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint64_t sck, tmp_sck; - uint64_t prsck, tmp_prsck; - uint64_t fscl, tmp_fscl; - uint64_t fx; - - SystemCoreClockUpdate(); - - if (hz <= 1000000) { - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - for (prsck = 1; prsck <= 32; prsck++) { - fx = ((uint64_t)SystemCoreClock / prsck); - if ((fx < 20000000U) && (fx > 6666666U)) { - for (sck = 0; sck <= 7; sck++) { - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32) ? prsck : 0; - } - } - } - } - clk.sck = (uint32_t)tmp_sck; - clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; - } - - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); -} - -int i2c_start(i2c_t *obj) -{ - start_flag = 1; // Start Condition - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t timeout = I2C_TIMEOUT; - - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { - if (timeout == 0) - break; - timeout--; - } - return 0; -} - -void i2c_reset(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->CR2 = I2CxCR2_SWRES_10; - obj_s->i2c->CR2 = I2CxCR2_SWRES_01; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - int32_t pdata = 0; - - if (length > 0) { - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { - while (count < length) { - pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - } - return (result); -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, address) == I2C_ACK) { - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - return (result); -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (last) { - obj_s->i2c->OP |= I2CxOP_MFACK; - } else { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } - obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK); - if (wait_status(obj) < 0) { - result = -1; - } else { - result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK); - } - return (result); -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (start_flag == 1) { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - i2c_start_bit(obj); - start_flag = 0; - } else { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - } - - if (wait_status(obj) < 0) { - return (-1); - } - - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - result = 1; - } else { - result = 0; - } - return (result); -} - -static void i2c_start_bit(i2c_t *obj) // Send START command -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t opreg; - opreg = obj_s->i2c->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - if ((obj_s->i2c->SR & I2CxSR_BB)) { - opreg |= I2CxOP_SREN; - } - obj_s->i2c->OP = opreg; - obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION; -} - -static int32_t wait_status(i2c_t *p_obj) -{ - struct i2c_s *p_obj_s = I2C_S(p_obj); - volatile int32_t timeout; - timeout = I2C_TIMEOUT; - while (!((p_obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { - if ((timeout--) == 0) { - return (-1); - } - } - return (0); -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *obj_s = I2C_S(obj); - if (enable_slave) { - obj_s->i2c->OP = I2CxOP_SLAVE_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK); - obj_s->i2c->IE = I2CxIE_INTI2C; - } else { - i2c_reset(obj); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - NVIC_DisableIRQ(obj_s->IRQn); - NVIC_ClearPendingIRQ(obj_s->IRQn); - obj_s->i2c->ST = I2CxST_CLEAR; - } -} - -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = I2C_NO_DATA; - - if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) { - if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { - result = I2C_READ_ADDRESSED; - } else { - result = I2C_WRITE_ADDRESSED; - } - } - return (result); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t count = 0; - - while (count < length) { - int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if ((obj_s->i2c->SR & I2CxSR_TRX)) { - return (count); - } else { - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - } - i2c_slave_mode(obj,1); - return (count); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - i2c_slave_mode(obj,1); - return (count); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->address = address & I2CAR_SA_MASK; - i2c_slave_mode(obj,1); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h b/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h deleted file mode 100644 index 7a27af03e9f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h +++ /dev/null @@ -1,113 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "TMPM3HQ.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t BaudRate; - uint32_t DataBits; - uint32_t StopBits; - uint32_t Parity; - uint32_t Mode; - uint32_t FlowCtrl; -} uart_inittypedef_t; - -struct port_s { - PortName port; - uint32_t mask; -}; - -typedef struct { - uint8_t PinDATA; - uint8_t PinCR; - uint8_t PinFR[FRMAX]; - uint8_t PinOD; - uint8_t PinPUP; - uint8_t PinPDN; - uint8_t PinIE; -} gpio_regtypedef_t; - -typedef struct { - __IO uint32_t DATA; - __IO uint32_t CR; - __IO uint32_t FR[FRMAX]; - uint32_t RESERVED0[1]; - __IO uint32_t OD; - __IO uint32_t PUP; - __IO uint32_t PDN; - uint32_t RESERVED1; - __IO uint32_t IE; -} TSB_Port_TypeDef; - -struct serial_s { - PinName pin; - uint32_t index; - TSB_UART_TypeDef * UARTx; - uart_inittypedef_t uart_config; -}; - -struct analogin_s { - PinName pin; - ADCName adc; - TSB_AD_TypeDef* obj; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef* handler; -}; - -struct pwmout_s { - PinName pin; - TSB_T32A_TypeDef * channel; - uint16_t trailing_timing; - uint16_t leading_timing; - uint16_t divisor; - float period; -}; - -struct i2c_s { - uint32_t address; - IRQn_Type IRQn; - TSB_I2C_TypeDef *i2c; -}; - -struct spi_s { - TSB_TSPI_TypeDef *spi; - SPIName module; - uint8_t bits; -}; - -extern const gpio_regtypedef_t GPIO_SFRs[]; -extern const uint32_t GPIO_Base[]; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c deleted file mode 100644 index 8566cd6dd7b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c +++ /dev/null @@ -1,215 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "gpio_include.h" - -void pin_function(PinName pin, int function) -{ - int port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - uint32_t port_base = 0; - uint32_t mode_base = 0; - - /* Assert that pin is valid*/ - MBED_ASSERT(pin != NC); - - /* Calculate pin function and pin direction*/ - func = PIN_FUNC(function); - dir = PIN_DIR(function); - - /* Calculate port and pin position*/ - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(port); - /* Initialization PxFR OFF */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_CLR(mode_base, bit); - - /* Initialize Input */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - switch (func) { - case 0: - break; - case 1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - break; - case 2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - break; - case 3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - break; - case 4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - break; - case 5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - break; - case 6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - break; - case 7: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - break; - default: - break; - } - if (func != 0) - BITBAND_PORT_SET(mode_base, bit); - if(dir == PIN_OUTPUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } else if(dir == PIN_INOUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - int port = 0; - uint8_t bit = 0; - uint8_t val = 0; - - /* Assert that pin is valid*/ - MBED_ASSERT(pin != NC); - - /* Check if function is in range*/ - if (mode > OpenDrain) { - return; - } - - /* Calculate port and pin position*/ - port = PIN_PORT(pin); - bit = PIN_POS(pin); - val = (1 << bit); - - switch (port) { - case PortA: - if(mode == OpenDrain) TSB_PA->OD |= val; - else if(mode == PullUp) TSB_PA->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val; - break; - case PortB: - if(mode == OpenDrain) TSB_PB->OD |= val; - else if(mode == PullUp) TSB_PB->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val; - break; - case PortC: - if(mode == OpenDrain) TSB_PC->OD |= val; - else if(mode == PullUp) TSB_PC->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val; - break; - case PortD: - if(mode == OpenDrain) TSB_PD->OD |= val; - else if(mode == PullUp) TSB_PD->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val; - break; - case PortE: - if(mode == OpenDrain) TSB_PE->OD |= val; - else if(mode == PullUp) TSB_PE->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val; - break; - case PortF: - if(mode == OpenDrain) TSB_PF->OD |= val; - else if(mode == PullUp) TSB_PF->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val; - break; - case PortG: - if(mode == OpenDrain) TSB_PG->OD |= val; - else if(mode == PullUp) TSB_PG->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val; - break; - case PortH: - if(mode == PullDown) TSB_PH->PDN |= val; - break; - case PortJ: - if(mode == OpenDrain) TSB_PJ->OD |= val; - else if(mode == PullUp) TSB_PJ->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val; - break; - case PortK: - if(mode == OpenDrain) TSB_PK->OD |= val; - else if(mode == PullUp) TSB_PK->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val; - break; - case PortL: - if(mode == OpenDrain) TSB_PL->OD |= val; - else if(mode == PullUp) TSB_PL->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val; - break; - case PortM: - if(mode == OpenDrain) TSB_PM->OD |= val; - else if(mode == PullUp) TSB_PM->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val; - break; - case PortN: - if(mode == OpenDrain) TSB_PN->OD |= val; - else if(mode == PullUp) TSB_PN->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val; - break; - case PortP: - if(mode == OpenDrain) TSB_PP->OD |= val; - else if(mode == PullUp) TSB_PP->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val; - break; - case PortR: - if(mode == OpenDrain) TSB_PR->OD |= val; - else if(mode == PullUp) TSB_PR->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val; - break; - case PortT: - if(mode == OpenDrain) TSB_PT->OD |= val; - else if(mode == PullUp) TSB_PT->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PT->PDN |= val; - break; - case PortU: - if(mode == OpenDrain) TSB_PU->OD |= val; - else if(mode == PullUp) TSB_PU->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PU->PDN |= val; - break; - case PortV: - if(mode == OpenDrain) TSB_PV->OD |= val; - else if(mode == PullUp) TSB_PV->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PV->PDN |= val; - break; - default: - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c deleted file mode 100644 index 3ff6359bee2..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c +++ /dev/null @@ -1,150 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -#define PORT_PIN_NUM 8 - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName) ((port << 3 ) | pin_n); - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortV); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - // Enabling Port Clock Supply - TSB_CG->FSYSENA |= (1<<(obj->port)); - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t bit = 0; - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - // Set direction for masked pins - switch (dir) { - case PIN_INPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INPUT); - } - } - break; - case PIN_OUTPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_OUTPUT); - } - } - break; - case PIN_INOUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INOUT); - } - } - break; - default: - break; - } -} - -void port_write(port_t *obj, int value) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - if(((data >> bit) & 0x01) == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else { - BITBAND_PORT_CLR(base, bit); - } - } - } -} - -int port_read(port_t *obj) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - // Calculate data of masked pins - data = port_data & obj->mask; - return data; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c deleted file mode 100644 index e83666fc95a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c +++ /dev/null @@ -1,200 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -static const PinMap PinMap_PWM[] = { - {PB0, PWM_0, PIN_DATA(5, 1)}, - {PC0, PWM_1, PIN_DATA(4, 1)}, - {PJ0, PWM_2, PIN_DATA(4, 1)}, - {PK2, PWM_3, PIN_DATA(4, 1)}, - {PN0, PWM_4, PIN_DATA(4, 1)}, - {PL5, PWM_5, PIN_DATA(4, 1)}, - {PG2, PWM_6, PIN_DATA(4, 1)}, - {NC, NC, 0} -}; - -static const uint32_t prescale_tbl[] = { - 2, 8, 32, 128, 256, 512, 1024 -}; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - uint16_t counter = 0; - - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel - MBED_ASSERT(pwm != (PWMName)NC); - - switch (pwm) { - case PWM_0: - obj->channel = TSB_T32A1; - TSB_CG_FSYSENA_IPENA25 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case PWM_1: - obj->channel = TSB_T32A2; - TSB_CG_FSYSENA_IPENA26 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - break; - case PWM_2: - obj->channel = TSB_T32A3; - TSB_CG_FSYSENA_IPENA27 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case PWM_3: - obj->channel = TSB_T32A4; - TSB_CG_FSYSENA_IPENA28 = ENABLE; - TSB_CG_FSYSENA_IPENA09 = ENABLE; - break; - case PWM_4: - obj->channel = TSB_T32A5; - TSB_CG_FSYSENA_IPENA29 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - case PWM_5: - obj->channel = TSB_T32A6; - TSB_CG_FSYSENA_IPENA30 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - break; - case PWM_6: - obj->channel = TSB_T32A7; - TSB_CG_FSYSENA_IPENA31 = ENABLE; - TSB_CG_FSYSENA_IPENA06 = ENABLE; - break; - default: - obj->channel = NULL; - break; - } - - pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM - obj->pin = pin; - obj->period = DEFAULT_PERIOD; - obj->divisor = DEFAULT_CLOCK_DIVISION; - obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); - obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); - obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); - obj->channel->RGC0 = counter; - obj->channel->RGC1 = counter; - obj->trailing_timing = counter; - obj->leading_timing = counter; -} - -void pwmout_free(pwmout_t* obj) -{ - // Stops and clear count operation - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - pwmout_write(obj, 0); - obj->pin = NC; - obj->channel = NULL; - obj->trailing_timing = 0; - obj->leading_timing = 0; - obj->divisor = 0; -} - -void pwmout_write(pwmout_t* obj, float value) -{ - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again - obj->leading_timing = (obj->trailing_timing - - (obj->trailing_timing * value)); // leading_timing value - obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -float pwmout_read(pwmout_t* obj) -{ - float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - return duty_cycle; -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - float seconds = 0; - int cycles = 0; - uint32_t clkdiv = 0; - int i = 0; - float duty_cycle = 0; - - seconds = (float)(us / 1000000.0f); - // Select highest timer resolution - for (i = 0; i < 7; ++i) { - cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); - if (cycles <= MAX_COUNTER_16B) { - clkdiv = i + 1; // range 1:7 - clkdiv <<= 28; - break; - } else { - cycles = MAX_COUNTER_16B; - clkdiv = 7; - clkdiv <<= 28; - } - } - // Stop timer for setting clock again - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - obj->trailing_timing = cycles; - obj->leading_timing = (cycles - (cycles * duty_cycle)); - // Change the source clock division and period - obj->channel->MOD = T32A_MODE_32; - obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - obj->channel->RGC0 = obj->leading_timing; - obj->channel->RGC1 = obj->trailing_timing; - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c deleted file mode 100644 index 3b85770b6dc..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c +++ /dev/null @@ -1,471 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "serial_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" -#include "objects.h" - -static const PinMap PinMap_UART_TX[] = { - {PA1, SERIAL_0, PIN_DATA(1, 1)}, - {PJ1, SERIAL_1, PIN_DATA(1, 1)}, - {PB2, SERIAL_2, PIN_DATA(5, 1)}, - {PA6, SERIAL_3, PIN_DATA(2, 1)}, - {PV6, SERIAL_4, PIN_DATA(1, 1)}, - {PN2, SERIAL_5, PIN_DATA(2, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA2, SERIAL_0, PIN_DATA(1, 0)}, - {PJ2, SERIAL_1, PIN_DATA(1, 0)}, - {PB3, SERIAL_2, PIN_DATA(5, 0)}, - {PA7, SERIAL_3, PIN_DATA(2, 0)}, - {PV7, SERIAL_4, PIN_DATA(1, 0)}, - {PN3, SERIAL_5, PIN_DATA(2, 0)}, - {NC, NC, 0} -}; - -#define UART_NUM 6 - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct); -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); -static void uart_swreset(TSB_UART_TypeDef * UARTx); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - switch (uart_name) { /* Initialize UART instance */ - case SERIAL_0: - obj->UARTx = UART0; - TSB_CG_FSYSENB_IPENB05 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - break; - case SERIAL_1: - obj->UARTx = UART1; - TSB_CG_FSYSENB_IPENB06 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case SERIAL_2: - obj->UARTx = UART2; - TSB_CG_FSYSENB_IPENB07 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case SERIAL_3: - obj->UARTx = UART3; - TSB_CG_FSYSENB_IPENB08 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - break; - case SERIAL_4: - obj->UARTx = UART4; - TSB_CG_FSYSENB_IPENB09 = ENABLE; - TSB_CG_FSYSENA_IPENA17 = ENABLE; - break; - case SERIAL_5: - obj->UARTx = UART5; - TSB_CG_FSYSENB_IPENB10 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - default: - error("UART is not available"); - break; - } - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC && rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->uart_config.Mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX; - } - } - } - obj->uart_config.BaudRate = 9600; - obj->uart_config.DataBits = 8; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = ParityNone; - obj->uart_config.FlowCtrl = FlowControlNone; - - uart_init(obj->UARTx, &obj->uart_config); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = 0; - obj->UARTx->CR0 = 0; - obj->UARTx->CR1 = 0; - - uart_swreset(obj->UARTx); - - obj->uart_config.BaudRate = 0; - obj->uart_config.DataBits = 0; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = 0; - obj->uart_config.Mode = 0; - obj->uart_config.FlowCtrl = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->uart_config.BaudRate = baudrate; - uart_init(obj->UARTx, &obj->uart_config); -} -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - - obj->uart_config.DataBits = data_bits; - obj->uart_config.StopBits = stop_bits; - obj->uart_config.Parity = parity; - uart_init(obj->UARTx, &obj->uart_config); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void INTUART3TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); -} - -void INTUART3RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); -} - -void INTUART4TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); -} - -void INTUART4RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); -} - -void INTUART5TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); -} - -void INTUART5RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - case SERIAL_3: - if (irq == RxIrq) { - irq_n = INTUART3RX_IRQn; - } else { - irq_n = INTUART3TX_IRQn; - } - break; - case SERIAL_4: - if (irq == RxIrq) { - irq_n = INTUART4RX_IRQn; - } else { - irq_n = INTUART4TX_IRQn; - } - break; - case SERIAL_5: - if (irq == RxIrq) { - irq_n = INTUART5RX_IRQn; - } else { - irq_n = INTUART5TX_IRQn; - } - break; - default: - break; - } - NVIC_ClearPendingIRQ(irq_n); - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS &= 0x0D; - } - - data = data | (obj->UARTx->DR & 0xFFU); - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS |= UART_ENABLE_TX; - } - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - - while (!serial_writable(obj)) { - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS &= 0x0E; - } - - obj->UARTx->DR = c & 0xFFU; - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS |= UART_ENABLE_RX; - } -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x0000000F) != 0) { - ret = 1; - } - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR &0x8000) == 0) { - ret = 1; - } - - return ret; -} - -void serial_clear(serial_t *obj) -{ - obj->UARTx->FIFOCLR = 0x03; -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -static void uart_swreset(TSB_UART_TypeDef * UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) -{ - uint32_t clock = 0U; - uint32_t k = 0U; - uint64_t tx = 0U; - uint64_t work = 1U; - uint64_t p_range64 = 0U; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 1; - - SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency - clock = SystemCoreClock; - tx = (uint64_t)((uint64_t)clock << 6); - tx /= work; - tx64 = (uint64_t)((uint64_t)clock << 8); - tx64 /= work64; - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - - boud64 = (64U * boudrate); - p_range64 = ((boud64 / 100) * 3); - - for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { - work = tx + k; - if (work >= (uint64_t)((uint64_t)1 << 6)) { - work -= (uint64_t)((uint64_t)1 << 6); - work >>= 6; - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { - work64 = work <<6; - work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); - work64 = (tx64 / work64); - if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { - brddiviser->brn = work; - brddiviser->brk = k; - break; - } - } - } - } -} - -static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct) -{ - uart_boudrate_t UTx_brd = {0}; - uint32_t brk; - uint32_t tmp; - uint32_t parity_check; - uint32_t data_length; - - UARTx->CLK = UART_PLESCALER_1; // Register Setting - uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); - UTx_brd.ken = UART_DIVISION_ENABLE; - brk = (UTx_brd.brk << 16); - UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); - parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); - data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); - tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); - UARTx->CR0 = tmp; - UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - UARTx->TRANS = InitStruct->Mode; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c b/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c deleted file mode 100644 index 9e1d93c2b1f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "gpio_include.h" - -static void warming_up_time(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - __DSB(); // Enter idle mode - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t tmp; - // WDT sysclock enable - TSB_CG_FSYSENB_IPENB31 = ENABLE; - while ((TSB_FC->SR0 & 0x01) != 0x01); // Flash Wait - // Wait for end of Warming-up for IHOSC1 - while(TSB_CG_WUPHCR_WUEF); - // Set Warm-up clock to IHOSC1 - TSB_CG_WUPHCR_WUCLK = DISABLE; - // Set Warming-up time (xxxx) for IHOSC1 return from STOP1 mode - warming_up_time(); - // Set low power consumption mode STOP1 - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - // Set PLL of fsys to fosc(= PLL no USE) - TSB_CG_PLL0SEL_PLL0SEL = DISABLE; - // Wait for PLL status of fsys until off state(fosc = 0) - while(TSB_CG_PLL0SEL_PLL0ST); - TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys - TSB_CG_OSCCR_IHOSC1EN = ENABLE; // Enable IHOSC1 - TSB_CG_OSCCR_OSCSEL = DISABLE; // Set fosc to IHOSC1 - while(TSB_CG_OSCCR_OSCF); // Wait for fosc status until IHOSC1 - tmp = TSB_CG->OSCCR; // Set EHOSC off - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - TSB_CG_OSCCR_IHOSC2EN = DISABLE; //Stop IHOSC2 of OFD - // Wait for status of OFD until off ”0” - while(TSB_CG_OSCCR_IHOSC2F); - __DSB(); // Enter STOP1 mode - __WFI(); -} - -static void warming_up_time(void) -{ - uint32_t work; - uint64_t x; - x = (uint64_t)((uint64_t)(IHOSC_CFG_WARM_UP_TIME) * (uint64_t)(IHOSC_CFG_CLOCK)); - x = (uint64_t)(x / (uint64_t)(1000000)); - if (x > (uint64_t)(0xFFFF)) { - // invalid value - } - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 16; - work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); - TSB_CG->WUPHCR = work; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c deleted file mode 100644 index 9865a4d0429..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c +++ /dev/null @@ -1,329 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "spi_api.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_SPI_ASYNCH -#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) -#else -#define SPI_S(obj) (struct spi_s *) (obj) -#endif - -static const PinMap PinMap_SPI_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 1)}, - {PB2, SPI_1, PIN_DATA(3, 1)}, - {PT2, SPI_2, PIN_DATA(1, 1)}, - {PP5, SPI_3, PIN_DATA(1, 1)}, - {PH4, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PM1, SPI_0, PIN_DATA(3, 1)}, - {PB3, SPI_1, PIN_DATA(3, 1)}, - {PT3, SPI_2, PIN_DATA(1, 1)}, - {PP4, SPI_3, PIN_DATA(1, 1)}, - {PH5, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PM2, SPI_0, PIN_DATA(3, 0)}, - {PB4, SPI_1, PIN_DATA(3, 0)}, - {PT4, SPI_2, PIN_DATA(1, 0)}, - {PP3, SPI_3, PIN_DATA(1, 0)}, - {PH6, SPI_4, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PM3, SPI_0, PIN_DATA(3, 1)}, - {PB5, SPI_1, PIN_DATA(3, 1)}, - {PT1, SPI_2, PIN_DATA(2, 1)}, - {PP6, SPI_3, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - spi = obj_s->spi; - switch ((int)obj_s->module) { - case SPI_0: - TSB_CG_FSYSENA_IPENA11 = ENABLE; - TSB_CG_FSYSENB_IPENB00 = ENABLE; - spi = TSB_TSPI0; - break; - case SPI_1: - TSB_CG_FSYSENA_IPENA01 = ENABLE; - TSB_CG_FSYSENB_IPENB01 = ENABLE; - spi = TSB_TSPI1; - break; - case SPI_2: - TSB_CG_FSYSENA_IPENA15 = ENABLE; - TSB_CG_FSYSENB_IPENB02 = ENABLE; - spi = TSB_TSPI2; - break; - case SPI_3: - TSB_CG_FSYSENA_IPENA13 = ENABLE; - TSB_CG_FSYSENB_IPENB03 = ENABLE; - spi = TSB_TSPI3; - break; - case SPI_4: - TSB_CG_FSYSENA_IPENA07 = ENABLE; - TSB_CG_FSYSENB_IPENB04 = ENABLE; - spi = TSB_TSPI4; - break; - default: - error("Cannot found SPI module corresponding with input pins."); - break; - } - obj_s->spi = spi; - // pin out the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - // TTSPI Software Reset - spi->CR0 = TSPI_RESET10; - spi->CR0 = TSPI_RESET01; - - // Wait for 2 clocks of reset completion - __NOP(); - __NOP(); - - // Enable the selected TSPI peripheral (TTSPIE) - spi->CR0 = TSPI_ENABLE; - spi->CR1 = 0; - spi->CR1 = TSPI_MASTER_OPEARTION; - spi->CR2 = 0; - spi->CR2 = (TSPI_TIDLE_LOW | TSPI_TXDEMP_HI); - // Format control0 Register Set - spi->FMTR0 = (TSPI_DATA_DIRECTION_MSB | TSPI_DATA_LENGTH_8 | - TSPI_MIN_IDLE_TIME_1); - // Format control1 Register Set - spi->FMTR1 = 0; - // Enable the selected TSPI peripheral - spi->CR0 |= TSPI_ENABLE; - spi_frequency(obj, 1000000); -} - -void spi_free(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - - spi = obj_s->spi; - spi->CR0 |= TSPI_DISABLE; - spi->CR2 = TSPI_INT_ALL; // Disable all interrupt -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - - obj_s->bits = bits; - spi = obj_s->spi; - obj_s->bits = bits; - spi->CR0 |= TSPI_DISABLE; - - if (bits >= 8 || bits <= 32) { - spi->FMTR0 |= (bits << 24); - } else { - // Do nothing - } - spi->FMTR0 |= (((mode >> 1) & 0x1) << 14); - spi->FMTR0 |= ((mode & 0x01) << 15); - spi->CR0 |= TSPI_ENABLE; -} - -void spi_frequency(spi_t *obj, int hz) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - int clk_div = 1; - uint32_t clocks = ((SystemCoreClock / 2) / hz); - obj_s->spi->CR0 |= TSPI_DISABLE; - - while (clk_div < 10) { - if (clocks < 16) { - break; - } - clk_div++; - clocks >>= 1; - } - clk_div--; - if (clk_div == 0) { - clocks++; - } - spi = obj_s->spi; - spi->CR0 |= TSPI_DISABLE; - spi->BR = ((clk_div << 4) | clocks); - spi->CR0 |= TSPI_ENABLE; -} - -int spi_master_write(spi_t *obj, int value) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - MBED_ASSERT(obj_s != NULL); - spi = obj_s->spi; - spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; // FIFO Cear - // Check if the TSPI is already enabled - if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { - spi->CR0 |= TSPI_ENABLE; - } - // Enable TSPI Transmission Control - spi->CR1 |= TSPI_TRXE_ENABLE; - // Check the current fill level - if(((spi->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { - do { - spi->DR = (value & TSPI_DR_8BIT_MASK); - // check complete transmit - } while ((spi->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE); - spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; - spi->CR1 &= TSPI_TRXE_DISABLE_MASK; - } - if((spi->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - // Enable TSPI Transmission Control - spi->CR1 |= TSPI_TRXE_ENABLE; - } - // Check if the TSPI is already enabled - if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { - // Enable TSPI Transmission Control - spi->CR0 |= TSPI_ENABLE; - } - value = 0; - // Wait until Receive Complete Flag is set to receive data - if((spi->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { - // Check the remain data exist - if((spi->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { - value = (spi->DR & TSPI_DR_8BIT_MASK); - } - spi->SR |= TSPI_RX_DONE_CLR; // Receive Complete Flag is clear - spi->CR2 |= TSPI_RX_BUFF_CLR_DONE; // FIFO Clear - spi->CR1 &= TSPI_TRXE_DISABLE_MASK; - } - return value; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - uint8_t result = 0; - - spi = obj_s->spi; - if( (spi->SR & (1<<7)) || (spi->SR & (1<<23))) { - result = 1; - } else { - result = 0; - } - return result; -} - -uint8_t spi_get_module(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - return (uint8_t)(obj_s->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c b/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c deleted file mode 100644 index 6a0ef9f8517..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "gpio_include.h" - - -#define T32A_INT_MASK ((uint32_t)0x0000000F) -#define TXZ_ENABLE 1 -static bool us_ticker_inited = false; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 1248125, // (39.94 MHz / 32 ) - 32 // 32 bit counter - }; - return &info; -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = true; - - TSB_CG_FSYSENA_IPENA24 = TXZ_ENABLE; - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - - NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -uint32_t us_ticker_read(void) -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - return (TSB_T32A0->TMRC); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp; - NVIC_EnableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00C_IRQn); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts by NVIC - NVIC_DisableIRQ(INTT32A00C_IRQn); - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - TSB_T32A0->STC = T32A_INT_MASK; -} - -void us_ticker_clear_interrupt(void) -{ - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); -} - -void us_ticker_free(void) -{ - TSB_T32A0->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - us_ticker_inited = false; - TSB_T32A0->STC = 0x0F; - // Clear Pending interrupt in NVIC - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - // Disable interrupt in NVIC - NVIC_DisableIRQ(INTT32A00C_IRQn); - // Disable Clock. - TSB_CG_FSYSENA_IPENA24 = 0; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h deleted file mode 100644 index 4ffb4cd46a1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - ******************************************************************************* - * @file adc.h - * @brief This file provides all the functions prototypes for ADC driver. - * @version V1.0.0.0 - * $Date:: 2017-09-12 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_H -#define __ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "adc_ch.h" -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/** - * @defgroup ADC_ChannelMax Channel Num Max - * @brief Max Num of channel. - * @{ - */ - - #define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */ -/** - * @} - */ /* End of group ADC_ChannelMax */ -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - @defgroup ADC_Exported_define ADC Exported Define - @{ - */ -/** @enum adc_sampling_period0_t - @brief Outside AIN sampling period. - */ -typedef enum -{ - ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */ - ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */ - ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */ - ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */ - ADC_SAMPLING_PERIOD0_X16N = 0x28, /*!< SCLK Period (1/SCLK)x16N */ - ADC_SAMPLING_PERIOD0_X64N = 0x38, /*!< SCLK Period (1/SCLK)x64N */ -}adc_sampling_period0_t; -/** @enum adc_sampling_period1_t - @brief Outside AIN sampling period. - */ -typedef enum -{ - ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */ - ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */ - ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */ - ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */ - ADC_SAMPLING_PERIOD1_X16N = 0x500, /*!< SCLK Period (1/SCLK)x16N */ - ADC_SAMPLING_PERIOD1_X64N = 0x700, /*!< SCLK Period (1/SCLK)x64N */ -}adc_sampling_period1_t; - -/*! @enum adc_sclk_t - @brief Select AD prescaler output (SCLK). - */ -typedef enum -{ - ADC_SCLK_1 = (0x00000000U), /*!< ADCLK/1 */ - ADC_SCLK_2 = (0x00000001U), /*!< ADCLK/2 */ - ADC_SCLK_4 = (0x00000002U), /*!< ADCLK/4 */ - ADC_SCLK_8 = (0x00000003U), /*!< ADCLK/8 */ - ADC_SCLK_16 = (0x00000004U), /*!< ADCLK/16 */ -}adc_sclk_t; - -/*! @enum adc_mod1_t - @brief Select SCLK Frequency Band (MOD1). - */ -typedef enum -{ - ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 40MHz > */ - ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 40MHz < SCLK =< 50MHz > */ - ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 50MHz < SCLK =< 60MHz > */ - ADC_MOD1_SCLK_4 = (0x00106011U), /*!< 60MHz < SCLK =< 80MHz > */ -}adc_mod1_t; - -/*! @enum adc_mod2_t - @brief Select ADC Product Setting Value (MOD2). - */ -typedef enum -{ - ADC_MOD2_TMPM4G9 = (0x00000000U), /*!< TMPM4G9 */ - ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */ -}adc_mod2_t; - -/*! @enum adc_int_t - @brief Select Interrupt Enable/Disable. - */ -typedef enum -{ - ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */ -}adc_int_t; - -/*! @enum adc_conversion_t - @brief Select conversion method. - */ -typedef enum -{ - ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */ - ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */ - ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */ - ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */ -}adc_conversion_t; - -/*! @enum adc_dma_int_t - @brief Select DMA interrupt method. - */ -typedef enum -{ - ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */ - ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */ - ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */ - ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */ - ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */ - ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */ - ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */ -}adc_dma_int_t; - -/*! @enum adc_ain_range_t - @brief Range of AIN Macro Definisiton. - Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)". - */ -typedef enum -{ - ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */ - ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */ -}adc_ain_range_t; - -/*! @enum adc_status_t - @brief AD Running Status. - */ -typedef enum -{ - ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */ - ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */ -}adc_status_t; - -/*! @enum adc_cnt_status_t - @brief Continuity Conversion Running Status. - */ -typedef enum -{ - ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */ - ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */ -}adc_cnt_status_t; - -/*! @enum adc_sgl_status_t - @brief Single Conversion Running Status. - */ -typedef enum -{ - ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */ - ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */ -}adc_sgl_status_t; - -/*! @enum adc_trg_status_t - @brief Trigger Conversion Running Status. - */ -typedef enum -{ - ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */ - ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */ -}adc_trg_status_t; - -/*! @enum adc_hpri_status_t - @brief Trigger Conversion Running Status. - */ -typedef enum -{ - ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */ - ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */ -}adc_hpri_status_t; - -/*! @enum adcmpxen_t - @brief Select Enable, Disable setting(ADxCMPEN). - */ -typedef enum -{ - ADCMP3EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP3EN_ENABLE = (0x00000008U), /*!< Enable. */ - ADCMP2EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP2EN_ENABLE = (0x00000004U), /*!< Enable. */ - ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */ - ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */ -}adcmpxen_t; - -/*! @enum adcmpcnt_t - @brief Select Compare count num. - */ -typedef enum -{ - ADCMPCNT_1 = (0x00000000U), /*!< 1 time */ - ADCMPCNT_2 = (0x00000100U), /*!< 2 times */ - ADCMPCNT_3 = (0x00000200U), /*!< 3 times */ - ADCMPCNT_4 = (0x00000300U), /*!< 4 times */ - ADCMPCNT_5 = (0x00000400U), /*!< 5 times */ - ADCMPCNT_6 = (0x00000500U), /*!< 6 times */ - ADCMPCNT_7 = (0x00000600U), /*!< 7 times */ - ADCMPCNT_8 = (0x00000700U), /*!< 8 times */ - ADCMPCNT_9 = (0x00000800U), /*!< 9 times */ - ADCMPCNT_10 = (0x00000900U), /*!< 10 times */ - ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */ - ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */ - ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */ - ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */ - ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */ - ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */ -}adcmpcnt_t; - -/*! @enum adcmpcond_t - @brief Compare condition - */ -typedef enum -{ - ADCMPCond_CNT = (0x00000000U), /*!< Continuous */ - ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */ -}adcmpcond_t; - -/*! @enum adcmpbigsml_t - @brief Compare Big, Small condition - */ -typedef enum -{ - ADCMPBigSml_Big = (0x00000000U), /*!< Big */ - ADCMPBigSml_Sml = (0x00000020U), /*!< Small */ -}adcmpbigsml_t; - -/*! @enum adcmpstr_t - @brief Select Compare Store register - */ -typedef enum -{ - ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */ - ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */ - ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */ - ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */ - ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */ - ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */ - ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */ - ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */ - ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */ - ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */ - ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */ - ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */ - ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */ - ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */ - ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */ - ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */ - ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */ - ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */ - ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */ - ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */ - ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */ - ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */ - ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */ - ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */ -}adcmpstr_t; -/*! @enum adcexazain_t - @brief Select AIN no. - */ - -typedef enum -{ - ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */ - ADCEXAZSEL_AIN1, /*!< AIN1 */ - ADCEXAZSEL_AIN2, /*!< AIN2 */ - ADCEXAZSEL_AIN3, /*!< AIN3 */ - ADCEXAZSEL_AIN4, /*!< AIN4 */ - ADCEXAZSEL_AIN5, /*!< AIN5 */ - ADCEXAZSEL_AIN6, /*!< AIN6 */ - ADCEXAZSEL_AIN7, /*!< AIN7 */ - ADCEXAZSEL_AIN8, /*!< AIN8 */ - ADCEXAZSEL_AIN9, /*!< AIN9 */ - ADCEXAZSEL_AIN10, /*!< AIN10 */ - ADCEXAZSEL_AIN11, /*!< AIN11 */ - ADCEXAZSEL_AIN12, /*!< AIN12 */ - ADCEXAZSEL_AIN13, /*!< AIN13 */ - ADCEXAZSEL_AIN14, /*!< AIN14 */ - ADCEXAZSEL_AIN15, /*!< AIN15 */ - ADCEXAZSEL_AIN16, /*!< AIN16 */ - ADCEXAZSEL_AIN17, /*!< AIN17 */ - ADCEXAZSEL_AIN18, /*!< AIN18 */ - ADCEXAZSEL_AIN19, /*!< AIN19 */ - ADCEXAZSEL_AIN20, /*!< AIN20 */ - ADCEXAZSEL_AIN21, /*!< AIN21 */ - ADCEXAZSEL_AIN22, /*!< AIN22 */ - ADCEXAZSEL_AIN23, /*!< AIN23 */ -}adcexazain_t; -/*! @enum adcexazsel_t - @brief Select sampling period, EXAS0 or EXAS1. - */ -typedef enum -{ - ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */ - ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */ -}adcexazsel_t; - -/*! - @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/*! - @defgroup ADC_Exported_typedef ADC Exported Typedef - @{ - */ - -/*----------------------------------*/ -/*! @struct adc_clock_t - @brief Clock information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period. - : Use @ref adc_sampling_period0_t. */ - adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period. - : Use @ref adc_sampling_period1_t. */ - adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK). - : Use @ref adc_sclk_t. */ - uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */ -} adc_clock_t; - -/*----------------------------------*/ -/*! @struct adc_cmpx_t - @brief Clock information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t CMPEN; /*!< Enable Register status */ - uint32_t CMPCNT; /*!< Compare count num. */ - uint32_t CMPCond; /*!< Compare condition */ - uint32_t CMPBigSml; /*!< Compare Big/Small condition */ - uint32_t StrReg; /*!< Compare Store register */ - uint32_t ADComp; /*!< ADxCMP0 register data */ - void (*handle)(uint32_t id, TXZ_Result result); /*!< Notity Compare Done. */ -} adc_cmpx_t; - -/*----------------------------------*/ -/*! @struct adc_initial_setting_t - @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - adc_clock_t clk; /*!< Clock setting. - : Use @ref adc_clock_t. */ - uint32_t mod1; /*!< AVDD3 voltage band setting. - : Use @ref adc_mod1_t. */ - uint32_t mod2; /*!< Product info setting. - : Use @ref adc_mod2_t. */ - adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */ - - -} adc_initial_setting_t; - -/*----------------------------------*/ -/*! @struct adc_channel_setting_t - @brief Channel Setting. \n -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t interrupt; /*!< Interrupt Enable/Disable. - : Use @ref adc_dma_int_t. */ - uint32_t type; /*!< Conversion Type. - : Use @ref adc_conversion_t. */ - uint32_t ain; /*!< AIN. */ -} adc_channel_setting_t; - -/*----------------------------------*/ -/*! @struct adc_internal_info_t - @brief Driver internal information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */ -} adc_internal_info_t; - -/*----------------------------------*/ -/*! @struct adc_t - @brief ADC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_AD_TypeDef *p_instance; /*!< Registers base address. */ - adc_initial_setting_t init; /*!< Initial setting. */ - adc_internal_info_t info; /*!< Driver internal information. */ - struct - { - void (*single)(uint32_t id, TXZ_Result result); /*!< Notity Single Conversion Done. */ - void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notity Continuity Conversion Done. */ - void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notity Trigger Conversion Done. */ - void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notity HighPriority Conversion Done. */ - } handler; /*!< Handler structure. */ -} adc_t; - -/** - * @} - */ /* End of group ADC_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_functions ADC Exported Functions - * @{ - */ -TXZ_Result adc_init(adc_t *p_obj); -TXZ_Result adc_deinit(adc_t *p_obj); -TXZ_Result adc_mode1_setting(void); -TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting); -TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch); -TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); -TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); -TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value); -TXZ_Result adc_start(adc_t *p_obj); -TXZ_Result adc_stop(adc_t *p_obj); -TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status); -TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout); -void adc_compa_irq_handler( void ); -void adc_compb_irq_handler( void ); -void adc_single_irq_handler( void ); -void adc_continuity_irq_handler( void ); -void adc_trigger_irq_handler( void ); -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h deleted file mode 100644 index 098d889a8e6..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ******************************************************************************* - * @file adc_ch.h - * @brief This file provides all the functions prototypes for ADC driver. \n - * Channel Class. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_CH_H -#define __ADC_CH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_typedef ADC Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/*! @struct adc_ch_initial_setting_t - * @brief Initialize Setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t interrupt; /*!< Interrupt Enable/Disable. - : Use @ref adc_dma_int_t. */ - uint32_t type; /*!< Conversion Type. - : Use @ref adc_conversion_t. */ - uint32_t ain; /*!< AIN. */ -} adc_ch_initial_setting_t; - -/*----------------------------------*/ -/*! @struct adc_ch_t - * @brief ADC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - __IO uint32_t *p_tset; /*!< ADxTSETn Address. */ - __I uint32_t *p_reg; /*!< ADxREGx Address. */ - adc_ch_initial_setting_t init; /*!< Initial setting. */ -} adc_ch_t; - -/** - * @} - */ /* End of group ADC_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_functions ADC Exported Functions - * @{ - */ -uint32_t get_conversion_data(uint32_t reg); -TXZ_Result adc_ch_init(adc_ch_t *p_obj); -TXZ_Result adc_ch_deinit(adc_ch_t *p_obj); -TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj); -TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj); -TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value); -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_CH_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h deleted file mode 100644 index 011bc2967d4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - ******************************************************************************* - * @file adc_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_INCLUDE_H -#define __ADC_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "txz_hal.h" - -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/** - * @defgroup NULL_Pointer NULL Pointer - * @brief NULL Pointer. - * @{ - */ -#define ADC_NULL ((void *)0) /*!< NULL Pointer. */ -/** - * @} - */ /* End of group NULL_Pointer */ - -/** - * @defgroup Parameter_Result Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group Parameter_Result */ - -/** - * @defgroup ADxCR0 ADxCR0 - * @brief ADxCR0 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ADEN | - * | 6-3 | - | - * | 2 | HPSGL | - * | 1 | SGL | - * | 0 | CNT | - * @{ - */ -/* ADEN */ -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */ -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */ -/* HPSGL */ -#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */ -/* SGL */ -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */ -/* CNT */ -#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */ -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */ -#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */ -/** - * @} - */ /* End of group ADxCR0 */ - -/** - * @defgroup ADxCR1 ADxCR1 - * @brief ADxCR1 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | HPDMEN | - * | 6 | CNTDMEN | - * | 5 | SGLDMEN | - * | 4 | TRGDMEN | - * | 3:2 | - | - * | 1 | HPTRGEN | - * | 0 | TRGEN | - * @{ - */ -/* HPDMEN */ -#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */ -#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */ -/* CNTDMEN */ -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */ -#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */ -/* SGLDMEN */ -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */ -#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */ -/* TRGDMEN */ -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */ -#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */ -/* HPTRGEN */ -#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */ -#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */ -/* TRGEN */ -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */ -#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */ -/** - * @} - */ /* End of group ADxCR1 */ - -/** - * @defgroup ADxST ADxST - * @brief ADxST Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ADBF | - * | 6-4 | - | - * | 3 | CNTF | - * | 2 | SNGF | - * | 1 | TRGF | - * | 0 | HPF | - * @{ - */ -/* ADBF */ -#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */ -#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */ -#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */ -/* CNTF */ -#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */ -#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */ -#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */ -/* SNGF */ -#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */ -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */ -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */ -/* TRGF */ -#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */ -#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */ -#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */ -/* PMDF */ -#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */ -#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */ -#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */ -/** - * @} - */ /* End of group ADxST */ - -/** - * @defgroup ADxMOD0 ADxMOD0. - * @brief ADxMOD0 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-2 | - | - * | 1 | RCUT | - * | 0 | DACON | - * @{ - */ -/* RCUT */ -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */ -#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */ -/* DACON */ -#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */ -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */ -/** - * @} - */ /* End of group ADxMOD0 */ - -/** - * @name ADxCMPEN Macro Definition. - * @brief ADxCMPEN Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-4 | - | - * | 3 | CMP3EN | - * | 2 | CMP2EN | - * | 1 | CMP1EN | - * | 0 | CMP0EN | - * @{ - */ -/* CMP3EN */ -#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */ -#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */ -/* CMP2EN */ -#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */ -#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */ -/* CMP1EN */ -#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */ -#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */ -/* CMP0EN */ -#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */ -#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */ -/** - * @} - */ /* End of name ADxCMPEN Macro Definition */ - -/** - * @name ADxTSETn Macro Definition. - * @brief ADxTSETn Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ENINT0 | - * | 6-5 | TRGS0[1:0] | - * | 4-0 | AINST0[4:0]| - * @{ - */ -/* ENINT0 */ -#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */ -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */ -#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */ -/* TRGS0[1:0] */ -#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */ -#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */ -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */ -#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */ -#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */ -/** - * @} - */ /* End of name ADxTSETn Macro Definition */ - -/** - * @name ADxREGn Macro Definition. - * @brief ADxREGn Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-30 | - | - * | 29 | ADOVRF_Mn | - * | 28 | ADRF_Mn | - * | 27-16 | ADR_Mn[11:0] | - * | 15-4 | ADRn[11:0] | - * | 3-2 | - | - * | 1 | ADOVRFn | - * | 0 | ADRFn | - * @{ - */ -/* ADOVRF_Mn */ -#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */ -#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ -#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */ -/* ADRF_Mn */ -#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */ -#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */ -#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */ -/* ADR_Mn */ -#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */ -/* ADRn */ -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */ -/* ADOVRFn */ -#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */ -#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ -#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */ -/* ADRFn */ -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */ -#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */ -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */ -/** - * @} - */ /* End of name ADxREGn Macro Definition */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group ADC_Private_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_INCLUDE_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h deleted file mode 100644 index c9f80b2e027..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - ******************************************************************************* - * @file fc.h - * @brief Flash_Userboot Sample Application. - * @version V1.0.0.0 - * $date:: $ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FC_H -#define __FC_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -#if defined(__FC_H) -/** @addtogroup Periph driver - * @{ - */ - -/** @defgroup fc - * @brief fc - * @{ - */ - - -/** @defgroup FlashApi_Exported_Types - * @{ - */ - -/** - * @enum fc_sr0_t - * @brief Enumerated type definition of the FCSR0 register. - */ -typedef enum { - FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */ -} fc_sr0_t; - -/*----------------------------------*/ -/** - * @enum fc_erase_kind_t - * @brief FC Erase Flash Kind structure definenition. -*/ -/*----------------------------------*/ -typedef enum { - FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */ - FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */ -} fc_erase_kind_t; - -typedef enum { - FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */ - FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */ - FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */ - FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */ - FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */ - FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */ - FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */ - FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */ - FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */ - FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */ - FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */ - FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */ - FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */ - FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */ - FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */ - FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */ - FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */ - FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */ - FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */ - FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */ - FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */ - FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */ - FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */ - FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */ - FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */ - FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */ - FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */ - FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */ - FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */ - FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */ - FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */ - FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */ -} fc_code_flash_page_number_t; - -/** @} */ -/* End of group FlashApi_Exported_Types */ - -/** @defgroup FlashApi_Exported_Constants - * @{ - */ - -//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */ -//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */ -#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */ -//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */ -#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */ -//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */ -#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */ - -/** @} */ -/* End of group FlashApi_Exported_Constants */ - - - -/** @weakgroup FlashApi_Exported_FunctionPrototypes - * @{ - */ -TXZ_WorkState fc_get_status(fc_sr0_t status); -TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages); -TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page); -TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr); - -/** @} */ -/* End of group FlashApi_Exported_FunctionPrototypes */ - - -/** @} */ -/* End of group fc */ - -/** @} */ -/* End of group Periph_driver */ - -#endif /* defined(__FC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __FC_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h deleted file mode 100644 index 75380e3e6c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h +++ /dev/null @@ -1,386 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_rtc.h - * @brief This file provides all the functions prototypes for RTC Class. - * @version V1.0.0.1 - * $Date:: 2017-09-01 08:26:38 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __BSP_RTC_H -#define __BSP_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -//#include "txz_sample_def.h" -#include "txz_driver_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup BSP_UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/** - * @defgroup RTC_RangeSec Range Second - * @brief Range of Second. - * @brief Range of Second "(RTC_RANGE_SEC_MIN <= Value <= RTC_RANGE_SEC_MAX)". - * @{ - */ -#define RTC_RANGE_SEC_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 sec */ -#define RTC_RANGE_SEC_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 sec */ -/** - * @} - */ /* End of group RTC_RangeSec */ - -/** - * @defgroup RTC_RangeMin Range Minute - * @brief Range of Minute. - * @brief Range of Minute "(RTC_RANGE_MIN_MIN <= Value <= RTC_RANGE_MIN_MAX)". - * @{ - */ -#define RTC_RANGE_MIN_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 min */ -#define RTC_RANGE_MIN_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 min */ -/** - * @} - */ /* End of group RTC_RangeMin */ - -/** - * @defgroup RTC_AlarmMin Alarm Minute - * @brief Compare/No Compare minute. - * @{ - */ -#define RTC_ALARM_MIN_OFF ((uint8_t)0x7F) /*!< No compare. */ -#define RTC_ALARM_MIN_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmMin */ - -/** - * @defgroup RTC_Range24Hour Range 24 Hour - * @brief Range of 24 Hour. - * @brief Range of 24 Hour "(RTC_RANGE_24_HOUR_MIN <= Value <= RTC_RANGE_24_HOUR_MAX)". - * @{ - */ -#define RTC_RANGE_24_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */ -#define RTC_RANGE_24_HOUR_MAX ((uint8_t)0x17) /*!< Maximum Value :23 hour */ -/** - * @} - */ /* End of group RTC_Range24Hour */ - -/** - * @defgroup RTC_Range12Hour Range 12 Hour - * @brief Range of 12 Hour. - * @brief Range of 12 Hour "(RTC_RANGE_12_HOUR_MIN <= Value <= RTC_RANGE_12_HOUR_MAX)". - * @{ - */ -#define RTC_RANGE_12_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */ -#define RTC_RANGE_12_HOUR_MAX ((uint8_t)0x0B) /*!< Maximum Value :11 hour */ -/** - * @} - */ /* End of group RTC_Range12Hour */ - -/** - * @defgroup RTC_Meridiem Meridiem - * @brief AM/PM. - * @{ - */ -#define RTC_MERIDIEM_AM ((uint8_t)0x00) /*!< A.M. */ -#define RTC_MERIDIEM_PM ((uint8_t)0x20) /*!< P.M. */ -/** - * @} - */ /* End of group RTC_Meridiem */ - -/** - * @defgroup RTC_AlarmHour Alarm Hour - * @brief Compare/No Compare hour. - * @{ - */ -#define RTC_ALARM_HOUR_OFF ((uint8_t)0x3F) /*!< No compare. */ -#define RTC_ALARM_HOUR_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmHour */ - -/** - * @defgroup RTC_Day Day Of Week - * @brief Day of week. - * @{ - */ -#define RTC_DAY_SUNDAY ((uint8_t)0x00) /*!< Sunday. */ -#define RTC_DAY_MONDAY ((uint8_t)0x01) /*!< Monday. */ -#define RTC_DAY_TUESDAY ((uint8_t)0x02) /*!< Tuesday. */ -#define RTC_DAY_WEDNESDAY ((uint8_t)0x03) /*!< Wednesday. */ -#define RTC_DAY_THURSDAY ((uint8_t)0x04) /*!< Thursday. */ -#define RTC_DAY_FRIDAY ((uint8_t)0x05) /*!< Friday. */ -#define RTC_DAY_SATURDAY ((uint8_t)0x06) /*!< Saturday. */ -/** - * @} - */ /* End of group RTC_Day */ - -/** - * @defgroup RTC_AlarmDay Alarm Day - * @brief Compare/No Compare day. - * @{ - */ -#define RTC_ALARM_DAY_OFF ((uint8_t)0x03) /*!< No compare. */ -#define RTC_ALARM_DAY_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmDay */ - -/** - * @defgroup RTC_RangeDate Range Date - * @brief Range of Date. - * @brief Range of Date "(RTC_RANGE_DATE_MIN <= Value <= RTC_RANGE_DATE_MAX)". - * @{ - */ -#define RTC_RANGE_DATE_MIN ((uint8_t)0x00) /*!< Minimum Value :date 00 */ -#define RTC_RANGE_DATE_MAX ((uint8_t)0x1F) /*!< Maximum Value :date 31 */ -/** - * @} - */ /* End of group RTC_RangeDate */ - -/** - * @defgroup RTC_AlarmDate Alarm Date - * @brief Compare/No Compare date. - * @{ - */ -#define RTC_ALARM_DATE_OFF ((uint8_t)0x3F) /*!< No compare. */ -#define RTC_ALARM_DATE_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmDate */ - -/** - * @defgroup RTC_Month Month - * @brief Month. - * @{ - */ -#define RTC_MONTH_JAN ((uint8_t)0x01) /*!< January. */ -#define RTC_MONTH_FEB ((uint8_t)0x02) /*!< February. */ -#define RTC_MONTH_MAR ((uint8_t)0x03) /*!< March. */ -#define RTC_MONTH_APR ((uint8_t)0x04) /*!< April. */ -#define RTC_MONTH_MAY ((uint8_t)0x05) /*!< May. */ -#define RTC_MONTH_JUN ((uint8_t)0x06) /*!< June. */ -#define RTC_MONTH_JUL ((uint8_t)0x07) /*!< July. */ -#define RTC_MONTH_AUG ((uint8_t)0x08) /*!< August. */ -#define RTC_MONTH_SEP ((uint8_t)0x09) /*!< September. */ -#define RTC_MONTH_OCT ((uint8_t)0x10) /*!< October. */ -#define RTC_MONTH_NOV ((uint8_t)0x11) /*!< November. */ -#define RTC_MONTH_DEC ((uint8_t)0x12) /*!< December. */ -/** - * @} - */ /* End of group RTC_Month */ - -/** - * @defgroup BSP_RTC_HourNotation Hour Notation - * @brief 24/12 Hour Notation. - * @{ - */ -#define RTC_HOUR_NOTATION_12 ((uint8_t)0x00) /*!< 12-hour notation. */ -#define RTC_HOUR_NOTATION_24 ((uint8_t)0x01) /*!< 24-hour notation. */ -/** - * @} - */ /* End of group BSP_RTC_HourNotation */ - -/** - * @defgroup RTC_RangeYear Range Year - * @brief Range of Year. - * @brief Range of Year "(RTC_RANGE_YEAR_MIN <= Value <= RTC_RANGE_YEAR_MAX)". - * @{ - */ -#define RTC_RANGE_YEAR_MIN ((uint8_t)0x00) /*!< Minimum Value :year 00 */ -#define RTC_RANGE_YEAR_MAX ((uint8_t)0x63) /*!< Maximum Value :year 99 */ -/** - * @} - */ /* End of group RTC_RangeYear */ - -/** - * @defgroup RTC_LeapYear Leap Year - * @brief Leap Year. - * @{ - */ -#define RTC_LEAP_YEAR_0 ((uint8_t)0x00) /*!< Leap year. */ -#define RTC_LEAP_YEAR_1 ((uint8_t)0x01) /*!< 1 year since leap year. */ -#define RTC_LEAP_YEAR_2 ((uint8_t)0x02) /*!< 2 years since leap year. */ -#define RTC_LEAP_YEAR_3 ((uint8_t)0x03) /*!< 3 years since leap year. */ -/** - * @} - */ /* End of group RTC_LeapYear */ - -/** - * @defgroup RTC_IntSource Interrupt Source Signal - * @brief Interrupt Source Signal. - * @{ - */ -#define RTC_INT_SRC_1HZ ((uint8_t)0x47) /*!< 1 Hz. */ -#define RTC_INT_SRC_2HZ ((uint8_t)0xC3) /*!< 2 Hz. */ -#define RTC_INT_SRC_4HZ ((uint8_t)0xC5) /*!< 4 Hz. */ -#define RTC_INT_SRC_8HZ ((uint8_t)0x01) /*!< 8 Hz. */ -#define RTC_INT_SRC_16HZ ((uint8_t)0xC6) /*!< 16 Hz. */ -#define RTC_INT_SRC_ALARM ((uint8_t)0xC7) /*!< Alarm. */ -/** - * @} - */ /* End of group RTC_IntSource */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup BSP_UTILITIES_Exported_typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief RTC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct uart_handle -{ - TSB_RTC_TypeDef *p_instance; /*!< Registers base address. */ -} rtc_t; -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_functions - * @{ - */ -TXZ_Result m4g9_rtc_init(rtc_t *p_obj); -TXZ_Result rtc_deinit(rtc_t *p_obj); -TXZ_Result rtc_enable_int(rtc_t *p_obj); -TXZ_Result rtc_disable_int(rtc_t *p_obj); -TXZ_Result rtc_set_int_source(rtc_t *p_obj, uint8_t src); -TXZ_Result rtc_set_hour_notation(rtc_t *p_obj, uint8_t notation); -TXZ_Result rtc_get_hour_notation(rtc_t *p_obj, uint8_t *p_notation); -/* clock */ -TXZ_Result rtc_clock_enable(rtc_t *p_obj); -TXZ_Result rtc_clock_disable(rtc_t *p_obj); -TXZ_Result rtc_clock_reset_counter(rtc_t *p_obj); -TXZ_Result rtc_clock_set_sec(rtc_t *p_obj, uint8_t sec); -TXZ_Result rtc_clock_get_sec(rtc_t *p_obj, uint8_t *p_sec); -TXZ_Result rtc_clock_set_min(rtc_t *p_obj, uint8_t min); -TXZ_Result rtc_clock_get_min(rtc_t *p_obj, uint8_t *p_min); -TXZ_Result rtc_clock_set_hour_24(rtc_t *p_obj, uint8_t hour); -TXZ_Result rtc_clock_get_hour_24(rtc_t *p_obj, uint8_t *p_hour); -TXZ_Result rtc_clock_set_hour_12(rtc_t *p_obj, uint8_t meridiem, uint8_t hour); -TXZ_Result rtc_clock_get_hour_12(rtc_t *p_obj, uint8_t *p_meridiem, uint8_t *p_hour); -TXZ_Result rtc_clock_set_day(rtc_t *p_obj, uint8_t day); -TXZ_Result rtc_clock_get_day(rtc_t *p_obj, uint8_t *p_day); -TXZ_Result rtc_clock_set_date(rtc_t *p_obj, uint8_t date); -TXZ_Result rtc_clock_get_date(rtc_t *p_obj, uint8_t *p_date); -TXZ_Result rtc_clock_set_month(rtc_t *p_obj, uint8_t month); -TXZ_Result rtc_clock_get_month(rtc_t *p_obj, uint8_t *p_month); -TXZ_Result rtc_clock_set_year(rtc_t *p_obj, uint8_t year); -TXZ_Result rtc_clock_get_year(rtc_t *p_obj, uint8_t *p_year); -TXZ_Result rtc_clock_set_leap(rtc_t *p_obj, uint8_t leap); -TXZ_Result rtc_clock_get_leap(rtc_t *p_obj, uint8_t *p_leap); -/* alarm */ -TXZ_Result rtc_alarm_enable(rtc_t *p_obj); -TXZ_Result rtc_alarm_disable(rtc_t *p_obj); -TXZ_Result rtc_alarm_reset(rtc_t *p_obj); -TXZ_Result rtc_alarm_set_min(rtc_t *p_obj, uint8_t compare, uint8_t min); -TXZ_Result rtc_alarm_get_min(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_min); -TXZ_Result rtc_alarm_set_hour_24(rtc_t *p_obj, uint8_t compare, uint8_t hour); -TXZ_Result rtc_alarm_get_hour_24(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_hour); -TXZ_Result rtc_alarm_set_hour_12(rtc_t *p_obj, uint8_t compare, uint8_t meridiem, uint8_t hour); -TXZ_Result rtc_alarm_get_hour_12(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_meridiem, uint8_t *p_hour); -TXZ_Result rtc_alarm_set_day(rtc_t *p_obj, uint8_t compare, uint8_t day); -TXZ_Result rtc_alarm_get_day(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_day); -TXZ_Result rtc_alarm_set_date(rtc_t *p_obj, uint8_t compare, uint8_t date); -TXZ_Result rtc_alarm_get_date(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_date); -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group BSP_UTILITIES */ - -/** - * @} - */ /* End of group Sample_Appli */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __BSP_RTC_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h deleted file mode 100644 index 4244e9fa7f3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ******************************************************************************* - * @file txz_cg.h - * @brief This file provides all the functions prototypes for CG driver. - * @version V1.0.0.0 - * $Date:: 2018-04-02 19:31:41 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __CG_H -#define __CG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup CG CG - * @brief CG Driver. - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_define CG Exported Define - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group CG_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_define CG Exported Define - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group CG_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_typedef CG Exported Typedef - * @{ - */ -/** - * @brief CG member. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ -} cg_t; - -/** - * @} - */ /* End of group CG_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_functions CG Exported Functions - * @{ - */ -uint32_t cg_get_fsysm(cg_t *p_obj); -uint32_t cg_get_phyt0(cg_t *p_obj); -uint32_t cg_get_mphyt0(cg_t *p_obj); -TXZ_Result cg_ihosc_enable(cg_t *p_obj); -TXZ_Result cg_ihosc_disable(cg_t *p_obj); -/** - * @} - */ /* End of group CG_Exported_functions */ - -/** - * @} - */ /* End of group CG */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __CG_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h deleted file mode 100644 index 61fbc050717..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ******************************************************************************* - * @file txz_driver_def.h - * @brief All common macro and definition for TXZ peripheral drivers - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TXZ_DRIVER_DEF_H -#define __TXZ_DRIVER_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF - * @brief All common macro and definition for TXZ peripheral drivers - * @{ - */ - -/** @defgroup Device_Header_Included Device Header Included - * @brief Include the Device header file of a Target. - * @{ - */ -#include "TMPM4G9.h" /*!< TMPM4Gx Group Header file. */ -/** - * @} - */ /* End of group Device_Header */ - - -/** @defgroup TXZ_Exported_typedef TXZ Exported typedef - * @{ - */ -typedef enum { - TXZ_SUCCESS = 0U, - TXZ_ERROR = 1U -} TXZ_Result; - -typedef enum { - TXZ_BUSY = 0U, - TXZ_DONE = 1U -} TXZ_WorkState; - -typedef enum { - TXZ_DISABLE = 0U, - TXZ_ENABLE = 1U -} TXZ_FunctionalState; -/** - * @} - */ /* End of group TXZ_Exported_typedef */ - -/** @defgroup TXZ_Exported_macro TXZ Exported macro - * @{ - */ -#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) - -/** - * @brief To report the name of the source file and source line number where the - * assert_param error has occurred, "DEBUG" must be defined. And detailed - * definition of assert_failed() is needed to be implemented, which can be - * done, for example, in the main.c file. - */ -#ifdef DEBUG -void assert_failed(char *file, int32_t line); -#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) -#else -#define assert_param(expr) -#endif /* DEBUG */ -/** - * @} - */ /* End of group TXZ_Exported_macro */ - -/** - * @} - */ /* End of group Periph_Driver */ - -/** - * @} - */ /* End of group TXZ_DRIVER_DEF */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h deleted file mode 100644 index 4cd694b17e0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart.h - * @brief This file provides all the functions prototypes for FUART driver. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_H -#define __FUART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup FUART FUART - * @brief FUART Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_define FUART Exported Define - * @{ - */ - -/** - * @defgroup FUART_FifoMax Max Num of FIFO - * @brief Max Num of Tx/Rx Fifo. - * @{ - */ -#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */ -#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */ -/** - * @} - */ /* End of group UART_FifoMax */ - -/** - * @defgroup FUART_CTSHandshake CTS Handshake - * @brief Available CTS Handshake Macro Definisiton. - * @{ - */ -#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */ -/** - * @} - */ /* End of group FUART_CTSHandshake */ - - -/** - * @defgroup FUART_RTSHandshake RTS Handshake - * @brief Available RTS Handshake Macro Definisiton. - * @{ - */ -#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */ -/** - * @} - */ /* End of group FUART_RTSHandshake */ - -/** - * @defgroup FUART_FIFO FIFO Enable - * @brief FIFO Enable Bit Macro Definisiton. - * @{ - */ -#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */ -#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */ -/** - * @} - */ /* End of group FUART_FIFO */ - - -/** - * @defgroup FUART_StopBit Stop Bit - * @brief Stop Bit Macro Definisiton. - * @{ - */ -#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ -#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */ -/** - * @} - */ /* End of group FUART_StopBit */ - - -/** - * @defgroup FUART_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */ -/** - * @} - */ /* End of group FUART_ParityBit */ - - -/** - * @defgroup FUART_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group FUART_ParityEnable */ - -/** - * @defgroup FUART_StaticParityEnable Static Parity Enable - * @brief Enable/Disable Static Parity Macro Definisiton. - * @{ - */ -#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group FUART_ParityEnable */ - -/** - * @defgroup FUART_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */ -#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */ -#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */ -#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */ -/** - * @} - */ /* End of group FUART_DataLength */ - -/** - * @defgroup FUART_FIFO_Level FIFO Level - * @brief FIFO Level Macro Definisiton. - * @{ - */ -#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */ -#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */ -#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */ -#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */ -#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */ - -/** - * @} - */ /* End of group FUART_DataLength */ - -/** - * @defgroup FUART_TxInterrupt Tx Interrpt - * @brief Available Transmit Interrupt Macro Definisiton. - * @{ - */ -#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ -/** - * @} - */ /* End of group FUART_TxInterrupt */ - - -/** - * @defgroup FUART_RxInterrupt Rx Interrpt - * @brief Available Receive Interrupt Macro Definisiton. - * @{ - */ -#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ -/** - * @} - */ /* End of group FUART_RxInterrupt */ - - -/** - * @defgroup FUART_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -/** - * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */ -/** - * @} - */ /* End of group FUART_OVER_RUN_ErrorInterrupt */ - -/** - * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */ -/** - * @} - */ /* End of group FUART_BREAK_ErrorInterrupt */ - -/** - * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */ -/** - * @} - */ /* End of group FUART_PARITY_ErrorInterrupt */ - -/** - * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group FUART_FRAMING_ErrorInterrupt */ - -/** - * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */ -/** - * @} - */ /* End of group FUART_ErrorInterrupt */ - - -/** - * @defgroup FUART_RangeK Range K - * @brief Range of K Macro Definisiton. - * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)". - * @{ - */ -#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ -#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ -/** - * @} - */ /* End of group FUART_RangeK */ - - -/** - * @defgroup FUART_RangeN Range N - * @brief Range of N Macro Definisiton. - * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)". - * @{ - */ -#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */ -#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ -/** - * @} - */ /* End of group FUART_RangeN */ - - -/** - * @defgroup FUART_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ -/** - * @} - */ /* End of group FUART_OverrunErr */ - - -/** - * @defgroup FUART_BreakErr Break Error - * @brief Break Error Macro Definisiton. - * @{ - */ -#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */ -/** - * @} - */ /* End of group FUART_BreakErr */ - - -/** - * @defgroup FUART_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */ -/** - * @} - */ /* End of group FUART_ParityErr */ - - -/** - * @defgroup FUART_FramingErr Framing Error - * @brief Framing Error Macro Definisiton. - * @{ - */ -#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */ -/** - * @} - */ /* End of group FUART_FramingErr */ - -/** - * @defgroup FUARTxFR FUARTxFR Register - * @brief FUARTxFR Register Definition. - * @{ - */ -/* FR */ -#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */ -#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */ -#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */ -#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */ -#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */ -#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */ - -#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */ -#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */ -#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */ -#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */ -#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */ -#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */ - -#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */ -#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */ -#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */ -#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */ -#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */ -#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */ -/** - * @} - */ /* End of group FUARTxFR */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_define FUART Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_typedef FUART Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} fuart_receive_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} fuart_transmit_t; - -/*----------------------------------*/ -/** - * @brief Boudrate setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brk; /*!< Division Value K. - : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */ - uint32_t brn; /*!< Division Value N. - : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */ -} fuart_boudrate_t; - -/*----------------------------------*/ -/** - * @brief Transmit FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t inttx; /*!< Available Transmit Interrupt. - : Use @ref FUART_TxInterrupt */ - uint32_t level; /*!< Transmit Fill Level. - : Use @ref FUART_FIFO_Level */ -} fuart_tx_int_t; - -/*----------------------------------*/ -/** - * @brief Receive FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intrx; /*!< Available Receive Interrupt. - : Use @ref FUART_RxInterrupt */ - uint32_t level; /*!< Receive Fill Level. - : Use @ref FUART_FIFO_Level */ -} fuart_rx_int_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - fuart_boudrate_t boudrate; /*!< Boudrate setting. - : Use @ref fuart_boudrate_t */ - uint32_t interr; /*!< Available Error Interrupt. - : Use @ref FUART_ErrorInterrupt */ - fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting. - : Use @ref fuart_tx_int_t */ - fuart_rx_int_t rx_int; /*!< Receive Interrupt setting. - : Use @ref fuart_rx_int_t */ - uint32_t ctse; /*!< Available CTS Handshake. - : Use @ref FUART_CTSHandshake */ - uint32_t rtse; /*!< Available RTS Handshake. - : Use @ref FUART_RTSHandshake */ - uint32_t stpa; /*!< Enable/Disable Static Parity. - : Use @ref FUART_StaticParityEnable */ - uint32_t sm; /*!< Data Length. - : Use @ref FUART_DataLength */ - uint32_t fifo; /*!< Available FIFO. - : Use @ref FUART_FIFO */ - uint32_t sblen; /*!< Stop Bit. - : Use @ref FUART_StopBit */ - uint32_t even; /*!< Odd/Even Parity Bit. - : Use @ref FUART_ParityBit */ - uint32_t pe; /*!< Enable/Disable Parity Bit. - : Use @ref FUART_ParityEnable */ -} fuart_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief FUART handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */ - fuart_initial_setting_t init; /*!< Initial setting. */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - fuart_transmit_t info; /*!< Transmit Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t wp; /*!< Num of received data. */ - fuart_receive_t info; /*!< Receive Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} fuart_t; - -/** - * @} - */ /* End of group FUART_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_functions FUART Exported Functions - * @{ - */ -TXZ_Result fuart_init(fuart_t *p_obj); -TXZ_Result fuart_deinit(fuart_t *p_obj); -TXZ_Result fuart_discard_transmit(fuart_t *p_obj); -TXZ_Result fuart_discard_receive(fuart_t *p_obj); -TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info); -TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info); -void fuart_transmit_irq_handler(fuart_t *p_obj); -void fuart_receive_irq_handler(fuart_t *p_obj); -void fuart_error_irq_handler(fuart_t *p_obj); -void fuart_irq_handler(fuart_t *p_obj); -TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status); -TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error); -TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting); -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h deleted file mode 100644 index 674772d8322..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_ex.h - * @brief This file provides all the functions prototypes for FUART driver. - * @brief Extended functionality. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_EX_H -#define __FUART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "txz_fuart.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -TXZ_Result fuart_send_break(fuart_t *p_obj); -TXZ_Result fuart_stop_break(fuart_t *p_obj); -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __FUART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h deleted file mode 100644 index f94dc388510..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h +++ /dev/null @@ -1,390 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_INCLUDE_H -#define __FUART_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/** - * @defgroup FUART_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define FUART_NULL ((void *)0) /*!< Null Pointer. */ -/** - * @} - */ /* End of group FUART_NullPointer */ - -/** - * @defgroup FUART_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group FUART_ParameterResult */ - -/** - * @defgroup FUARTxDR FUARTxDR Register - * @brief FUARTxDR Register Definition. - * @{ - */ -/* DR */ -#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -/** - * @} - */ /* End of group FUARTxDR */ - -/** - * @defgroup FUARTxCR FUARTxCR Register - * @brief FUARTxCR Register Definition. - * @{ - */ -#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */ -#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */ -#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */ -#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */ -#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */ - -#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */ -#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */ -#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */ -#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */ -#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */ - -#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */ -#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */ -#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */ -#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */ -#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */ -/** - * @} - */ /* End of group FUARTxRSR */ - -/** - * @defgroup FUARTxRSR FUARTxRSR Register - * @brief FUARTxRSR Register Definition. - * @{ - */ -#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ -#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ -#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ -#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ - -#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */ -#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */ -#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */ -#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */ -/** - * @} - */ /* End of group FUARTxRSR */ - -/** - * @defgroup FUARTxECR FUARTxECR Register - * @brief FUARTxECR Register Definition. - * @{ - */ -/* ECR */ -#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ -#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ -#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ -#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ - -#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */ -#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */ -#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */ -#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */ - -/** - * @} - */ /* End of group FUARTxECR */ - -/** - * @defgroup FUARTxLCR_H FUARTxRSR Register - * @brief FUARTxLCR_H Register Definition. - * @{ - */ -#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */ - -#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */ -#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */ -/** - * @} - */ /* End of group FUARTxLCR_H */ - -/** - * @defgroup FUARTxRIS FUARTxRIS Register - * @brief FUARTxRIS Register Definition. - * @{ - */ -#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */ -#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */ -#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */ -#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */ -#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */ -#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */ -#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */ - -#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */ -#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */ -#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */ -#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */ -#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */ -#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */ -#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */ - -/** - * @} - */ /* End of group FUARTxRIS */ - -/** - * @defgroup FUARTxMIS FUARTxMIS Register - * @brief FUARTxMIS Register Definition. - * @{ - */ -#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */ -#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */ -#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */ -#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */ -#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */ -#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */ -#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */ - -#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */ -#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */ -#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */ -#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */ -#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */ -#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */ -#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */ - -/** - * @} - */ /* End of group FUARTxMIS */ - -/** - * @defgroup FUARTxICR FUARTxICR Register - * @brief FUARTxICR Register Definition. - * @{ - */ -#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */ -#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */ -#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */ -#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */ -#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */ -#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */ -#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */ - -#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */ -#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */ -#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */ -#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */ -#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */ -#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */ -#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */ - -/** - * @} - */ /* End of group FUARTxICR */ - -/** - * @defgroup FUARTxDMACR FUARTxDMACR Register - * @brief FUARTxDMACR Register Definition. - * @{ - */ -#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */ -#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */ - -#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */ -#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */ - -#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */ -#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */ -/** - * @} - */ /* End of group FUARTxDMACR */ - - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_fuctions - * @{ - */ -__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); -/*--------------------------------------------------*/ -/** - * @brief Disable FUARTxCR TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable FUARTxCR TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable FUARTxCR RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable FUARTxCR RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1; -#endif -} - - -/** - * @} - */ /* End of group FUART_Private_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h deleted file mode 100644 index fc21163d8c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h +++ /dev/null @@ -1,2406 +0,0 @@ -/** - ******************************************************************************* - * @file txz_gpio.h - * @brief This file provides all the functions prototypes for GPIO driver. - * @version V1.0.0. - * $Date:: 2017-11-09 16:44:27 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __GPIO_H -#define __GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define TMPM4G9 - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup GPIO GPIO - * @brief GPIO Driver. - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Exported_define GPIO Exported Define - * @{ - */ - - -/** - * @defgroup GPIO_Result Result - * @brief GPIO Result Macro Definition. - * @{ - */ -#define GPIO_RESULT_SUCCESS (0) /*!< Success */ -#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ -#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ -/** - * @} - */ /* End of group GPIO_Result */ - -/** - * @} - */ /* End of group GPIO_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef - * @{ - */ - -/** - * @enum gpio_pinstate_t - * @brief Pin State Reset/Set Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PIN_RESET = 0, /*!< 0: Clear */ - GPIO_PIN_SET, /*!< 1: Set */ -}gpio_pinstate_t; - -/** - * @enum gpio_pininout_t - * @brief Pin Input/Output Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PIN_INPUT = 0, /*!< 0: Input */ - GPIO_PIN_OUTPUT, /*!< 1: Output */ - GPIO_PIN_INOUT, /*!< 2: Input/Output */ - GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */ -}gpio_pininout_t; - -/** - * @enum gpio_gr_t - * @brief Port Group Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PORT_A = 0x0, /*!< 0: PA */ - GPIO_PORT_B, /*!< 1: PB */ - GPIO_PORT_C, /*!< 2: PC */ - GPIO_PORT_D, /*!< 3: PD */ - GPIO_PORT_E, /*!< 4: PE */ - GPIO_PORT_F, /*!< 5: PF */ - GPIO_PORT_G, /*!< 6: PG */ - GPIO_PORT_H, /*!< 7: PH */ - GPIO_PORT_J, /*!< 8: PJ */ - GPIO_PORT_K, /*!< 9: PK */ - GPIO_PORT_L, /*!< 10:PL */ - GPIO_PORT_M, /*!< 11: PM */ - GPIO_PORT_N, /*!< 12: PN */ - GPIO_PORT_P, /*!< 13: PP */ - GPIO_PORT_R, /*!< 14: PR */ - GPIO_PORT_T, /*!< 15: PT */ - GPIO_PORT_U, /*!< 16: PU */ - GPIO_PORT_V, /*!< 17: PV */ - GPIO_PORT_W, /*!< 18: PW */ - GPIO_PORT_Y, /*!< 19: PY */ - GPIO_GROUP_Max /*!< Max Number */ -}gpio_gr_t; - -/** - * @enum gpio_num_t - * @brief Port Number Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ - GPIO_PORT_1, /*!< 1: Port1 */ - GPIO_PORT_2, /*!< 2: Port2 */ - GPIO_PORT_3, /*!< 3: Port3 */ - GPIO_PORT_4, /*!< 4: Port4 */ - GPIO_PORT_5, /*!< 5: Port5 */ - GPIO_PORT_6, /*!< 6: Port6 */ - GPIO_PORT_7, /*!< 7: Port7 */ - GPIO_PORT_Max /*!< Max Number */ -}gpio_num_t; - -/** - * @enum gpio_fr_t - * @brief Port Function Number Enumerated Type Definition. - */ -typedef enum -{ - GPIO_FR_1 = 1, /*!< 1: PxFR1 */ - GPIO_FR_2, /*!< 2: PxFR2 */ - GPIO_FR_3, /*!< 3: PxFR3 */ - GPIO_FR_4, /*!< 4: PxFR4 */ - GPIO_FR_5, /*!< 5: PxFR5 */ - GPIO_FR_6, /*!< 6: PxFR6 */ - GPIO_FR_7, /*!< 7: PxFR7 */ - GPIO_FR_NA, /*!< 8: N/A */ - GPIO_FR_Max, /*!< Max Number */ -}gpio_fr_t; - -/** - * @enum gpio_mode_t - * @brief Port Mode Enumerated Type Definition. - */ -typedef enum -{ - GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ - GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ - GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ - GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ - GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ - GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ - GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ - GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ - GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */ - GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ - GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ - GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ - GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ -}gpio_mode_t; - -/** - * @enum gpio_pa0_func_t - * @brief PortA0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA0_INT02a = 0, /*!< 0: INT02a */ - GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */ - GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */ - GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */ - GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */ - GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */ - GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */ -}gpio_pa0_func_t; - -/** - * @enum gpio_pa1_func_t - * @brief PortA1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */ - GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */ - GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */ - GPIO_PA1_TSPI0CLK = GPIO_FR_7, /*!< PAFR7: TSPI0CLK */ -}gpio_pa1_func_t; - -/** - * @enum gpio_pa2_func_t - * @brief PortA2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */ - GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */ - GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */ -}gpio_pa2_func_t; - - /** - * @enum gpio_pa3_func_t - * @brief PortA3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */ - GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */ - GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */ - GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */ - GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */ - GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR6: TSPI2CS1 */ -}gpio_pa3_func_t; - - /** - * @enum gpio_pa4_func_t - * @brief PortA4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */ - GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */ - GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */ - GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */ - GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */ - GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */ -}gpio_pa4_func_t; - -/** - * @enum gpio_pa5_func_t - * @brief PortA5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */ - GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */ - GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */ - GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */ - GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */ -}gpio_pa5_func_t; - -/** - * @enum gpio_pa6_func_t - * @brief PortA6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */ - GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */ - GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */ - GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */ -}gpio_pa6_func_t; - - -/** - * @enum gpio_pa7_func_t - * @brief PortA6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA7_INT03a = 0, /*!< 0: INT03a */ - GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */ - GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */ - GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */ - GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */ - GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */ - GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */ -}gpio_pa7_func_t; - - - -/** - * @enum gpio_pb0_func_t - * @brief PortB0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB0_INT04a = 0, /*!< 0: INT04a */ - GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */ - GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */ - GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */ - GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */ -}gpio_pb0_func_t; - -/** - * @enum gpio_pb1_func_t - * @brief PortB1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB1_INT05a = 0, /*!< 0: INT05a */ - GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */ - GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */ - GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */ - GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */ - GPIO_PB1_HDMAREQB = GPIO_FR_6, /*!< PBFR6: HDMAREQB */ -}gpio_pb1_func_t; - -/** - * @enum gpio_pb2_func_t - * @brief PortB2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */ - GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */ - GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */ -}gpio_pb2_func_t; - - /** - * @enum gpio_pb3_func_t - * @brief PortB3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */ - GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */ -}gpio_pb3_func_t; - - /** - * @enum gpio_pb4_func_t - * @brief PortB4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB4_EA12 = GPIO_FR_1, /*!< PBFR1: EA12 */ - GPIO_PB4_T32A03OUTA = GPIO_FR_3, /*!< PBFR3: T32A03OUTA */ - GPIO_PB4_T32A03OUTC = GPIO_FR_5, /*!< PBFR5: T32A03OUTC */ -}gpio_pb4_func_t; - -/** - * @enum gpio_pb5_func_t - * @brief PortB5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB5_EA13 = GPIO_FR_1, /*!< PBFR1: EA13 */ - GPIO_PB5_T32A03OUTB = GPIO_FR_3, /*!< PBFR3: T32A03OUTB */ -}gpio_pb5_func_t; - -/** - * @enum gpio_pb6_func_t - * @brief PortB6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB6_INT06a = 0, /*!< 0: INT06a */ - GPIO_PB6_EA14 = GPIO_FR_1, /*!< PBFR1: EA14 */ - GPIO_PB6_T32A03INB1 = GPIO_FR_2, /*!< PBFR2: T32A03INB1 */ - GPIO_PB6_T32A03INA0 = GPIO_FR_3, /*!< PBFR3: T32A03INA0 */ - GPIO_PB6_T32A03INC0 = GPIO_FR_5, /*!< PBFR5: T32A03INC0 */ -}gpio_pb6_func_t; - -/** - * @enum gpio_pb7_func_t - * @brief PortB7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB7_INT07a = 0, /*!< 0: INT07a */ - GPIO_PB7_EA15 = GPIO_FR_1, /*!< PBFR1: EA15 */ - GPIO_PB7_T32A03INA1 = GPIO_FR_2, /*!< PBFR2: T32A03INA1 */ - GPIO_PB7_T32A03INB0 = GPIO_FR_3, /*!< PBFR3: T32A03INB0 */ - GPIO_PB7_T32A03INC1 = GPIO_FR_5, /*!< PBFR5: T32A03INC1 */ -}gpio_pb7_func_t; - - -/** - * @enum gpio_pc0_func_t - * @brief PortC0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC0_INT12a = 0, /*!< 0: INT12a */ - GPIO_PC0_EA16 = GPIO_FR_1, /*!< PCFR1: EA16 */ - GPIO_PC0_T32A08INA0 = GPIO_FR_3, /*!< PCFR3: T32A08INA0 */ - GPIO_PC0_T32A08INC0 = GPIO_FR_5, /*!< PCFR5: T32A08INC0 */ -}gpio_pc0_func_t; - -/** - * @enum gpio_pc1_func_t - * @brief PortC1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC1_INT13a = 0, /*!< 0: INT13a */ - GPIO_PC1_EA17 = GPIO_FR_1, /*!< PCFR1: EA17 */ - GPIO_PC1_T32A08INB0 = GPIO_FR_3, /*!< PCFR3: T32A08INB0 */ - GPIO_PC1_T32A08INC1 = GPIO_FR_5, /*!< PCFR5: T32A08INC1 */ -}gpio_pc1_func_t; - -/** - * @enum gpio_pc2_func_t - * @brief PortC2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC2_EA18 = GPIO_FR_1, /*!< PCFR1: UT4TXDB */ - GPIO_PC2_T32A08OUTA = GPIO_FR_3, /*!< PCFR3: T32A08OUTA */ - GPIO_PC2_T32A08OUTC = GPIO_FR_5, /*!< PCFR5: T32A08OUTC */ -}gpio_pc2_func_t; - - /** - * @enum gpio_pc3_func_t - * @brief PortC3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC3_EA19 = GPIO_FR_1, /*!< PCFR1: EA19 */ - GPIO_PC3_T32A08OUTB = GPIO_FR_3, /*!< PCFR3: T32A08OUTB */ -}gpio_pc3_func_t; - - /** - * @enum gpio_pc4_func_t - * @brief PortC4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */ - GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */ - GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */ -}gpio_pc4_func_t; - -/** - * @enum gpio_pc5_func_t - * @brief PortC5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */ - GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */ -}gpio_pc5_func_t; - -/** - * @enum gpio_pc6_func_t - * @brief PortC6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC6_INT14a = 0, /*!< 0: INT14a */ - GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */ -}gpio_pc6_func_t; - -/** - * @enum gpio_pc7_func_t - * @brief PortC7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC7_INT15a = 0, /*!< 0: INT15a */ - GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */ -}gpio_pc7_func_t; - -/** - * @enum gpio_pd0_func_t - * @brief PortD0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */ - GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */ - GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */ - GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */ - GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */ - GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */ - GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */ -}gpio_pd0_func_t; - -/** - * @enum gpio_pd1_func_t - * @brief PortD1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */ - GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */ - GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */ - GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */ - GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */ - GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */ -}gpio_pd1_func_t; - -/** - * @enum gpio_pd2_func_t - * @brief PortD2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */ - GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */ - GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */ - GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */ - GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */ -}gpio_pd2_func_t; - - /** - * @enum gpio_pd3_func_t - * @brief PortD3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */ - GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */ - GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */ - GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */ -}gpio_pd3_func_t; - -/** - * @enum gpio_pd4_func_t - * @brief PortD4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */ - GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */ - GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */ - GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ -}gpio_pd4_func_t; - -/** - * @enum gpio_pd5_func_t - * @brief PortD5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */ - GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */ - GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ -}gpio_pd5_func_t; - -/** - * @enum gpio_pd6_func_t - * @brief PortD6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */ - GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */ - GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */ - GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */ - GPIO_PD6_EMG_N = GPIO_FR_7, /*!< PCFR7: EMG_N */ -}gpio_pd6_func_t; - -/** - * @enum gpio_pd7_func_t - * @brief PortD7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */ - GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */ - GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */ - GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */ - GPIO_PD7_OVV0_N = GPIO_FR_7, /*!< PCFR7: OVV0_N */ -}gpio_pd7_func_t; - -/** - * @enum gpio_pe0_func_t - * @brief PortE0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */ - GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */ - GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */ - GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */ - GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */ - GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */ -}gpio_pe0_func_t; - -/** - * @enum gpio_pe1_func_t - * @brief PortE1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */ - GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */ - GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */ - GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */ - GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */ -}gpio_pe1_func_t; - -/** - * @enum gpio_pe2_func_t - * @brief PortE2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */ - GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */ - GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */ - GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */ - GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */ -}gpio_pe2_func_t; - - /** - * @enum gpio_pe3_func_t - * @brief PortE3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */ - GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */ - GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */ - GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */ - GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */ -}gpio_pe3_func_t; - - /** - * @enum gpio_pe4_func_t - * @brief PortE4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */ - GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */ - GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */ - GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */ - GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */ -}gpio_pe4_func_t; - -/** - * @enum gpio_pe5_func_t - * @brief PortE5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */ - GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */ - GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */ - GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */ - GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */ -}gpio_pe5_func_t; - -/** - * @enum gpio_pe6_func_t - * @brief PortE6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */ - GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */ - GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */ - GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */ - GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */ -}gpio_pe6_func_t; - -/** - * @enum gpio_pe7_func_t - * @brief PortE7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */ - GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */ - GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */ - GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */ - GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */ - GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */ -}gpio_pe7_func_t; - -/** - * @enum gpio_pf0_func_t - * @brief PortF0 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF0_INT04b = 0, /*!< 0: INT04b */ - GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */ -}gpio_pf0_func_t; - -/** - * @enum gpio_pf1_func_t - * @brief PortF1 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */ -}gpio_pf1_func_t; - -/** - * @enum gpio_pf2_func_t - * @brief PortF2 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */ -}gpio_pf2_func_t; - - /** - * @enum gpio_pf3_func_t - * @brief PortF3 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */ -}gpio_pf3_func_t; - - /** - * @enum gpio_pf4_func_t - * @brief PortF4 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */ -}gpio_pf4_func_t; - - /** - * @enum gpio_pf5_func_t - * @brief PortF5 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */ -}gpio_pf5_func_t; - - /** - * @enum gpio_pf6_func_t - * @brief PortF6 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */ -}gpio_pf6_func_t; - - /** - * @enum gpio_pf7_func_t - * @brief PortF7 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF7_INT05b = 0, /*!< 0: INT05b */ - GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */ -}gpio_pf7_func_t; - -/** - * @enum gpio_pg0_func_t - * @brief PortG0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG0_INT08a = 0, /*!< 0: INT08a */ - GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */ - GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */ - GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */ -}gpio_pg0_func_t; - -/** - * @enum gpio_pg1_func_t - * @brief PortG1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG1_INT09a = 0, /*!< 0: INT09a */ - GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */ - GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */ - GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */ -}gpio_pg1_func_t; - -/** - * @enum gpio_pg2_func_t - * @brief PortG2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */ - GPIO_PG2_RTCALARM = GPIO_FR_4, /*!< PCFR4: RTCALARM */ - GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */ - GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */ -}gpio_pg2_func_t; - -/** - * @enum gpio_pg3_func_t - * @brief PortG3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */ - GPIO_PG3_TRGIN = GPIO_FR_4, /*!< PCFR4: TRGIN */ - GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */ - GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */ -}gpio_pg3_func_t; - -/** - * @enum gpio_pg4_func_t - * @brief PortG4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ - GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */ - GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */ - GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */ -}gpio_pg4_func_t; - -/** - * @enum gpio_pg5_func_t - * @brief PortG5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ - GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */ - GPIO_PG5_FUT0SI_SIRIN = GPIO_FR_4, /*!< PCFR4: FUT0SI_SIRIN */ - GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */ - GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */ -}gpio_pg5_func_t; - -/** - * @enum gpio_pg6_func_t - * @brief PortG6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */ - GPIO_PG6_NBD0CLK = GPIO_FR_4, /*!< PCFR4: NBD0CLK */ - GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */ -}gpio_pg6_func_t; - -/** - * @enum gpio_pg7_func_t - * @brief PortG7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */ - GPIO_PG7_NBD0DATA0 = GPIO_FR_4, /*!< PCFR4: NBD0DATA0 */ - GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */ -}gpio_pg7_func_t; - -/** - * @enum gpio_ph0_func_t - * @brief PortH0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */ - GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */ - GPIO_PH0_NBD0DATA1 = GPIO_FR_4, /*!< PCFR4: NBD0DATA1 */ - GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */ -}gpio_ph0_func_t; - -/** - * @enum gpio_ph1_func_t - * @brief PortH1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */ - GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */ - GPIO_PH1_NBD0DATA2 = GPIO_FR_4, /*!< PCFR4: NBD0DATA2 */ - GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */ -}gpio_ph1_func_t; - -/** - * @enum gpio_ph2_func_t - * @brief PortH2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */ - GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */ - GPIO_PH2_NBD0DATA3 = GPIO_FR_4, /*!< PCFR4: NBD0DATA3 */ - GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */ -}gpio_ph2_func_t; - - /** - * @enum gpio_ph3_func_t - * @brief PortH3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */ - GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */ - GPIO_PH3_NBD0SYNC = GPIO_FR_4, /*!< PCFR4: NBD0SYNC */ - GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */ -}gpio_ph3_func_t; - - /** - * @enum gpio_ph4_func_t - * @brief PortH4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */ - GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */ - GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */ -}gpio_ph4_func_t; - - /** - * @enum gpio_ph5_func_t - * @brief PortH5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */ - GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */ - GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */ -}gpio_ph5_func_t; - - /** - * @enum gpio_ph6_func_t - * @brief PortH6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */ - GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */ - GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */ -}gpio_ph6_func_t; - - /** - * @enum gpio_ph7_func_t - * @brief PortH7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */ - GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */ - GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */ -}gpio_ph7_func_t; - -/** - * @enum gpio_pj0_func_t - * @brief PortJ0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */ - GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */ -}gpio_pj0_func_t; - -/** - * @enum gpio_pj1_func_t - * @brief PortJ1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */ - GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */ -}gpio_pj1_func_t; - -/** - * @enum gpio_pj2_func_t - * @brief PortJ2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */ - GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */ - GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */ -}gpio_pj2_func_t; - - /** - * @enum gpio_pj3_func_t - * @brief PortJ3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */ - GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */ - GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */ -}gpio_pj3_func_t; - - /** - * @enum gpio_pj4_func_t - * @brief PortJ4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */ - GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */ - GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */ -}gpio_pj4_func_t; - -/** - * @enum gpio_pj5_func_t - * @brief PortJ5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */ - GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */ - GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */ -}gpio_pj5_func_t; - -/** - * @enum gpio_pj6_func_t - * @brief PortJ6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */ - GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */ -}gpio_pj6_func_t; - -/** - * @enum gpio_pj7_func_t - * @brief PortJ7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */ - GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */ -}gpio_pj7_func_t; - -/** - * @enum gpio_pk0_func_t - * @brief PortK0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK0_INT10a = 0, /*!< 0: INT10a */ - GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */ - GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */ - GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */ - GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */ -}gpio_pk0_func_t; - -/** - * @enum gpio_pk1_func_t - * @brief PortK1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK1_INT11a = 0, /*!< 0: INT11a */ - GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */ - GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */ - GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */ - GPIO_PK1_HDMAREQA = GPIO_FR_4, /*!< PKFR4: HDMAREQA */ -}gpio_pk1_func_t; - -/** - * @enum gpio_pk2_func_t - * @brief PortK2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */ - GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */ -}gpio_pk2_func_t; - - /** - * @enum gpio_pk3_func_t - * @brief PortK3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */ - GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */ -}gpio_pk3_func_t; - - /** - * @enum gpio_pk4_func_t - * @brief PortK4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */ - GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */ - GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */ -}gpio_pk4_func_t; - -/** - * @enum gpio_pk5_func_t - * @brief PortK5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */ - GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */ - GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */ -}gpio_pk5_func_t; - -/** - * @enum gpio_pk6_func_t - * @brief PortK6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */ - GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */ - GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */ - GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */ - GPIO_PK6_SMI0SCK = GPIO_FR_6, /*!< PKFR6: SMI0SCK */ -}gpio_pk6_func_t; - -/** - * @enum gpio_pk7_func_t - * @brief PortK7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK7_INT00a = 0, /*!< 0: INT00a */ - GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */ - GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */ - GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */ - GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */ - GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */ -}gpio_pk7_func_t; - -/** - * @enum gpio_pl0_func_t - * @brief PortL0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL0_INT01a = 0, /*!< 0: INT01a */ - GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */ - GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */ - GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */ - GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */ -}gpio_pl0_func_t; - -/** - * @enum gpio_pl1_func_t - * @brief PortL1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL1_TPI1SCK = GPIO_FR_7, /*!< PLFR7: TPI1SCK */ -}gpio_pl1_func_t; - -/** - * @enum gpio_pl2_func_t - * @brief PortL2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */ -}gpio_pl2_func_t; - - /** - * @enum gpio_pl3_func_t - * @brief PortL3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */ - GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */ - GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */ - GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */ -}gpio_pl3_func_t; - - /** - * @enum gpio_pl4_func_t - * @brief PortL4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL4_INT12b = 0, /*!< 0: IN112b */ - GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */ - GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */ -}gpio_pl4_func_t; - -/** - * @enum gpio_pl5_func_t - * @brief PortL5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL5_INT13b = 0, /*!< 0: INT13b */ - GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */ -}gpio_pl5_func_t; - -/** - * @enum gpio_pl6_func_t - * @brief PortL6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL6_INT03b = 0, /*!< 0: INT03b */ - GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */ - GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */ -}gpio_pl6_func_t; - -/** - * @enum gpio_pl7_func_t - * @brief PortL7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL7_TRGIN = GPIO_FR_1, /*!< PLFR1: TRGIN */ - GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */ -}gpio_pl7_func_t; - -/** - * @enum gpio_pm0_func_t - * @brief PortM0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */ - GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */ - GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */ - GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */ -}gpio_pm0_func_t; - -/** - * @enum gpio_pm1_func_t - * @brief PortM1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */ - GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */ - GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */ - GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */ -}gpio_pm1_func_t; - -/** - * @enum gpio_pm2_func_t - * @brief PortM2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */ - GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */ - GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */ - GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */ - GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */ -}gpio_pm2_func_t; - - /** - * @enum gpio_pm3_func_t - * @brief PortM3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM3_INT14b = 0, /*!< 0: INT14b */ - GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */ - GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */ - GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */ - GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */ - GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */ -}gpio_pm3_func_t; - - /** - * @enum gpio_pm4_func_t - * @brief PortM4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM4_INT15b = 0, /*!< 0: INT15b */ - GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */ - GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */ - GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */ - GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */ -}gpio_pm4_func_t; - -/** - * @enum gpio_pm5_func_t - * @brief PortM5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */ - GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */ - GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */ - GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */ -}gpio_pm5_func_t; - -/** - * @enum gpio_pm6_func_t - * @brief PortM6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */ - GPIO_PM6_T32A76OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */ - GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */ - GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */ - GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */ - GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */ -}gpio_pm6_func_t; - -/** - * @enum gpio_pm7_func_t - * @brief PortM7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */ - GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */ - GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */ - GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */ - GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */ -}gpio_pm7_func_t; - -/** - * @enum gpio_pn0_func_t - * @brief PortN0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */ -}gpio_pn0_func_t; - -/** - * @enum gpio_pn1_func_t - * @brief PortN1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */ -}gpio_pn1_func_t; - -/** - * @enum gpio_pn2_func_t - * @brief PortN2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */ -}gpio_pn2_func_t; - -/** - * @enum gpio_pn3_func_t - * @brief PortN3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */ -}gpio_pn3_func_t; - - /** - * @enum gpio_pn4_func_t - * @brief PortN4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */ -}gpio_pn4_func_t; - -/** - * @enum gpio_pn5_func_t - * @brief PortN5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */ -}gpio_pn5_func_t; - -/** - * @enum gpio_pn6_func_t - * @brief PortN6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */ -}gpio_pn6_func_t; - -/** - * @enum gpio_pn7_func_t - * @brief PortN7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */ -}gpio_pn7_func_t; - -/** - * @enum gpio_pp0_func_t - * @brief PortP0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */ - GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */ - GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */ - GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */ -}gpio_pp0_func_t; - -/** - * @enum gpio_pp1_func_t - * @brief PortP1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */ - GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */ - GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */ - GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */ -}gpio_pp1_func_t; - -/** - * @enum gpio_pp2_func_t - * @brief PortP2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */ - GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */ - GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */ - GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */ -}gpio_pp2_func_t; - - /** - * @enum gpio_pp3_func_t - * @brief PortP3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */ - GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */ - GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */ - GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */ -}gpio_pp3_func_t; - - /** - * @enum gpio_pp4_func_t - * @brief PortP4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */ - GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */ - GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */ - GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */ -}gpio_pp4_func_t; - - /** - * @enum gpio_pp5_func_t - * @brief PortP5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */ - GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */ - GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */ - GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */ -}gpio_pp5_func_t; - -/** - * @enum gpio_pp6_func_t - * @brief PortP6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */ - GPIO_PP6_INT10b = 0, /*!< 0: INT10b */ - GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */ - GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */ - GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */ -}gpio_pp6_func_t; - - /** - * @enum gpio_pp7_func_t - * @brief PortP7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */ - GPIO_PP7_INT11b = 0, /*!< 0: INT11b */ - GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */ - GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */ - GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */ -}gpio_pp7_func_t; - -/** - * @enum gpio_pr0_func_t - * @brief PortR0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */ - GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */ - GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */ -}gpio_pr0_func_t; - -/** - * @enum gpio_pr1_func_t - * @brief PortR1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */ - GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */ - GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */ -}gpio_pr1_func_t; - -/** - * @enum gpio_pr2_func_t - * @brief PortR2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */ - GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */ - GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */ -}gpio_pr2_func_t; - -/** - * @enum gpio_pr3_func_t - * @brief PortR3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */ - GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */ - GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */ -}gpio_pr3_func_t; - -/** - * @enum gpio_pr4_func_t - * @brief PortR4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */ - GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */ - GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */ -}gpio_pr4_func_t; - -/** - * @enum gpio_pr5_func_t - * @brief PortR5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */ - GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */ - GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */ -}gpio_pr5_func_t; - -/** - * @enum gpio_pr6_func_t - * @brief PortR6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */ - GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */ - GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */ -}gpio_pr6_func_t; - -/** - * @enum gpio_pr7_func_t - * @brief PortR7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */ - GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */ - GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */ -}gpio_pr7_func_t; - - -/** - * @enum gpio_pt0_func_t - * @brief PortT0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */ -}gpio_pt0_func_t; - -/** - * @enum gpio_pt1_func_t - * @brief PortT1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */ -}gpio_pt1_func_t; - -/** - * @enum gpio_pt2_func_t - * @brief PortT2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */ -}gpio_pt2_func_t; - -/** - * @enum gpio_pt3_func_t - * @brief PortT3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT3_INT00b = 0, /*!< 0: INT00b */ - GPIO_PT3_RTCCLK = GPIO_FR_1, /*!< PTFR1: RTCCLK */ - GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */ - GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */ - GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */ - GPIO_PT3_MDMAREQA = GPIO_FR_6, /*!< PTFR6: MDMAREQA */ -}gpio_pt3_func_t; - -/** - * @enum gpio_pt4_func_t - * @brief PortT4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT4_INT01b = 0, /*!< 0: INT01b */ - GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */ -}gpio_pt4_func_t; - -/** - * @enum gpio_pt5_func_t - * @brief PortT5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT5_INT02b = 0, /*!< 0: INT02b */ - GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */ -}gpio_pt5_func_t; - -/** - * @enum gpio_pu0_func_t - * @brief PortU0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */ - GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */ - GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */ -}gpio_pu0_func_t; - -/** - * @enum gpio_pu1_func_t - * @brief PortU1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU1_T32A12OUTB = GPIO_FR_2, /*!< PUFR2: T32A12OUTB */ - GPIO_PU1_UT4RXD = GPIO_FR_7, /*!< PUFR7: UT4RXD */ -}gpio_pu1_func_t; - -/** - * @enum gpio_pu2_func_t - * @brief PortU2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU2_INT06b = 0, /*!< 0: INT06b */ - GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */ - GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */ - GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */ -}gpio_pu2_func_t; - -/** - * @enum gpio_pu3_func_t - * @brief PortU3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU3_INT07b = 0, /*!< 0: INT07b */ - GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */ - GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */ - GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */ -}gpio_pu3_func_t; - -/** - * @enum gpio_pu4_func_t - * @brief PortU4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU4_INT08b = 0, /*!< 0: INT08b */ - GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */ - GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */ - GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */ -}gpio_pu4_func_t; - -/** - * @enum gpio_pu5_func_t - * @brief PortU5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU5_INT09b = 0, /*!< 0: INT09b */ - GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */ - GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */ - GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */ -}gpio_pu5_func_t; - -/** - * @enum gpio_pu6_func_t - * @brief PortU6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */ - GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */ - GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */ -}gpio_pu6_func_t; - -/** - * @enum gpio_pu7_func_t - * @brief PortU7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */ - GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */ -}gpio_pu7_func_t; - -/** - * @enum gpio_pv0_func_t - * @brief PortV0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */ - GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */ - GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */ - GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */ - GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */ - GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */ -}gpio_pv0_func_t; - -/** - * @enum gpio_pv1_func_t - * @brief PortV1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */ - GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */ - GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */ - GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */ - GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */ - GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */ -}gpio_pv1_func_t; - -/** - * @enum gpio_pv2_func_t - * @brief PortV2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */ - GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */ - GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */ - GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */ - GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */ - GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */ -}gpio_pv2_func_t; - -/** - * @enum gpio_pv3_func_t - * @brief PortV3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */ - GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */ - GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */ - GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */ - GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */ -}gpio_pv3_func_t; - -/** - * @enum gpio_pv4_func_t - * @brief PortV4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */ - GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */ - GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */ - GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */ - GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */ -}gpio_pv4_func_t; - -/** - * @enum gpio_pv5_func_t - * @brief PortV5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */ - GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */ - GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */ - GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */ - GPIO_PV5_I2CSDA = GPIO_FR_6, /*!< PVFR6: I2CSDA */ - GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */ -}gpio_pv5_func_t; - -/** - * @enum gpio_pv6_func_t - * @brief PortV6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */ - GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */ - GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */ - GPIO_PV6_EMG0_N = GPIO_FR_5, /*!< PVFR5: EMG0_N */ - GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */ -}gpio_pv6_func_t; - -/** - * @enum gpio_pv7_func_t - * @brief PortV7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */ - GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */ - GPIO_PV7_OVV0_N = GPIO_FR_5, /*!< PVFR5: OVV0_N */ - GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */ - GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */ -}gpio_pv7_func_t; - -/** - * @enum gpio_pw0_func_t - * @brief PortW0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */ - GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */ - GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */ -}gpio_pw0_func_t; - -/** - * @enum gpio_pw1_func_t - * @brief PortW1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */ - GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */ - GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */ -}gpio_pw1_func_t; - -/** - * @enum gpio_pw2_func_t - * @brief PortW2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */ - GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */ - GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */ -}gpio_pw2_func_t; - -/** - * @enum gpio_pw3_func_t - * @brief PortW3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */ - GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */ -}gpio_pw3_func_t; - -/** - * @enum gpio_pw4_func_t - * @brief PortW4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */ - GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */ - GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */ - GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */ -}gpio_pw4_func_t; - -/** - * @enum gpio_pw5_func_t - * @brief PortW5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */ - GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */ - GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */ -}gpio_pw5_func_t; - -/** - * @enum gpio_pw6_func_t - * @brief PortW6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */ - GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */ - GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */ -}gpio_pw6_func_t; - -/** - * @enum gpio_pw7_func_t - * @brief PortW7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */ - GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */ - GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */ - GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */ -}gpio_pw7_func_t; - -/** - * @enum gpio_py0_func_t - * @brief PortY0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */ -}gpio_py0_func_t; - -/** - * @enum gpio_py1_func_t - * @brief PortY1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */ -}gpio_py1_func_t; - -/** - * @enum gpio_py2_func_t - * @brief PortY2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */ -}gpio_py2_func_t; - -/** - * @enum gpio_py3_func_t - * @brief PortY3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */ -}gpio_py3_func_t; - -/** - * @enum gpio_py4_func_t - * @brief PortY4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */ - GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */ -}gpio_py4_func_t; - -/** - * @} - */ /* End of group GPIO_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief GPIO handle structure definenition. -*/ -/*----------------------------------*/ -#if defined(TMPM4G6) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G9 */ - -/** - * @} - */ /* End of group GPIO_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Exported_functions GPIO Exported Functions - * @{ - */ -TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); -TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); -TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); -TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); -TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout); -TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); -TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); - -/** - * @} - */ /* End of group GPIO_Exported_functions */ - -/** - * @} - */ /* End of group GPIO */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __GPIO_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h deleted file mode 100644 index 0828e9f586e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ******************************************************************************* - * @file txz_hal.h - * @brief This file provides all the functions prototypes for driver common part. - * @version V1.0.0.0 - * $Date:: 2017-08-09 11:01:04 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __HAL_H -#define __HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup HAL HAL - * @brief HAL Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_macro HAL Exported Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_define HAL Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_define HAL Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_typedef HAL Exported Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_functions HAL Exported Functions - * @{ - */ - -void hal_inc_tick(void); -uint32_t hal_get_tick(void); - - -/** - * @} - */ /* End of group HAL_Exported_functions */ - -/** - * @} - */ /* End of group HAL */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __HAL_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h deleted file mode 100644 index 5150ea196c8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h +++ /dev/null @@ -1,843 +0,0 @@ -/** - ******************************************************************************* - * @file txz_i2c.h - * @brief This file provides all the functions prototypes for I2C Class. - * @version V1.0.0.4 - * $Date:: 2016-11-24 00:00:00 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __I2C_H -#define __I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -#ifdef DEBUG -/** - * @name I2C_NULL Pointer - * @brief NULL Pointer. - * @{ - */ -#define I2C_NULL ((void *)0) -/** - * @} - */ /* End of name I2C_NULL Pointer */ -#endif - -/** - * @name I2CxST Macro Definition. - * @brief I2CxST Register Macro Definition. - * @{ - */ -#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ -#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ -#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ -#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ -#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ -/** - * @} - */ /* End of name I2CxST Macro Definition */ - -/** - * @name I2CxCR1 Macro Definition. - * @brief I2CxCR1 Register Macro Definition. - * @{ - */ -#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ -#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ -#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ - -/** - * @} - */ /* End of name I2CxCR1 Macro Definition */ - -/** - * @name I2CxDBR Macro Definition. - * @brief I2CxDBR Register Macro Definition. - * @{ - */ -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ -/** - * @} - */ /* End of name I2CxDBR Macro Definition */ - - -/** - * @name I2CxCR2 Macro Definition. - * @brief I2CxCR2 Register Macro Definition. - * @{ - */ -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ -#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ -#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ - -/** - * @} - */ /* End of name I2CxCR2 Macro Definition */ - -/** - * @name I2CxSR Macro Definition. - * @brief I2CxSR Register Macro Definition. - * @{ - */ -#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ -#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ -#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ -#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ -#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ -#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ -#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ -#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ -/** - * @} - */ /* End of name I2CxSR Macro Definition */ - -/** - * @name I2CxPRS Macro Definition. - * @brief I2CxPRS Register Macro Definition. - * @{ - */ -#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ -/** - * @} - */ /* End of name I2CxPRS Macro Definition */ - -/** - * @name I2CxIE Macro Definition. - * @brief I2CxIE Register Macro Definition. - * @{ - */ -#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ -#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ -#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ -#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ -#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ - -/** - * @} - */ /* End of name I2CxIE Macro Definition */ - - -/** - * @name I2CxOP Macro Definition. - * @brief I2CxOP Register Macro Definition. - * @{ - */ -#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ -#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ -#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ -#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */ -#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ -#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ -#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ -#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ -#ifndef I2C_MULTI_MASTER - #define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ -#else - #define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ -#endif -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ -/** - * @} - */ /* End of name I2CxOP Macro Definition */ - -/** - * @name I2CxAR Macro Definition. - * @brief I2CxAR Register Macro Definition. - * @{ - */ -#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ -#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ -#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ - -/** - * @} - */ /* End of name I2CxAR Macro Definition */ - - -/** - * @name I2CxPM Macro Definition. - * @brief I2CxPM Register Macro Definition. - * @{ - */ -#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ -/** - * @} - */ /* End of name I2CxPM Macro Definition */ - -/** - * @name I2CxWUPCR_INT Macro Definition. - * @brief I2CxWUPCR_INT Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ -#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ -/** - * @} - */ /* End of name I2CxWUPCR_INT Macro Definition */ - -/** - * @name I2CxWUPCR_RST Macro Definition. - * @brief I2CxWUPCR_RST Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ -#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ -/** - * @} - */ /* End of name I2CxWUPCR_RST Macro Definition */ - - -/** - * @name I2CxWUPCR_ACK Macro Definition. - * @brief I2CxWUPCR_ACK Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ -#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ -/** - * @} - */ /* End of name I2CxWUPCR_RST Macro Definition */ -/** - * @} - */ /* End of group UTILITIES_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t sck; /*!< Select internal SCL output clock frequency. */ - uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ -} I2C_clock_setting_t; - -/*----------------------------------*/ -/** - * @brief Wakeup Control setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ - uint32_t ack; /*!< Select ACK output. */ - uint32_t reset; /*!< I2C BUS Rest. */ - uint32_t intend; /*!< Interrupt release. */ -} I2CS_wup_setting_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2C_clock_setting_t clock; /*!< Serial clock setting. */ -} I2C_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ -} I2CS_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief I2C handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ - I2C_initial_setting_t init; /*!< Initial setting. */ -} I2C_t; -#if defined(I2CSxWUP_EN) -/*----------------------------------*/ -/** - * @brief I2CS handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ - I2CS_initial_setting_t init; /*!< Initial setting. */ -} I2CS_t; -#endif -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -__STATIC_INLINE void I2C_reset(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); -__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); -__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); -__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); -__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); -__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); -__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); -__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); -__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); -__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); -__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); -__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); -__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); - -/*--------------------------------------------------*/ -/** - * @brief I2C software reset. - * @param p_obj :I2C object. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_reset(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; - p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; - } -#else - p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; - p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief I2C bus port high - * @param p_obj :I2C object. - * @retval true :SDA and SCL Port High. - * @retval false :Bus Error. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); - } - return (0); -#else - return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Generate stop condition. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; - } -#else - p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Read from Data buffer - * @param p_obj :I2C object. - * @retval result :Read data. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); - } - return (0); -#else - return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Write to Data buffer. - * @param p_obj :I2C object. - * @param data :Write data. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); - } -#else - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return restart condition - * @param p_obj :I2C object. - * @retval true :Restart Detected. - * @retval false :Restart Non-Detected. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - __IO uint32_t opreg = p_obj->p_instance->OP; - p_obj->p_instance->OP &= ~I2CxOP_RSTA; - return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); - } - return (0); -#else - __IO uint32_t opreg = p_obj->p_instance->OP; - p_obj->p_instance->OP &= ~I2CxOP_RSTA; - return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Set Ack condition - * @param p_obj :I2C object. - * @param nack :1 NACK, 0 ACK. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - if (nack) - { - p_obj->p_instance->OP |= I2CxOP_MFACK; - } - else - { - p_obj->p_instance->OP &= ~I2CxOP_MFACK; - } - } -#else - if (nack) - { - p_obj->p_instance->OP |= I2CxOP_MFACK; - } - else - { - p_obj->p_instance->OP &= ~I2CxOP_MFACK; - } -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return received Ack condition - * @param p_obj :I2C object. - * @retval true :NACK Received. - * @retval false :ACK Received. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return Busy condition - * @param p_obj :I2C object. - * @retval true :I2C bus busy. - * @retval false :I2C bus free. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return The Master status - * @param p_obj :I2C object. - * @retval true :Master mode. - * @retval false :Slave mode. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return The Transmitter - * @param p_obj :I2C object. - * @retval true :Transmitter. - * @retval false :Receiver. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Interrupt Status - * @param p_obj :I2C object. - * @retval true :Interruput Occured. - * @retval false :No Interruput Occured. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); - } - return (0); -#else - return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Interrupt Status Clear - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->ST = I2CxST_CLEAR; - } -#else - p_obj->p_instance->ST = I2CxST_CLEAR; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable Interrupt setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->IE = I2CxIE_I2C; - } -#else - p_obj->p_instance->IE = I2CxIE_I2C; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable Interrupt setting. - * @param p_obj :I2C object. - * @param tx :Direction of transfer(1=tx 0=rx). - * @retval - - * @note For DMA transfer. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - if (tx) - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); - } - else - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); - } - } -#else - if (tx) - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); - } - else - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); - } -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable Interrupt setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->IE = I2CxIE_CLEAR; - } -#else - p_obj->p_instance->IE = I2CxIE_CLEAR; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Set slave address. - * @param p_obj :I2C object. - * @param addr :slave address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); - p_obj->p_instance->AR2 = I2CxAR2_INIT; - } -#else - p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); - p_obj->p_instance->AR2 = I2CxAR2_INIT; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Detecting Slave Address - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) - && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); - } - return (0); -#else - return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) - && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); -#endif -} - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -void I2C_init(I2C_t *p_obj); -void I2C_start_condition(I2C_t *p_obj, uint32_t data); -uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); -void I2C_slave_init(I2C_t *p_obj); -#if defined(I2CSxWUP_EN) -void I2CS_init(I2CS_t *p_obj); -void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); -void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); -#endif -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __I2C_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h deleted file mode 100644 index bc7c862515e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h +++ /dev/null @@ -1,311 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_i2c.h - * @brief This file provides all the functions prototypes for I2C Driver. - * @version V1.0.0.2 - * $Date:: 2017-10-03 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __BSP_I2C_H -#define __BSP_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ -/** - * @defgroup I2C_NullPointer Null Pointer - * @brief I2C NULL Pointer. - * @{ - */ -#define I2C_NULL ((void *)0) -/** - * @} - */ /* End of group I2C_NullPointer */ - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ - -/** - * @defgroup I2C_ACK I2C ACK Macros - * @brief I2C Type of Acknowledge. - * @{ - */ -#define I2C_NACK (0) /*!< NACK Received. */ -#define I2C_ACK (1) /*!< ACK Received. */ -/** - * @} - */ /* End of group I2C_ACK */ - - -/** - * @defgroup I2C_ERROR I2C ERROR Macros - * @brief I2C Error definitions. - * @{ - */ -#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ -#if 0 -#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ -#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ -#endif -#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ -#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ -#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ -/** - * @} - */ /* End of group I2C_ERROR */ - - -/** - * @defgroup I2C_Events I2C Events Macros - * @brief I2C Asynch Events. - * @{ - */ -#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ -#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ -#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ -#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ -#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) -/** - * @} - */ /* End of group I2C_Events */ - -/** - * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros - * @brief I2C Received Contents of Slave. - * @{ - */ -#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ -#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ -#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ -#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ -/** - * @} - */ /* End of group I2C_SlaveReceive */ - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ - -/*----------------------------------*/ -/** - * @brief i2c Port Enumerated Type Definition. -*/ -/*----------------------------------*/ -typedef enum { - I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ - I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ - I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ - I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ - I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ - I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ - I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ - I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ - I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ - I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */} -i2c_port_t; - -/*----------------------*/ -/* I2C Setting */ -/*----------------------*/ -/* #define I2C_CHANNEL0 */ -#define I2C_CHANNEL3 -/* #define I2C_CHANNEL2 */ -/* #define I2C_CHANNEL3 */ -/* #define I2C_CHANNEL4 */ -#if defined(I2C_CHANNEL0) - #define I2Cx_TEXT "I2C0" - #define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL1) - #define I2Cx_TEXT "I2C1" - #define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL2) - #define I2Cx_TEXT "I2C2" - #define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL3) - #define I2Cx_TEXT "I2C3" - #define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL4) - #define I2Cx_TEXT "I2C4" - #define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ -#else - #error "target channel is non-select." -#endif - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief I2C internal information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t bus_free; /*!< Bus free information. */ - uint8_t start; /*!< Start condition information. */ - uint32_t irqn; /*!< IRQ number table pointer. */ - struct - { - uint32_t address; /*!< Slave address. */ - uint32_t stop; /*!< Stop control */ - uint32_t event; /*!< I2C Event information. */ - uint32_t state; /*!< Transfer State. */ - } asynch; -} i2c_internal_info_t; - -/*----------------------------------*/ -/** - * @brief I2C buffer structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_buffer; /*!< Buffer address. */ - uint32_t length; /*!< Buffer length. */ - uint32_t pos; /*!< Buffer pointer. */ -} i2c_buffer_t; - -/*----------------------------------*/ -/** - * @brief I2C handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2C_t i2c; /*!< I2C class structure. */ - i2c_internal_info_t info; /*!< Internal Information. */ - i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ - i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ -} _i2c_t; - -/** - * @} - */ /* End of group UTILITIES_Exported_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_functions - * @{ - */ -TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); -TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); -void i2c_reset_t(_i2c_t *p_obj); -TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); -TXZ_Result i2c_start_t(_i2c_t *p_obj); -TXZ_Result i2c_stop_t(_i2c_t *p_obj); -int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); -int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); -int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); -int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); -uint8_t i2c_active_t(_i2c_t *p_obj); -TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); -uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); -void i2c_abort_asynch_t(_i2c_t *p_obj); - -/* For slave */ -void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); -int32_t i2c_slave_receive_t(_i2c_t *p_obj); -int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); -int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); -void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); -TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); -uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); -void i2c_slave_abort_asynch_t(_i2c_t *p_obj); - -/** - * @} - */ /* End of group UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __BSP_I2C_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h deleted file mode 100644 index 8bbbd7e45e8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h +++ /dev/null @@ -1,30 +0,0 @@ -/** - ******************************************************************************* - * @file txz_sample_def.h - * @brief This file includes header files for sample application. - * @version V1.0.0.3 - * $Date:: 2017-10-26 13:33:43 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TXZ_SAMPLE_DEF_H -#define __TXZ_SAMPLE_DEF_H - -#include "txz_driver_def.h" -#include "txz_hal.h" -#if defined(TMPM4G9) - #include "txz_cg.h" - #include "txz_gpio.h" -#else - #include "txz_cg.h" - #include "txz_gpio.h" - #include "txz_dma.h" -#endif -#include "txz_uart.h" -#include "txz_t32a.h" -#endif /* __TXZ_SAMPLE_DEF_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h deleted file mode 100644 index 35d2c87d835..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h +++ /dev/null @@ -1,1024 +0,0 @@ -/** - ******************************************************************************* - * @file txz_t32a.h - * @brief This file provides all the functions prototypes for T32A driver. - * @version V1.0.0.7 - * $Date:: 2017-11-30 17:34:52 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __T32A_H -#define __T32A_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup T32A T32A - * @brief T32A Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Exported_define T32A Exported Define - * @{ - */ - -/** - * @defgroup T32A_Result Result - * @brief T32A Result Macro Definition. - * @{ - */ -#define T32A_RESULT_SUCCESS (0) /*!< Success */ -#define T32A_RESULT_FAILURE (-1) /*!< Failure */ -#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ -/** - * @} - */ /* End of group T32A_Result */ - -/** - * @defgroup T32A_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ -/** - * @} - */ /* End of group T32A_NullPointer */ - - /** - * @defgroup T32A_HALT T32A Debug HALT Control - * @brief Debug HALT Control Run/Stop HALT Macro Definition. - * @{ - */ -#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ -/** - * @} - */ /* End of group T32A_HALT */ - - /** - * @defgroup T32A_MODE32 T32A 16bit/32bit MODE - * @brief T32A 16bit/32bit MODE MODE32 Macro Definition. - * @{ - */ -#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ -#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ -/** - * @} - */ /* End of group T32A_MODE32 */ - - /** - * @defgroup T32A_RUNFLGx T32A RUNFLG Control - * @brief Run/Stop RUNFLGx Macro Definition. - * @{ - */ -#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ -#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ -/** - * @} - */ /* End of group T32A_RUNFLGx */ - -/** - * @defgroup T32A_SFTSTPx T32A SW STOP Control - * @brief T32A SW STOPx SFTSTPx Macro Definition. - * @{ - */ -#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ -#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ -/** - * @} - */ /* End of group T32A_SFTSTPx */ - -/** - * @defgroup T32A_SFTSTAx T32A SW START Control - * @brief T32A SW STARTx SFTSTAx Macro Definition. - * @{ - */ -#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ -#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ -/** - * @} - */ /* End of group T32A_SFTSTAx */ - -/** - * @defgroup T32A_RUNx T32A RUN Disable/Enable Control - * @brief RUN Disable/Enable RUNx Macro Definition. - * @{ - */ -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group T32A_RUNx */ - - -/** - * @defgroup T32A_PRSCLx T32A PRESCALER Control - * @brief PRESCALER Control PRSCLx Macro Definition. - * @{ - */ -#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ -#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ -#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ -#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ -#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ -#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ -#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ -/** - * @} - */ /* End of group T32A_PRSCLx */ - -/** - * @defgroup T32A_CLKx T32A COLCK Control - * @brief CLOCK Control CLKA Macro Definition. - * @{ - */ -#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ -#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ -#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ -#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ -#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ -#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ -/** - * @} - */ /* End of group T32A_CLKx */ - -/** - * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control - * @brief Double Buffer Disable/Enable WBFx Macro Definition. - * @{ - */ -#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ -/** - * @} - */ /* End of group T32A_WBFx */ - - /** - * @defgroup T32A_UPDNx T32A Counter Up/Down Control - * @brief Counter Up/Down Control UPDNx Macro Definition. - * @{ - */ -#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ -#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ -#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ -#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ -/** - * @} - */ /* End of group T32A_UPDNx */ - - /** - * @defgroup T32A_RELDx T32A Counter Reload Control - * @brief Counter Reload Control RELDx Macro Definition. - * @{ - */ -#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ -#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ -#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ -#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ -#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ -#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ -#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ -/** - * @} - */ /* End of group T32A_RELDx */ - - /** - * @defgroup T32A_STOPx T32A Counter Stop Control - * @brief Counter Stop Control STOPx Macro Definition. - * @{ - */ -#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ -#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ -#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ -#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ -#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ -#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ -#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ -/** - * @} - */ /* End of group T32A_STOPx */ - - - /** - * @defgroup T32A_STARTx T32A Counter Start Control - * @brief Counter Start Control STARTx Macro Definition. - * @{ - */ -#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ -#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ -#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ -#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ -#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ -#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ -#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ -/** - * @} - */ /* End of group T32A_STARTx */ - -/** - * @defgroup T32A_OCRx T32AxOUTA Control - * @brief T32AxOUTA Control OCRx Macro Definition. - * @{ - */ -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothig */ -#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ -#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ -#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRx */ - -/** - * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 - * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. - * @{ - */ -#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ -#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ -#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCAPx1 */ - -/** - * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value - * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. - * @{ - */ -#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ -#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ -#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCAPx0 */ - -/** - * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value - * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. - * @{ - */ -#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ -#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCMPx1 */ - -/** - * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value - * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. - * @{ - */ -#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ -#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ -#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCMPx0 */ - -/** - * @defgroup T32A_RGx0 T32A Timer Register x0 MASK - * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. - * @{ - */ -#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RGx0 */ - -/** - * @defgroup T32A_RGx1 T32A Timer Register x1 MASK - * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. - * @{ - */ -#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RGx0 */ - -/** - * @defgroup T32A_TMRx T32A Counter Capture Register x MASK - * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. - * @{ - */ -#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_TMRx */ - -/** - * @defgroup T32A_RELD T32A Counter Reload Register x MASK - * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. - * @{ - */ -#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RELD */ - - /** - * @defgroup T32A_CAPMx1 T32A Capture Control Register x1 - * @brief Capture Control Register A1 CAPMx1 Macro Definition. - * @{ - */ -#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ -#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ -#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ -#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ -#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ -#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ -#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ -/** - * @} - */ /* End of group T32A_CAPMx1 */ - - /** - * @defgroup T32A_CAPMx0 T32A Capture Control Register x0 - * @brief Capture Control Register x0 CAPMx0 Macro Definition. - * @{ - */ -#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ -#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ -#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ -#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ -#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ -#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ -#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ -/** - * @} - */ /* End of group T32A_CAPMx0 */ - -/** - * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK - * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. - * @{ - */ -#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_CAPx0 */ - -/** - * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK - * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. - * @{ - */ -#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_CAPx1 */ - -/** - * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK - * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. - * @{ - */ -#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) -#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) -/** - * @} - */ /* End of group T32A_IMSTERR */ - -/** - * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK - * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. - * @{ - */ -#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ -/** - * @} - */ /* End of group T32A_IMUFx */ - -/** - * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK - * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. - * @{ - */ -#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ -/** - * @} - */ /* End of group T32A_IMOFx */ - -/** - * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK - * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. - * @{ - */ -#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ -/** - * @} - */ /* End of group T32A_IMx1 */ - -/** - * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK - * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. - * @{ - */ -#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ -/** - * @} - */ /* End of group T32A_IMx0 */ - -/** - * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status - * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. - * @{ - */ -#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) -#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) -/** - * @} - */ /* End of group T32A_INTSTERR */ - -/** - * @defgroup T32A_INTUFA T32A Underflow Flag Status - * @brief T32A Underflow Flag Status INTUFA Macro Definition. - * @{ - */ -#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ -#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ -/** - * @} - */ /* End of group T32A_INTUFA */ - -/** - * @defgroup T32A_INTOFA T32A Overflow Flag Status - * @brief T32A Overflow Flag Status INTOFA Macro Definition. - * @{ - */ -#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ -#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ -/** - * @} - */ /* End of group T32A_INTOFA */ - -/** - * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status - * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. - * @{ - */ -#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ -#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ -/** - * @} - */ /* End of group T32A_INTA1 */ - -/** - * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status - * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. - * @{ - */ -#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ -#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ -/** - * @} - */ /* End of group T32A_INTA0 */ - -/** - * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control - * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. - * @{ - */ -#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx2 */ - -/** - * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control - * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. - * @{ - */ -#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx1 */ - -/** - * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control - * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. - * @{ - */ -#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx0 */ - - /** - * @defgroup T32A_PDN T32A Pulse Mode Count Down Control - * @brief Pulse Mode Count Down Control PDN Macro Definition. - * @{ - */ -#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ -#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ -#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ -#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ -#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ -#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ -#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ -#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ -/** - * @} - */ /* End of group T32A_PDN */ - - /** - * @defgroup T32A_PUP T32A Pulse Mode Count UP Control - * @brief Pulse Mode Count UP Control PUP Macro Definition. - * @{ - */ -#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ -#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ -#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ -#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ -#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ -#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ -#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ -#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ -/** - * @} - */ /* End of group T32A_PUP */ - - /** - * @defgroup T32A_NF T32A Noise Filter control - * @brief Noise Filter control NF Macro Definition. - * @{ - */ -#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ -#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/��T0 */ -#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/��T0 */ -#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/��T0 */ -/** - * @} - */ /* End of group T32A_NF */ - -/** - * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control - * @brief Phase 2 Pulse Direction control PDIR Macro Definition. - * @{ - */ -#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ -#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ -/** - * @} - */ /* End of group T32A_PDIR */ - -/** - * @defgroup T32A_PMODE T32A Pulse Count Mode control - * @brief Pulse Count Mode control PDIR Macro Definition. - * @{ - */ -#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ -#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ -/** - * @} - */ /* End of group T32A_PMODE */ - -/** - * @} - */ /* End of group T32A_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** @defgroup T32A_Exported_Typedef T32A Exported Typedef - * @{ - */ - -/** - * @enum t32_type_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_TIMERA = 0, /*!< 0: Timer A */ - T32A_TIMERB, /*!< 1: Timer B */ - T32A_TIMERC, /*!< 2: Timer C */ - T32A_TIMERMAX, -}t32_type_t; - -/** - * @enum t32_regnum_t - * @brief Use of Timer register number. - */ -typedef enum -{ - T32A_REG0 = 0, /*!< 0: Register 0 */ - T32A_REG1, /*!< 1: Register 1 */ - T32A_RELOAD, /*!< 2: Reload Register */ -}t32_regnum_t; -/** - * @enum t32_mode_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_MATCH = 0, /*!< 0: compare match detection 0 */ - T32A_OVERFLOW, /*!< 1: Overfloe detection */ - T32A_UNDERFLOW, /*!< 2: Underflow detection */ - T32A_CAPTURE0, /*!< 3: Capture 0 */ - T32A_CAPTURE1, /*!< 4: Capture 0 */ -}t32_mode_t; - -/** - * @enum t32_triger_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_INTRG = 0, /*!< 0: internal triger */ - T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ - T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ - T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ - T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ -}t32_triger_t; -/** - * @} - */ /* End of group T32A_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Exported_Typedef T32A Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct t32a_mode_t - * @brief TimerA Mode Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t halt; /*!< T32A Debug HALT Control. - : Use @ref T32A_HALT */ - uint32_t mode; /*!< T32A 16bit/32bit MODE . - : Use @ref T32A_MODE32 */ -} t32a_mode_t; - -/*----------------------------------*/ -/** - * @struct t32a_runx_t - * @brief TimerA Run Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t runflg; /*!< TimerA Run Control Flag. - : Use @ref T32A_RUNFLGx */ - uint32_t sftstp; /*!< SW Counter STOP Control. - : Use @ref T32A_SFTSTPx */ - uint32_t sftsta; /*!< SW Counter START Control. - : Use @ref T32A_SFTSTAx */ - uint32_t run; /*!< TimerA Run Control. - : Use @ref T32A_RUNx */ -} t32a_runx_t; - -/*----------------------------------*/ -/** - * @struct t32a_crx_t - * @brief Counter Register Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t prscl; /*!< T32A PRESCALER Control. - : Use @ref T32A_PRSCLx */ - uint32_t clk; /*!< T32A COLCK Control. - : Use @ref T32A_CLKx */ - uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. - : Use @ref T32A_WBFx */ - uint32_t updn; /*!< T32A Counter Up/Down Control. - : Use @ref T32A_UPDNx */ - uint32_t reld; /*!< T32A Counter Reload Control. - : Use @ref T32A_RELDx */ - uint32_t stop; /*!< T32A Counter Stop Control. - : Use @ref T32A_STOPx */ - uint32_t start; /*!< T32A Counter Start Controlc. - : Use @ref T32A_STARTx */ -} t32a_crx_t; - -/*----------------------------------*/ -/** - * @struct t32a_outcrx0_t - * @brief TimerA Output Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ocr; /*!< T32AxOUTA Control. - : Use @ref T32A_OCRx */ -} t32a_outcrx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_outcrx1_t - * @brief T32AxOUTA Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. - : Use @ref T32A_OCRCAPx1 */ - uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. - : Use @ref T32A_OCRCAPx0 */ - uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value - : Use @ref T32A_OCRCMPx1 */ - uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value - : Use @ref T32A_OCRCMPx0 */ -} t32a_outcrx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_capcrx_t - * @brief Capture Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capmx1; /*!< T32A Capture Control Register x1. - : Use @ref T32A_CAPMx1 */ - uint32_t capmx0; /*!< T32A Capture Control Register A0. - : Use @ref T32A_CAPMx0 */ -} t32a_capcrx_t; - -/*----------------------------------*/ -/** - * @struct t32a_rgx0_t - * @brief T32A Timer Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t rgx0; /*!< T32A Timer Register x0. - : Use @ref T32A_RGx0 */ -} t32a_rgx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_rgx1_t - * @brief T32A Timer Register x1 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t rgx1; /*!< T32A Timer Register x1. - : Use @ref T32A_RGx1 */ -} t32a_rgx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_tmrx_t - * @brief T32A Counter Capture Register A Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tmrx; /*!< T32A Counter Capture Register x. - : Use @ref T32A_TMRx */ -} t32a_tmrx_t; - -/*----------------------------------*/ -/** - * @struct t32a_reldx_t - * @brief T32A Counter Reload Register Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reld; /*!< T32A Counter Reload Register. - : Use @ref T32A_RELD */ -} t32a_reldx_t; - -/*----------------------------------*/ -/** - * @struct t32a_capx0_t - * @brief T32A Capture Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capx0; /*!< T32A Capture Register x0. - : Use @ref T32A_CAPx0 */ -} t32a_capx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_capx1_t - * @brief T32A Capture Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capx1; /*!< T32A Capture Register x1. - : Use @ref T32A_CAPx1 */ -} t32a_capx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_imx_t - * @brief Interrupt mask register Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). - : Use @ref T32A_IMSTERR */ - uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. - : Use @ref T32A_IMUFx */ - uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. - : Use @ref T32A_IMOFx */ - uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. - : Use @ref T32A_IMx1 */ - uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. - : Use @ref T32A_IMx0 */ -} t32a_imx_t; - -/*----------------------------------*/ -/** - * @struct t32a_stx_t - * @brief Status register structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). - : Use @ref T32A_INTSTERR */ - uint32_t intuf; /*!< T32A Underflow Flag Status. - : Use @ref T32A_INTUFA */ - uint32_t intof; /*!< T32A Overflow Flag Status. - : Use @ref T32A_INTOFA */ - uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. - : Use @ref T32A_INTA1 */ - uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. - : Use @ref T32A_INTA0 */ -} t32a_stx_t; - -/*----------------------------------*/ -/** - * @struct t32a_dma_req_t - * @brief DMA Request register setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. - : Use @ref T32A_DMAENx2 */ - uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. - : Use @ref T32A_DMAENx1 */ - uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. - : Use @ref T32A_DMAENx0 */ -} t32a_dma_req_t; - -/*----------------------------------*/ -/** - * @struct t32a_pulse_cr_t - * @brief Pulse Count Control register setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t pdn; /*!< Pulse Mode Count Down Control. - : Use @ref T32A_PDN */ - uint32_t pup; /*!< Pulse Mode Count UP Control. - : Use @ref T32A_PUP */ - uint32_t nf; /*!< Noise Filter control. - : Use @ref T32A_NF */ - uint32_t pdir; /*!< Phase 2 Pulse Direction control. - : Use @ref T32A_PDIR */ - uint32_t pmode; /*!< Pulse Count Mode control. - : Use @ref T32A_PMODE */ -} t32a_pulse_cr_t; - -/** - * @struct t32a_initial_setting_t - * @brief Initial Timer setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - t32a_runx_t runx; /*!< Timer Run Control Setting */ - t32a_crx_t crx; /*!< Counter Register Control Setting */ - t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ - t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ - t32a_capcrx_t capcrx; /*!< Capture Control Setting */ - t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ - t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ - t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ - t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ - t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ - t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ - t32a_imx_t imx; /*!< Interrupt mask register Setting */ - t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ - t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ - void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ - void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ - void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ -} t32a_initial_setting_t; - -/** - * @struct t32a_initial_mode_t - * @brief Initial Mode setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - t32a_mode_t mode; /*!< Timer Mode Setting */ -} t32a_initial_mode_t; - - -/*----------------------------------*/ -/** - * @brief T32A handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct t32a_handle -{ - TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ - t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ - t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ -}t32a_t; - -/** @} */ -/* End of group T32A_Exported_Types */ -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Exported_functions T32A Exported Functions - * @{ - */ -TXZ_Result t32a_mode_init(t32a_t *p_obj); -TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); -TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); -TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); -void t32a_timer_IRQHandler(t32a_t *p_obj); -void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); -void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); -TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); -/** - * @} - */ /* End of group T32A_Exported_functions */ - -/** - * @} - */ /* End of group T32A */ - -/** - * @} - */ /* End of group Periph_Driver */ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __T32A_H */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h deleted file mode 100644 index 1f422aa07d1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h +++ /dev/null @@ -1,1322 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.h - * @brief This file provides all the functions prototypes for TSPI driver. - * @version V1.0.0.3 - * $Date:: 2018-02-28 13:37:55 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __TSPI_H -#define __TSPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup TSPI TSPI - * @brief TSPI Driver. - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_define TSPI Exported Define - * @{ - */ -/** - * @defgroup TSPI_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define TSPI_NULL ((void *)0) -/** - * @} - */ /* End of group TSPI_NullPointer */ - -/** - * @defgroup TSPI_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group TSPI_ParameterResult */ - - -/** - * @defgroup TSPI_Result Result - * @brief TSPI Result Macro Definition. - * @{ - */ -#define TSPI_RESULT_SUCCESS (0) /*!< Success */ -#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ -/** - * @} - */ /* End of group TSPI_Result */ - -/** - * @defgroup TSPI_SW_Reset SW Reset - * @brief Software Rest Macro Definition. - * @{ - */ -#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ -/** - * @} - */ /* End of group TSPI_SW_Reset */ - - -/** - * @defgroup TSPI_Enable TSPI Enable/Disable Control - * @brief Enable/Disable TSPIE Macro Definition. - * @{ - */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Enable */ - -/** - * @defgroup TSPI_Triger_Control Triger Control - * @brief Enable/Disable TRGEN Macro Definition. - * @{ - */ -#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Control Transmission Control - * @brief Enable/Disable TRXE Macro Definition. - * @{ - */ -#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Mode Transmission Mode - * @brief TSPIIMS Mode Macro Definisiton. - * @{ - */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ -#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ -/** - * @} - */ /* End of group TSPI_Transmission_Mode */ - - -/** - * @defgroup TSPI_Operation_Select Operation Select - * @brief Master/Slave MSTR Operation Macro Definisiton. - * @{ - */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */ -#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ -/** - * @} - */ /* End of group TSPI_Operation_Select */ - - -/** - * @defgroup TSPI_Transfer_Mode Transfer Mode - * @brief Transfer Mode TMMD Macro Definisiton. - * @{ - */ -#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ -/** - * @} - */ /* End of group TSPI_Transfer_Mode */ - - -/** - * @defgroup TSPI_CSSEL_Select CSSEL Select - * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ -#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ -#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ -#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ -/** - * @} - */ /* End of group TSPI_CSSEL_Select */ - -/** - * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range - * @brief Transfer Frame Range Macro Definisiton. - * @{ - */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */ -#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ -/** - * @} - */ /* End of group TSPI_Transfer_Frame_Range */ -/** - * @defgroup TSPI_IDLE_Output_value IDLE Output Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ -#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ -#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_IDLE_Output_value */ - -/** - * @defgroup TSPI_RXDLY_value RXDLY Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_RXDLY_SET ((uint32_t)0x00010000) /*!< RXDLY SET */ -/** - * @} - */ /* End of group TSPI_RXDLY_value*/ - - - /** - * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value - * @brief In case of Under Run Output Value TXDEMP Macro Definisiton. - * @{ - */ -#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_Underrun_Output_value */ - - -/** - * @defgroup TSPI_TxFillLevel Tx Fill Level - * @brief Transmit Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ -#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ -#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ -#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ -#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ -#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ -#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ -#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ -/*! - * @} - */ /* End of group TSPI_TxFillLevel */ - - -/** - * @defgroup TSPI_RxFillLevel Rx Fill Level - * @brief Receive Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ -#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ -#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ -#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ -#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ -#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ -#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ -#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ -#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_RxFillLevel */ - - -/** - * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterrupt */ - - -/** - * @defgroup TSPI_TxInterrupt Tx Interrpt - * @brief Enable/Disable Transmit Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxInterrupt */ - - -/** - * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterrupt */ - - -/** - * @defgroup TSPI_RxInterrupt Rx Interrpt - * @brief Enable/Disable Receive Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxInterrupt */ - - -/** - * @defgroup TSPI_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ErrorInterrupt */ - - -/** - * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt - * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxDMAInterrupt */ - - -/** - * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt - * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxDMAInterrupt */ - - -/** - * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear - * @brief Tx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Tx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear - * @brief Rx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Rx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock - * @brief Baudrate Input Clock Macro Definisiton. - * @{ - */ -#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ -#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ -#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ -#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ -#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ -#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ -#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ -#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ -#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Clock */ - - -/** - * @defgroup TSPI_Baudrate_Divider Baudrate Divider - * @brief Baudrate IDivider Macro Definisiton. - * @{ - */ -#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ -#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ -#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ -#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ -#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ -#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ -#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ -#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ -#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ -#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ -#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ -#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ -#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ -#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ -#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Divider */ - - -/** - * @defgroup TSPI_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ -/*! - * @} - */ /* End of group TSPI_DataDirection */ - - -/** - * @defgroup TSPI_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ -#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ -#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ -#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ -#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ -#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ -#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ -#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ -#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ -#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ -#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ -#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ -#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ -#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ -#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ -#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ -#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ -#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ -#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ -#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ -#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ -#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ -#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ -#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ -#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ -#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ -/** - * @} - */ /* End of group TSPI_DataLength */ - - -/** - * @defgroup TSPI_Frame_Interval_Time Frame Interval time - * @brief Frame Interval time Macro Definisiton. - * @{ - */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Frame_Interval_Time */ - - -/** - * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity - * @brief TSPIxCS3 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS3_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity - * @brief TSPIxCS2 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS2_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity - * @brief TSPIxCS1 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS1_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity - * @brief TSPIxCS0 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS0_Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity - * @brief Serial Clock Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ -#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ -/** - * @} - */ /* End of group Serial Clock Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity - * @brief Serial Clock IDLE Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ -#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ - - -/** - * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time - * @brief Minimum IDLE Time Macro Definisiton. - * @{ - */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Minimum_IDLE_Time */ - - -/** - * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay - * @brief Serial Clock Delay Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_Delay */ - - -/** - * @defgroup TSPI_Negate_Delay Negate Delay - * @brief Negate Delay Macro Definisiton. - * @{ - */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ -#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ -#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ -#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ -#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ -#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ -#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ -#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ -#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ -#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ -#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ -#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ -#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ -#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ -#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Negate_Delay */ - - -/** - * @defgroup TSPI_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ParityEnable */ - - -/** - * @defgroup TSPI_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ -/** - * @} - */ /* End of group TSPI_ParityBit */ - - -/** - * @defgroup TSPI_Status_Setting_flag Status Setting Flag - * @brief Enable/Disable Status Setting Flag Macro Definisiton. - * @{ - */ -#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group TSPI_Status_Setting_flag */ - - -/** - * @defgroup TSPI_TxState Transmitting State Flag - * @brief Transmitting State Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ -#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_TxState */ - - -/** - * @defgroup TSPI_TxDone Transmitting Complete Flag - * @brief Transmitting Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ -#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxDone */ - - -/** - * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag - * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ -#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag - * @brief Transmitting FIFO Empty Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_TxFIFOEmptyFlag */ - -/** - * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level - * @brief Current Transmitting FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ -#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ -#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ -#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ -#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ -#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ -#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_TxReachFillLevel */ - - -/** - * @defgroup TSPI_RxState Receive State Flag - * @brief Receive State Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ -#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_RxState */ - - -/** - * @defgroup TSPI_RxDone Receive Complete Flag - * @brief Receive Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxDone */ - - -/** - * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag - * @brief Rx FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ -#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag - * @brief Receiving FIFO Full Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_RxFIFOFullFlag */ - - -/** - * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level - * @brief Current Receive FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ -#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ -#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ -#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ -#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ -#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ -#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_RxReachFillLevel */ - - -/** - * @defgroup TSPI_TRGErr Triger Error - * @brief Triger Error Macro Definisiton. - * @{ - */ -#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ -#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_TRGErr */ - -/** - * @defgroup TSPI_UnderrunErr Underrun Error - * @brief Underrun Error Macro Definisiton. - * @{ - */ -#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ -#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_UnderrunErr */ - -/** - * @defgroup TSPI_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ -#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_OverrunErr */ - - -/** - * @defgroup TSPI_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ -#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_ParityErr */ - - /** - * @defgroup TSPI_Data_allign Data allign - * @brief Data allign Macro Definisiton. - * @{ - */ -#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ -#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ -#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ -/** - * @} - */ /* End of group TSPI_Data_allign */ - - /** - * @defgroup TSPI_FifoMax FIFO MAX - * @brief FIFO MAX LEVEL - * @{ - */ -#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ -/** - * @} - */ /* End of group TSPI_FifoMax */ - - /** - * @defgroup TSPI_ErrCode Error Code - * @brief Error Code Macro Definisiton. - * @{ - */ -#define NOERROR ((uint32_t)0x00000000) /*!< no error */ -#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ -#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ -#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ -#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ -#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ -#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ -#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ -#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ -#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ -#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ -/** -* @} - */ /* End of group TSPI_ErrCode */ - - /** - * @defgroup TSPI_Buffer_Size Receive Buffer size - * @brief Error Code Macro Definisiton. - * @{ - */ -#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ -/** -* @} - */ /* End of group TSPI_Buffer_Size */ -/** - * @} - */ /* End of group TSPI_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/* No define */ -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct tspi_receive8_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive8_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive16_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive16_t; - -/** - * @struct tspi_receive32_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive32_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive_t - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ - tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ - tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ -} tspi_receive_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit8_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit8_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit16_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit16_t; -/*----------------------------------*/ -/** - * @struct tspi_transmit32_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit32_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit_t - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ - tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ - tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ -} tspi_transmit_t; - -/*----------------------------------*/ -/** - * @struct tspi_control1_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t trgen; /*!< TRGEN Transmission Triger Control. - : Use @ref TSPI_Triger_Control */ - uint32_t trxe; /*!< TRXE Transmission Control. - : Use @ref TSPI_Transmission_Control */ - uint32_t tspims; /*!< TSPI/SIO Transmission Mode. - : Use @ref TSPI_Transmission_Mode */ - uint32_t mstr; /*!< Master/Slave Operation Select. - : Use @ref TSPI_Operation_Select */ - uint32_t tmmd; /*!< Transfer Mode Select. - : Use @ref TSPI_Transfer_Mode */ - uint32_t cssel; /*!< CSSEL Select. - : Use @ref TSPI_CSSEL_Select */ - uint32_t fc; /*!< Transfer Frame Value. - : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ -} tspi_control1_t; - -/*----------------------------------*/ -/** - * @struct tspi_control2_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tidle; /*!< IDLE Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t txdemp; /*!< Under Run Occur Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t rxdly; /*!< Fsys Select. - : Use @ref TSPI_RXDLY_value */ - uint32_t til; /*!< Transmit Fill Level. - : Use @ref TSPI_TxFillLevel */ - uint32_t ril; /*!< Receive Fill Level. - : Use @ref TSPI_RxFillLevel */ - uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. - : Use @ref TSPI_TxFIFOInterrupt */ - uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. - : Use @ref TSPI_TxInterrupt */ - uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. - : Use @ref TSPI_RxFIFOInterrupt */ - uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. - : Use @ref TSPI_RxInterrupt */ - uint32_t interr; /*!< Enable/Disable Error Interrupt. - : Use @ref TSPI_ErrorInterrupt */ - uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. - : Use @ref TSPI_TxDMAInterrupt */ - uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. - : Use @ref TSPI_RxDMAInterrupt */ -} tspi_control2_t; - -/*----------------------------------*/ -/** - * @struct tspi_control3_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tfempclr; /*!< Transmit Buffer Clear. - : Use @ref TSPI_Tx_Buffer_Clear */ - uint32_t rffllclr; /*!< Receive Buffer Clear. - : Use @ref TSPI_Rx_Buffer_Clear */ -} tspi_control3_t; - -/*----------------------------------*/ -/** - * @struct tspi_baudrate_t - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brck; /*!< Baudrate Input Clock. - : Use @ref TSPI_Baudrate_Clock */ - uint32_t brs; /*!< Baudrate Divider. - : Use @ref TSPI_Baudrate_Divider */ -} tspi_baudrate_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr0_t - * @brief Format control0. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dir; /*!< Data Direction. - : Use @ref TSPI_DataDirection */ - uint32_t fl; /*!< Data Length. - : Use @ref TSPI_DataLength */ - uint32_t fint; /*!< Frame Interval time. - : Use @ref TSPI_Frame_Interval_Time */ - uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS3_Polarity */ - uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS2_Polarity */ - uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS1_Polarity */ - uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS0_Polarity */ - uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. - : Use @ref TSPI_Serial_Clock_Polarity */ - uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. - : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ - uint32_t csint; /*!< Minimum IDLE Time. - : Use @ref TSPI_Minimum_IDLE_Time */ - uint32_t cssckdl; /*!< Serial Clock Delay. - : Use @ref TSPI_Serial_Clock_Delay */ - uint32_t sckcsdl; /*!< Negate Delay. - : Use @ref TSPI_Negate_Delay */ -} tspi_fmtr0_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr1_t - * @brief Format control1. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reserved; /*!< SIO Slave MOde. - : */ - uint32_t vpe; /*!< Enable/Disable Parity Function. - : Use @ref TSPI_ParityEnable */ - uint32_t vpm; /*!< Odd/Even Parity Bit. - : Use @ref TSPI_ParityBit */ -} tspi_fmtr1_t; - -/*----------------------------------*/ -/** - * @struct tspi_status_t - * @brief Status register. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. - : Use @ref TSPI_Status_Setting_flag */ - uint32_t txrun; /*!< Stop/Active Tx Active Flag. - : Use @ref TSPI_TxState */ - uint32_t txend; /*!< Tx Data Send Complete Flag. - : Use @ref TSPI_TxDone */ - uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. - : Use @ref TSPI_TxFIFOInterruptFlag */ - uint32_t tfemp; /*!< Tx FIFO Empty Flag. - : Use @ref TSPI_TxFIFOEmptyFlag */ - uint32_t tlvll; /*!< Tx Reach Fill Level - : Use @ref TSPI_TxReachFillLevel */ - uint32_t rxrun; /*!< Stop/Active Rx Active Flag. - : Use @ref TSPI_RxState */ - uint32_t rxend; /*!< Rx Data Receive Complete Flag. - : Use @ref TSPI_RxDone */ - uint32_t intrxff; /*!< Rx FIFO Interrpt Flag - : Use @ref TSPI_RxFIFOInterruptFlag */ - uint32_t rffll; /*!< Rx FIFO Full Flag - : Use @ref TSPI_RxFIFOFullFlag */ - uint32_t rlvl; /*!< Rx Reach Fill Level - : Use @ref TSPI_RxReachFillLevel */ -} tspi_status_t; - -/*----------------------------------*/ -/** - * @struct tspi_error_t - * @brief Error flag. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t udrerr; /*!< Underrun Error. - : Use @ref TSPI_UnderrunErr */ - uint32_t ovrerr; /*!< Overrun Error. - : Use @ref TSPI_OverrunErr */ - uint32_t perr; /*!< Parity Error. - : Use @ref TSPI_ParityErr */ -} tspi_error_t; - - -/*----------------------------------*/ -/** - * @struct tspi_initial_setting_t - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - tspi_control1_t cnt1; /*!< Control1 setting. - : Use @ref tspi_control1_t */ - tspi_control2_t cnt2; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_control3_t cnt3; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_baudrate_t brd; /*!< Baudrate setting. - : Use @ref tspi_baudrate_t */ - tspi_fmtr0_t fmr0; /*!< Format control0 setting. - : Use @ref tspi_fmtr0_t */ - tspi_fmtr1_t fmr1; /*!< Format control1 setting. - : Use @ref tspi_fmtr1_t */ -} tspi_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief TSPI handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct tspi_handle -{ - TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ - tspi_initial_setting_t init; /*!< Initial setting. */ - uint32_t errcode; /*!< ErrorCode */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - tspi_transmit_t info; /*!< Transmit Data Information. */ - uint8_t tx_allign; /*!< Transmit Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - tspi_receive_t info; /*!< Receive Data Information. */ - uint8_t rx_allign; /*!< Receive Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} tspi_t; -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_functions TSPI Exported Functions - * @{ - */ -TXZ_Result tspi_init(tspi_t *p_obj); -TXZ_Result tspi_deinit(tspi_t *p_obj); -TXZ_Result tspi_format(tspi_t *p_obj); -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); -TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info); -void tspi_irq_handler_transmit(tspi_t *p_obj); -void tspi_irq_handler_receive(tspi_t *p_obj); -void tspi_error_irq_handler(tspi_t *p_obj); -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); -TXZ_Result tspi_error_clear(tspi_t *p_obj); -TXZ_Result tspi_discard_transmit(tspi_t *p_obj); -TXZ_Result tspi_discard_receive(tspi_t *p_obj); -/** - * @} - */ /* End of group TSPI_Exported_functions */ -/** - * @} - */ /* End of group TSPI */ -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TSPI_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h deleted file mode 100644 index fb78eb6e171..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h +++ /dev/null @@ -1,812 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart.h - * @brief This file provides all the functions prototypes for UART driver. - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __UART_H -#define __UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup UART UART - * @brief UART Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_define UART Exported Define - * @{ - */ - -/** - * @defgroup UART_FifoMax Max Num of FIFO - * @brief Max Num of Tx/Rx Fifo. - * @{ - */ -#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ -#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ -/** - * @} - */ /* End of group UART_FifoMax */ - -/** - * @defgroup UART_HalfClockSelect Half Clock Select - * @brief Output Terminal Select - * @{ - */ -#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ -#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ -/** - * @} - */ /* End of group UART_HalfClockSelect */ - -/** - * @defgroup UART_HalfClockMode Half Clock Mode - * @brief Half Clock Mode Setting. - * @{ - */ -#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ -#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ -/** - * @} - */ /* End of group UART_HalfClockMode */ - -/** - * @defgroup UART_HalfClockCTR Half Clock Mode Control - * @brief Half Clock Control. - * @{ - */ -#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ -#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ -/** - * @} - */ /* End of group UART_HalfClockCTR */ - -/** - * @defgroup UART_LoopBack Loop Back Function - * @brief Half Clock Control. - * @{ - */ -#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ -#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ -/** - * @} - */ /* End of group UART_LoopBack */ - - -/** - * @defgroup UART_NoiseFilter Noise Filter - * @brief Noise Filter Setting. - * @{ - */ -#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ -#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ -/** - * @} - */ /* End of group UART_NoiseFilter */ - - -/** - * @defgroup UART_CTSHandshake CTS Handshake - * @brief Available CTS Handshake Macro Definisiton. - * @{ - */ -#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ -/** - * @} - */ /* End of group UART_CTSHandshake */ - - -/** - * @defgroup UART_RTSHandshake RTS Handshake - * @brief Available RTS Handshake Macro Definisiton. - * @{ - */ -#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ -/** - * @} - */ /* End of group UART_RTSHandshake */ - - -/** - * @defgroup UART_DataComplementation Data Complementation - * @brief Enable/Disable Data Signal Complementation Macro Definisiton. - * @{ - */ -#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group UART_DataComplementation */ - - -/** - * @defgroup UART_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ -/*! - * @} - */ /* End of group UART_DataDirection */ - - -/** - * @defgroup UART_StopBit Stop Bit - * @brief Stop Bit Macro Definisiton. - * @{ - */ -#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ -#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ -/** - * @} - */ /* End of group UART_StopBit */ - - -/** - * @defgroup UART_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ -/** - * @} - */ /* End of group UART_ParityBit */ - - -/** - * @defgroup UART_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group UART_ParityEnable */ - - -/** - * @defgroup UART_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ -#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ -#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ -/** - * @} - */ /* End of group UART_DataLength */ - - -/** - * @defgroup UART_TxFillLevelRange Tx Fill Level Range - * @brief Transmit Fill Level Range Macro Definisiton. - * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". - * @{ - */ -#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ -#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ -/*! - * @} - */ /* End of group UART_TxFillLevelRange */ - - -/** - * @defgroup UART_RxFillLevelRange Rx Fill Level Range - * @brief Receive Fill Level Range Macro Definisiton. - * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". - * @{ - */ -#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ -#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ -/** - * @} - */ /* End of group UART_RxFillLevelRange */ - - -/** - * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Available Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ -/** - * @} - */ /* End of group UART_TxFIFOInterrupt */ - - -/** - * @defgroup UART_TxInterrupt Tx Interrpt - * @brief Available Transmit Interrupt Macro Definisiton. - * @{ - */ -#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ -/** - * @} - */ /* End of group UART_TxInterrupt */ - - -/** - * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Available Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ -/** - * @} - */ /* End of group UART_RxFIFOInterrupt */ - - -/** - * @defgroup UART_RxInterrupt Rx Interrpt - * @brief Available Receive Interrupt Macro Definisiton. - * @{ - */ -#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ -/** - * @} - */ /* End of group UART_RxInterrupt */ - - -/** - * @defgroup UART_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group UART_ErrorInterrupt */ - - -/** - * @defgroup UART_Prescaler Prescaler - * @brief Prescaler Macro Definisiton. - * @{ - */ -#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ -#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ -#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ -#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ -#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ -#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ -#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ -#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ -#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ -#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ -/** - * @} - */ /* End of group UART_Prescaler */ - - -/** - * @defgroup UART_Clock_Mask Clock Mask - * @brief Clock Mask Macro Definisiton. - * @{ - */ -#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ -/** - * @} - */ /* End of group UART_Clock_Mask */ - - -/** - * @defgroup UART_Division Division - * @brief Enable/Disable Division Macro Definisiton. - * @{ - */ -#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ -/** - * @} - */ /* End of group UART_Division */ - - -/** - * @defgroup UART_RangeK Range K - * @brief Range of K Macro Definisiton. - * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". - * @{ - */ -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ -/** - * @} - */ /* End of group UART_RangeK */ - - -/** - * @defgroup UART_RangeN Range N - * @brief Range of N Macro Definisiton. - * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". - * @{ - */ -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ -/** - * @} - */ /* End of group UART_RangeN */ - - -/** - * @defgroup UART_SettingEnable Setting Enable - * @brief Enable/Disable Setting Macro Definisiton. - * @{ - */ -#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ -#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group UART_SettingEnable */ - - -/** - * @defgroup UART_TxState Tx State - * @brief Transmitting State Macro Definisiton. - * @{ - */ -#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ -#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ -#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ -/** - * @} - */ /* End of group UART_TxState */ - - -/** - * @defgroup UART_TxDone Transmitting Done - * @brief Transmitting Done Macro Definisiton. - * @{ - */ -#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ -#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ -/** - * @} - */ /* End of group UART_TxDone */ - - -/** - * @defgroup UART_TxReachFillLevel Tx Reach Fill Level - * @brief Reach Transmitting Fill Level Macro Definisiton. - * @{ - */ -#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ -#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ -/** - * @} - */ /* End of group UART_TxReachFillLevel */ - - -/** - * @defgroup UART_TxFifoLevel Tx FIFO Fill Level - * @brief Transmitting FIFO Fill Level Macro Definisiton. - * @{ - */ -#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ -/** - * @} - */ /* End of group UART_TxFifoLevel */ - - -/** - * @defgroup UART_RxState Rx State - * @brief Receive State Macro Definisiton. - * @{ - */ -#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ -#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ -#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ -/** - * @} - */ /* End of group UART_RxState */ - - -/** - * @defgroup UART_RxDone Rx Done - * @brief Receive Done Macro Definisiton. - * @{ - */ -#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ -#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ -/** - * @} - */ /* End of group UART_RxDone */ - - -/** - * @defgroup UART_RxReachFillLevel Rx Reach Fill Level - * @brief Reach Receive Fill Level Macro Definisiton. - * @{ - */ -#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ -#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ -/** - * @} - */ /* End of group UART_RxReachFillLevel */ - - -/** - * @defgroup UART_RxFifoLevel Rx FIFO Fill Level - * @brief Receive FIFO Fill Level Macro Definisiton. - * @{ - */ -#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ -/** - * @} - */ /* End of group UART_RxFifoLevel */ - - -/** - * @defgroup UART_TriggerErr Trigger Error - * @brief Trigger Error Macro Definisiton. - * @{ - */ -#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ -/** - * @} - */ /* End of group UART_TxTriggerErr */ - - -/** - * @defgroup UART_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ -/** - * @} - */ /* End of group UART_OverrunErr */ - - -/** - * @defgroup UART_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ -/** - * @} - */ /* End of group UART_ParityErr */ - - -/** - * @defgroup UART_FramingErr Framing Error - * @brief Framing Error Macro Definisiton. - * @{ - */ -#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ -/** - * @} - */ /* End of group UART_FramingErr */ - - -/** - * @defgroup UART_BreakErr Break Error - * @brief Break Error Macro Definisiton. - * @{ - */ -#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ -/** - * @} - */ /* End of group UART_BreakErr */ - -/** - * @} - */ /* End of group UART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_define UART Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_typedef UART Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. - * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. - * @attention "num" must be over FIFO max num. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} uart_receive8_t; - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} uart_receive16_t; - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - uart_receive8_t rx8; /*!< @ref uart_receive8_t */ - uart_receive16_t rx16; /*!< @ref uart_receive16_t */ -} uart_receive_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} uart_transmit8_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. - Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ - uint32_t num; /*!< The number of transmit data. */ -} uart_transmit16_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ - uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ -} uart_transmit_t; - -/*----------------------------------*/ -/** - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t prsel; /*!< Prescaler. - : Use @ref UART_Prescaler */ -} uart_clock_t; - -/*----------------------------------*/ -/** - * @brief Boudrate setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ken; /*!< Enable/Disable Division Definisiton. - : Use @ref UART_Division */ - uint32_t brk; /*!< Division Value K. - : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ - uint32_t brn; /*!< Division Value N. - : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ -} uart_boudrate_t; - -/*----------------------------------*/ -/** - * @brief Transmit FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t inttx; /*!< Available Transmit FIFO Interrupt. - : Use @ref UART_TxFIFOInterrupt */ - uint32_t level; /*!< Transmit Fill Level. - : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ -} uart_tx_fifo_t; - -/*----------------------------------*/ -/** - * @brief Receive FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intrx; /*!< Available Receive FIFO Interrupt. - : Use @ref UART_RxFIFOInterrupt */ - uint32_t level; /*!< Receive Fill Level. - : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ -} uart_rx_fifo_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - uart_clock_t clock; /*!< Clock setting. - : Use @ref uart_clock_t */ - uart_boudrate_t boudrate; /*!< Boudrate setting. - : Use @ref uart_boudrate_t */ - uint32_t inttx; /*!< Available Transmit Interrupt. - : Use @ref UART_TxInterrupt */ - uint32_t intrx; /*!< Available Receive Interrupt. - : Use @ref UART_RxInterrupt */ - uint32_t interr; /*!< Available Error Interrupt. - : Use @ref UART_ErrorInterrupt */ - uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. - : Use @ref uart_tx_fifo_t */ - uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. - : Use @ref uart_rx_fifo_t */ - uint32_t hct; /*!< Half Clock Terminal Select. - : Use @ref UART_HalfClockSelect */ - uint32_t hcm; /*!< Half Clock Mode Select. - : Use @ref UART_HalfClockMode */ - uint32_t hcc; /*!< Half Clock Control. - : Use @ref UART_HalfClockCTR */ - uint32_t lbc; /*!< Loop Back Control. - : Use @ref UART_LoopBack */ - uint32_t nf; /*!< UTxRXD Noise Filter. - : Use @ref UART_NoiseFilter */ - uint32_t ctse; /*!< Available CTS Handshake. - : Use @ref UART_CTSHandshake */ - uint32_t rtse; /*!< Available RTS Handshake. - : Use @ref UART_RTSHandshake */ - uint32_t iv; /*!< Data Signal Complementation. - : Use @ref UART_DataComplementation */ - uint32_t dir; /*!< Data Direction. - : Use @ref UART_DataDirection */ - uint32_t sblen; /*!< Stop Bit. - : Use @ref UART_StopBit */ - uint32_t even; /*!< Odd/Even Parity Bit. - : Use @ref UART_ParityBit */ - uint32_t pe; /*!< Enable/Disable Parity Bit. - : Use @ref UART_ParityEnable */ - uint32_t sm; /*!< Data Length. - : Use @ref UART_DataLength */ -} uart_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief UART handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ - uart_initial_setting_t init; /*!< Initial setting. */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - uart_transmit_t info; /*!< Transmit Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - uart_receive_t info; /*!< Receive Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} uart_t; - -/** - * @} - */ /* End of group UART_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_functions UART Exported Functions - * @{ - */ -TXZ_Result uart_init(uart_t *p_obj); -TXZ_Result uart_deinit(uart_t *p_obj); -TXZ_Result uart_discard_transmit(uart_t *p_obj); -TXZ_Result uart_discard_receive(uart_t *p_obj); -TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); -TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); -void uart_transmit_irq_handler(uart_t *p_obj); -void uart_receive_irq_handler(uart_t *p_obj); -void uart_error_irq_handler(uart_t *p_obj); -TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); -TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); -TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); -/** - * @} - */ /* End of group UART_Exported_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h deleted file mode 100644 index 95357511930..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h +++ /dev/null @@ -1,476 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __UART_INCLUDE_H -#define __UART_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_define - * @{ - */ - -/** - * @defgroup UART_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define UART_NULL ((void *)0) -/** - * @} - */ /* End of group UART_NullPointer */ - -/** - * @defgroup UART_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group UART_ParameterResult */ - -/** - * @defgroup UARTxSWRST UARTxSWRST Register - * @brief UARTxSWRST Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | SWRSTF | - * | 6:2 | - | - * | 1:0 | SWRST | - * @{ - */ -/* SWRSTF */ -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ -#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ -/* SWRST */ -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ -/** - * @} - */ /* End of group UARTxSWRST */ - -/** - * @defgroup UARTxCR0 UARTxCR0 Register - * @brief UARTxCR0 Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-19 | - | - * | 18 | HBSST | - * | 17 | HBSMD | - * | 16 | HBSEN | - * | 15 | LPB | - * | 14-12 | NF[2:0] | - * | 11 | - | - * | 10 | CTSE | - * | 9 | RTSE | - * | 8 | WU | - * | 7 | - | - * | 6 | IV | - * | 5 | DIR | - * | 4 | SBLEN | - * | 3 | EVEN | - * | 2 | PE | - * | 1-0 | SM[1:0] | - * @{ - */ -/* HBSST */ -#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ -/* HBSMD */ -#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ -/* HBSEN */ -#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ -#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ -#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ -/* LPB */ -#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ -#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ -#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ -/* WU */ -#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ -#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ -#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ -/** - * @} - */ /* End of group UARTxCR0 */ - -/** - * @defgroup UARTxCR1 UARTxCR1 Register - * @brief UARTxCR1 Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-15 | - | - * | 14-12 | TIL[2:0] | - * | 11 | - | - * | 10-8 | RIL[2:0] | - * | 7 | INTTXFE | - * | 6 | INTTXWE | - * | 5 | INTRXFE | - * | 4 | INTRXWE | - * | 3 | - | - * | 2 | INTERR | - * | 1 | DMATE | - * | 0 | DMARE | - * @{ - */ -/* RIL */ -#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ -/* DMATE */ -#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ -#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ -#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ -/* DMARE */ -#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ -#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ -#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ -/** - * @} - */ /* End of group UARTxCR1 */ - -/** - * @defgroup UARTxTRANS UARTxTRANS Register - * @brief UARTxTRANS Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-4 | - | - * | 3 | BK | - * | 2 | TXTRG | - * | 1 | TXE | - * | 0 | RXE | - * @{ - */ -/* BK */ -#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ -#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ -#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ -/* TXTRG */ -#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ -#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ -#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ -/* TXE */ -#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ -#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ -#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ -/* RXE */ -#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ -#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ -#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ -/* TXE,RXE */ -#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ -/** - * @} - */ /* End of group UARTxTRANS */ - -/** - * @defgroup UARTxDR UARTxDR Register - * @brief UARTxDR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-19 | - | - * | 18 | PERR | - * | 17 | FERR | - * | 16 | BERR | - * | 15:9 | - | - * | 8:0 | DR | - * @{ - */ -/* DR */ -#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ -#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ -/** - * @} - */ /* End of group UARTxDR */ - -/** - * @defgroup UARTxSR UARTxSR Register - * @brief UARTxSR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31 | SUE | - * | 30:16 | - | - * | 15 | TXRUN | - * | 14 | TXEND | - * | 13 | TXFF | - * | 12 | - | - * | 11:8 | TLVL | - * | 7 | RXRUN | - * | 6 | RXEND | - * | 5 | RXFF | - * | 4 | - | - * | 3:0 | RLVL | - * @{ - */ -/* SUE */ -#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ -/* TXEND */ -#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ -#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ -#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ -/* TXFF */ -#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ -#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ -#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ -/* TLVL */ -#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ -/* RXEND */ -#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ -#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ -#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ -/* RXFF */ -#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ -#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ -#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ -/* RLVL */ -#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ -/** - * @} - */ /* End of group UARTxSR */ - -/** - * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register - * @brief UARTxFIFOCLR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-2 | - | - * | 1 | TFCLR | - * | 0 | RFCLR | - * @{ - */ -/* TFCLR */ -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ -/* RFCLR */ -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ -/** - * @} - */ /* End of group UARTxFIFOCLR */ - -/** - * @defgroup UARTxERR UARTxERR Register - * @brief UARTxERR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-5 | - | - * | 4 | TRGERR | - * | 3 | OVRERR | - * | 2 | PERR | - * | 1 | FERR | - * | 0 | BERR | - * @{ - */ -/* TRGERR */ -#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ -#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ -#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ -#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ -/* OVRERR */ -#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ -#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ -#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ -#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ -/* PERR */ -#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ -#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ -#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ -#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ -/* FERR */ -#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ -#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ -#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ -#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ -/* BERR */ -#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ -#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ -#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ -#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ -/** - * @} - */ /* End of group UARTxERR */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_fuctions - * @{ - */ -__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); -/*--------------------------------------------------*/ -/** - * @brief Disable UARTxTRANS TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable UARTxTRANS TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable UARTxTRANS RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable UARTxTRANS RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1; -#endif -} - - -/** - * @} - */ /* End of group UART_Private_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c deleted file mode 100644 index e7ecba3c6e6..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c +++ /dev/null @@ -1,1200 +0,0 @@ -/** - ******************************************************************************* - * @file adc.c - * @brief This file provides API functions for ADC driver. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "adc_include.h" -#include "adc_ch.h" -#include "adc.h" - -#if defined(__ADC_H) -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @addtogroup ADC - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_macro ADC Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_Enumeration ADC Private Enumeration - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_Enumeration */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Variable Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_variable ADC Private Variable Definition - * @{ - */ -static adc_t *p_AdcObj; -/** - * @} - */ /* End of group ADC_Private_variable */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -static int32_t check_param_sampling_period0(adc_sampling_period0_t param); -static int32_t check_param_sampling_period1(adc_sampling_period1_t param); -static int32_t check_param_prescaler_output(adc_sclk_t param); -static int32_t check_param_interrupt(adc_int_t param); -static int32_t check_param_type(adc_conversion_t param); -static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max); -static void clear_ch_instance_info(adc_ch_t *p_ch); - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param) - * @brief Check the Sampling Period's parameter. - * @param[in] param :Sampling Period's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_sampling_period0(adc_sampling_period0_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SAMPLING_PERIOD0_XN: - case ADC_SAMPLING_PERIOD0_X2N: - case ADC_SAMPLING_PERIOD0_X3N: - case ADC_SAMPLING_PERIOD0_X4N: - case ADC_SAMPLING_PERIOD0_X16N: - case ADC_SAMPLING_PERIOD0_X64N: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param) - * @brief Check the Sampling Period's parameter. - * @param[in] param :Sampling Period's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_sampling_period1(adc_sampling_period1_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SAMPLING_PERIOD1_XN: - case ADC_SAMPLING_PERIOD1_X2N: - case ADC_SAMPLING_PERIOD1_X3N: - case ADC_SAMPLING_PERIOD1_X4N: - case ADC_SAMPLING_PERIOD1_X16N: - case ADC_SAMPLING_PERIOD1_X64N: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_prescaler_output(adc_sclk_t param) - * @brief Check the AD Prescaler Output's parameter. - * @param[in] param :AD Prescaler Output's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_prescaler_output(adc_sclk_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SCLK_1: - case ADC_SCLK_2: - case ADC_SCLK_4: - case ADC_SCLK_8: - case ADC_SCLK_16: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_interrupt(adc_int_t param) - * @brief Check the Interrupt's parameter. - * @param[in] param :Interrupt's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_interrupt(adc_int_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_INT_DISABLE: - case ADC_INT_ENABLE: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_type(adc_conversion_t param) - * @brief Check the Conversion Type's parameter. - * @param[in] param :Conversion Type's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_type(adc_conversion_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_CONVERSION_DISABLE: - case ADC_CONVERSION_CNT: - case ADC_CONVERSION_SGL: - case ADC_CONVERSION_TRG: - case ADC_CONVERSION_HPTG: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) - * @brief Check the AIN Range's parameter. - * @param[in] ain :AIN Range's parameter - * @param[in] min :Range Min. - * @param[in] max :Range Max. - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note - - */ -/*--------------------------------------------------*/ -static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) -{ - int32_t result = ADC_PARAM_NG; - - if (min == 0) - { - if (ain <= max) - { - result = ADC_PARAM_OK; - } - } - else - { - if ((min <= ain) && (ain <= max)) - { - result = ADC_PARAM_OK; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static void clear_ch_instance_info(adc_ch_t *p_ch) - * @brief Channel Instance Information Clear. - * @param[in] p_ch :Channel Instance Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -static void clear_ch_instance_info(adc_ch_t *p_ch) -{ - p_ch->p_tset = ADC_NULL; - p_ch->p_reg = ADC_NULL; - p_ch->init.type = ADC_CONVERSION_DISABLE; -} -/*--------------------------------------------------*/ -/*! - * @fn static void adc_compa_irq_handler( void ) - * @brief IRQ Handler for Compare_A done. - * @param - - * @retval - - * @note Call by Compare_A Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_compa_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL)) - { - p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_compb_irq_handler( void ) - * @brief IRQ Handler for Compare_B done. - * @param - - * @retval - - * @note Call by Compare_B Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_compb_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL)) - { - p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_single_irq_handler( void ) - * @brief IRQ Handler for single conversion done. - * @param - - * @retval - - * @note Call by Single Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_single_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.single != ADC_NULL)) - { - p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_continuity_irq_handler( void ) - * @brief IRQ Handler for continuity conversion done. - * @param - - * @retval - - * @note Call by Continuity Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_continuity_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.continuity != ADC_NULL)) - { - p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_trigger_irq_handler( void ) - * @brief IRQ Handler for trigger conversion done. - * @param - - * @retval - - * @note Call by Trigger Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_trigger_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.trigger != ADC_NULL)) - { - p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_highpriority_irq_handler( void ) - * @brief IRQ Handler for highpriority conversion done. - * @param - - * @retval - - * @note Call by HigPriority Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_highpriority_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.highpriority != ADC_NULL)) - { - p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/** - * @} - */ /* End of group ADC_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup ADC_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_init(adc_t *p_obj) - * @brief Initialize the ADC object. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_init(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - /* Check the parameter. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if ((void*)(p_obj->p_instance) == (void*)0) - { - result = TXZ_ERROR; - } - if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (p_obj->init.clk.sampling_select > 0x0100000) - { - result = TXZ_ERROR; - } - if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if(result == TXZ_SUCCESS) - { - /*------------------------------*/ - /* Init Variable */ - /*------------------------------*/ - uint32_t i; - - for (i=0; iinfo.ch[i]); - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCLK ---*/ - p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld); - /*--- ADxEXAZSEL ---*/ - p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select; - /*--- ADxMOD0 ---*/ - p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - /*--- ADxMOD1 ---*/ - p_obj->p_instance->MOD1 = p_obj->init.mod1; - /*--- ADxMOD2 ---*/ - p_obj->p_instance->MOD2 = p_obj->init.mod2; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_deinit(adc_t *p_obj) - * @brief Release the ADC object. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_deinit(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t i; - adc_ch_t *p_ch; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - /*------------------------------*/ - /* Wait Stop */ - /*------------------------------*/ - /*--- ADxST ---*/ - /* When all convetion stop, ADxST is set "0". */ - while(p_obj->p_instance->ST != 0) - { - /* no processing */ - } - /*------------------------------*/ - /* Channel Class Destruct */ - /*------------------------------*/ - for (i=0; iinfo.ch[i]; - if (p_ch->init.type == ADC_CONVERSION_DISABLE) - { - if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) - { - clear_ch_instance_info(p_ch); - } - } - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCMPEN ---*/ - p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); - /*--- ADxCR1 ---*/ - p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - /*--- ADxMOD0 ---*/ - p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); - /*--- ADxMOD1 ---*/ - p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3; - /*--- ADxMOD2 ---*/ - p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) - * @brief ADC Channel Setting - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @param[in] p_setting :Channel Setting Source Address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_setting) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if(result == TXZ_SUCCESS) - { - /*------------------------------*/ - /* Channel Class Construct */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); - p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); - p_ch->init.interrupt = p_setting->interrupt; - p_ch->init.type = p_setting->type; - p_ch->init.ain = p_setting->ain; - result = adc_ch_init(p_ch); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) - * @brief ADC Channel Clear - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Channel Class Destruct */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - result = adc_ch_deinit(p_ch); - /* Init Variable */ - clear_ch_instance_info(p_ch); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) - * @brief Initialize the ADC Compare register - * @param[in] p_obj :ADC object. - * @param[in] p_cmpx_t :Clock information structure. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_cmpx_t) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Init Variable */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE; - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE) - { - p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP0 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE) - { - p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP1 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP2EN_ENABLE) - { - p_obj->init.CMPxEN[2].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[2].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[2].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[2].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[2].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[2].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[2].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR2 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP2 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP3EN_ENABLE) - { - p_obj->init.CMPxEN[3].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[3].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[3].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[3].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[3].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[3].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[3].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR3 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP3 = p_cmpx_t->ADComp; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) - * @brief Release the ADC Compare register - * @param[in] p_obj :ADC object. - * @param[in] p_cmpx_t :Clock information structure. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_cmpx_t) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) - { - p_obj->init.CMPxEN[0].CMPEN = 0; - p_obj->init.CMPxEN[0].CMPCNT = 0; - p_obj->init.CMPxEN[0].CMPCond = 0; - p_obj->init.CMPxEN[0].CMPBigSml = 0; - p_obj->init.CMPxEN[0].StrReg = 0; - p_obj->init.CMPxEN[0].ADComp = 0; - p_obj->init.CMPxEN[0].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; - p_obj->p_instance->CMPCR0 = 0; - p_obj->p_instance->CMP0 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) - { - p_obj->init.CMPxEN[1].CMPEN = 0; - p_obj->init.CMPxEN[1].CMPCNT = 0; - p_obj->init.CMPxEN[1].CMPCond = 0; - p_obj->init.CMPxEN[1].CMPBigSml = 0; - p_obj->init.CMPxEN[1].StrReg = 0; - p_obj->init.CMPxEN[1].ADComp = 0; - p_obj->init.CMPxEN[1].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; - p_obj->p_instance->CMPCR1 = 0; - p_obj->p_instance->CMP1 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE) - { - p_obj->init.CMPxEN[2].CMPEN = 0; - p_obj->init.CMPxEN[2].CMPCNT = 0; - p_obj->init.CMPxEN[2].CMPCond = 0; - p_obj->init.CMPxEN[2].CMPBigSml = 0; - p_obj->init.CMPxEN[2].StrReg = 0; - p_obj->init.CMPxEN[2].ADComp = 0; - p_obj->init.CMPxEN[2].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE; - p_obj->p_instance->CMPCR2 = 0; - p_obj->p_instance->CMP2 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE) - { - p_obj->init.CMPxEN[3].CMPEN = 0; - p_obj->init.CMPxEN[3].CMPCNT = 0; - p_obj->init.CMPxEN[3].CMPCond = 0; - p_obj->init.CMPxEN[3].CMPBigSml = 0; - p_obj->init.CMPxEN[3].StrReg = 0; - p_obj->init.CMPxEN[3].ADComp = 0; - p_obj->init.CMPxEN[3].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE; - p_obj->p_instance->CMPCR3 = 0; - p_obj->p_instance->CMP3 = 0; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) - * @brief Get AD value - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @param p_value :AD value. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_value) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Get Value */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - result = adc_ch_get_value(p_ch, p_value); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_start(adc_t *p_obj) - * @brief Start Conversion. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_start(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Enable Conversion */ - /*------------------------------*/ - uint32_t i; - adc_ch_t *p_ch; - uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE); - uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - - for (i=0; iinfo.ch[i]; - switch (p_ch->init.type) - { - case ADC_CONVERSION_CNT: - cr0 |= ADxCR0_CNT_ENABLE; - break; - case ADC_CONVERSION_SGL: - cr0 |= ADxCR0_SGL_ENABLE; - break; - case ADC_CONVERSION_TRG: - cr1 |= ADxCR1_TRGEN_ENABLE; - break; - case ADC_CONVERSION_HPTG: - cr1 |= ADxCR1_HPTRGEN_ENABLE; - break; - default: - /* no processing */ - break; - } - } - /*--- ADxCR1 ---*/ - p_obj->p_instance->CR1 = cr1; - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = cr0; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_stop(adc_t *p_obj) - * @brief Stop Conversion. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_stop(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t i; - adc_ch_t *p_ch; - uint32_t value; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Disable Conversion */ - /*------------------------------*/ - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - /*------------------------------*/ - /* Wait Stop */ - /*------------------------------*/ - /*--- ADxST ---*/ - /* When all convetion stop, ADxST is set "0". */ - while(p_obj->p_instance->ST != 0) - { - /* no processing */ - } - /*------------------------------*/ - /* Dummy Read */ - /*------------------------------*/ - /* Read is needed before the next convertion. */ - for (i=0; iinfo.ch[i]; - if (p_ch->init.type == ADC_CONVERSION_DISABLE) - { - if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) - { - /* no processing */ - } - } - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) - * @brief Wait for single conversion to be completed - * @param[in] p_obj :ADC object. - * @param[in] timeout :Timeout(tick). - * @retval TXZ_DONE :Success. - * @retval TXZ_BUSY :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) -{ - TXZ_WorkState result = TXZ_BUSY; - TXZ_WorkState loopBreak = TXZ_BUSY; - uint32_t base = hal_get_tick(); - uint32_t current = 0; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_DONE; - } - else - { - /*------------------------------*/ - /* Check Status */ - /*------------------------------*/ - while(loopBreak == TXZ_BUSY) - { - /*--- Check Status ---*/ - /* Read status. */ - status = p_obj->p_instance->ST; - /* Check status. */ - if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE) - { - result = TXZ_DONE; - loopBreak = TXZ_DONE; - } - else - { - /*--- Check Timeout ---*/ - if (timeout == 0) - { - loopBreak = TXZ_DONE; - } - else - { - current = hal_get_tick(); - if (current > base) - { - if ((current - base) >= timeout) - { - loopBreak = TXZ_DONE; - } - } - else - { - base = current; - } - } - } - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) - * @brief Get Conversion Status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-8 | - | - | - * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. | - * | 6-4 | - | - | - * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. | - * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. | - * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. | - * | 0 | - | - | - * - * @param[in] p_obj :ADC object. - * @param[out] p_status :Conversion Status. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_status) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Read Register */ - /*------------------------------*/ - *p_status = p_obj->p_instance->ST; - } - - return (result); -} -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__ADC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c deleted file mode 100644 index cddd4de4cf4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c +++ /dev/null @@ -1,351 +0,0 @@ -/** - ******************************************************************************* - * @file adc_ch.c - * @brief This file provides API functions for ADC driver. \n - * Channel Class. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "adc_include.h" -#include "adc_ch.h" - -#if defined(__ADC_CH_H) -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @addtogroup ADC - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -#ifdef DEBUG - /* no define */ -#endif - -/** - * @} - */ /* End of group ADC_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup ADC_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn static uint32_t get_conversion_data(uint32_t reg) - * @brief Get convertion data from ADxREGn. - * @param[in] reg :ADxREGn data. - * @retval Convertion data. - * @note - - */ -/*--------------------------------------------------*/ -uint32_t get_conversion_data(uint32_t reg) -{ - uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); - - return (result); -} -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj) - * @brief Initialize the ADC Channel object. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_init(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxREGx ---*/ - /* Read is needed before the next convertion. */ - { - volatile uint32_t reg; - reg = *p_obj->p_reg; - } - /*--- ADxTSET ---*/ - *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) - * @brief Release the ADC Channel object. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); - /*--- ADxREGx ---*/ - /* Read is needed before the next convertion. */ - { - volatile uint32_t reg; - reg = *p_obj->p_reg; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) - * @brief Enable Interrupt. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - { - uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); - - *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) - * @brief Disable Interrupt. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - { - uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); - - *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) - * @brief Get conversion value. - * @param p_obj :ADC Channel object. - * @param p_value :AD value. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has done. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) -{ - TXZ_Result result = TXZ_ERROR; - uint32_t reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - reg = *p_obj->p_reg; - /*------------------------------*/ - /* Check Result */ - /*------------------------------*/ - if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) - { - *p_value = get_conversion_data(reg); - result = TXZ_SUCCESS; - } - } - - return (result); -} -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__ADC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c deleted file mode 100644 index 564d8270577..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c +++ /dev/null @@ -1,646 +0,0 @@ -/** - ******************************************************************************* - * @file fc.c - * @brief Flash_Userboot Sample Application. - * @version V1.0.1.0 - * $Date:: 2017-06-23 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include -#include "tmpm4g9_fc.h" -//#include "txz_sample_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @defgroup Flash_Userboot Flash_Userboot Sample Appli - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ -#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ -#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ -#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ -#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ -#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ - -/****************** Changed by TSIP *************************************/ -///* Area Selection All */ -#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) -#define FC_AREASEL_AREA0 (uint32_t)(0x00000777UL) //select Area 0,1 and 2 -#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0888UL) //mask Area 0,1 and 2 -#define FC_AREASEL_WRITE_MODE (uint32_t)(0x1C000000UL) - -static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { - (0x5E000000UL), /*!< CODE FLASH Page0 */ - (0x5E001000UL), /*!< CODE FLASH Page1 */ - (0x5E002000UL), /*!< CODE FLASH Page2 */ - (0x5E003000UL), /*!< CODE FLASH Page3 */ - (0x5E004000UL), /*!< CODE FLASH Page4 */ - (0x5E005000UL), /*!< CODE FLASH Page5 */ - (0x5E006000UL), /*!< CODE FLASH Page6 */ - (0x5E007000UL), /*!< CODE FLASH Page7 */ - (0x5E008000UL), /*!< CODE FLASH Page8 */ - (0x5E009000UL), /*!< CODE FLASH Page9 */ - (0x5E00A000UL), /*!< CODE FLASH Page10 */ - (0x5E00B000UL), /*!< CODE FLASH Page11 */ - (0x5E00C000UL), /*!< CODE FLASH Page12 */ - (0x5E00D000UL), /*!< CODE FLASH Page13 */ - (0x5E00E000UL), /*!< CODE FLASH Page14 */ - (0x5E00F000UL), /*!< CODE FLASH Page15 */ - (0x5E010000UL), /*!< CODE FLASH Page16 */ - (0x5E011000UL), /*!< CODE FLASH Page17 */ - (0x5E012000UL), /*!< CODE FLASH Page18 */ - (0x5E013000UL), /*!< CODE FLASH Page19 */ - (0x5E014000UL), /*!< CODE FLASH Page20 */ - (0x5E015000UL), /*!< CODE FLASH Page21 */ - (0x5E016000UL), /*!< CODE FLASH Page22 */ - (0x5E017000UL), /*!< CODE FLASH Page23 */ - (0x5E018000UL), /*!< CODE FLASH Page24 */ - (0x5E019000UL), /*!< CODE FLASH Page25 */ - (0x5E01A000UL), /*!< CODE FLASH Page26 */ - (0x5E01B000UL), /*!< CODE FLASH Page27 */ - (0x5E01C000UL), /*!< CODE FLASH Page28 */ - (0x5E01D000UL), /*!< CODE FLASH Page29 */ - (0x5E01E000UL), /*!< CODE FLASH Page30 */ - (0x5E01F000UL) /*!< CODE FLASH Page31 */ -}; - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -/** - * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables - * @{ - */ -/** - * @} - */ /* End of group Flash_Userboot_Private_variables */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions - * @{ - */ -__STATIC_INLINE TXZ_Result fc_enable_areasel(void); -__STATIC_INLINE TXZ_Result fc_disable_areasel(void); -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static TXZ_Result fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind); -static TXZ_Result fc_blank_check(uint32_t* address, uint32_t size); - -/*--------------------------------------------------*/ -/** - * @brief Enables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_enable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_AREA0; - } - - /* Confirms the FCAREASEL register the SSF0 was set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Disables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_disable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_EXPECT_AREA0; - } - - /* Confirms the SSF0 of the FCAREASEL register is not set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Writes data of the Flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return - - * @note It works in the inner RAM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval; - /******** Changed/Added by TSIP next 12 lines *************/ - volatile uint32_t* addr1; - volatile uint32_t* addr2; - if(dst_address <= (uint32_t *)0x0007FFFFUL) { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); - } else if(dst_address <= (uint32_t *)0x000FFFFF) { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x10000); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x10000); - } else { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x100000); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x100000); - } - volatile uint32_t* addr3 = (uint32_t *) ((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); - uint32_t* source = (uint32_t *) src_address; - - /* Enables the AREA0. Write Mode. */ - retval = fc_enable_areasel(); - - if(retval == TXZ_SUCCESS){ - uint32_t i; - - *addr1 = (0x000000AAUL); /* bus cycle 1 */ - *addr2 = (0x00000055UL); /* bus cycle 2 */ - *addr1 = (0x000000A0UL); /* bus cycle 3 */ - for(i=(0UL); iSR0 & (uint32_t)status; - - /* Confirms the specific status of the flash ROM */ - if(work32 == (uint32_t)status){ - retval = TXZ_DONE; - } - - return (retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Auto write command of the code flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function writes 16bytes data to the code Flash ROM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval = TXZ_SUCCESS; - - /* Checks the code Flash ROM status */ - if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){ - - uint32_t i; - /* Checks the code Flash ROM status */ - for(i=0;ip_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) - { - case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */ - result = SystemCoreClock / CG_FSYSM_1_DIV; - break; - case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */ - result = SystemCoreClock / CG_FSYSM_2_DIV; - break; - case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */ - result = SystemCoreClock / CG_FSYSM_4_DIV; - break; - default: - result = 0U; - break; - } - return (result); - -} - -/*--------------------------------------------------*/ -/** - * @brief Update PrescalerClock according register values. - * @param p_obj :CG object. - * @retval PrescalerClock Frequency. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint32_t cg_get_phyt0(cg_t *p_obj) -{ - uint32_t result = 0U; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - /* Get Gear status. */ - switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) - { - case CG_FSYS_1: /* Gear -> fc */ - result = SystemCoreClock * CG_FSYS_1_MUL; - break; - case CG_FSYS_2: /* Gear -> fc/2 */ - result = SystemCoreClock * CG_FSYS_2_MUL; - break; - case CG_FSYS_4: /* Gear -> fc/4 */ - result = SystemCoreClock * CG_FSYS_4_MUL; - break; - case CG_FSYS_8: /* Gear -> fc/8 */ - result = SystemCoreClock * CG_FSYS_8_MUL; - break; - case CG_FSYS_16: /* Gear -> fc/16 */ - result = SystemCoreClock * CG_FSYS_16_MUL; - break; - default: - result = 0U; - break; - } - - switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) - { - case CG_PRCKST_1: /* ��T0 -> fc */ - result /= CG_PRCK_1_DIV; - break; - case CG_PRCKST_2: /* ��T0 -> fc/2 */ - result /= CG_PRCK_2_DIV; - break; - case CG_PRCKST_4: /* ��T0 -> fc/4 */ - result /= CG_PRCK_4_DIV; - break; - case CG_PRCKST_8: /* ��T0 -> fc/8 */ - result /= CG_PRCK_8_DIV; - break; - case CG_PRCKST_16: /* ��T0 -> fc/16 */ - result /= CG_PRCK_16_DIV; - break; - case CG_PRCKST_32: /* ��T0 -> fc/32 */ - result /= CG_PRCK_32_DIV; - break; - case CG_PRCKST_64: /* ��T0 -> fc/64 */ - result /= CG_PRCK_64_DIV; - break; - case CG_PRCKST_128: /* ��T0 -> fc/128 */ - result /= CG_PRCK_128_DIV; - break; - case CG_PRCKST_256: /* ��T0 -> fc/256 */ - result /= CG_PRCK_256_DIV; - break; - case CG_PRCKST_512: /* ��T0 -> fc/512 */ - result /= CG_PRCK_512_DIV; - break; - default: - result = 0U; - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Update Middle PrescalerClock according register values. - * @param p_obj :CG object. - * @retval Middle PrescalerClock Frequency. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint32_t cg_get_mphyt0(cg_t *p_obj) -{ - uint32_t result = 0U; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - /* Get Gear status. */ - switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) - { - case CG_FSYS_1: /* Gear -> fc */ - result = SystemCoreClock * CG_FSYS_1_MUL; - break; - case CG_FSYS_2: /* Gear -> fc/2 */ - result = SystemCoreClock * CG_FSYS_2_MUL; - break; - case CG_FSYS_4: /* Gear -> fc/4 */ - result = SystemCoreClock * CG_FSYS_4_MUL; - break; - case CG_FSYS_8: /* Gear -> fc/8 */ - result = SystemCoreClock * CG_FSYS_8_MUL; - break; - case CG_FSYS_16: /* Gear -> fc/16 */ - result = SystemCoreClock * CG_FSYS_16_MUL; - break; - default: - result = 0U; - break; - } - switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) - { - case CG_PRCKST_1: /* ��T0 -> fc */ - result /= CG_PRCK_1_DIV; - break; - case CG_PRCKST_2: /* ��T0 -> fc/2 */ - result /= CG_PRCK_2_DIV; - break; - case CG_PRCKST_4: /* ��T0 -> fc/4 */ - result /= CG_PRCK_4_DIV; - break; - case CG_PRCKST_8: /* ��T0 -> fc/8 */ - result /= CG_PRCK_8_DIV; - break; - case CG_PRCKST_16: /* ��T0 -> fc/16 */ - result /= CG_PRCK_16_DIV; - break; - case CG_PRCKST_32: /* ��T0 -> fc/32 */ - result /= CG_PRCK_32_DIV; - break; - case CG_PRCKST_64: /* ��T0 -> fc/64 */ - result /= CG_PRCK_64_DIV; - break; - case CG_PRCKST_128: /* ��T0 -> fc/128 */ - result /= CG_PRCK_128_DIV; - break; - case CG_PRCKST_256: /* ��T0 -> fc/256 */ - result /= CG_PRCK_256_DIV; - break; - case CG_PRCKST_512: /* ��T0 -> fc/512 */ - result /= CG_PRCK_512_DIV; - break; - default: - result = 0U; - break; - } - - switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) - { - case CG_MCKSELPST_1: /* ��T0 -> fc/PRCK */ - result /= CG_FSYSM_1_DIV; - break; - case CG_MCKSELPST_2: /* ��T0 -> fc/PRCK/2 */ - result /= CG_FSYSM_2_DIV; - break; - case CG_MCKSELPST_4: /* ��T0 -> fc/PRCK/4 */ - result /= CG_FSYSM_4_DIV; - break; - default: - result = 0U; - break; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Internal high-speed oscillator enable. - * @param p_obj :CG object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result cg_ihosc_enable(cg_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* Internal high-speed oscillator is enable. */ - (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Internal high-speed oscillator disable. - * @param p_obj :CG object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result cg_ihosc_disable(cg_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* Internal high-speed oscillator is disable. */ - (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_DISABLE; - - return (result); -} -/** - * @} - */ /* End of group CG_Exported_functions */ - -/** - * @} - */ /* End of group CG */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__CG_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c deleted file mode 100644 index 157ceaab0cb..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c +++ /dev/null @@ -1,1438 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart.c - * @brief This file provides API functions for FUART driver. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_fuart_include.h" -#include "txz_fuart.h" - -#if defined(__FUART_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/** - * @defgroup FUART_BourateConfig Bourate Setting Configuration - * @brief Bourate Setting Configuration. - * @{ - */ -#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ -#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ -#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */ - -#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ -#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ -#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */ - -#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */ -#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ -/** - * @} - */ /* End of group FUART_BourateConfig */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_typedef FUART Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_fuctions FUART Private Fuctions - * @{ - */ -#ifdef DEBUG - __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); - __STATIC_INLINE int32_t check_param_data_length(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_err_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeK(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeN(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); -#endif /* #ifdef DEBUG */ -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) - static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); -#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the CTS Handshake's parameter. - * @param param :CTS Handshake's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_CTS_DISABLE: - case FUART_CTS_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the RTS Handshake's parameter. - * @param param :RTS Handshake's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_RTS_DISABLE: - case FUART_RTS_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Stop Bit's parameter. - * @param param :Stop Bit's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_STOP_BIT_1: - case FUART_STOP_BIT_2: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_PARITY_BIT_ODD: - case FUART_PARITY_BIT_EVEN: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_PARITY_DISABLE: - case FUART_PARITY_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_length(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_DATA_LENGTH_5: - case FUART_DATA_LENGTH_6: - case FUART_DATA_LENGTH_7: - case FUART_DATA_LENGTH_8: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level Range's parameter. - * @param param :Tx Fill Level Range's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_FIFO_LEVEL_4: - case FUART_FIFO_LEVEL_8: - case FUART_FIFO_LEVEL_16: - case FUART_FIFO_LEVEL_24: - case FUART_FIFO_LEVEL_28: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_FIFO_LEVEL_4: - case FUART_FIFO_LEVEL_8: - case FUART_FIFO_LEVEL_16: - case FUART_FIFO_LEVEL_24: - case FUART_FIFO_LEVEL_28: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_TX_INT_DISABLE: - case FUART_TX_INT_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_RX_INT_DISABLE: - case FUART_RX_INT_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrpt's parameter. - * @param param :Error Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_err_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE); - - if(param == 0){ - result = FUART_PARAM_OK; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Range K's parameter. - * @param param :Range K's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - /*--- Now, FUART_RANGE_K_MIN is 0. ---*/ -#if 0 - if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX)) -#else - if (param <= FUART_RANGE_K_MAX) -#endif - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range N's parameter. - * @param param :Range N's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX)) - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for transmit. - * @param param :Num of buff. - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if (param != 0) - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for receive. - * @param param :Num of buff. - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if (param != 0) - { - result = FUART_PARAM_OK; - } - - return (result); -} -#endif /* #ifdef DEBUG */ - -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) -/*--------------------------------------------------*/ -/** - * @brief Check the within error margin. - * @param boudrate :Boudrate(bps). - * @param clock :Clock(hz). - * @param boudrate :Boudrate(bps). - * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" - * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" - * @param p_range64 :Error range(after fixed point bit shift). - * @retval TXZ_SUCCESS :Within error margin. - * @retval TXZ_ERROR :Without error margin. - * @note For N+(64-K)/64 division. - */ -/*--------------------------------------------------*/ -static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) -{ - TXZ_Result result = TXZ_ERROR; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 0; - - /* phi T0 */ - tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT+2)); - - /* Bourate */ - boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); - *p_range64 = ((boud64/100)*FUART_CFG_BOUDRATE_ERROR_RANGE); - /* BourateX */ - work64 = (uint64_t)((uint64_t)n << 6); - work64 = (uint64_t)(work64 + (uint64_t)k); - work64 = (tx64 / work64); - if (boud64 >= *p_range64) - { - if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) - { - if( boud64 < work64 ) - { - *p_range64 = (work64 - boud64); - } - else - { - *p_range64 = (boud64 - work64); - } - result = TXZ_SUCCESS; - } - } - - return (result); -} -#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - -/** - * @} - */ /* End of group FUART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the FUART object. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_init(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); - assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); - assert_param(check_param_tx_int(p_obj->init.tx_int.inttx)); - assert_param(check_param_rx_int(p_obj->init.rx_int.intrx)); - assert_param(check_param_err_int(p_obj->init.interr)); - assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level)); - assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level)); - assert_param(check_param_cts_handshake(p_obj->init.ctse)); - assert_param(check_param_rts_handshake(p_obj->init.rtse)); - assert_param(check_param_stop_bit(p_obj->init.sblen)); - assert_param(check_param_parity_bit(p_obj->init.even)); - assert_param(check_param_parity_enable(p_obj->init.pe)); - assert_param(check_param_data_length(p_obj->init.sm)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable FUART */ - /*------------------------------*/ - p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | - FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); - /*------------------------------*/ - /* Interrupt Disable */ - /*------------------------------*/ - p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | - FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | - FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | - FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | - FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); - - /*------------------------------*/ - /* FIFO Disable */ - /*------------------------------*/ - p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - p_obj->p_instance->BRD = p_obj->init.boudrate.brn; - p_obj->p_instance->FBRD = p_obj->init.boudrate.brk; - p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm | - p_obj->init.fifo | p_obj->init.sblen | - p_obj->init.even | p_obj->init.pe); - p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level); - p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx); - p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the FUART object. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_deinit(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable FUART */ - /*------------------------------*/ - p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | - FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); - /*------------------------------*/ - /* Interrupt Disable */ - /*------------------------------*/ - p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | - FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | - FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | - FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | - FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); - /*------------------------------*/ - /* FIFO Disable */ - /*------------------------------*/ - p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_discard_transmit(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - disable_FUARTxCR_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_discard_receive(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - disable_FUARTxCR_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :FUART object. - * @param p_info :The information of transmit data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); - assert_param(check_param_tx_buff_num(p_info->num)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - p_obj->transmit.info.p_data = p_info->p_data; - p_obj->transmit.info.num = p_info->num; - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - volatile uint32_t fr_reg; - - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- FUARTxDR ---*/ - if (p_obj->transmit.info.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=1). */ - /* Bitband Access. */ - enable_FUARTxCR_TXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :FUART object. - * @param p_info :The information of receive buffer. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - volatile uint8_t dummy; - volatile uint32_t fr_reg; - uint32_t rx_count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); - assert_param(check_param_rx_buff_num(p_info->num)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_RXE(p_obj->p_instance); - /* FIFO CLR */ - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) - { - dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - if(p_obj->init.fifo == 1) - { - if(++rx_count > FUART_RX_FIFO_MAX) - { - break; - } - } - else{ - if(++rx_count > 1) - { - break; - } - } - fr_reg = p_obj->p_instance->FR; - } - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->receive.wp = 0; - p_obj->receive.info.p_data = p_info->p_data; - p_obj->receive.info.num = p_info->num; - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to RXE(=1). */ - /* Bitband Access. */ - enable_FUARTxCR_RXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_transmit_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - volatile uint32_t fr_reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE) - { - if (p_obj->transmit.info.num <= p_obj->transmit.rp) - { - /*=== Transmit Done!! ===*/ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - /* disable_FUARTxCR_TXE(p_obj->p_instance); */ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != FUART_NULL) - { - /* Call the transmit handler with TXZ_SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- FUARTxDR ---*/ - if (p_obj->transmit.info.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_receive_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - volatile uint32_t fr_reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) - { - uint32_t rx_count = 0; - - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) - { - *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - p_obj->receive.wp += 1; - if(p_obj->receive.wp >= p_obj->receive.info.num) - { - break; - } - if(p_obj->init.fifo == 1) - { - if(++rx_count >= FUART_RX_FIFO_MAX) - { - break; - } - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if(p_obj->receive.wp >= p_obj->receive.info.num) - { - if(p_obj->receive.handler != FUART_NULL) - { - fuart_receive_t param; - param.p_data = p_obj->receive.info.p_data; - param.num = p_obj->receive.wp; - p_obj->receive.wp = 0; - /* Call the receive handler with TXZ_SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_error_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - uint32_t error; - uint32_t ecr_reg = 0x00; - uint32_t icr_reg = 0x00; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current FUARTxRSR. */ - error = p_obj->p_instance->RSR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- FUARTxRSR ---*/ - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* OVER RUN */ - if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR) - { - volatile uint8_t dummy; - - icr_reg |= FUARTxICR_OEIC_CLR; - ecr_reg |= FUARTxECR_OE_CLR; - dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - err = TXZ_ERROR; - } - /* BREAK */ - if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR) - { - icr_reg |= FUARTxICR_BEIC_CLR; - ecr_reg |= FUARTxECR_BE_CLR; - err = TXZ_ERROR; - } - /* PARITY */ - if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR) - { - icr_reg |= FUARTxICR_PEIC_CLR; - ecr_reg |= FUARTxECR_PE_CLR; - err = TXZ_ERROR; - } - /* FRAMING */ - if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR) - { - icr_reg |= FUARTxICR_FEIC_CLR; - ecr_reg |= FUARTxECR_FE_CLR; - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - p_obj->p_instance->ICR = icr_reg; - p_obj->p_instance->ECR = ecr_reg; - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != FUART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for timeout error. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_timeout_error_irq_handler(fuart_t *p_obj) -{ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != FUART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler . - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_irq_handler(fuart_t *p_obj) -{ - uint32_t interrupt_status = p_obj->p_instance->MIS; - if((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK; - fuart_receive_irq_handler(p_obj); - } - if((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK; - fuart_transmit_irq_handler(p_obj); - } - if((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0) - { - p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK); - fuart_error_irq_handler(p_obj); - } - if((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK; - fuart_timeout_error_irq_handler(p_obj); - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | 31-8 | - | - | - * | 7 | TXFE | Transmit FIFO Empty Flag. | - * | 6 | RXFF | Reach Receive Fill Level Flag. | - * | 5 | TXFF | Reach Transmit Fill Level Flag. | | - * | 4 | RXFE | Receive FIFO Empty Flag. | - * | 3 | BUSY | Transmit BUSY Flag. | - * | 2-1 | - | - | - * | 0 | CTS | FUTxCTS Flag. | - * - * @param p_obj :FUART object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - /*--- FUARTxFR ---*/ - /* Read current FUARTxFR. */ - *p_status = p_obj->p_instance->FR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-4 | - | - | - * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. | - * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. | - * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. | - * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. | - * - * @param p_obj :FUART object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_error)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Read */ - /*------------------------------*/ - /*--- FUARTxRSR ---*/ - /* Read current FUARTxRSR. */ - *p_error = p_obj->p_instance->RSR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get the setting of boudrate. - * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". - * @param boudrate :Boudrate(bps). - * @param p_brd :Save area for Division Setting. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Not support setting. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd) -{ - TXZ_Result result = TXZ_ERROR; -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) - uint64_t tx = 0; - uint64_t work = 0; - uint64_t range64 = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_brd)); - /* Check the parameter of FUARTxCLK. */ -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Calculate Division Setting */ - /*------------------------------*/ - if ((clock > 0) && (boudrate > 0)) - { - /*--- phi T0 ---*/ - tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); - - /*--- N+(K/64) division ---*/ - { - uint8_t k = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) - { - work = tx - (uint64_t)k; - work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ - if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX)) - { - uint64_t workRange = 0; - /* Verification */ - if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) - { -#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL) - /* Compare the previous range. */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - } - else - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - result = TXZ_SUCCESS; -#else - /* Finish!! */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - } - else - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - result = TXZ_SUCCESS; - loopBreak = TXZ_DONE; -#endif - } - } - } - } - } -#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - - return (result); -} - -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c deleted file mode 100644 index 131037c5f73..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c +++ /dev/null @@ -1,206 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_ex.c - * @brief This file provides API functions for FUART driver. - * @brief Extended functionality. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_fuart_include.h" -#include "txz_fuart_ex.h" - -#if defined(__FUART_EX_H) - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_fuctions - * @{ - */ - -/** - * @} - */ /* End of group FUART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Send Break. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_send_break(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Set Break */ - /*------------------------------*/ - { - uint32_t trans = p_obj->p_instance->LCR_H; - - trans &= ~FUARTxLCR_H_BRK_MASK; - trans |= FUARTxLCR_H_BRK_SEND; - p_obj->p_instance->LCR_H = trans; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Stop Break. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_stop_break(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Set Break */ - /*------------------------------*/ - { - uint32_t trans = p_obj->p_instance->LCR_H; - - trans &= ~FUARTxLCR_H_BRK_MASK; - trans |= FUARTxLCR_H_BRK_STOP; - p_obj->p_instance->LCR_H = trans; - } - - return (result); -} - - -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_EX_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c deleted file mode 100644 index f7f84fd125e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c +++ /dev/null @@ -1,4751 +0,0 @@ -/** - ******************************************************************************* - * @file txz_gpio.c - * @brief This file provides API functions for GPIO driver. - * @version V1.0.0.2 - * $Date:: 2018-04-11 14:13:48 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_gpio.h" - -#if defined(__GPIO_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup GPIO - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_define GPIO Private Define - * @{ - */ -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name Bit Operation Macro - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ -#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */ -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */ -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */ -#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)(0x0000001UL<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */ -/** - * @} - */ /* End of Bit Operation Macro */ -/** - * @} - */ /* End of group GPIO_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_define GPIO Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group GPIO_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_typedef GPIO Private Typedef - * @{ - */ -/*! - * @brief Pin Exist Table - * @details Bit0 :GPIO_Mode_DATA - * @details Bit1 :GPIO_Mode_CR - * @details Bit2 :GPIO_Mode_FR1 - * @details Bit3 :GPIO_Mode_FR2 - * @details Bit4 :GPIO_Mode_FR3 - * @details Bit5 :GPIO_Mode_FR4 - * @details Bit6 :GPIO_Mode_FR5 - * @details Bit7 :GPIO_Mode_FR6 - * @details Bit8 :GPIO_Mode_FR7 - * @details Bit9 :GPIO_Mode_OD - * @details Bit10 :GPIO_Mode_PUP - * @details Bit11 :GPIO_Mode_PDN - * @details Bit12 :GPIO_Mode_IE - */ -#if defined(TMPM4G6) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x0000, 0x0000, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E47, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1F03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x1E53, 0x1E53, 0x1F53, 0x1F53, 0x1E5B, 0x1E5B, 0x1F43, 0x1F43 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x1E1B, 0x1E0B, 0x1E1B, 0x1E0F }, /** GPIO_PORT_L */ - { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x1F1B, 0x1F0B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F0B }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x1EE3, 0x1F63, 0x1F63, 0x1E63, 0x1FD3, 0x1FC3, 0x1FC3, 0x1FD3 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G9 */ - -/** - * @} - */ /* End of group GPIO_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_fuctions GPIO Private Fuctions - * @{ - */ - -static uint8_t change_mode_to_num( uint32_t mode ); -static uint8_t change_func_to_num( uint32_t mode ); -static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); -static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) - * @brief Check the Pin Exist. - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - */ -/*--------------------------------------------------*/ - -static uint8_t change_mode_to_num( uint32_t mode ) -{ - uint8_t retVal = 0; - - if (mode == GPIO_Mode_DATA) {retVal = 0;} - else if (mode == GPIO_Mode_CR) {retVal = 1;} - else if (mode == GPIO_Mode_FR1) {retVal = 2;} - else if (mode == GPIO_Mode_FR2) {retVal = 3;} - else if (mode == GPIO_Mode_FR3) {retVal = 4;} - else if (mode == GPIO_Mode_FR4) {retVal = 5;} - else if (mode == GPIO_Mode_FR5) {retVal = 6;} - else if (mode == GPIO_Mode_FR6) {retVal = 7;} - else if (mode == GPIO_Mode_FR7) {retVal = 8;} - else if (mode == GPIO_Mode_OD) {retVal = 9;} - else if (mode == GPIO_Mode_PUP) {retVal = 10;} - else if (mode == GPIO_Mode_PDN) {retVal = 11;} - else if (mode == GPIO_Mode_IE) {retVal = 12;} - else {retVal = 13;} - - return retVal; -} - -static uint8_t change_func_to_num( uint32_t mode ) -{ - uint8_t retVal = 0; - - if (mode == GPIO_FR_1) {retVal = 2;} - else if (mode == GPIO_FR_2) {retVal = 3;} - else if (mode == GPIO_FR_3) {retVal = 4;} - else if (mode == GPIO_FR_4) {retVal = 5;} - else if (mode == GPIO_FR_5) {retVal = 6;} - else if (mode == GPIO_FR_6) {retVal = 7;} - else if (mode == GPIO_FR_7) {retVal = 8;} - else if (mode == GPIO_FR_NA) {retVal = 1;} - else if (mode == 0) {retVal = 1;} - else {retVal = 13;} - - return retVal; -} - -static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) -{ - int32_t result = PARAM_NG; - uint8_t chgmode; - uint16_t tmp; - - chgmode = change_mode_to_num(mode); - if ((chgmode < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) - { - tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; - result = PARAM_OK; - if (tmp == 0){ result = PARAM_NG;} - } - else - { - result = PARAM_NG; - } - - return (result); -} -static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) -{ - int32_t result = PARAM_NG; - uint8_t chgfunc; - uint16_t tmp; - - chgfunc = change_func_to_num(mode); - /* param check skip if func is INPUT or OUTPUT */ - if(chgfunc == 1) - { - return (PARAM_OK); - } - if ((chgfunc < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) - { - tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; - result = PARAM_OK; - if (tmp == 0){ result = PARAM_NG;} - } - else - { - result = PARAM_NG; - } - - return (result); -} -/** - * @} - */ /* End of group GPIO_Private_functions */ - - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup GPIO_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) - * @brief Initialize the GPIO object. - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) -{ - TXZ_Result result = TXZ_SUCCESS; - - /* Check the NULL of address. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_M: - /* PM Clock Enable */ - TSB_CG_FSYSMENB_IPMENB13 = 1U; - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_J: - /* PJ Clock Enable */ - TSB_CG_FSYSMENB_IPMENB10 = 1U; - p_obj->p_pj_instance->DATA = 0x00; - p_obj->p_pj_instance->CR = 0x00; - p_obj->p_pj_instance->FR2 = 0x00; - p_obj->p_pj_instance->FR3 = 0x00; - p_obj->p_pj_instance->FR5 = 0x00; - p_obj->p_pj_instance->FR7 = 0x00; - p_obj->p_pj_instance->OD = 0x00; - p_obj->p_pj_instance->PUP = 0x00; - p_obj->p_pj_instance->PDN = 0x00; - p_obj->p_pj_instance->IE = 0x00; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_M: - /* PM Clock Enable */ - TSB_CG_FSYSMENB_IPMENB13 = 1U; - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_U: - /* PU Clock Enable */ - TSB_CG_FSYSMENB_IPMENB18 = 1U; - p_obj->p_pu_instance->DATA = 0x00; - p_obj->p_pu_instance->CR = 0x00; - p_obj->p_pu_instance->FR2 = 0x00; - p_obj->p_pu_instance->FR3 = 0x00; - p_obj->p_pu_instance->FR7 = 0x00; - p_obj->p_pu_instance->OD = 0x00; - p_obj->p_pu_instance->PUP = 0x00; - p_obj->p_pu_instance->PDN = 0x00; - p_obj->p_pu_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_W: - /* PW Clock Enable */ - TSB_CG_FSYSMENB_IPMENB20 = 1U; - p_obj->p_pw_instance->DATA = 0x00; - p_obj->p_pw_instance->CR = 0x00; - p_obj->p_pw_instance->FR3 = 0x00; - p_obj->p_pw_instance->FR4 = 0x00; - p_obj->p_pw_instance->FR5 = 0x00; - p_obj->p_pw_instance->FR6 = 0x00; - p_obj->p_pw_instance->FR7 = 0x00; - p_obj->p_pw_instance->OD = 0x00; - p_obj->p_pw_instance->PUP = 0x00; - p_obj->p_pw_instance->PDN = 0x00; - p_obj->p_pw_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) - * @brief Release the GPIO object. - * @param p_obj :GPIO object. - * @param group :GPIO Port Group.: Use @ref gpio_gr_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) -{ - TXZ_Result result = TXZ_SUCCESS; - - /* Check the NULL of address. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - /* Disable the selected GPIO peripheral */ - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_M: - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - /* PM Clock Disable */ - TSB_CG_FSYSMENB_IPMENB13 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_J: - p_obj->p_pj_instance->DATA = 0x00; - p_obj->p_pj_instance->CR = 0x00; - p_obj->p_pj_instance->FR2 = 0x00; - p_obj->p_pj_instance->FR3 = 0x00; - p_obj->p_pj_instance->FR5 = 0x00; - p_obj->p_pj_instance->FR7 = 0x00; - p_obj->p_pj_instance->OD = 0x00; - p_obj->p_pj_instance->PUP = 0x00; - p_obj->p_pj_instance->PDN = 0x00; - p_obj->p_pj_instance->IE = 0x00; - /* PJ Clock Disable */ - TSB_CG_FSYSMENB_IPMENB10 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_M: - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - /* PM Clock Disable */ - TSB_CG_FSYSMENB_IPMENB13 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_U: - p_obj->p_pu_instance->DATA = 0x00; - p_obj->p_pu_instance->CR = 0x00; - p_obj->p_pu_instance->FR2 = 0x00; - p_obj->p_pu_instance->FR3 = 0x00; - p_obj->p_pu_instance->FR7 = 0x00; - p_obj->p_pu_instance->OD = 0x00; - p_obj->p_pu_instance->PUP = 0x00; - p_obj->p_pu_instance->PDN = 0x00; - p_obj->p_pu_instance->IE = 0x00; - /* PU Clock Disable */ - TSB_CG_FSYSMENB_IPMENB18 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_W: - p_obj->p_pw_instance->DATA = 0x00; - p_obj->p_pw_instance->CR = 0x00; - p_obj->p_pw_instance->FR3 = 0x00; - p_obj->p_pw_instance->FR4 = 0x00; - p_obj->p_pw_instance->FR5 = 0x00; - p_obj->p_pw_instance->FR6 = 0x00; - p_obj->p_pw_instance->FR7 = 0x00; - p_obj->p_pw_instance->OD = 0x00; - p_obj->p_pw_instance->PUP = 0x00; - p_obj->p_pw_instance->PDN = 0x00; - p_obj->p_pw_instance->IE = 0x00; - /* PW Clock Disable */ - TSB_CG_FSYSMENB_IPMENB20 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) - * @brief Port Mode Write - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t - * @param[in] val :value - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t i; - int32_t param_result = PARAM_NG; - - /* Check the parameters, the NULL of address */ - for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) - { - param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); - if(param_result == PARAM_OK) - { - break; - } - else - { - result = TXZ_ERROR; - } - } - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_J: - if(mode == GPIO_Mode_DATA) {p_obj->p_pj_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pj_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pj_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pj_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pj_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pj_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pj_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pj_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pj_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pj_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_U: - if(mode == GPIO_Mode_DATA) {p_obj->p_pu_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pu_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pu_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pu_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pu_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pu_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pu_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pu_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pu_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_W: - if(mode == GPIO_Mode_DATA) {p_obj->p_pw_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pw_instance->CR = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pw_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pw_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pw_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pw_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pw_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pw_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pw_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pw_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pw_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) - * @brief Port Mode Read - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t - * @param[out] val :Store of value - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t param_result = PARAM_NG; - int32_t i; - - /* Check the parameters, the NULL of address */ - for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++ ) - { - param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); - if(param_result == PARAM_OK) - { - break; - } - else - { - result = TXZ_ERROR; - } - } - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_J: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pj_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pj_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pj_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pj_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pj_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pj_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pj_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pj_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pj_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pj_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_U: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pu_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pu_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pu_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pu_instance->FR3;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pu_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pu_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pu_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pu_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pu_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_W: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pw_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pw_instance->CR;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pw_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pw_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pw_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pw_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pw_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pw_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pw_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pw_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pw_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - } - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Port Function switching - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t - * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t - * @retval GPIO_RESULT_SUCCESS :Success. - * @retval GPIO_RESULT_FAILURE :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - int32_t param_result = PARAM_NG; - - /* Check the parameters, the NULL of address */ - param_result = check_param_func_pin_exist(p_obj, group, num, func); - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { - #if defined(TMPM4G6) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G6 */ - #if defined(TMPM4G7) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G7 */ - #if defined(TMPM4G8) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_M: - port_base = (uint32_t)p_obj->p_pm_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G8 */ - #if defined(TMPM4G9) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_J: - port_base = (uint32_t)p_obj->p_pj_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_M: - port_base = (uint32_t)p_obj->p_pm_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_U: - port_base = (uint32_t)p_obj->p_pu_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_W: - port_base = (uint32_t)p_obj->p_pw_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - } - if(result == TXZ_ERROR) - { - return (result); - } - - /* Initialization PxFR OFF */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_CLR(mode_base, num); - - /* Initialize Input/Output */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - - switch (func) { - case 0: - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - } - break; - case GPIO_FR_6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_7: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_NA: - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Pull up mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Set Pull down mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Set Open drain mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) - * @brief Port Bit Write - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @param val :GPIO Pin Reset/Set. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t base; - - /* Check the parameters */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - base = BITBAND_PORT_BASE(group); - base = BITBAND_PORT_MODE_BASE(base, mode); - if (val == GPIO_PIN_SET){ BITBAND_PORT_SET(base, num);} - else if (val == GPIO_PIN_RESET){ BITBAND_PORT_CLR(base, num);} - else{ result = TXZ_ERROR;} - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) - * @brief Port Bit Read - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t base; - uint32_t val; - - /* Check the parameters */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - base = BITBAND_PORT_BASE(group); - base = BITBAND_PORT_MODE_BASE(base, mode); - BITBAND_PORT_READ(val, base, num); - if(val == GPIO_PIN_RESET){ *pinstate = GPIO_PIN_RESET;} - else if (val == GPIO_PIN_SET){ *pinstate = GPIO_PIN_SET;} - else{ result = TXZ_ERROR;} - } - - return result; -} - -/** - * @} - */ /* End of group GPIO_Exported_functions */ - -/** - * @} - */ /* End of group GPIO */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__GPIO_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c deleted file mode 100644 index 26c3c1fc293..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c +++ /dev/null @@ -1,175 +0,0 @@ -/** - ******************************************************************************* - * @file txz_hal.c - * @brief This file provides API functions for driver common part. - * @version V1.0.0.0 - * $Date:: 2017-08-09 11:01:04 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_hal.h" - -#if defined(__HAL_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup HAL - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_macro HAL Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_typedef HAL Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_fuctions HAL Private Fuctions - * @{ - */ - -static uint32_t tick; - -/** - * @} - */ /* End of group HAL_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup HAL_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Increment a tick value. - * @param - - * @retval - - * @note Please call by user. - * @note In the sample, this variable is incremented each 1ms timer interrupt. - */ -/*--------------------------------------------------*/ -void hal_inc_tick(void) -{ - tick++; -} - -/*--------------------------------------------------*/ -/** - * @brief Provides a tick value. - * @param - - * @return Tick value. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -uint32_t hal_get_tick(void) -{ - return(tick); -} - -/** - * @} - */ /* End of group HAL_Exported_functions */ - -/** - * @} - */ /* End of group HAL */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__HAL_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c deleted file mode 100644 index f9f30720f1b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c +++ /dev/null @@ -1,415 +0,0 @@ -/** - ******************************************************************************* - * @file txz_i2c.c - * @brief This file provides API functions for I2C Class. - * @version V1.0.0.2 - * $Date:: 2016-11-08 00:00:00 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c.h" - -#if defined(__I2C_H) - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_variables - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_variables */ - -/*------------------------------------------------------------------------------*/ -/* Const Table */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_const - * @{ - */ -/*----------------------------------*/ -/** - * @brief SCK Divider value table. - * @details SCK = b000 - b111. - * @note NFSEL=0 (Digital Setting) Divider value. -*/ -/*----------------------------------*/ -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20,24,32,48,80,144,272,528 }; -static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; - -/** - * @} - */ /* End of group UTILITIES_Private_const */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ - -/*--------------------------------------------------*/ -/** - * @brief Initializing I2C Regester - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_init(I2C_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; - p_obj->p_instance->OP = I2CxOP_INIT; - p_obj->p_instance->CR1 = (I2CxCR1_ACK | /* I2CxCR1_NOACK | */ p_obj->init.clock.sck); - p_obj->p_instance->AR = I2CxAR_INIT; - p_obj->p_instance->AR2 = I2CxAR2_INIT; - p_obj->p_instance->CR2 = I2CxCR2_INIT; - p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); - p_obj->p_instance->IE = I2CxIE_CLEAR; -} - -/*--------------------------------------------------*/ -/** - * @brief Generate start condition - * @param p_obj :I2C object. - * @param data :Slave address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_start_condition(I2C_t *p_obj, uint32_t data) -{ - __IO uint32_t opreg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - opreg = p_obj->p_instance->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - if(I2C_master(p_obj)){ - if ((p_obj->p_instance->SR & I2CxSR_BB)) - { - opreg |= I2CxOP_SREN; - } - } - p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); - p_obj->p_instance->OP = opreg; - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); - p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; -} - -/*--------------------------------------------------*/ -/** - * @brief Return the I2c clock setting - * @param p_obj :I2C object. - * @param frequency :Maximum frequency. - * @param fsys :SystemCoreClock. - * @param p_setting :Clock data pointer. - * @retval Non-zero :Scl frequency. - * @retval 0 :Error. - * @note - - */ -/*--------------------------------------------------*/ -uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) -{ - uint32_t result = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_setting)); -#endif /* #ifdef DEBUG */ - - if (frequency <= 1000000) - { - uint64_t sck, tmp_sck; - uint64_t prsck, tmp_prsck; - uint64_t fscl, tmp_fscl; - uint64_t fx; - uint64_t max_fx, min_fx; - uint64_t low_width,low_width_min; - - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - - if(frequency <= 400000) - { - max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ - min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ - low_width_min = 1600; - } - else - { - max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ - min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ - low_width_min = 675; - } - for (prsck = 1; prsck <= 32; prsck++) - { - fx = ((uint64_t)fsys / prsck); - - if ((fx < max_fx) && (fx >= min_fx)) - { - for (sck = 0; sck <= 7; sck++) - { - low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; - if(low_width < low_width_min) - { - continue; - } - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - - if ((fscl <= frequency) && (fscl > tmp_fscl)) - { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32)? prsck: 0; - } - } - } - } - result = (uint32_t)tmp_fscl; - p_setting->sck = (uint32_t)tmp_sck; - p_setting->prsck = (tmp_prsck < 32)? (uint32_t)tmp_prsck: 0; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Slave mode setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_slave_init(I2C_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; - p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); - p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - p_obj->p_instance->CR2 = I2CxCR2_INIT; - p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); - p_obj->p_instance->IE = 1; -} -#if defined(I2CSxWUP_EN) -/*--------------------------------------------------*/ -/** - * @brief I2C Wakeup Control setting. - * @param p_obj :I2CS object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_init(I2CS_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR1 = (p-obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); -} - -/*--------------------------------------------------*/ -/** - * @brief Primary Slave Address setting. - * @param p_obj :I2CS object. - * @param addr :Primary Slave Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR2 = (0x0000000E & adr); -} - -/*--------------------------------------------------*/ -/** - * @brief Secondary Slave Address setting. - * @param p_obj :I2CS object. - * @param addr :Secondary Slave Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR3 = (0x0000000E & adr); - p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ -} -#endif -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#endif /* defined(__I2C_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c deleted file mode 100644 index 4a1bab48336..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c +++ /dev/null @@ -1,1865 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_i2c.c - * @brief This file provides API functions for BSP I2C driver. - * @version V1.0.0.1 - * $Date:: 2017-10-03 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c_api.h" - -#if defined(__BSP_I2C_H) - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name timeout - * @brief This timeouts are not based on accurate values, this just guarantee that - the application will not remain stuck if the I2C communication is corrupted. - * @{ - */ -#define I2C_TIMEOUT (100000) /*>! fail safe. */ - -/** - * @} - */ /* End of name timeout */ - -#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ -#define I2C_CH0 (0) /*!< I2C Channel 0. */ -#define I2C_CH1 (1) /*!< I2C Channel 1. */ -#define I2C_CH2 (2) /*!< I2C Channel 2. */ -#define I2C_CH3 (3) /*!< I2C Channel 3. */ -#define I2C_CH4 (4) /*!< I2C Channel 3. */ -#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ -/*----------------------------------*/ -/** - * @brief Transfer State. -*/ -/*----------------------------------*/ -enum { - I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ - I2C_TRANSFER_STATE_BUSY /*!< Busy. */ -} TransferState; - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief For IRQn_Type number definition. -*/ -/*----------------------------------*/ -typedef struct -{ - IRQn_Type i2c; - IRQn_Type al; - IRQn_Type bf; - IRQn_Type na; -} i2c_irq_t; - -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_variables - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_variables */ - -/*------------------------------------------------------------------------------*/ -/* Const Table */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_const - * @{ - */ -/*----------------------------------*/ -/** - * @brief Channel 0 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = -{ - { INTI2C0_IRQn, INTI2C0AL_IRQn, INTI2C0BF_IRQn, INTI2C0NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 1 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = -{ - { INTI2C1_IRQn, INTI2C1AL_IRQn, INTI2C1BF_IRQn, INTI2C1NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 2 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = -{ - { INTI2C2_IRQn, INTI2C2AL_IRQn, INTI2C2BF_IRQn, INTI2C2NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 3 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = -{ - { INTI2C3_IRQn, INTI2C3AL_IRQn, INTI2C3BF_IRQn, INTI2C3NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 4 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH4_IRQN_TBL[1] = -{ - { INTI2C4_IRQn, INTI2C4AL_IRQn, INTI2C4BF_IRQn, INTI2C4NACK_IRQn } -}; -/** - * @} - */ /* End of group UTILITIES_Private_const */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -#ifdef DEBUG -__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); -__STATIC_INLINE int32_t check_param_address(int32_t address); -#endif -__STATIC_INLINE void enable_irq(uint32_t irqn); -__STATIC_INLINE void disable_irq(uint32_t irqn); -__STATIC_INLINE void clear_irq(uint32_t irqn); -__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); -__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); -__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); -static void i2c_irq_handler(_i2c_t *p_obj); -static void i2c_slave_irq_handler(_i2c_t *p_obj); - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Compare the IRQn's parameter. - * @param irqn :I2C IRQn List. - * @retval I2C_PARAM_OK :Available. - * @retval I2C_PARAM_NG :Not Available. - * @note -. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) -{ - int32_t result = I2C_PARAM_NG; - - if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Compare the Slave address's parameter. - * @param address :Address. - * @retval I2C_PARAM_OK :Available. - * @retval I2C_PARAM_NG :Not Available. - * @note Here, 10bit address has not supported. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_address(int32_t address) -{ - int32_t result = I2C_PARAM_NG; - - if ((address >= 0) && (address <= 255)) - { - result = I2C_PARAM_OK; - } - return (result); -} -#endif - -/*--------------------------------------------------*/ -/** - * @brief Enable I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_EnableIRQ(p_irqn->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Disable I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_DisableIRQ(p_irqn->i2c); - NVIC_DisableIRQ(p_irqn->al); - NVIC_DisableIRQ(p_irqn->bf); - NVIC_DisableIRQ(p_irqn->na); -} - -/*--------------------------------------------------*/ -/** - * @brief ClearPending I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void clear_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_ClearPendingIRQ(p_irqn->i2c); - NVIC_ClearPendingIRQ(p_irqn->al); - NVIC_ClearPendingIRQ(p_irqn->bf); - NVIC_ClearPendingIRQ(p_irqn->na); -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PG2, PG3) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) - { - /* Port G */ - - /* SCL */ - TSB_PG_IE_PG3IE = 0; /* Input :Disable */ - TSB_PG_CR_PG3C = 0; /* Output :Disable */ - TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG3 = 0; /* Data :0 */ - TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */ - TSB_PG_IE_PG3IE = 1; /* Input :Enable */ - TSB_PG_CR_PG3C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PG_IE_PG2IE = 0; /* Input :Disable */ - TSB_PG_CR_PG2C = 0; /* Output :Disable */ - TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG2 = 0; /* Data :0 */ - TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */ - TSB_PG_IE_PG2IE = 1; /* Input :Enable */ - TSB_PG_CR_PG2C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PF2, PF3) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) - { - /* Port F */ - - /* SCL */ - TSB_PF_IE_PF3IE = 0; /* Input :Disable */ - TSB_PF_CR_PF3C = 0; /* Output :Disable */ - TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */ - TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */ - TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */ - TSB_PF_DATA_PF3 = 0; /* Data :0 */ - TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */ - TSB_PF_IE_PF3IE = 1; /* Input :Enable */ - TSB_PF_CR_PF3C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PF_IE_PF2IE = 0; /* Input :Disable */ - TSB_PF_CR_PF2C = 0; /* Output :Disable */ - TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */ - TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */ - TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */ - TSB_PF_DATA_PF2 = 0; /* Data :0 */ - TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */ - TSB_PF_IE_PF2IE = 1; /* Input :Enable */ - TSB_PF_CR_PF2C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PG4, PG5) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) - { - /* Port G */ - - /* SCL */ - TSB_PG_IE_PG5IE = 0; /* Input :Disable */ - TSB_PG_CR_PG5C = 0; /* Output :Disable */ - TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG5 = 0; /* Data :0 */ - TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */ - TSB_PG_IE_PG5IE = 1; /* Input :Enable */ - TSB_PG_CR_PG5C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PG_IE_PG4IE = 0; /* Input :Disable */ - TSB_PG_CR_PG4C = 0; /* Output :Disable */ - TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG4 = 0; /* Data :0 */ - TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */ - TSB_PG_IE_PG4IE = 1; /* Input :Enable */ - TSB_PG_CR_PG4C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PM0, PM1) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) - { - /* Port M */ - - /* SCL */ - TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ6C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ6 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */ - TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ6C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ7C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ7 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */ - TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ7C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PM6, PM7) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) - { - /* Port M */ - - /* SCL */ - TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ2C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ2 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */ - TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ2C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ3C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ3 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */ - TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ3C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Setting - * @param ch :I2C Channel. - * @param p_irqn :Destination Address of a I2C IRQn List. - * @retval non-zero :Instance Address. - * @retval zero :Channel not supported. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn) -{ - uint32_t instance = 0; - - switch (ch) - { - case I2C_CH0: - instance = (uint32_t)TSB_I2C0; - *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL; - break; - - case I2C_CH1: - instance = (uint32_t)TSB_I2C1; - *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL; - break; - - case I2C_CH2: - instance = (uint32_t)TSB_I2C2; - *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL; - break; - - case I2C_CH3: - instance = (uint32_t)TSB_I2C3; - *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL; - break; - - case I2C_CH4: - instance = (uint32_t)TSB_I2C4; - *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL; - break; - - default: - break; - } - return (instance); -} - -/*--------------------------------------------------*/ -/** - * @brief Reset Asynch Transfer - * @param p_obj :i2c object - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) -{ - disable_irq(p_obj->info.irqn); - I2C_disable_interrupt(&p_obj->i2c); -} - -__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); -#endif -} -/*--------------------------------------------------*/ -/** - * @brief Waiting i2c status - * @param p_obj :i2c object - * @retval 0 :Success. - * @retval -1 :Failure. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) -{ - int32_t timeout; - - timeout = I2C_TIMEOUT; - while (!I2C_int_status(&p_obj->i2c)) - { - if (I2C_status_arbitration(&p_obj->i2c)) - { - volatile uint32_t dummy = 0; - dummy = I2C_read_data(&p_obj->i2c); - return (-5); - } - if ((timeout--) == 0) - { - return (-1); - } - } - if (I2C_status_arbitration(&p_obj->i2c)) - { - volatile uint32_t dummy = 0; - dummy = I2C_read_data(&p_obj->i2c); - return (-5); - } - return (0); -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Transfer handler - * @param p_obj :i2c object. - * @retval - - * @note Called by i2c_irq_handler_asynch_t. - */ -/*--------------------------------------------------*/ -static void i2c_irq_handler(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - - if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) - { - p_obj->info.asynch.event = I2C_EVENT_ERROR; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - if (I2C_transmitter(&p_obj->i2c)) - { - int32_t start = I2C_restart(&p_obj->i2c); - - if (!I2C_get_ack(&p_obj->i2c)) - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); - } - else if (p_obj->rx_buff.length != 0) - { - I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - if (p_obj->tx_buff.pos == 0) - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else if (p_obj->rx_buff.length != 0) - { - if (p_obj->tx_buff.pos == 0) - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - else - { - int32_t start = I2C_restart(&p_obj->i2c); - - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - if (!start) - { - p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - } - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1))); - I2C_write_data(&p_obj->i2c, 0); - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - reset_asynch(p_obj); - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Transfer handler - * @param p_obj :i2c object. - * @retval - - * @note Called by i2c_slave_irq_handler_asynch_t. - */ -/*--------------------------------------------------*/ -static void i2c_slave_irq_handler(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - - if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) - { - p_obj->info.asynch.event = I2C_EVENT_ERROR; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - int32_t start = I2C_slave_detected(&p_obj->i2c); - if (start) - { - uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); - } - if (I2C_transmitter(&p_obj->i2c)) - { - if (!I2C_get_ack(&p_obj->i2c)) - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); - } - else - { /* dummy, wait nack */ - I2C_write_data(&p_obj->i2c, 0); - } - } - else - { - /* error event not be set */ - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - if (!start) - { - p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - } - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1))); - I2C_write_data(&p_obj->i2c, 0); - } - else - { - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - reset_asynch(p_obj); - I2C_slave_init(&p_obj->i2c); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Enable I2C IRQ - * @param p_obj :i2c object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void i2c_enable_irq(_i2c_t *p_obj) -{ - enable_irq(p_obj->info.irqn); -} - -/*--------------------------------------------------*/ -/** - * @brief Disable I2C IRQ - * @param p_obj :i2c object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void i2c_disable_irq(_i2c_t *p_obj) -{ - disable_irq(p_obj->info.irqn); -} - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_functions - * @{ - */ - -/*--------------------------------------------------*/ -/** - * @brief Initialize the I2C Driver - * @param p_obj :i2c object. - * @param sda :SDA port. - * @param scl :SCL port. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl) -{ - TXZ_Result result = TXZ_ERROR; - uint32_t instance = 0; - uint32_t irqn = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - /* ch0 */ - if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) - { - set_port_ch0(sda, scl); - instance = set_i2c(I2C_CH0, &irqn); - } - /* ch1 */ - if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) - { - set_port_ch1(sda, scl); - instance = set_i2c(I2C_CH1, &irqn); - } - /* ch2 */ - if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) - { - set_port_ch2(sda, scl); - instance = set_i2c(I2C_CH2, &irqn); - } - /* ch3 */ - if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) - { - set_port_ch3(sda, scl); - instance = set_i2c(I2C_CH3, &irqn); - } - /* ch4 */ - if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) - { - set_port_ch4(sda, scl); - instance = set_i2c(I2C_CH3, &irqn); - } - - if ((instance != 0) && (irqn != 0)) - { - disable_irq(irqn); - clear_irq(irqn); - - /* Set irqn table */ - p_obj->info.irqn = irqn; - - /* Set instance */ - p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance; - - /* I2C Reset */ - i2c_reset_t(p_obj); - - /* Set Frequency Default at 100KHz */ - if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS) - { - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Reset I2C peripheral - * @param p_obj :i2c object. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_reset_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - /* Software reset */ - I2C_reset(&p_obj->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure the I2C frequency - * @param p_obj :i2c object. - * @param hz :frequency in Hz. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_port_high(&p_obj->i2c)) - { - uint32_t fval; - - SystemCoreClockUpdate(); - - fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); - if (fval != 0) - { - //I2C_init(&p_obj->i2c); - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - p_obj->info.asynch.address = 0; - p_obj->info.asynch.stop = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - p_obj->info.asynch.event = 0; - p_obj->tx_buff.p_buffer = I2C_NULL; - p_obj->tx_buff.length = 0; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = I2C_NULL; - p_obj->rx_buff.length = 0; - p_obj->rx_buff.pos = 0; - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check bus free on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - p_obj->info.bus_free = 1; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Creates a start condition on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure.(now, not use) - * @note Start condition is not generate yet, after this function returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_start_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - p_obj->info.start = 1; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Creates a stop condition on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_stop_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t timeout; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_stop_condition(&p_obj->i2c); - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - - timeout = I2C_TIMEOUT; - while (i2c_active_t(p_obj)) - { - if ((timeout--) == 0) - { - result = TXZ_ERROR; - break; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking reading data - * @param p_obj :i2c object. - * @param address :Slave address(7-bit) and last bit is 0. - * @param p_data :Address of Read data. - * @param length :Number of the bytes to read. - * @param stop :Stop to be generated after the transfer is done. - * @retval Number of read bytes. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) -{ - int32_t result = 0; - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - if (length > 0) - { - /* Start Condition */ - if (i2c_start_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); - if (result == I2C_ACK) - { - /* Read all bytes */ - while (count < length) - { - int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1))? 0: 1)); - if (data < 0) - { - result = data; - break; - } - p_data[count++] = (uint8_t)data; - } - result = count; - } - else if (result == I2C_ERROR_ARBITRATION) - { - } - else if (result == (-2)) //I2C_ERROR_BUS_BUSY - { - } - else - { - stop = 1; - result = (-1) ;//I2C_ERROR_NO_SLAVE; - } - /* Stop Condition */ - if (stop) - { - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking sending data - * @param p_obj :i2c object. - * @param address :Slave address(7-bit) and last bit is 0. - * @param p_data :Destination address of Write data. - * @param length :Number of the bytes to write. - * @param stop :Stop to be generated after the transfer is done. - * @retval Number of write bytes. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) -{ - int32_t result = 0; - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - /* Start Condition */ - if (i2c_start_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - result = i2c_byte_write_t(p_obj, address); - if (result == I2C_ACK) - { - /* Write all bytes */ - while (count < length) - { - int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); - if (data < I2C_ACK) - { - result = data; - break; - } - } - if(result >=0){ - result = count; - } - } - else if (result == I2C_ERROR_ARBITRATION) - { - } - else if (result == (-2)) //I2C_ERROR_BUS_BUSY - { - } - else - { - stop = 1; - result = (-1); //I2C_ERROR_NO_SLAVE; - } - /* Stop Condition */ - if (stop) - { - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Read one byte - * @param p_obj :i2c object. - * @param last :last acknowledge. - * @retval The read byte (but -1 is timout error). - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) -{ - int32_t result; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - I2C_set_ack(&p_obj->i2c, last); - I2C_write_data(&p_obj->i2c, 0); - result = wait_status(p_obj); - if (result < 0) - { - // result = -1; - } - else - { - result = (int32_t)I2C_read_data(&p_obj->i2c); - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Write one byte - * @param p_obj :i2c object. - * @param data :Write data. - * @retval 0 :NACK was received. - * @retval 1 :ACK was received. - * @retval -1 :Timout error. - * @note Macro definition of return values is @ref I2C_ACK. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) -{ - int32_t result; - int32_t timeout; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - if (p_obj->info.start == 1) - { - p_obj->info.start = 0; - if (p_obj->info.bus_free == 1) - { - timeout = I2C_TIMEOUT; - while (i2c_active_t(p_obj)) - { - if ((timeout--) == 0) - { - p_obj->info.bus_free = 0; - return (-1); - } - } - } - /* Start Condition */ - I2C_start_condition(&p_obj->i2c, (uint32_t)data); - if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) - { - p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - p_obj->info.bus_free = 0; - if (I2C_status_arbitration(&p_obj->i2c)) - { - return (-5); - } - return (-2); - } - } - else - { - I2C_write_data(&p_obj->i2c, (uint32_t)data); - } - p_obj->info.bus_free = 0; - result = wait_status(p_obj); - if (result < 0) - { - return (result); - } - if (!I2C_get_ack(&p_obj->i2c)) - { - result = 1; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Attempts to determine if the I2C bus is already in use - * @param p_obj :i2c object. - * @retval 0 :Non-active. - * @retval 1 :Active. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint8_t i2c_active_t(_i2c_t *p_obj) -{ - uint8_t result; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_status_busy(&p_obj->i2c)) - { - result = 1; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Start I2C asynchronous transfer - * @param p_obj :i2c object. - * @param p_tx :Buffer of write data. - * @param tx_length :Length of write data. - * @param p_rx :Buffer of read data. - * @param rx_length :Length of read data. - * @param address :Slave address(7-bit) and last bit is 0. - * @param stop :Stop to be generated after the transfer is done. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Master and non-blocking function. - * @note Events of this function will be notified on i2c_irq_handler_asynch_t. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) - { - reset_asynch(p_obj); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); - p_obj->info.asynch.address = (uint32_t)address; - p_obj->info.asynch.event = 0; - p_obj->info.asynch.stop = (uint32_t)stop; - p_obj->tx_buff.p_buffer = p_tx; - p_obj->tx_buff.length = (uint32_t)tx_length; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = p_rx; - p_obj->rx_buff.length = (uint32_t)rx_length; - p_obj->rx_buff.pos = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; - I2C_enable_interrupt(&p_obj->i2c); - if ((tx_length == 0) && (rx_length != 0)) - { - I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); - } - else - { - I2C_start_condition(&p_obj->i2c, (uint32_t)address); - } - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - enable_irq(p_obj->info.irqn); - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief The asynchronous IRQ handler - * @param p_obj :i2c object. - * @retval zero :Transfer in progress. - * @retval non-zero :Event information. - * @note Macro definition of return values is @ref I2C_Events. - * @attention This function should be implement as INTI2Cx_IRQHandler. - */ -/*--------------------------------------------------*/ -uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - i2c_irq_handler(p_obj); - - return (p_obj->info.asynch.event & I2C_EVENT_ALL); -} - -/*--------------------------------------------------*/ -/** - * @brief Abort asynchronous transfer - * @param p_obj :i2c object. - * @retval - - * @note After error event occurred on i2c_irq_handler_asynch_t, - * @note call this function and clear error status. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_abort_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - reset_asynch(p_obj); - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - i2c_reset_t(p_obj); - I2C_init(&p_obj->i2c); - clear_irq(p_obj->info.irqn); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure I2C as slave or master. - * @param p_obj :i2c object. - * @param enable_slave :Enable slave mode. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - disable_irq(p_obj->info.irqn); - - if (enable_slave) - { - I2C_slave_init(&p_obj->i2c); - } - else - { - /* Slave Disable Settings. */ - i2c_reset_t(p_obj); - I2C_init(&p_obj->i2c); - } - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - I2C_clear_int_status(&p_obj->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Check to see if the I2C slave has been addressed. - * @param p_obj :i2c object. - * @retval I2C_NO_DATA :The slave has not been addressed. - * @retval I2C_READ_ADDRESSED :Read addresses. - * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). - * @retval I2C_WRITE_ADDRESSED :Write addressed. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_receive_t(_i2c_t *p_obj) -{ - int32_t result = I2C_NO_DATA; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_slave_detected(&p_obj->i2c)) - { - uint32_t sa = I2C_read_data(&p_obj->i2c); - - if (!I2C_transmitter(&p_obj->i2c)) - { - result = I2C_WRITE_ADDRESSED; - } - else - { - result = I2C_READ_ADDRESSED; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking reading data. - * @param p_obj :i2c object. - * @param p_data :Destination address of read data. - * @param length :Number of bytes to read. - * @retval Number of read bytes. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) -{ - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); -#endif /* #ifdef DEBUG */ - - /* Read all bytes */ - while (count < length) - { - I2C_clear_int_status(&p_obj->i2c); - I2C_set_ack(&p_obj->i2c, ((count < (length - 1))? 0: 1)); - I2C_write_data(&p_obj->i2c, 0); - if (wait_status(p_obj) < 0) - { - break; - } - if (I2C_slave_detected(&p_obj->i2c)) - { - return (count); - } - p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - I2C_slave_init(&p_obj->i2c); - return (count); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking sending data. - * @param p_obj :i2c object. - * @param p_data :Source address of write data. - * @param length :Number of bytes to write. - * @retval Number of written bytes. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) -{ - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); -#endif /* #ifdef DEBUG */ - - /* Write all bytes */ - while (count < length) - { - I2C_clear_int_status(&p_obj->i2c); - I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); - if (wait_status(p_obj) < 0) - { - break; - } - if (!I2C_get_ack(&p_obj->i2c)) - { - /* continue */ - } - else - { - break; - } - } - I2C_slave_init(&p_obj->i2c); - return (count); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure I2C slave address. - * @param p_obj :i2c object. - * @param address :Address to be set. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(check_param_address((int32_t)address)); -#endif /* #ifdef DEBUG */ - - I2C_set_address(&p_obj->i2c, address); -} - - -/*--------------------------------------------------*/ -/** - * @brief Start I2C asynchronous transfer - * @param p_obj :i2c object. - * @param p_tx :Buffer of write data. - * @param tx_length :Length of write data. - * @param p_rx :Buffer of read data. - * @param rx_length :Length of read data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Slave and non-blocking function. - * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) - { - reset_asynch(p_obj); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); - p_obj->info.asynch.address = 0; - p_obj->info.asynch.event = 0; - p_obj->info.asynch.stop = 0; - p_obj->tx_buff.p_buffer = p_tx; - p_obj->tx_buff.length = (uint32_t)tx_length; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = p_rx; - p_obj->rx_buff.length = (uint32_t)rx_length; - p_obj->rx_buff.pos = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; - I2C_enable_interrupt(&p_obj->i2c); - enable_irq(p_obj->info.irqn); - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief The asynchronous IRQ handler - * @param p_obj :i2c object. - * @retval zero :Transfer in progress. - * @retval non-zero :Event information. - * @note Macro definition of return values is @ref I2C_Events. - * @attention This function should be implement as INTI2Cx_IRQHandler. - */ -/*--------------------------------------------------*/ -uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - i2c_slave_irq_handler(p_obj); - - return (p_obj->info.asynch.event & I2C_EVENT_ALL); -} - -/*--------------------------------------------------*/ -/** - * @brief Abort asynchronous transfer - * @param p_obj :i2c object. - * @retval - - * @note For a non-blocking function. - * @note After error event occurred on i2c_slave_irq_handler_asynch_t, - * @note call this function and clear error status. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_abort_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - reset_asynch(p_obj); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - I2C_slave_init(&p_obj->i2c); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); -} - -/** - * @} - */ /* End of group UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#endif /* defined(__BSP_I2C_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c deleted file mode 100644 index fd4c7507cb0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c +++ /dev/null @@ -1,2034 +0,0 @@ - /** - ******************************************************************************* - * @file txz_t32a.c - * @brief This file provides API functions for T32A driver. - * @version V1.0.0.7 - * $Date:: 2018-03-30 13:56:50 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_t32a.h" - -#if defined(__T32A_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup T32A - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_define T32A Private Define - * @{ - */ -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ -/** - * @} - */ /* End of group T32A_Private_typedef */ -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_define T32A Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_typedef T32A Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Private_member T32A Private Member - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_member */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_fuctions TSPI Private Fuctions - * @{ - */ -#ifdef DEBUG - __INLINE static int32_t check_param_mode_halt(uint32_t param); - __INLINE static int32_t check_param_mode_mode32(uint32_t param); - __INLINE static int32_t check_param_runx_sftstpx(uint32_t param); - __INLINE static int32_t check_param_runx_sftstax(uint32_t param); - __INLINE static int32_t check_param_runx_runx(uint32_t param); - __INLINE static int32_t check_param_crx_prsclx(uint32_t param); - __INLINE static int32_t check_param_crx_clkx(uint32_t param); - __INLINE static int32_t check_param_crx_wbfx(uint32_t param); - __INLINE static int32_t check_param_crx_updnx(uint32_t param); - __INLINE static int32_t check_param_crx_reldx(uint32_t param); - __INLINE static int32_t check_param_crx_stopx(uint32_t param); - __INLINE static int32_t check_param_crx_startx(uint32_t param); - __INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); - __INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); - __INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); - __INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); - __INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); - __INLINE static int32_t check_param_reldx_reld(uint32_t param); - __INLINE static int32_t check_param_imx_imsterr(uint32_t param); - __INLINE static int32_t check_param_imx_imufx(uint32_t param); - __INLINE static int32_t check_param_imx_imofx(uint32_t param); - __INLINE static int32_t check_param_imx_imx1(uint32_t param); - __INLINE static int32_t check_param_imx_imx0(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pup(uint32_t param); - __INLINE static int32_t check_param_pls_cr_nf(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); -#endif - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Mode HALT's parameter. - * @param param :Mode HALT's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_HALT - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_mode_halt(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DBG_HALT_RUN: - case T32A_DBG_HALT_STOP: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Mode mode32's parameter. - * @param param :Mode mode32's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_MODE32 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_mode_mode32(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_MODE_16: - case T32A_MODE_32: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the SW Counter STOP Control's parameter. - * @param param :SW Counter STOP Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_SFTSTPx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_DONT_STOP: - case T32A_COUNT_STOP: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the SW START Control's parameter. - * @param param :SW START Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_SFTSTAx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_sftstax(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_DONT_START: - case T32A_COUNT_START: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A RUN Disable/Enable Control's parameter. - * @param param :T32A RUN Disable/Enable Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PRSCLx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_runx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_RUN_DISABLE: - case T32A_RUN_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A PRESCALER Control's parameter. - * @param param :T32A PRESCALER Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PRSCLx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_prsclx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PRSCLx_1: - case T32A_PRSCLx_2: - case T32A_PRSCLx_8: - case T32A_PRSCLx_32: - case T32A_PRSCLx_128: - case T32A_PRSCLx_256: - case T32A_PRSCLx_512: - case T32A_PRSCLx_1024: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A PRESCALER Control's parameter. - * @param param :T32A PRESCALER Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CLKx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_clkx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CLKx_PRSCLx: - case T32A_CLKx_INTRG: - case T32A_CLKx_TIM_RISING_EDGE: - case T32A_CLKx_TIM_TRAILING_EDGE: - case T32A_CLKx_EXTTRG_RISING_EDGE: - case T32A_CLKx_EXTTRG_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Double Buffer Disable/Enable Control's parameter. - * @param param :Double Buffer Disable/Enable Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_WBFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_wbfx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_WBF_DISABLE: - case T32A_WBF_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Up/Down Control's parameter. - * @param param :T32A Counter Up/Down Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_UPDNx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_updnx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_UP: - case T32A_COUNT_DOWN: - case T32A_COUNT_UPDOWN: - case T32A_COUNT_PLS: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Reload Control's parameter. - * @param param :T32A Counter Reload Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RELDx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_reldx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_RELOAD_NON: - case T32A_RELOAD_INTRG: - case T32A_RELOAD_EXTTRG_RISING_EDGE: - case T32A_RELOAD_EXTTRG_TRAILING_EDGE: - case T32A_RELOAD_TIM_RISING_EDGE: - case T32A_RELOAD_TIM_TRAILING_EDGE: - case T32A_RELOAD_SYNC: - case T32A_RELOAD_TREGx: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Stop Control's parameter. - * @param param :T32A Counter Stop Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_STOPx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_stopx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_STOP_NON: - case T32A_STOP_INTRG: - case T32A_STOP_EXTTRG_RISING_EDGE: - case T32A_STOP_EXTTRG_TRAILING_EDGE: - case T32A_STOP_TIM_RISING_EDGE: - case T32A_STOP_TIM_TRAILING_EDGE: - case T32A_STOP_SYNC: - case T32A_STOP_TREGx: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Start Control's parameter. - * @param param :T32A Counter Start Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_STARTx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_startx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_START_NON: - case T32A_START_INTRG: - case T32A_START_EXTTRG_RISING_EDGE: - case T32A_START_EXTTRG_TRAILING_EDGE: - case T32A_START_TIM_RISING_EDGE: - case T32A_START_TIM_TRAILING_EDGE: - case T32A_START_SYNC: - result = PARAM_OK; - break; - case T32A_START_Rsvd: - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control's parameter. - * @param param :T32AxOUTA Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCR_DISABLE: - case T32A_OCR_SET: - case T32A_OCR_CLR: - case T32A_OCR_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. - * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCAPx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCAPx1_DISABLE: - case T32A_OCRCAPx1_SET: - case T32A_OCRCAPx1_CLR: - case T32A_OCRCAPx1_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. - * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCAPx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCAPx0_DISABLE: - case T32A_OCRCAPx0_SET: - case T32A_OCRCAPx0_CLR: - case T32A_OCRCAPx0_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. - * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCMPx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCMPx1_DISABLE: - case T32A_OCRCMPx1_SET: - case T32A_OCRCMPx1_CLR: - case T32A_OCRCMPx1_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. - * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCMPx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCMPx0_DISABLE: - case T32A_OCRCMPx0_SET: - case T32A_OCRCMPx0_CLR: - case T32A_OCRCMPx0_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Capture Control Register A1's parameter. - * @param param :T32A Capture Control Register A1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CAPMx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CAPMx1_DISABLE: - case T32A_CAPMx1_INTRG: - case T32A_CAPMx1_INx0_RISING_EDGE: - case T32A_CAPMx1_INx0_TRAILING_EDGE: - case T32A_CAPMx1_INx1_RISING_EDGE: - case T32A_CAPMx1_INx1_TRAILING_EDGE: - case T32A_CAPMx1_TIM_RISING_EDGE: - case T32A_CAPMx1_TIM_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Capture Control Register A0's parameter. - * @param param :T32A Capture Control Register A0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CAPMx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CAPMx0_DISABLE: - case T32A_CAPMx0_INTRG: - case T32A_CAPMx0_INx0_RISING_EDGE: - case T32A_CAPMx0_INx0_TRAILING_EDGE: - case T32A_CAPMx0_INx1_RISING_EDGE: - case T32A_CAPMx0_INx1_TRAILING_EDGE: - case T32A_CAPMx0_TIM_RISING_EDGE: - case T32A_CAPMx0_TIM_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Timer Register A0's parameter. - * @param param :T32A Timer Register A0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RGx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RGx0_MASK){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Timer Register A1's parameter. - * @param param :T32A Timer Register A1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RGx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RGx1_MASK){ - result = PARAM_OK; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Reload Register A's parameter. - * @param param :T32A Counter Reload Register A's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RELD - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_reldx_reld(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RELDx_MASK){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. - * @param param :T32A Statuserr Interrupt Request MASK's parameter. - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMSTEER - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imsterr(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMSTERR_MASK_NOREQ: - case T32A_IMSTERR_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Overflow Interrupt Request MASK's parameter. - * @param param :T32A Overflow Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMUFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imufx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMOFx_MASK_NOREQ: - case T32A_IMOFx_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Overflow Interrupt Request MASK's parameter. - * @param param :T32A Overflow Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMOFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imofx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMOFx_MASK_NOREQ: - case T32A_IMOFx_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. - * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMx1_MASK_NOREQ: - case T32A_IMx1_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. - * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMx0_MASK_NOREQ: - case T32A_IMx0_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA Converter1 Request control's parameter. - * @param param :T32A DMA Converter1 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx2 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx2_DISABLE: - case T32A_DMAENx2_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA InputCapture1 Request control's parameter. - * @param param :T32A DMA InputCapture1 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx1_DISABLE: - case T32A_DMAENx1_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA InputCapture0 Request control's parameter. - * @param param :T32A DMA InputCapture0 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx0_DISABLE: - case T32A_DMAENx0_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Mode Count Down Control's parameter. - * @param param :T32A Pulse Mode Count Down Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PDN - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PDN_NON0: - case T32A_PDN_NON1: - case T32A_PDN_INC0_RISING_EDGE: - case T32A_PDN_INC0_TRAILING_EDGE: - case T32A_PDN_INC1_RISING_EDGE: - case T32A_PDN_INC1_TRAILING_EDGE: - case T32A_PDN_INC0_BOTH_EDGE: - case T32A_PDN_INC1_BOTH_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Mode Count UP Control's parameter. - * @param param :T32A Pulse Mode Count UP Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PUP - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PUP_NON0: - case T32A_PUP_NON1: - case T32A_PUP_INC0_RISING_EDGE: - case T32A_PUP_INC0_TRAILING_EDGE: - case T32A_PUP_INC1_RISING_EDGE: - case T32A_PUP_INC1_TRAILING_EDGE: - case T32A_PUP_INC0_BOTH_EDGE: - case T32A_PUP_INC1_BOTH_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Noise Filter control's parameter. - * @param param :T32A Noise Filter control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_NF - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_NF_NON: - case T32A_NF_2: - case T32A_NF_4: - case T32A_NF_8: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Phase 2 Pulse Direction control's parameter. - * @param param :T32A Phase 2 Pulse Direction control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PDIR - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PDIR_FORWARD: - case T32A_PDIR_BACKWARD: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Count Mode control's parameter. - * @param param :T32A Pulse Count Mode control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PMODE - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PMODE_PHASE_2: - case T32A_PMODE_PHASE_1: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - - - -#endif -/** - * @} - */ /* End of group T32A_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Exported_functions - - */ -/*--------------------------------------------------*/ -/** - * @brief Mode Initialize the T32A object. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_mode_init(t32a_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - check_param_mode_halt(p_obj->init_mode.mode.halt); - check_param_mode_mode32(p_obj->init_mode.mode.mode); -#endif /* DEBUG */ - /* Timer Mode Set */ - p_obj->p_instance->MOD = 0; - p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Initialize the T32A object. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_init(t32a_t *p_obj,uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - /* Check the parameter of TimerA Mode Set */ - check_param_mode_halt(p_obj->init_mode.mode.halt); - check_param_mode_mode32(p_obj->init_mode.mode.mode); - /* Check the parameter of TimerA Run Control Set */ - check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); - check_param_runx_sftstax(p_obj->init[type].runx.sftsta); - check_param_runx_runx(p_obj->init[type].runx.run); - /* Check the parameter of Counter Register Control Set */ - check_param_crx_prsclx(p_obj->init[type].crx.prscl); - check_param_crx_clkx(p_obj->init[type].crx.clk); - check_param_crx_wbfx(p_obj->init[type].crx.wbf); - check_param_crx_updnx(p_obj->init[type].crx.updn); - check_param_crx_reldx(p_obj->init[type].crx.reld); - check_param_crx_stopx(p_obj->init[type].crx.stop); - check_param_crx_startx(p_obj->init[type].crx.start); - /* Check the parameter of TimerA Output Control Set */ - check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); - /* Check the parameter of T32AxOUTA Control Set */ - check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); - check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); - check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); - check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); - /* Check the parameter of Capture Control Set */ - check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); - check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); - /* Check the parameter of T32A Timer Register 0 Set */ - check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); - /* Check the parameter of T32A Timer Register 1 Set */ - check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); - /* Check the parameter of T32A Counter Reload Register Set */ - check_param_reldx_reld(p_obj->init[type].reldx.reld); - /* Check the parameter of Interrupt mask register Set */ - check_param_imx_imsterr(p_obj->init[type].imx.imsterr); - check_param_imx_imufx(p_obj->init[type].imx.imuf); - check_param_imx_imofx(p_obj->init[type].imx.imof); - check_param_imx_imx1(p_obj->init[type].imx.imx1); - check_param_imx_imx0(p_obj->init[type].imx.imx0); - /* Check the parameter of DMA Request register Set */ - check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); - check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); - check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); -#endif - - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - if(p_obj->init_mode.mode.mode != T32A_MODE_16) { - result = TXZ_ERROR; - return (result); - } - /* TimerA Run Control Disable */ - p_obj->p_instance->RUNA = 0; - /* Counter Register Control Set */ - p_obj->p_instance->CRA = 0; - p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerA Output Control Set */ - p_obj->p_instance->OUTCRA0 = 0; - p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTA Control Set */ - p_obj->p_instance->OUTCRA1 = 0; - p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register A0 Set */ - p_obj->p_instance->RGA0 = 0; - p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register A1 Set */ - p_obj->p_instance->RGA1 = 0; - p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDA = 0; - p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; - /* TimerB Capture Control Set */ - p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMA = 0; - p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAA = 0; - p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* TimerA Run Control Set */ - p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - case T32A_TIMERB: - /* Timer B */ - if(p_obj->init_mode.mode.mode != T32A_MODE_16) { - result = TXZ_ERROR; - return (result); - } - /* TimerB Run Control Disable */ - p_obj->p_instance->RUNB = 0; - /* Counter Register Control Set */ - p_obj->p_instance->CRB = 0; - p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerB Output Control Set */ - p_obj->p_instance->OUTCRB0 = 0; - p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTB Control Set */ - p_obj->p_instance->OUTCRB1 = 0; - p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register B0 Set */ - p_obj->p_instance->RGB0 = 0; - p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register B1 Set */ - p_obj->p_instance->RGB1 = 0; - p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDB = 0; - p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; - /* TimerB Capture Control Set */ - p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMB = 0; - p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAB = 0; - p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* TimerB Run Control Set */ - p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - case T32A_TIMERC: - /* Timer C */ - if(p_obj->init_mode.mode.mode != T32A_MODE_32) { - result = TXZ_ERROR; - return (result); - } - /* TimerC Run Control Disable */ - p_obj->p_instance->RUNC = 0; - #ifdef DEBUG - /* Pulse Count Control register Set */ - check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); - check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); - check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); - check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); - check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); - #endif - /* Counter Register Control Set */ - p_obj->p_instance->CRC = 0; - p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerC Output Control Set */ - p_obj->p_instance->OUTCRC0 = 0; - p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTC Control Set */ - p_obj->p_instance->OUTCRC1 = 0; - p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register C0 Set */ - p_obj->p_instance->RGC0 = 0; - p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register C1 Set */ - p_obj->p_instance->RGC1 = 0; - p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDC = 0; - p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; - /* TimerC Capture Control Set */ - p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMC = 0; - p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAC = 0; - p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* Pulse Count Control register Set */ - p_obj->p_instance->PLSCR = 0; - p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ - p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); - /* TimerC Run Control Set */ - p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - default: - result = TXZ_ERROR; - return (result); - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the T32A object. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNA = T32A_RUN_DISABLE; - break; - case T32A_TIMERB: - /* Timer B */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNB = T32A_RUN_DISABLE; - break; - case T32A_TIMERC: - /* Timer C */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNC = T32A_RUN_DISABLE; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Timer Start in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){ - /* Timer A RUN */ - p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERB: - if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){ - /* Timer B RUN */ - p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERC: - if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){ - /* Timer C RUN */ - p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Stop in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A Stop */ - p_obj->p_instance->RUNA = T32A_RUN_DISABLE; - break; - case T32A_TIMERB: - /* Timer B Stop */ - p_obj->p_instance->RUNB = T32A_RUN_DISABLE; - break; - case T32A_TIMERC: - /* SW Counter Stop & Timer C Stop */ - p_obj->p_instance->RUNC = T32A_RUN_DISABLE; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Start in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){ - /* Timer A SW Counter start */ - p_obj->p_instance->RUNA |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERB: - if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){ - /* Timer SW Counter start */ - p_obj->p_instance->RUNB |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERC: - if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){ - /* Timer C SW Counter start */ - p_obj->p_instance->RUNC |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Stop in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* TimerA SW Counter Stop */ - p_obj->p_instance->RUNA = T32A_COUNT_STOP; - break; - case T32A_TIMERB: - /* Timer B SW Counter Stop */ - p_obj->p_instance->RUNB = T32A_COUNT_STOP; - break; - case T32A_TIMERC: - /* Timer C SW Counter Stop */ - p_obj->p_instance->RUNC = T32A_COUNT_STOP; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Register Value Setting - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @param num :T32A Register Number. : Use @ref t32_regnum_t - * @param value :Setting Value. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - if(num == T32A_REG0) {p_obj->p_instance->RGA0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGA1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDA = value;} - break; - case T32A_TIMERB: - /* Timer B */ - if(num == T32A_REG0) {p_obj->p_instance->RGB0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGB1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDB = value;} - break; - case T32A_TIMERC: - /* Timer C */ - if(num == T32A_REG0) {p_obj->p_instance->RGC0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGC1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDC = value;} - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Timer Register Value Read - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @param p_val :Save area for register value. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) -{ - TXZ_Result result = TXZ_SUCCESS; - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - *p_val = p_obj->p_instance->TMRA; - break; - case T32A_TIMERB: - /* Timer B */ - *p_val = p_obj->p_instance->TMRB; - break; - case T32A_TIMERC: - /* Timer C */ - *p_val = p_obj->p_instance->TMRC; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-4 | - | - | - * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | - * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | - * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | - * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | - * - * @param p_obj :T32A object. - * @param p_status :Save area for status. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - *p_status = p_obj->p_instance->STA; - break; - case T32A_TIMERB: - /* Timer B */ - *p_status = p_obj->p_instance->STB; - break; - case T32A_TIMERC: - /* Timer C */ - *p_status = p_obj->p_instance->STC; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for Timer interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief Calculate timer value to set timer register. - * @param p_value: time value store pointer. - * @param time: The require period which the uint is us. - * @param prescaler: System Clock Freq - * @param prscl: Select the division for source clock @ref T32A_PRSCLx. - * @retval the value set to Tmrb timer register. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) -{ - TXZ_Result result = TXZ_SUCCESS; - uint64_t denominator; - uint64_t numerator; - uint32_t div; - - /* div */ - switch (prscl) - { - case T32A_PRSCLx_1: - div = 1; - break; - case T32A_PRSCLx_2: - div = 2; - break; - case T32A_PRSCLx_8: - div = 8; - break; - case T32A_PRSCLx_32: - div = 32; - break; - case T32A_PRSCLx_128: - div = 128; - break; - case T32A_PRSCLx_256: - div = 256; - break; - case T32A_PRSCLx_512: - div = 512; - break; - case T32A_PRSCLx_1024: - div = 1024; - break; - default: - div = 1; - break; - } - /*-----------------------------------------------*/ - /* "1"counter (s) = 1 / fs */ - /* "1"counter (s) = 1 / (prescaler / div) */ - /* "1"counter (us) = (10^6) / (prescaler / div) */ - /* "1"counter (us) = ((10^6) * div)/prescaler */ - /* "x"counter (us) = time */ - /*-----------------------------------------------*/ - /* x : time = 1 : ((10^6) * div)/prescaler */ - /*-----------------------------------------------*/ - /* x = time / (((10^6) * div)/prescaler) */ - /* = (prescaler * time) / ((10^6) * div) */ - /*-----------------------------------------------*/ - denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); - numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); - denominator = (uint64_t)(denominator / numerator); - /* result */ - if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) - { - result = TXZ_ERROR; - } - else - { - *p_value = (uint32_t)denominator; - } - - return (result); -} - -/** - * @} - */ /* End of group T32A_Exported_functions */ - -/** - * @} - */ /* End of group T32A */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__T32A_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c deleted file mode 100644 index e8854d75105..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c +++ /dev/null @@ -1,2830 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.c - * @brief This file provides API functions for TSPI driver. - * @version V1.0.0.0 - * $Date:: 2018-01-25 17:07:20 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_tspi.h" - -#if defined(__TSPI_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup TSPI - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ -/** - * @name TSPI NULL Pointer - * @brief Null Pointer for TSPI - * @{ - */ -#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ -/** - * @} - */ /* End of name TSPI NULL Pointer */ - -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name FIFO Max Num. - * @brief Transfer's/Receive's FIFO Max Num. - * @{ - */ -#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ -#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ -/** - * @} - */ /* End of name FIFO Max Num */ - -/** - * @name TSPIxDR_MASK Macro Definition. - * @brief TSPIxDR_MASK Macro Definition. - * @{ - */ -/* DR */ -#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ -/** - * @} - */ /* End of name TSPIxDR_MASK Macro Definition */ - -/** - * @name TSPI _DATA_LENGTH Macro Definition. - * @brief TSPI DATA LENGTH Macro Definition. - * @{ - */ -#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ -#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ -#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ -#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ -#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ -#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ -#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ -#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ -#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ -#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ -#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ -#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ -#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ -#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ -#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ -#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ -#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ -#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ -#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ -#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ -#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ -#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ -#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ -#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ -#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ -/** - * @} - */ /* End of name TSPI _DATA_LENGTH Macro Definition */ -/** - * @} - */ /* End of group TSPI_Private_typedef */ -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group TSPI_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_typedef TSPI Private Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief TSPI mask array. -*/ -/*----------------------------------*/ -static uint32_t mask[32] ={ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TSPI_DR_8BIT_MASK, - TSPI_DR_9BIT_MASK, - TSPI_DR_10BIT_MASK, - TSPI_DR_11BIT_MASK, - TSPI_DR_12BIT_MASK, - TSPI_DR_13BIT_MASK, - TSPI_DR_14BIT_MASK, - TSPI_DR_15BIT_MASK, - TSPI_DR_16BIT_MASK, - TSPI_DR_17BIT_MASK, - TSPI_DR_18BIT_MASK, - TSPI_DR_19BIT_MASK, - TSPI_DR_20BIT_MASK, - TSPI_DR_21BIT_MASK, - TSPI_DR_22BIT_MASK, - TSPI_DR_23BIT_MASK, - TSPI_DR_24BIT_MASK, - TSPI_DR_25BIT_MASK, - TSPI_DR_26BIT_MASK, - TSPI_DR_27BIT_MASK, - TSPI_DR_28BIT_MASK, - TSPI_DR_29BIT_MASK, - TSPI_DR_30BIT_MASK, - TSPI_DR_31BIT_MASK -}; - -/** - * @} - */ /* End of group TSPI_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_fuctions TSPI Private Fuctions - * @{ - */ - -#ifdef DEBUG - __INLINE static int32_t check_param_transmit_enable(uint32_t param); - __INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); - __INLINE static int32_t check_param_transmit_master(uint32_t param); - __INLINE static int32_t check_param_transmit_mode(uint32_t param); - __INLINE static int32_t check_param_transmit_sel_select(uint32_t param); - __INLINE static int32_t check_param_frame_range(uint32_t param); - __INLINE static int32_t check_param_idle_imp(uint32_t param); - __INLINE static int32_t check_param_underrun_imp(uint32_t param); - __INLINE static int32_t check_param_tx_fill_level(uint32_t param); - __INLINE static int32_t check_param_rx_fill_level(uint32_t param); - __INLINE static int32_t check_param_tx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_rx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_err_int(uint32_t param); - __INLINE static int32_t check_param_tx_dma_int(uint32_t param); - __INLINE static int32_t check_param_rx_dma_int(uint32_t param); - __INLINE static int32_t check_param_input_clock(uint32_t param); - __INLINE static int32_t check_param_input_divider(uint32_t param); - __INLINE static int32_t check_param_data_direction(uint32_t param); - __INLINE static int32_t check_param_frame_length(uint32_t param); - __INLINE static int32_t check_param_frame_interval(uint32_t param); - __INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); - __INLINE static int32_t check_param_clock_edge_imp(uint32_t param); - __INLINE static int32_t check_param_clock_idle_imp(uint32_t param); - __INLINE static int32_t check_param_min_idle_time(uint32_t param); - __INLINE static int32_t check_param_clock_delay(uint32_t param); - __INLINE static int32_t check_param_negate_delay(uint32_t param); - __INLINE static int32_t check_param_parity_enable(uint32_t param); - __INLINE static int32_t check_param_parity_bit(uint32_t param); -#endif - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Enable's parameter. - * @param param :Transmit Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Control - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TRXE_DISABLE: - case TSPI_TRXE_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Mode's parameter. - * @param param :Transmit Mode's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SPI_MODE: - case TSPI_SIO_MODE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Master/Slave parameter. - * @param param :Transmit Master/Slave parameter (Only support Master mode) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Operation_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_master(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MASTER_OPEARTION: - case TSPI_SLAVE_OPERATION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transfer Mode's parameter. - * @param param :Transfer Mode's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_mode(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TWO_WAY: - case TSPI_TX_ONLY: - case TSPI_RX_ONLY: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Sel Select's parameter. - * @param param :Transmit Sel Select's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_CSSEL_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_ENABLE: - case TSPI_TSPIxCS1_ENABLE: - case TSPI_TSPIxCS2_ENABLE: - case TSPI_TSPIxCS3_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Frame Range's parameter. - * @param param :TransmitFrame Range's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Frame_Range - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_range(uint32_t param) - -{ - int32_t result = PARAM_NG; - - if ((TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the IDLE Output Value's parameter. - * @param param :IDLE Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_IDLE_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TIDLE_Hiz: - case TSPI_TIDLE_LAST_DATA: - case TSPI_TIDLE_LOW: - case TSPI_TIDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Underrun Occur Output Value's parameter. - * @param param :Underrun Occur Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Underrun_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_underrun_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TXDEMP_LOW: - case TSPI_TXDEMP_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level's parameter. - * @param param :Tx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FILL_LEVEL_0: - case TSPI_TX_FILL_LEVEL_1: - case TSPI_TX_FILL_LEVEL_2: - case TSPI_TX_FILL_LEVEL_3: - case TSPI_TX_FILL_LEVEL_4: - case TSPI_TX_FILL_LEVEL_5: - case TSPI_TX_FILL_LEVEL_6: - case TSPI_TX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FILL_LEVEL_0: - case TSPI_RX_FILL_LEVEL_1: - case TSPI_RX_FILL_LEVEL_2: - case TSPI_RX_FILL_LEVEL_3: - case TSPI_RX_FILL_LEVEL_4: - case TSPI_RX_FILL_LEVEL_5: - case TSPI_RX_FILL_LEVEL_6: - case TSPI_RX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx FIFO Interrpt's parameter. - * @param param :Tx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FIFO_INT_DISABLE: - case TSPI_TX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_INT_DISABLE: - case TSPI_TX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx FIFO Interrpt's parameter. - * @param param :Rx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFIFOInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FIFO_INT_DISABLE: - case TSPI_RX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_INT_DISABLE: - case TSPI_RX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrupt's parameter. - * @param param :Error Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ErrorInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_err_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_ERR_INT_DISABLE: - case TSPI_ERR_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx DMA Interrupt's parameter. - * @param param :Tx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_DMA_INT_DISABLE: - case TSPI_TX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx DMA Interrupt's parameter. - * @param param :Rx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_DMA_INT_DISABLE: - case TSPI_RX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Input Clock's parameter. - * @param param :Input Clock's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_clock(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_CLOCK_0: - case TSPI_BR_CLOCK_1: - case TSPI_BR_CLOCK_2: - case TSPI_BR_CLOCK_4: - case TSPI_BR_CLOCK_8: - case TSPI_BR_CLOCK_16: - case TSPI_BR_CLOCK_32: - case TSPI_BR_CLOCK_64: - case TSPI_BR_CLOCK_128: - case TSPI_BR_CLOCK_256: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Baudrate Divider's parameter. - * @param param :Baudrate Divider's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_divider(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_DIVIDER_16: - case TSPI_BR_DIVIDER_1: - case TSPI_BR_DIVIDER_2: - case TSPI_BR_DIVIDER_3: - case TSPI_BR_DIVIDER_4: - case TSPI_BR_DIVIDER_5: - case TSPI_BR_DIVIDER_6: - case TSPI_BR_DIVIDER_7: - case TSPI_BR_DIVIDER_8: - case TSPI_BR_DIVIDER_9: - case TSPI_BR_DIVIDER_10: - case TSPI_BR_DIVIDER_11: - case TSPI_BR_DIVIDER_12: - case TSPI_BR_DIVIDER_13: - case TSPI_BR_DIVIDER_14: - case TSPI_BR_DIVIDER_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Direction's parameter. - * @param param :Data Direction's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_data_direction(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_DIRECTION_LSB: - case TSPI_DATA_DIRECTION_MSB: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter (Only support 8bit DATA) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_length(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_LENGTH_8: - case TSPI_DATA_LENGTH_9: - case TSPI_DATA_LENGTH_10: - case TSPI_DATA_LENGTH_11: - case TSPI_DATA_LENGTH_12: - case TSPI_DATA_LENGTH_13: - case TSPI_DATA_LENGTH_14: - case TSPI_DATA_LENGTH_15: - case TSPI_DATA_LENGTH_16: - case TSPI_DATA_LENGTH_17: - case TSPI_DATA_LENGTH_18: - case TSPI_DATA_LENGTH_19: - case TSPI_DATA_LENGTH_20: - case TSPI_DATA_LENGTH_21: - case TSPI_DATA_LENGTH_22: - case TSPI_DATA_LENGTH_23: - case TSPI_DATA_LENGTH_24: - case TSPI_DATA_LENGTH_25: - case TSPI_DATA_LENGTH_26: - case TSPI_DATA_LENGTH_27: - case TSPI_DATA_LENGTH_28: - case TSPI_DATA_LENGTH_29: - case TSPI_DATA_LENGTH_30: - case TSPI_DATA_LENGTH_31: - case TSPI_DATA_LENGTH_32: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Frame Interval's parameter. - * @param param :Frame Interval's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Frame_Interval_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_interval(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_INTERVAL_TIME_0: - case TSPI_INTERVAL_TIME_1: - case TSPI_INTERVAL_TIME_2: - case TSPI_INTERVAL_TIME_3: - case TSPI_INTERVAL_TIME_4: - case TSPI_INTERVAL_TIME_5: - case TSPI_INTERVAL_TIME_6: - case TSPI_INTERVAL_TIME_7: - case TSPI_INTERVAL_TIME_8: - case TSPI_INTERVAL_TIME_9: - case TSPI_INTERVAL_TIME_10: - case TSPI_INTERVAL_TIME_11: - case TSPI_INTERVAL_TIME_12: - case TSPI_INTERVAL_TIME_13: - case TSPI_INTERVAL_TIME_14: - case TSPI_INTERVAL_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS3 Polarity's parameter. - * @param param :TTSPIxCS3 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS3_NEGATIVE: - case TSPI_TSPIxCS3_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS2 Polarity's parameter. - * @param param :TTSPIxCS2 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS2_NEGATIVE: - case TSPI_TSPIxCS2_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS1 Polarity's parameter. - * @param param :TTSPIxCS1 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS1_NEGATIVE: - case TSPI_TSPIxCS1_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS0 Polarity's parameter. - * @param param :TTSPIxCS0 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_NEGATIVE: - case TSPI_TSPIxCS0_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Polarity's parameter. - * @param param :Serial Clock Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_1ST_EDGE: - case TSPI_SERIAL_CK_2ND_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock IDLE Polarity's parameter. - * @param param :Serial Clock IDLE Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_IDLE_LOW: - case TSPI_SERIAL_CK_IDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Minimum IDLE Time's parameter. - * @param param :Minimum IDLE Time's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Minimum_IDLE_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_min_idle_time(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MIN_IDLE_TIME_1: - case TSPI_MIN_IDLE_TIME_2: - case TSPI_MIN_IDLE_TIME_3: - case TSPI_MIN_IDLE_TIME_4: - case TSPI_MIN_IDLE_TIME_5: - case TSPI_MIN_IDLE_TIME_6: - case TSPI_MIN_IDLE_TIME_7: - case TSPI_MIN_IDLE_TIME_8: - case TSPI_MIN_IDLE_TIME_9: - case TSPI_MIN_IDLE_TIME_10: - case TSPI_MIN_IDLE_TIME_11: - case TSPI_MIN_IDLE_TIME_12: - case TSPI_MIN_IDLE_TIME_13: - case TSPI_MIN_IDLE_TIME_14: - case TSPI_MIN_IDLE_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Delay's parameter. - * @param param :Serial Clock Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_DELAY_1: - case TSPI_SERIAL_CK_DELAY_2: - case TSPI_SERIAL_CK_DELAY_3: - case TSPI_SERIAL_CK_DELAY_4: - case TSPI_SERIAL_CK_DELAY_5: - case TSPI_SERIAL_CK_DELAY_6: - case TSPI_SERIAL_CK_DELAY_7: - case TSPI_SERIAL_CK_DELAY_8: - case TSPI_SERIAL_CK_DELAY_9: - case TSPI_SERIAL_CK_DELAY_10: - case TSPI_SERIAL_CK_DELAY_11: - case TSPI_SERIAL_CK_DELAY_12: - case TSPI_SERIAL_CK_DELAY_13: - case TSPI_SERIAL_CK_DELAY_14: - case TSPI_SERIAL_CK_DELAY_15: - case TSPI_SERIAL_CK_DELAY_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Negate Delay's parameter. - * @param param :Negate Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Negate_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_negate_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_NEGATE_1: - case TSPI_NEGATE_2: - case TSPI_NEGATE_3: - case TSPI_NEGATE_4: - case TSPI_NEGATE_5: - case TSPI_NEGATE_6: - case TSPI_NEGATE_7: - case TSPI_NEGATE_8: - case TSPI_NEGATE_9: - case TSPI_NEGATE_10: - case TSPI_NEGATE_11: - case TSPI_NEGATE_12: - case TSPI_NEGATE_13: - case TSPI_NEGATE_14: - case TSPI_NEGATE_15: - case TSPI_NEGATE_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_DISABLE: - case TSPI_PARITY_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_BIT_ODD: - case TSPI_PARITY_BIT_EVEN: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -#endif -/** - * @} - */ /* End of group TSPI_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_init(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxCR1. */ - assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); - assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); - assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); - assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); - assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); - assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); - /* Check the parameter of TTSPIxCR2 */ - assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); - assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); - assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); - assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); - assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); - assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); - assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); - assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); - assert_param(check_param_err_int(p_obj->init.cnt2.interr)); - assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); - assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); - /* Check the parameter of TTSPIxBR */ - assert_param(check_param_input_clock(p_obj->init.brd.brck)); - assert_param(check_param_input_divider(p_obj->init.brd.brs)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* TSPI Software Reset */ - p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); - p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);; - - /* Wait for 2 clocks of reset completion */ - __NOP(); - __NOP(); - - /* Enable the selected TSPI peripheral (TSPIE)*/ - p_obj->p_instance->CR0 = TSPI_ENABLE; - - /* Control1 Register1 Set*/ - p_obj->p_instance->CR1 = 0x00001C01U; - p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ - p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen); - /* Control2 Register Set */ - p_obj->p_instance->CR2 = 0x00E10100U; - p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ - p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \ - p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare ); - - /* Control3 Register is FIFO clear, do nothing */ - - /* Baudrate Register Set */ - p_obj->p_instance->BR = 0U; - p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); - - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = 0x8800C400U; - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = 0U; - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - - /* not created */ - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_deinit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Disable the selected TSPI peripheral */ - p_obj->p_instance->CR0 = TSPI_DISABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data.. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - - /* Transmit data check*/ - if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0)) - { - p_obj->errcode = DATABUFEMPERR; - result = TXZ_ERROR; - return (result); - } - - /* FIFO Cear */ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - /* Transmit Data write to D ata Register */ - while (p_info->tx8.num > 0) - { - /* Check the current fill level */ - if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) - { - *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); - p_info->tx8.num--; - /* check complete transmit */ - if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - else - { - /* Enable TSPI Transmission Control */ - if(p_info->tx8.num==0){ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - return (result); - } - else { - /* Next transmit data sending */ - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - } - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - - } - /* check complete transmit */ - while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - /* Check Error Flag */ - if((tspi_get_error(p_obj, &err)) != TXZ_ERROR) - { - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - }else{ - result = TXZ_ERROR; - return (result); - } - if(p_obj->errcode == NOERROR) { - //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - }else{ - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - uint32_t count = 0; - uint32_t index = 0; -// uint32_t level = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - /* Transmit data check*/ - if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0)) - { - result = TXZ_ERROR; - return (result); - } - count = p_info->rx8.num; - - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - while (timeout > 0) - { - /* Wait until Receive Complete Flag is set to receive data */ - if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) - { - while (count > 0) { - /* Check the remain data exist */ - if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){ - p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); - count--; - index++; - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - } - /* Receive Complete Flag is clear */ - p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; - /* FIFO Cear */ - p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - } - else {timeout--;} - } - /* Timeout management */ - p_obj->errcode = TIMEOUTERR; - - /* Check Error Flag set */ - if((tspi_get_error(p_obj, &err)) != TXZ_ERROR) - { - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - }else{ - result = TXZ_ERROR; - return (result); - } - - result = TXZ_ERROR; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - - - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data DMA. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /* Write to DMATE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE) - { - p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE; - } - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data DMA. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /* Write to DMARE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE) - { - p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE; - } - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_transmit(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - /* Check the transmit's end flag. */ - if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) || - ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Get the empty num in FIFO. */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - if (tlvl == TRANSFER_FIFO_MAX_NUM) - { - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.tx_allign = 8; - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.tx_allign = 16; - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.tx_allign = 32; - if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - #if 0 - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - #endif - } - } -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_receive(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.rx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - /* Check the receive's end flag. */ - if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) || - ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) - { - /* Read FIFO fill level. */ - __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); - //__IO uint32_t rlvl = 7; - /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ - if (rlvl > RECEIVE_FIFO_MAX_NUM) - { - rlvl = RECEIVE_FIFO_MAX_NUM; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; ireceive.rx_allign) - { - case 8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); - break; - case 16: - *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - case 32: - *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - tspi_receive_t param; - - switch (p_obj->receive.rx_allign) - { - case 8: - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - break; - case 16: - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - break; - case 32: - param.rx32.p_data = p_obj->receive.info.rx32.p_data; - param.rx32.num = rlvl; - break; - default: - /* no process */ - break; - } - /* Call the receive handler with SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_error_irq_handler(tspi_t *p_obj) -{ - __IO uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current TSPIxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- TSPIxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with FAILURE. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* UNDERERR */ - if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) - { - err = TXZ_ERROR; - } - /* OVRERR */ - if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - /* Call the receive handler with FAILURE. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); - } - } - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Data Format setting - * @param p_obj :TSPI object. - * @retval - - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_format(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | - * | 30-24 | - | - | - * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | - * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | - * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | - * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | - * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | - * | 15-8 | - | - | - * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | - * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | - * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | - * - * @param p_obj :TSPI object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_status is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI state */ - *p_status = p_obj->p_instance->SR; - if(p_status != TSPI_NULL){ return (result);} - else { - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI ERROR */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Error information clear. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_error_clear(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_transmit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_receive(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - - -/** - * @} - */ /* End of group TSPI_Exported_functions */ - -/** - * @} - */ /* End of group TSPI */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__TSPI_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c deleted file mode 100644 index 6ef89e65e51..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c +++ /dev/null @@ -1,1910 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart.c - * @brief This file provides API functions for UART driver. - * @version V1.0.0.1 - * $Date:: 2018-04-02 19:31:41 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_uart_include.h" -#include "txz_uart.h" - -#if defined(__UART_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/** - * @defgroup UART_BourateConfig Bourate Setting Configuration - * @brief Bourate Setting Configuration. - * @{ - */ -#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ -#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ -#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ - -#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ -#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ -#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL - -#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ -#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ -/** - * @} - */ /* End of group UART_BourateConfig */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_typedef UART Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_fuctions UART Private Fuctions - * @{ - */ -#ifdef DEBUG - __STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); - __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); - __STATIC_INLINE int32_t check_param_data_direction(uint32_t param); - __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); - __STATIC_INLINE int32_t check_param_data_length(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_err_int(uint32_t param); - __STATIC_INLINE int32_t check_param_prescaler(uint32_t param); - __STATIC_INLINE int32_t check_param_division(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeK(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeN(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); -#endif /* #ifdef DEBUG */ -__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); -__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) - static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); -#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Noize Fileter's parameter. - * @param param :Noize fileter's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_NOISE_FILTER_NON: - case UART_NOISE_FILTER_2_T0: - case UART_NOISE_FILTER_4_T0: - case UART_NOISE_FILTER_8_T0: - case UART_NOISE_FILTER_2_CLOCK: - case UART_NOISE_FILTER_3_CLOCK: - case UART_NOISE_FILTER_4_CLOCK: - case UART_NOISE_FILTER_5_CLOCK: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the CTS Handshake's parameter. - * @param param :CTS Handshake's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_CTS_DISABLE: - case UART_CTS_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the RTS Handshake's parameter. - * @param param :RTS Handshake's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RTS_DISABLE: - case UART_RTS_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Complementation's parameter. - * @param param :Data Complementation's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_COMPLEMENTION_DISABLE: - case UART_DATA_COMPLEMENTION_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Direction's parameter. - * @param param :Data Direction's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_DIRECTION_LSB: - case UART_DATA_DIRECTION_MSB: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Stop Bit's parameter. - * @param param :Stop Bit's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_STOP_BIT_1: - case UART_STOP_BIT_2: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PARITY_BIT_ODD: - case UART_PARITY_BIT_EVEN: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PARITY_DISABLE: - case UART_PARITY_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_length(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_LENGTH_7: - case UART_DATA_LENGTH_8: - case UART_DATA_LENGTH_9: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level Range's parameter. - * @param param :Tx Fill Level Range's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ -#if 0 - if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) -#else - if (param <= UART_TX_FILL_RANGE_MAX) -#endif - { - result = UART_PARAM_OK; - } - - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) - { - result = UART_PARAM_OK; - } - - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx FIFO Interrpt's parameter. - * @param param :Tx FIFO Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_TX_FIFO_INT_DISABLE: - case UART_TX_FIFO_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_TX_INT_DISABLE: - case UART_TX_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx FIFO Interrpt's parameter. - * @param param :Rx FIFO Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RX_FIFO_INT_DISABLE: - case UART_RX_FIFO_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RX_INT_DISABLE: - case UART_RX_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrupt's parameter. - * @param param :Error Interrupt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_err_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_ERR_INT_DISABLE: - case UART_ERR_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Prescaler's parameter. - * @param param :Prescaler's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PLESCALER_1: - case UART_PLESCALER_2: - case UART_PLESCALER_4: - case UART_PLESCALER_8: - case UART_PLESCALER_16: - case UART_PLESCALER_32: - case UART_PLESCALER_64: - case UART_PLESCALER_128: - case UART_PLESCALER_256: - case UART_PLESCALER_512: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Division's parameter. - * @param param :Division's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_division(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DIVISION_DISABLE: - case UART_DIVISION_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range K's parameter. - * @param param :Range K's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - /*--- Now, UART_RANGE_K_MIN is 0. ---*/ -#if 0 - if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) -#else - if (param <= UART_RANGE_K_MAX) -#endif - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range N's parameter. - * @param param :Range N's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for transmit. - * @param param :Num of buff. - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if (param != 0) - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for receive. - * @param param :Num of buff. - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if (param >= 8) - { - result = UART_PARAM_OK; - } - - return (result); -} -#endif /* #ifdef DEBUG */ - -/*--------------------------------------------------*/ -/** - * @brief Convert Tx FIFO fill level to register. - * @param level :Fill Level. - * @retval Register value. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) -{ - uint32_t result = (level << 12); - - return(result); -} - -/*--------------------------------------------------*/ -/** - * @brief Convert Rx FIFO fill level to register. - * @param level :Fill Level. - * @retval Register value. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) -{ - uint32_t result; - - if (level < 8) - { - result = (level << 8); - } - else - { - result = 0; - } - - return(result); -} - -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) -/*--------------------------------------------------*/ -/** - * @brief Check the within error margin. - * @param boudrate :Boudrate(bps). - * @param clock :Clock(hz). - * @param p_clk :Select Clock Setting. - * @param boudrate :Boudrate(bps). - * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" - * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" - * @param p_range64 :Error range(after fixed point bit shift). - * @retval TXZ_SUCCESS :Within error margin. - * @retval TXZ_ERROR :Without error margin. - * @note For N+(64-K)/64 division. - */ -/*--------------------------------------------------*/ -static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) -{ - TXZ_Result result = TXZ_ERROR; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 0; - - /* phi Tx */ - uint32_t prescaler = (p_clk->prsel >> 4); - - work64 = (uint64_t)((uint64_t)1 << prescaler); - tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT+2)); - tx64 /= work64; - - /* Bourate */ - boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - *p_range64 = ((boud64/100)*UART_CFG_BOUDRATE_ERROR_RANGE); - /* BourateX */ - work64 = (uint64_t)((uint64_t)n << 6); - work64 = (uint64_t)(work64 + (64-(uint64_t)k)); - work64 = (tx64 / work64); - if (boud64 >= *p_range64) - { - if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) - { - if( boud64 < work64 ) - { - *p_range64 = (work64 - boud64); - } - else - { - *p_range64 = (boud64 - work64); - } - result = TXZ_SUCCESS; - } - } - - return (result); -} -#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - -/** - * @} - */ /* End of group UART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the UART object. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_init(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(check_param_prescaler(p_obj->init.clock.prsel)); - assert_param(check_param_division(p_obj->init.boudrate.ken)); - assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); - assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); - assert_param(check_param_tx_int(p_obj->init.inttx)); - assert_param(check_param_rx_int(p_obj->init.intrx)); - assert_param(check_param_err_int(p_obj->init.interr)); - assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); - assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); - assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); - assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); - assert_param(check_param_noize_filter(p_obj->init.nf)); - assert_param(check_param_cts_handshake(p_obj->init.ctse)); - assert_param(check_param_rts_handshake(p_obj->init.rtse)); - assert_param(check_param_data_complemention(p_obj->init.iv)); - assert_param(check_param_data_direction(p_obj->init.dir)); - assert_param(check_param_stop_bit(p_obj->init.sblen)); - assert_param(check_param_parity_bit(p_obj->init.even)); - assert_param(check_param_parity_enable(p_obj->init.pe)); - assert_param(check_param_data_length(p_obj->init.sm)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* SW Reset */ - /*------------------------------*/ - /*--- UARTxSWRST ---*/ - /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ - /* Wait to "SWRSTF = 0". */ - while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) - { - /* no process */ - } - /* Write to SWRST(=10). */ - p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; - /* Write to SWRST(=01). */ - p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; - /* Wait to "SWRSTF = 0". */ - while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) - { - /* no process */ - } - /*------------------------------*/ - /* FIFO Clear */ - /*------------------------------*/ - /*--- UARTxFIFOCLR ---*/ - /* Write to TFCLR(=1), and RFCLR(=1) */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- UARTxCLK ---*/ - /* Reflecting "p_obj->init.clk" */ - p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); - /*--- UARTxBRD ---*/ - /* Reflecting "p_obj->init.brd" */ - /* Be careful, BRK needs to bit shit. */ - { - uint32_t brk = (p_obj->init.boudrate.brk << 16); - p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); - } - /*--- UARTxCR0 ---*/ - /* Reflecting "p_obj->init.cnt0" */ - p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | - p_obj->init.hcc | p_obj->init.lbc | - p_obj->init.nf | p_obj->init.ctse | - p_obj->init.rtse | p_obj->init.iv | - p_obj->init.dir | p_obj->init.sblen | - p_obj->init.even | p_obj->init.pe | - p_obj->init.sm); - /*--- UARTxCR1 ---*/ - /* Reflecting "p_obj->init.cnt1" */ - /* Fixed: "DMATE=0", "DMARE=0". */ - /* Be careful, "TIL", "RIL" need to bit shit. */ - p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | - convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | - p_obj->init.txfifo.inttx | p_obj->init.inttx | - p_obj->init.rxfifo.intrx | p_obj->init.intrx | - p_obj->init.interr); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the UART object. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_deinit(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*--- UARTxCR1 ---*/ - p_obj->p_instance->CR1 = 0; - /*--- UARTxCR0 ---*/ - p_obj->p_instance->CR0 = 0; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_discard_transmit(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t trans = 0; - uint32_t count = 10000000; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Read current UARTxTRANS value. */ - trans = p_obj->p_instance->TRANS; - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); - while((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) - { - if(--count == 0) - { - break; - } - } - /*--- UARTxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); - /*--- UARTxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /* Return RXE setting to UARTxTRANS */ - p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_discard_receive(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t trans = 0; - uint32_t count = 10000000; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Read current UARTxTRANS value. */ - trans = p_obj->p_instance->TRANS; - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Clear the receive's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); - while((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) - { - if(--count == 0) - { - break; - } - } - /*--- UARTxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to RFCLR(=1). */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_RFCLR_CLEAR); - /*--- UARTxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ - p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | - UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /* Return TXE setting to UARTxTRANS */ - p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :UART object. - * @param p_info :The information of transmit data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - assert_param(check_param_tx_buff_num(p_info->tx16.num)); - } - else - { - /* 7/8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - assert_param(check_param_tx_buff_num(p_info->tx8.num)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - if (p_obj->init.sm == UART_DATA_LENGTH_9) - { - /* 9 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - } - else - { - /* 7/8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /*--- UARTxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); - tlvl >>= 8; - /* FIFO Max = UART_TX_FIFO_MAX */ - if (tlvl > UART_TX_FIFO_MAX) - { - tlvl = UART_TX_FIFO_MAX; - } - /* Empty FIFO Num */ - { - uint32_t work = tlvl; - tlvl = (UART_TX_FIFO_MAX - work); - } - /*--- UARTxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_7: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=1). */ - /* Bitband Access. */ - enable_UARTxTRANS_TXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :UART object. - * @param p_info :The information of receive buffer. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - assert_param(check_param_rx_buff_num(p_info->rx16.num)); - } - else - { - /* 7/8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - assert_param(check_param_rx_buff_num(p_info->rx8.num)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - } - else - { - /* 7/8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to RXE(=1). */ - /* Bitband Access. */ - enable_UARTxTRANS_RXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_transmit_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current UARTxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) - { - /*---- UARTxSR ---*/ - /* Check the transmit's end flag. */ - if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || - ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - uint32_t tlvl = (status & UARTxSR_TLVL_MASK); - tlvl >>= 8; - /* FIFO Max = UART_TX_FIFO_MAX */ - if (tlvl > UART_TX_FIFO_MAX) - { - tlvl = UART_TX_FIFO_MAX; - } - /* Get the empty num in FIFO. */ - { - uint32_t work = tlvl; - tlvl = (UART_TX_FIFO_MAX - work); - } - if (tlvl == UART_TX_FIFO_MAX) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - break; - default: - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - break; - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != UART_NULL) - { - /* Call the transmit handler with TXZ_SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- UARTxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_7: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_receive_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current UARTxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) - { - /* Check the receive's end flag. */ - if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || - ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) - { - /* Read FIFO fill level. */ - uint32_t rlvl = (status & UARTxSR_RLVL_MASK); - /* FIFO Max = UART_RX_FIFO_MAX */ - if (rlvl > UART_RX_FIFO_MAX) - { - rlvl = UART_RX_FIFO_MAX; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; iinit.sm) - { - case UART_DATA_LENGTH_9: - *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); - break; - case UART_DATA_LENGTH_8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); - break; - case UART_DATA_LENGTH_7: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != UART_NULL) - { - uart_receive_t param; - - if (p_obj->init.sm == UART_DATA_LENGTH_9) - { - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - } - else - { - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - } - /* Call the receive handler with TXZ_SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_error_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current UARTxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- UARTxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) - { - /*------------------------------*/ - /* Transmit Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) - { - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != UART_NULL) - { - /* Call the transmit handler with TXZ_ERROR. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* OVRERR */ - if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) - { - err = TXZ_ERROR; - } - /* FERR */ - if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) - { - err = TXZ_ERROR; - } - /* BERR */ - if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != UART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | - * | 30-16 | - | - | - * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | - * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | - * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | - * | 12 | - | - | - * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | - * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | - * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | - * | 4 | - | - | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | - * - * @param p_obj :UART object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Read current UARTxSR. */ - *p_status = p_obj->p_instance->SR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-5 | - | - | - * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | - * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | - * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | - * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | - * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | - * - * @param p_obj :UART object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_error)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Read */ - /*------------------------------*/ - /*--- UARTxERR ---*/ - /* Read current UARTxERR. */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get the setting of boudrate. - * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". - * @param p_clk :Select Clock Setting. - * @param boudrate :Boudrate(bps). - * @param p_brd :Save area for Division Setting. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Not support setting. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) -{ - TXZ_Result result = TXZ_ERROR; -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) - uint64_t tx = 0; - uint64_t work = 0; - uint64_t range64 = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_clk)); - assert_param(IS_POINTER_NOT_NULL(p_brd)); - /* Check the parameter of UARTxCLK. */ -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Calculate Division Setting */ - /*------------------------------*/ - if ((clock > 0) && (boudrate > 0)) - { - /*--- phi Tx ---*/ - uint32_t prescaler = (p_clk->prsel >> 4); - - work = (uint64_t)((uint64_t)1 << prescaler); - tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - tx /= work; - - /*--- N+(64-K)/64 division ---*/ - { - uint8_t k = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) - { - work = tx + (uint64_t)k; - if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) - { - work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) - { - uint64_t workRange = 0; - - /* Verification */ - if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) - { -#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) - /* Compare the previous range. */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - } - else - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - result = TXZ_SUCCESS; -#else - /* Finish!! */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - } - else - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - result = TXZ_SUCCESS; - loopBreak = TXZ_DONE; -#endif - } - } - } - } - } - } -#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - - return (result); -} - -/** - * @} - */ /* End of group UART_Exported_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h deleted file mode 100644 index ecef2da7544..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h +++ /dev/null @@ -1,187 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - SERIAL_3, - SERIAL_4, - SERIAL_5, - SERIAL_6, - SERIAL_7, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - DAC_0 = 0, - DAC_1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11, - PWM_12, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - ADC_A0, - ADC_A1, - ADC_A2, - ADC_A3, - ADC_A4, - ADC_A5, - ADC_A6, - ADC_A7, - ADC_A8, - ADC_A9, - ADC_A10, - ADC_A11, - ADC_A12, - ADC_A13, - ADC_A14, - ADC_A15, - ADC_A16, - ADC_A17, - ADC_A18, - ADC_A19, - ADC_A20, - ADC_A21, - ADC_A22, - ADC_A23, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, - I2C_4, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, - SPI_5, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - GPIO_IRQ_0 = 0, - GPIO_IRQ_1 = 1, - GPIO_IRQ_2 = 2, - GPIO_IRQ_3 = 3, - GPIO_IRQ_4 = 4, - GPIO_IRQ_5 = 5, - GPIO_IRQ_6 = 6, - GPIO_IRQ_7 = 7, - GPIO_IRQ_8 = 8, - GPIO_IRQ_9 = 9, - GPIO_IRQ_A = 10, - GPIO_IRQ_B = 11, - GPIO_IRQ_C = 12, - GPIO_IRQ_D = 13, - GPIO_IRQ_E = 14, - GPIO_IRQ_F = 15, - INVALID_GPIO_IRQ = (int)NC -} GPIO_IRQName; - -// DAP UART -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -#define SERIAL_TX PU0 -#define SERIAL_RX PU1 - -#define STDIO_UART SERIAL_4 - -// TxD RxD -#define MBED_UART0 PE3, PE2 -#define MBED_UART1 PH1, PH0 -#define MBED_UART2 PG1, PG0 -#define MBED_UART3 PU7, PU6 -#define MBED_UART4 PM1, PM0 -#define MBED_UART5 PJ1, PJ0 -#define MBED_UART6 PG4, PG5 -#define MBED_UART7 PJ6, PJ7 -#define MBED_UARTUSB USBTX, USBRX - -// SDA SCK -#define MBED_I2C0 PG2, PG3 -#define MBED_I2C1 PF2, PF3 -#define MBED_I2C2 PG4, PG5 -#define MBED_I2C3 PJ6, PJ7 -#define MBED_I2C4 PJ3, PJ2 - -// MOSI, MISO, SCLK SS -#define MBED_SPI0 PA3, PA2, PA1, PA0 -#define MBED_SPI1 PL3, PL2, PL1, PL0 -#define MBED_SPI2 PA4, PA5, PA6, PA7 -#define MBED_SPI3 PK4, PK5, PK6, PK7 -#define MBED_SPI4 PD3, PD2, PD1, PD0 -#define MBED_SPI5 PM0, PM1, PM2, PM3 - -#define MBED_ANALOGIN0 A0 -#define MBED_ANALOGIN1 A1 -#define MBED_ANALOGIN2 A2 -#define MBED_ANALOGIN3 A3 -#define MBED_ANALOGIN4 A4 -#define MBED_ANALOGIN5 A5 - -#define MBED_PWMOUT0 PA5 -#define MBED_PWMOUT1 PB2 -#define MBED_PWMOUT2 PB4 -#define MBED_PWMOUT3 PD2 -#define MBED_PWMOUT4 PD4 -#define MBED_PWMOUT5 PE1 -#define MBED_PWMOUT6 PE6 -#define MBED_PWMOUT7 PC2 -#define MBED_PWMOUT8 PL6 -#define MBED_PWMOUT9 PC4 -#define MBED_PWMOUT10 PM2 -#define MBED_PWMOUT11 PU0 -#define MBED_PWMOUT12 PU6 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h deleted file mode 100644 index 28b0b37b20d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) - -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) -#define PIN_DIR(X) ((X) & 0xffff) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM4G9 Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, - PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, - PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7, - PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, - PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, - PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, - PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, - PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, - PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7, - PY0 = 19 << 3, PY1, PY2, PY3, PY4, - - // Other mbed Pin Names - LED0 = PE4, - LED1 = PE5, - LED2 = PE6, - LED3 = PE7, - - // External data bus Pin Names - D0 = PJ0, - D1 = PJ1, - D2 = PF4, - D3 = PB2, - D4 = PF5, - D5 = PB4, - D6 = PC2, - D7 = PF6, - D8 = PA4, - D9 = PC4, - D10 = PA6, - D11 = PA3, - D12 = PA2, - D13 = PA1, - D14 = PG2, - D15 = PG3, - - // Analogue out pins - A0 = PN0, - A1 = PN1, - A2 = PN2, - A3 = PN3, - A4 = PN4, - A5 = PN5, - - // USB2_UART - USBTX = PU0, - USBRX = PU1, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - MBED_CONF_APP_UART0_TX = PE3, - MBED_CONF_APP_UART0_RX = PE2, - - // Switches - SW1 = (int)0xFFFFFFFF, //Reset Button - SW2 = PL4, //Push button S2 - SW3 = PM0, //DIP switch J7_1 - SW4 = PM1, //DIP switch J7_2 - USER_BUTTON = PL4, - - // I2C pins - SDA = PG2, - SCL = PG3, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // SPI pins - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h deleted file mode 100644 index 3a3a0bda28c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, - PortT, - PortU, - PortV, - PortW, - PortY -} PortName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c deleted file mode 100644 index 35a3f5fd79d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "mbed_error.h" -#include "adc_include.h" - -#define ADC_12BIT_RANGE 0xFFF -#define CONVERSION_FLAG 0x4 - -static const PinMap PinMap_ADC[] = { - {PN0, ADC_A0, PIN_DATA(0, 0)}, - {PN1, ADC_A1, PIN_DATA(0, 0)}, - {PN2, ADC_A2, PIN_DATA(0, 0)}, - {PN3, ADC_A3, PIN_DATA(0, 0)}, - {PN4, ADC_A4, PIN_DATA(0, 0)}, - {PN5, ADC_A5, PIN_DATA(0, 0)}, - {PN6, ADC_A6, PIN_DATA(0, 0)}, - {PN7, ADC_A7, PIN_DATA(0, 0)}, - {PP0, ADC_A8, PIN_DATA(0, 0)}, - {PP1, ADC_A9, PIN_DATA(0, 0)}, - {PP2, ADC_A10, PIN_DATA(0, 0)}, - {PP3, ADC_A11, PIN_DATA(0, 0)}, - {PP4, ADC_A12, PIN_DATA(0, 0)}, - {PP5, ADC_A13, PIN_DATA(0, 0)}, - {PP6, ADC_A14, PIN_DATA(0, 0)}, - {PP7, ADC_A15, PIN_DATA(0, 0)}, - {PR0, ADC_A16, PIN_DATA(0, 0)}, - {PR1, ADC_A17, PIN_DATA(0, 0)}, - {PR2, ADC_A18, PIN_DATA(0, 0)}, - {PR3, ADC_A19, PIN_DATA(0, 0)}, - {PR4, ADC_A20, PIN_DATA(0, 0)}, - {PR5, ADC_A21, PIN_DATA(0, 0)}, - {PR6, ADC_A22, PIN_DATA(0, 0)}, - {PR7, ADC_A23, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Enable ADC clock supply - TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; - TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE; - TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; - - // Enable clock for GPIO - if(obj->adc <= ADC_A7) { - TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE; - } else if(obj->adc <= ADC_A15) { - TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE; - } else { - TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE; - } - - // Set pin function as ADC - pinmap_pinout(pin, PinMap_ADC); - - // Initialize - obj->p_adc.p_instance = TSB_ADA; - obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN; - obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN; - obj->p_adc.init.clk.vadcld = ADC_SCLK_1; - obj->p_adc.init.mod1 = ADC_MOD1_SCLK_3; - obj->p_adc.init.mod2 = ADC_MOD2_TMPM4G9; - obj->p_adc.handler.single = NULL; - obj->p_adc.handler.continuity = NULL; - obj->p_adc.handler.trigger = NULL; - obj->p_adc.handler.highpriority = NULL; - - if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { - error("Failed : ADC Initialization"); - } - - // ADC channel setting - obj->param.interrupt = ADC_INT_DISABLE; - obj->param.type = ADC_CONVERSION_SGL; - obj->param.ain = obj->adc; - - if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { - error("Failed : ADC channel setting"); - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t adc_result = 0; - - // Assert that ADC channel is valid - MBED_ASSERT(obj->adc != (ADCName)NC); - - if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { - // adc started - } - - // wait for Continuous conversion program flag clear. - while((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { - // Do nothing... - } - - if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { - error("Failed : To read ADC converted result"); - } - - if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { - error("Failed : To Stop ADC Conversion"); - } - return (uint16_t)adc_result; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c deleted file mode 100644 index bdbf9b3e4dd..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c +++ /dev/null @@ -1,127 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "cmsis.h" -#include "analogout_api.h" -#include "pinmap.h" - -#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable. -#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable. -#define DAC_RANGE (0xFF) // 8 bits -#define DAC_NB_BITS (8) -#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out -#define DAC1_CLR_IN_CLR_OUT (2) -#define MAX_ANALOG_VAL (1.0f) -#define MIN_ANALOG_VAL (0.0f) -#define MAX_DIGITAL_VAL (0xFF) -#define MIN_DIGITAL_VAL (0x00) - -static const PinMap PinMap_DAC[] = { - {PT0, DAC_0, PIN_DATA(0, 1)}, - {PT1, DAC_1, PIN_DATA(0, 1)}, - {NC, NC, 0} -}; - -static inline void dac_write(dac_t *obj,int val) -{ - // Set the DAC output - obj->DACx->REG = (val &= DAC_RANGE); -} - -static inline int dac_read(dac_t *obj) -{ - return ((obj->DACx->REG) & DAC_RANGE); -} - -void analogout_init(dac_t *obj, PinName pin) -{ - DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(dac_name != (DACName)NC); - obj->dac = dac_name; - switch (dac_name) { - case DAC_0: - obj->DACx = TSB_DA0; - //Enable clock for DAC0 and Port T - TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; - break; - case DAC_1: - obj->DACx = TSB_DA1; - //Enable clock for DAC1 and Port T - TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; - break; - default: - break; - } - // Pinout the chosen DAC - pinmap_pinout(pin, PinMap_DAC); - //DAC pins as neither input and nor output - if(dac_name == DAC_0) { - TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT); - TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT); - } else if(dac_name == DAC_1) { - TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT); - TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT); - } else { - return; - } - - //Enable DAC - obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; - analogout_write_u16(obj, MIN_DIGITAL_VAL); -} - -void analogout_free(dac_t *obj) -{ - obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; - obj->dac = (DACName)NC; -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < MIN_ANALOG_VAL) { - dac_write(obj, MIN_DIGITAL_VAL); - } else if (value > MAX_ANALOG_VAL) { - dac_write(obj,DAC_RANGE); - } else { - dac_write(obj, value * (float)DAC_RANGE); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - // writing higher 8-bits to Data Register - dac_write(obj, (value >> (16 - DAC_NB_BITS))); -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)value * (MAX_ANALOG_VAL / (float)DAC_RANGE); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint32_t value = dac_read(obj); - //Upper and lower byte stored with read value - return ((value << (16 - DAC_NB_BITS)) | value); -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device.h b/targets/TARGET_TT/TARGET_TT_M4G9/device.h deleted file mode 100644 index d05e3ffe69c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 - -#include "objects.h" -#include - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h deleted file mode 100644 index 89371d636e8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h +++ /dev/null @@ -1,6129 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM4G9.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version V1.0.9.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM4G9 - * @{ - */ - -#ifndef __TMPM4G9_H__ -#define __TMPM4G9_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ - -/****** TMPM4G9 Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */ - INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ - INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ - INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ - INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ - INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ - INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ - INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ - INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ - INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */ - INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */ - INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ - INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */ - INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */ - INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ - INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */ - INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */ - INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */ - INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */ - INTISDA_IRQn = 19, /*!< Interval Sensing Detector Interrupt (Unit A) */ - INTISDB_IRQn = 20, /*!< Interval Sensing Detector Interrupt (Unit B) */ - INTISDC_IRQn = 21, /*!< Interval Sensing Detector Interrupt (Unit C) */ - INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */ - INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */ - INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */ - INTHDMAATC_IRQn = 25, /*!< HDMA Complete of transfer(Unit A) */ - INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */ - INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */ - INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */ - INTMDMAATC_IRQn = 29, /*!< MDMA Complete of transfer(Unit A) */ - INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA All Interrupt/Timer Interrupt C */ - INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA All Interrupt/Timer Interrupt C */ - INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA All Interrupt/Timer Interrupt C */ - INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA All Interrupt/Timer Interrupt C */ - INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA All Interrupt/Timer Interrupt C */ - INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA All Interrupt/Timer Interrupt C */ - INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA All Interrupt/Timer Interrupt C */ - INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA All Interrupt/Timer Interrupt C */ - INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA All Interrupt/Timer Interrupt C */ - INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA All Interrupt/Timer Interrupt C */ - INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA All Interrupt/Timer Interrupt C */ - INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA All Interrupt/Timer Interrupt C */ - INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA All Interrupt/Timer Interrupt C */ - INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA All Interrupt/Timer Interrupt C */ - INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */ - INTPWM0_IRQn = 60, /*!< PMD0 interrupt */ - INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) */ - INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) */ - INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) */ - INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) */ - INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) */ - INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) */ - INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) */ - INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) */ - INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) */ - INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) */ - INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) */ - INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) */ - INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) */ - INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) */ - INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) */ - INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) */ - INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) */ - INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) */ - INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) */ - INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) */ - INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) */ - INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) */ - INTSMI0_IRQn = 88, /*!< Serial Memory Interface Interrupt */ - INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) */ - INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) */ - INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) */ - INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) */ - INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) */ - INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) */ - INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) */ - INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) */ - INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) */ - INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) */ - INTFUART0_IRQn = 107, /*!< FUART Interrupt(channel 0) */ - INTFUART1_IRQn = 108, /*!< FUART Interrupt(channel 1) */ - INTI2C0_IRQn = 109, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 110, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 111, /*!< I2C0 bus free interrupt */ - INTI2C0NACK_IRQn = 112, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 113, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 114, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 115, /*!< I2C1 bus free interrupt */ - INTI2C1NACK_IRQn = 116, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 117, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 118, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 119, /*!< I2C2 bus free interrupt */ - INTI2C2NACK_IRQn = 120, /*!< I2C2 no ack interrupt */ - INTI2C3_IRQn = 121, /*!< I2C3 transmission and reception interrupt */ - INTI2C3AL_IRQn = 122, /*!< I2C3 arbitration lost interrupt */ - INTI2C3BF_IRQn = 123, /*!< I2C3 bus free interrupt */ - INTI2C3NACK_IRQn = 124, /*!< I2C3 no ack interrupt */ - INTI2C4_IRQn = 125, /*!< I2C4 transmission and reception interrupt */ - INTI2C4AL_IRQn = 126, /*!< I2C4 arbitration lost interrupt */ - INTI2C4BF_IRQn = 127, /*!< I2C4 bus free interrupt */ - INTI2C4NACK_IRQn = 128, /*!< I2C4 no ack interrupt */ - INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */ - INTADAHP_IRQn = 134, /*!< ADC High Priority AD conversion interrupt */ - INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */ - INTFLCRDY0_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */ - INTFLCRDY1_IRQn = 137, /*!< Code FLASH Area2 Ready interrupt */ - INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) */ - INTMDMAADERR_IRQn = 140 /*!< MDMA descriptor error(Unit A) */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_TMPM4G9.h" /* TMPM4G9 System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */ - __I uint32_t INTTCSTATUS; /*!< DMAC Interrupt Terminal Count Status Register*/ - __O uint32_t INTTCCLEAR; /*!< DMAC Interrupt Terminal Count Clear Register */ - __I uint32_t INTERRORSTATUS; /*!< DMAC Interrupt Error Status Register */ - __O uint32_t INTERRCLR; /*!< DMAC Interrupt Error Clear Register */ - __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Interrupt Terminal Count Status Register*/ - __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */ - __I uint32_t ENBLDCHNS; /*!< DMAC Enabled Channel Register */ - __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Request Register */ - __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Request Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */ - uint32_t RESERVED1[51]; - __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Source Address Register */ - __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Destination Address Register */ - __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */ - __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */ - __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */ - uint32_t RESERVED2[3]; - __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Source Address Register */ - __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Destination Address Register */ - __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */ - __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */ - __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */ -} TSB_DMAC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MAP0; /*!< SMIF Flash Memory Map0 Register */ - __IO uint32_t MAP1; /*!< SMIF Flash Memory Map1 Register */ - __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */ - __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */ - __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */ - __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */ - uint32_t RESERVED0[250]; - __IO uint32_t RACR0; /*!< SMIF Program Register Access Control Register 0*/ - __IO uint32_t RACR1; /*!< SMIF Program Register Access Control Register 1*/ - __IO uint32_t INT; /*!< SMIF Program Register Access Interrupt Enable Register*/ - __IO uint32_t STAT; /*!< SMIF Program Register Access Status Register */ - uint32_t RESERVED1[60]; - __IO uint32_t PBUF0; /*!< SMIF Program Register Primary Buffer Data Register 0*/ - __IO uint32_t PBUF1; /*!< SMIF Program Register Primary Buffer Data Register 1*/ - uint32_t RESERVED2[62]; - __IO uint32_t SBUF00; /*!< SMIF Program Register Secondary Buffer Data Register 00*/ - __IO uint32_t SBUF01; /*!< SMIF Program Register Secondary Buffer Data Register 01*/ - __IO uint32_t SBUF02; /*!< SMIF Program Register Secondary Buffer Data Register 02*/ - __IO uint32_t SBUF03; /*!< SMIF Program Register Secondary Buffer Data Register 03*/ - __IO uint32_t SBUF04; /*!< SMIF Program Register Secondary Buffer Data Register 04*/ - __IO uint32_t SBUF05; /*!< SMIF Program Register Secondary Buffer Data Register 05*/ - __IO uint32_t SBUF06; /*!< SMIF Program Register Secondary Buffer Data Register 06*/ - __IO uint32_t SBUF07; /*!< SMIF Program Register Secondary Buffer Data Register 07*/ - __IO uint32_t SBUF08; /*!< SMIF Program Register Secondary Buffer Data Register 08*/ - __IO uint32_t SBUF09; /*!< SMIF Program Register Secondary Buffer Data Register 09*/ - __IO uint32_t SBUF10; /*!< SMIF Program Register Secondary Buffer Data Register 10*/ - __IO uint32_t SBUF11; /*!< SMIF Program Register Secondary Buffer Data Register 11*/ - __IO uint32_t SBUF12; /*!< SMIF Program Register Secondary Buffer Data Register 12*/ - __IO uint32_t SBUF13; /*!< SMIF Program Register Secondary Buffer Data Register 13*/ - __IO uint32_t SBUF14; /*!< SMIF Program Register Secondary Buffer Data Register 14*/ - __IO uint32_t SBUF15; /*!< SMIF Program Register Secondary Buffer Data Register 15*/ - __IO uint32_t SBUF16; /*!< SMIF Program Register Secondary Buffer Data Register 16*/ - __IO uint32_t SBUF17; /*!< SMIF Program Register Secondary Buffer Data Register 17*/ - __IO uint32_t SBUF18; /*!< SMIF Program Register Secondary Buffer Data Register 18*/ - __IO uint32_t SBUF19; /*!< SMIF Program Register Secondary Buffer Data Register 19*/ - __IO uint32_t SBUF20; /*!< SMIF Program Register Secondary Buffer Data Register 20*/ - __IO uint32_t SBUF21; /*!< SMIF Program Register Secondary Buffer Data Register 21*/ - __IO uint32_t SBUF22; /*!< SMIF Program Register Secondary Buffer Data Register 22*/ - __IO uint32_t SBUF23; /*!< SMIF Program Register Secondary Buffer Data Register 23*/ - __IO uint32_t SBUF24; /*!< SMIF Program Register Secondary Buffer Data Register 24*/ - __IO uint32_t SBUF25; /*!< SMIF Program Register Secondary Buffer Data Register 25*/ - __IO uint32_t SBUF26; /*!< SMIF Program Register Secondary Buffer Data Register 26*/ - __IO uint32_t SBUF27; /*!< SMIF Program Register Secondary Buffer Data Register 27*/ - __IO uint32_t SBUF28; /*!< SMIF Program Register Secondary Buffer Data Register 28*/ - __IO uint32_t SBUF29; /*!< SMIF Program Register Secondary Buffer Data Register 29*/ - __IO uint32_t SBUF30; /*!< SMIF Program Register Secondary Buffer Data Register 30*/ - __IO uint32_t SBUF31; /*!< SMIF Program Register Secondary Buffer Data Register 31*/ - __IO uint32_t SBUF32; /*!< SMIF Program Register Secondary Buffer Data Register 32*/ - __IO uint32_t SBUF33; /*!< SMIF Program Register Secondary Buffer Data Register 33*/ - __IO uint32_t SBUF34; /*!< SMIF Program Register Secondary Buffer Data Register 34*/ - __IO uint32_t SBUF35; /*!< SMIF Program Register Secondary Buffer Data Register 35*/ - __IO uint32_t SBUF36; /*!< SMIF Program Register Secondary Buffer Data Register 36*/ - __IO uint32_t SBUF37; /*!< SMIF Program Register Secondary Buffer Data Register 37*/ - __IO uint32_t SBUF38; /*!< SMIF Program Register Secondary Buffer Data Register 38*/ - __IO uint32_t SBUF39; /*!< SMIF Program Register Secondary Buffer Data Register 39*/ - __IO uint32_t SBUF40; /*!< SMIF Program Register Secondary Buffer Data Register 40*/ - __IO uint32_t SBUF41; /*!< SMIF Program Register Secondary Buffer Data Register 41*/ - __IO uint32_t SBUF42; /*!< SMIF Program Register Secondary Buffer Data Register 42*/ - __IO uint32_t SBUF43; /*!< SMIF Program Register Secondary Buffer Data Register 43*/ - __IO uint32_t SBUF44; /*!< SMIF Program Register Secondary Buffer Data Register 44*/ - __IO uint32_t SBUF45; /*!< SMIF Program Register Secondary Buffer Data Register 45*/ - __IO uint32_t SBUF46; /*!< SMIF Program Register Secondary Buffer Data Register 46*/ - __IO uint32_t SBUF47; /*!< SMIF Program Register Secondary Buffer Data Register 47*/ - __IO uint32_t SBUF48; /*!< SMIF Program Register Secondary Buffer Data Register 48*/ - __IO uint32_t SBUF49; /*!< SMIF Program Register Secondary Buffer Data Register 49*/ - __IO uint32_t SBUF50; /*!< SMIF Program Register Secondary Buffer Data Register 50*/ - __IO uint32_t SBUF51; /*!< SMIF Program Register Secondary Buffer Data Register 51*/ - __IO uint32_t SBUF52; /*!< SMIF Program Register Secondary Buffer Data Register 52*/ - __IO uint32_t SBUF53; /*!< SMIF Program Register Secondary Buffer Data Register 53*/ - __IO uint32_t SBUF54; /*!< SMIF Program Register Secondary Buffer Data Register 54*/ - __IO uint32_t SBUF55; /*!< SMIF Program Register Secondary Buffer Data Register 55*/ - __IO uint32_t SBUF56; /*!< SMIF Program Register Secondary Buffer Data Register 56*/ - __IO uint32_t SBUF57; /*!< SMIF Program Register Secondary Buffer Data Register 57*/ - __IO uint32_t SBUF58; /*!< SMIF Program Register Secondary Buffer Data Register 58*/ - __IO uint32_t SBUF59; /*!< SMIF Program Register Secondary Buffer Data Register 59*/ - __IO uint32_t SBUF60; /*!< SMIF Program Register Secondary Buffer Data Register 60*/ - __IO uint32_t SBUF61; /*!< SMIF Program Register Secondary Buffer Data Register 61*/ - __IO uint32_t SBUF62; /*!< SMIF Program Register Secondary Buffer Data Register 62*/ - __IO uint32_t SBUF63; /*!< SMIF Program Register Secondary Buffer Data Register 63*/ -} TSB_SMI_TypeDef; - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non Maskable interrupt Mode Control Register A 00*/ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< interrupt Mode Control Register A 00 */ - __IO uint8_t IMC01; /*!< interrupt Mode Control Register A 01 */ - __IO uint8_t IMC02; /*!< interrupt Mode Control Register A 02 */ - __IO uint8_t IMC03; /*!< interrupt Mode Control Register A 03 */ - __IO uint8_t IMC04; /*!< interrupt Mode Control Register A 04 */ - __IO uint8_t IMC05; /*!< interrupt Mode Control Register A 05 */ - __IO uint8_t IMC06; /*!< interrupt Mode Control Register A 06 */ - __IO uint8_t IMC07; /*!< interrupt Mode Control Register A 07 */ - __IO uint8_t IMC08; /*!< interrupt Mode Control Register A 08 */ - __IO uint8_t IMC09; /*!< interrupt Mode Control Register A 09 */ - __IO uint8_t IMC10; /*!< interrupt Mode Control Register A 10 */ - __IO uint8_t IMC11; /*!< interrupt Mode Control Register A 11 */ - __IO uint8_t IMC12; /*!< interrupt Mode Control Register A 12 */ - __IO uint8_t IMC13; /*!< interrupt Mode Control Register A 13 */ - __IO uint8_t IMC14; /*!< interrupt Mode Control Register A 14 */ - __IO uint8_t IMC15; /*!< interrupt Mode Control Register A 15 */ - __IO uint8_t IMC16; /*!< interrupt Mode Control Register A 16 */ - __IO uint8_t IMC17; /*!< interrupt Mode Control Register A 17 */ - __IO uint8_t IMC18; /*!< interrupt Mode Control Register A 18 */ - __IO uint8_t IMC19; /*!< interrupt Mode Control Register A 19 */ - __IO uint8_t IMC20; /*!< interrupt Mode Control Register A 20 */ - __IO uint8_t IMC21; /*!< interrupt Mode Control Register A 21 */ - __IO uint8_t IMC22; /*!< interrupt Mode Control Register A 22 */ - __IO uint8_t IMC23; /*!< interrupt Mode Control Register A 23 */ - __IO uint8_t IMC24; /*!< interrupt Mode Control Register A 24 */ - __IO uint8_t IMC25; /*!< interrupt Mode Control Register A 25 */ - __IO uint8_t IMC26; /*!< interrupt Mode Control Register A 26 */ - __IO uint8_t IMC27; /*!< interrupt Mode Control Register A 27 */ - __IO uint8_t IMC28; /*!< interrupt Mode Control Register A 28 */ - __IO uint8_t IMC29; /*!< interrupt Mode Control Register A 29 */ - __IO uint8_t IMC30; /*!< interrupt Mode Control Register A 30 */ - __IO uint8_t IMC31; /*!< interrupt Mode Control Register A 31 */ - uint8_t RESERVED1[17]; - __IO uint8_t IMC49; /*!< interrupt Mode Control Register A 49 */ - __IO uint8_t IMC50; /*!< interrupt Mode Control Register A 50 */ - __IO uint8_t IMC51; /*!< interrupt Mode Control Register A 51 */ - __IO uint8_t IMC52; /*!< interrupt Mode Control Register A 52 */ - __IO uint8_t IMC53; /*!< interrupt Mode Control Register A 53 */ - __IO uint8_t IMC54; /*!< interrupt Mode Control Register A 54 */ - __IO uint8_t IMC55; /*!< interrupt Mode Control Register A 55 */ - __IO uint8_t IMC56; /*!< interrupt Mode Control Register A 56 */ - __IO uint8_t IMC57; /*!< interrupt Mode Control Register A 57 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset Low power Management Register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC and IHOSC2 clock supply Control Register*/ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR1; /*!< LVD Control register1 */ - __IO uint8_t CR2; /*!< LVD Control register2 */ - __IO uint8_t LVL1; /*!< LVD detection voltage select register 1 */ - __IO uint8_t LVL2; /*!< LVD detection voltage select register 2 */ - __I uint8_t SR; /*!< LVD status register */ -} TSB_LVD_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ - __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ - __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ - __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ -} TSB_TSEL_TypeDef; - -/** - * @brief Long Term Timer(LTTMR) - */ -typedef struct -{ - __IO uint8_t CR0; /*!< Long Term Control Register */ - __IO uint8_t VALL; /*!< Long Term Setting Register */ - __IO uint8_t VALH; /*!< Long Term Setting Register */ -} TSB_LTT_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -/** - * @brief External Bus Interface(EXB) - */ -typedef struct -{ - __IO uint32_t MOD; /*!< External Bus Mode Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t AS0; /*!< External Bus Base Address and CS Space setting Register 0*/ - __IO uint32_t AS1; /*!< External Bus Base Address and CS Space setting Register 1 */ - __IO uint32_t AS2; /*!< External Bus Base Address and CS Space setting Register 2*/ - __IO uint32_t AS3; /*!< External Bus Base Address and CS Space setting Register 3*/ - uint32_t RESERVED1[8]; - __IO uint32_t CS0; /*!< Chip Select and Wait Controller Register 0 */ - __IO uint32_t CS1; /*!< Chip Select and Wait Controller Register 1 */ - __IO uint32_t CS2; /*!< Chip Select and Wait Controller Register 2 */ - __IO uint32_t CS3; /*!< Chip Select and Wait Controller Register 3 */ - uint32_t RESERVED2[4]; - __IO uint32_t CLKCTL; /*!< Clock output controlRegister */ -} TSB_EXB_TypeDef; - -/** - * @brief Clock Generator (CG) - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< Protect Register */ - __IO uint32_t OSCCR; /*!< Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< System Clock Control Register */ - __IO uint32_t STBYCR; /*!< Standby Control Register */ - uint32_t RESERVED0[4]; - __IO uint32_t PLL0SEL; /*!< PLL Selection Register 0 */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< High OSC Warming-up Register */ - __IO uint32_t WUPLCR; /*!< Low OSC Warming-up Register */ - uint32_t RESERVED2[4]; - __IO uint32_t FSYSMENA; /*!< Middle fsys Supply Stop Register A */ - __IO uint32_t FSYSMENB; /*!< Middle fsys Supply Stop Register A */ - __IO uint32_t FSYSENA; /*!< High fsys Supply Stop Register A */ - uint32_t RESERVED3; - __IO uint32_t FCEN; /*!< FC Supply Stop Register */ - __IO uint32_t SPCLKEN; /*!< ADC TRACE Clock Supply Stop Register */ - uint32_t RESERVED4[2]; - __IO uint32_t EXTEND2; /*!< Extend for MDMAC Register */ -} TSB_CG_TypeDef; - -/** - * @brief Interrupt Control B Register - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non maskable interrupt Control Register 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< interrupt Mode Control Register 000 */ - __IO uint8_t IMC001; /*!< interrupt Mode Control Register 001 */ - __IO uint8_t IMC002; /*!< interrupt Mode Control Register 002 */ - __IO uint8_t IMC003; /*!< interrupt Mode Control Register 003 */ - __IO uint8_t IMC004; /*!< interrupt Mode Control Register 004 */ - __IO uint8_t IMC005; /*!< interrupt Mode Control Register 005 */ - __IO uint8_t IMC006; /*!< interrupt Mode Control Register 006 */ - __IO uint8_t IMC007; /*!< interrupt Mode Control Register 007 */ - __IO uint8_t IMC008; /*!< interrupt Mode Control Register 008 */ - __IO uint8_t IMC009; /*!< interrupt Mode Control Register 009 */ - __IO uint8_t IMC010; /*!< interrupt Mode Control Register 010 */ - __IO uint8_t IMC011; /*!< interrupt Mode Control Register 011 */ - __IO uint8_t IMC012; /*!< interrupt Mode Control Register 012 */ - __IO uint8_t IMC013; /*!< interrupt Mode Control Register 013 */ - __IO uint8_t IMC014; /*!< interrupt Mode Control Register 014 */ - __IO uint8_t IMC015; /*!< interrupt Mode Control Register 015 */ - __IO uint8_t IMC016; /*!< interrupt Mode Control Register 016 */ - __IO uint8_t IMC017; /*!< interrupt Mode Control Register 017 */ - __IO uint8_t IMC018; /*!< interrupt Mode Control Register 018 */ - __IO uint8_t IMC019; /*!< interrupt Mode Control Register 019 */ - __IO uint8_t IMC020; /*!< interrupt Mode Control Register 020 */ - __IO uint8_t IMC021; /*!< interrupt Mode Control Register 021 */ - __IO uint8_t IMC022; /*!< interrupt Mode Control Register 022 */ - __IO uint8_t IMC023; /*!< interrupt Mode Control Register 023 */ - __IO uint8_t IMC024; /*!< interrupt Mode Control Register 024 */ - __IO uint8_t IMC025; /*!< interrupt Mode Control Register 025 */ - __IO uint8_t IMC026; /*!< interrupt Mode Control Register 026 */ - __IO uint8_t IMC027; /*!< interrupt Mode Control Register 027 */ - __IO uint8_t IMC028; /*!< interrupt Mode Control Register 028 */ - __IO uint8_t IMC029; /*!< interrupt Mode Control Register 029 */ - __IO uint8_t IMC030; /*!< interrupt Mode Control Register 030 */ - __IO uint8_t IMC031; /*!< interrupt Mode Control Register 031 */ - __IO uint8_t IMC032; /*!< interrupt Mode Control Register 032 */ - __IO uint8_t IMC033; /*!< interrupt Mode Control Register 033 */ - __IO uint8_t IMC034; /*!< interrupt Mode Control Register 034 */ - __IO uint8_t IMC035; /*!< interrupt Mode Control Register 035 */ - __IO uint8_t IMC036; /*!< interrupt Mode Control Register 036 */ - __IO uint8_t IMC037; /*!< interrupt Mode Control Register 037 */ - __IO uint8_t IMC038; /*!< interrupt Mode Control Register 038 */ - __IO uint8_t IMC039; /*!< interrupt Mode Control Register 039 */ - __IO uint8_t IMC040; /*!< interrupt Mode Control Register 040 */ - __IO uint8_t IMC041; /*!< interrupt Mode Control Register 041 */ - __IO uint8_t IMC042; /*!< interrupt Mode Control Register 042 */ - __IO uint8_t IMC043; /*!< interrupt Mode Control Register 043 */ - __IO uint8_t IMC044; /*!< interrupt Mode Control Register 044 */ - __IO uint8_t IMC045; /*!< interrupt Mode Control Register 045 */ - __IO uint8_t IMC046; /*!< interrupt Mode Control Register 046 */ - __IO uint8_t IMC047; /*!< interrupt Mode Control Register 047 */ - __IO uint8_t IMC048; /*!< interrupt Mode Control Register 048 */ - __IO uint8_t IMC049; /*!< interrupt Mode Control Register 049 */ - __IO uint8_t IMC050; /*!< interrupt Mode Control Register 050 */ - __IO uint8_t IMC051; /*!< interrupt Mode Control Register 051 */ - __IO uint8_t IMC052; /*!< interrupt Mode Control Register 052 */ - __IO uint8_t IMC053; /*!< interrupt Mode Control Register 053 */ - __IO uint8_t IMC054; /*!< interrupt Mode Control Register 054 */ - __IO uint8_t IMC055; /*!< interrupt Mode Control Register 055 */ - __IO uint8_t IMC056; /*!< interrupt Mode Control Register 056 */ - __IO uint8_t IMC057; /*!< interrupt Mode Control Register 057 */ - __IO uint8_t IMC058; /*!< interrupt Mode Control Register 058 */ - __IO uint8_t IMC059; /*!< interrupt Mode Control Register 059 */ - __IO uint8_t IMC060; /*!< interrupt Mode Control Register 060 */ - __IO uint8_t IMC061; /*!< interrupt Mode Control Register 061 */ - __IO uint8_t IMC062; /*!< interrupt Mode Control Register 062 */ - __IO uint8_t IMC063; /*!< interrupt Mode Control Register 063 */ - __IO uint8_t IMC064; /*!< interrupt Mode Control Register 064 */ - __IO uint8_t IMC065; /*!< interrupt Mode Control Register 065 */ - __IO uint8_t IMC066; /*!< interrupt Mode Control Register 066 */ - __IO uint8_t IMC067; /*!< interrupt Mode Control Register 067 */ - __IO uint8_t IMC068; /*!< interrupt Mode Control Register 068 */ - __IO uint8_t IMC069; /*!< interrupt Mode Control Register 069 */ - __IO uint8_t IMC070; /*!< interrupt Mode Control Register 070 */ - __IO uint8_t IMC071; /*!< interrupt Mode Control Register 071 */ - __IO uint8_t IMC072; /*!< interrupt Mode Control Register 072 */ - __IO uint8_t IMC073; /*!< interrupt Mode Control Register 073 */ - __IO uint8_t IMC074; /*!< interrupt Mode Control Register 074 */ - __IO uint8_t IMC075; /*!< interrupt Mode Control Register 075 */ - __IO uint8_t IMC076; /*!< interrupt Mode Control Register 076 */ - __IO uint8_t IMC077; /*!< interrupt Mode Control Register 077 */ - __IO uint8_t IMC078; /*!< interrupt Mode Control Register 078 */ - __IO uint8_t IMC079; /*!< interrupt Mode Control Register 079 */ - __IO uint8_t IMC080; /*!< interrupt Mode Control Register 080 */ - __IO uint8_t IMC081; /*!< interrupt Mode Control Register 081 */ - __IO uint8_t IMC082; /*!< interrupt Mode Control Register 082 */ - __IO uint8_t IMC083; /*!< interrupt Mode Control Register 083 */ - __IO uint8_t IMC084; /*!< interrupt Mode Control Register 084 */ - __IO uint8_t IMC085; /*!< interrupt Mode Control Register 085 */ - __IO uint8_t IMC086; /*!< interrupt Mode Control Register 086 */ - __IO uint8_t IMC087; /*!< interrupt Mode Control Register 087 */ - __IO uint8_t IMC088; /*!< interrupt Mode Control Register 088 */ - __IO uint8_t IMC089; /*!< interrupt Mode Control Register 089 */ - __IO uint8_t IMC090; /*!< interrupt Mode Control Register 090 */ - __IO uint8_t IMC091; /*!< interrupt Mode Control Register 091 */ - __IO uint8_t IMC092; /*!< interrupt Mode Control Register 092 */ - __IO uint8_t IMC093; /*!< interrupt Mode Control Register 093 */ - __IO uint8_t IMC094; /*!< interrupt Mode Control Register 094 */ - __IO uint8_t IMC095; /*!< interrupt Mode Control Register 095 */ - __IO uint8_t IMC096; /*!< interrupt Mode Control Register 096 */ - __IO uint8_t IMC097; /*!< interrupt Mode Control Register 097 */ - __IO uint8_t IMC098; /*!< interrupt Mode Control Register 098 */ - __IO uint8_t IMC099; /*!< interrupt Mode Control Register 099 */ - __IO uint8_t IMC100; /*!< interrupt Mode Control Register 100 */ - __IO uint8_t IMC101; /*!< interrupt Mode Control Register 101 */ - __IO uint8_t IMC102; /*!< interrupt Mode Control Register 102 */ - __IO uint8_t IMC103; /*!< interrupt Mode Control Register 103 */ - __IO uint8_t IMC104; /*!< interrupt Mode Control Register 104 */ - __IO uint8_t IMC105; /*!< interrupt Mode Control Register 105 */ - __IO uint8_t IMC106; /*!< interrupt Mode Control Register 106 */ - __IO uint8_t IMC107; /*!< interrupt Mode Control Register 107 */ - __IO uint8_t IMC108; /*!< interrupt Mode Control Register 108 */ - __IO uint8_t IMC109; /*!< interrupt Mode Control Register 109 */ - __IO uint8_t IMC110; /*!< interrupt Mode Control Register 110 */ - __IO uint8_t IMC111; /*!< interrupt Mode Control Register 111 */ - __IO uint8_t IMC112; /*!< interrupt Mode Control Register 112 */ - __IO uint8_t IMC113; /*!< interrupt Mode Control Register 113 */ - __IO uint8_t IMC114; /*!< interrupt Mode Control Register 114 */ - __IO uint8_t IMC115; /*!< interrupt Mode Control Register 115 */ - __IO uint8_t IMC116; /*!< interrupt Mode Control Register 116 */ - __IO uint8_t IMC117; /*!< interrupt Mode Control Register 117 */ - __IO uint8_t IMC118; /*!< interrupt Mode Control Register 118 */ - __IO uint8_t IMC119; /*!< interrupt Mode Control Register 119 */ - __IO uint8_t IMC120; /*!< interrupt Mode Control Register 120 */ - __IO uint8_t IMC121; /*!< interrupt Mode Control Register 121 */ - __IO uint8_t IMC122; /*!< interrupt Mode Control Register 122 */ - __IO uint8_t IMC123; /*!< interrupt Mode Control Register 123 */ - __IO uint8_t IMC124; /*!< interrupt Mode Control Register 124 */ - __IO uint8_t IMC125; /*!< interrupt Mode Control Register 125 */ - __IO uint8_t IMC126; /*!< interrupt Mode Control Register 126 */ - __IO uint8_t IMC127; /*!< interrupt Mode Control Register 127 */ - __IO uint8_t IMC128; /*!< interrupt Mode Control Register 128 */ - __IO uint8_t IMC129; /*!< interrupt Mode Control Register 129 */ - __IO uint8_t IMC130; /*!< interrupt Mode Control Register 130 */ - __IO uint8_t IMC131; /*!< interrupt Mode Control Register 131 */ - __IO uint8_t IMC132; /*!< interrupt Mode Control Register 132 */ - __IO uint8_t IMC133; /*!< interrupt Mode Control Register 133 */ - __IO uint8_t IMC134; /*!< interrupt Mode Control Register 134 */ - __IO uint8_t IMC135; /*!< interrupt Mode Control Register 135 */ - __IO uint8_t IMC136; /*!< interrupt Mode Control Register 136 */ - __IO uint8_t IMC137; /*!< interrupt Mode Control Register 137 */ - __IO uint8_t IMC138; /*!< interrupt Mode Control Register 138 */ - __IO uint8_t IMC139; /*!< interrupt Mode Control Register 139 */ - __IO uint8_t IMC140; /*!< interrupt Mode Control Register 140 */ - __IO uint8_t IMC141; /*!< interrupt Mode Control Register 141 */ -} TSB_IB_TypeDef; - -/** - * @brief Interrupt Monitor Register - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< NMI Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 (032 - 063) */ - __I uint32_t FLG2; /*!< Interrupt Monitor Flag 2 (064 - 095) */ - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 (096 - 127) */ - __I uint32_t FLG4; /*!< Interrupt Monitor Flag 4 (128 - 159) */ - __I uint32_t FLG5; /*!< Interrupt Monitor Flag 5 (160 - 191) */ - __I uint32_t FLG6; /*!< Interrupt Monitor Flag 6 (192 - 223) */ - __I uint32_t FLG7; /*!< Interrupt Monitor Flag 7 (224 - 225) */ -} TSB_IMN_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief Watchdog Timer (WD) - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect Register */ - __IO uint32_t EN; /*!< SIWD Enable Register */ - __O uint32_t CR; /*!< SIWD Control Register */ - __IO uint32_t MOD; /*!< SIWD Mode Register */ - __I uint32_t MONI; /*!< SIWD Monitor Register */ -} TSB_SIWD_TypeDef; - -/** - * @brief NBD - */ -typedef struct -{ - __IO uint32_t CR0; /*!< NBD control register 0 */ - __IO uint32_t CR1; /*!< NBD control register 1 */ -} TSB_NBD_TypeDef; - -/** - * @brief Malti Porpose Direct Memory Accsess(MDMA) - */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t CEN; /*!< MDMAC Channel Enable Register */ - __IO uint32_t REQ; /*!< MDMAC Transfer Request Register */ - __IO uint32_t SUS; /*!< MDMAC Transfer Suspension Register */ - __IO uint32_t ACT; /*!< MDMAC Transfer Active Register */ - __IO uint32_t END; /*!< MDMAC Transfer End Register */ - __IO uint32_t PRI; /*!< MDMAC Priority Setting Register */ - __IO uint32_t ENE; /*!< MDMAC End Interrupt Enable Register */ - __IO uint32_t DTAB; /*!< MDMAC Channel Information Address Register */ - uint32_t RESERVED1; - __I uint32_t CHN; /*!< MDMAC Channel Number Register */ - __I uint32_t XFTYP; /*!< MDMAC Channel Number Register */ - __I uint32_t XFSAD; /*!< MDMAC Transfer Source Address Register */ - __I uint32_t XFDAD; /*!< MDMAC Transfer Destination Address Register */ - __I uint32_t XFSIZ; /*!< MDMAC Transfer Size Register */ - __I uint32_t DSADS; /*!< MDMAC Descriptor Address Register */ - __I uint32_t DSNUM; /*!< MDMAC Descriptor Number Register */ - uint32_t RESERVED2[3]; - __I uint32_t C00XFTYP; /*!< MDMAC Channel 00 Number Avoidance Register */ - __I uint32_t C00XFSAD; /*!< MDMAC Channel 00 Transfer Source Address Avoidance Register*/ - __I uint32_t C00XFDAD; /*!< MDMAC Channel 00 Transfer Destination Address Avoidance Register*/ - __I uint32_t C00XFSIZ; /*!< MDMAC Channel 00 Transfer Size Avoidance Register*/ - __I uint32_t C00DSADS; /*!< MDMAC Channel 00 Descriptor Address Avoidance Register*/ - __I uint32_t C00DSNUM; /*!< MDMAC Channel 00 Descriptor Number Avoidance Register*/ - uint32_t RESERVED3[2]; - __I uint32_t C01XFTYP; /*!< MDMAC Channel 01 Number Avoidance Register */ - __I uint32_t C01XFSAD; /*!< MDMAC Channel 01 Transfer Source Address Avoidance Register*/ - __I uint32_t C01XFDAD; /*!< MDMAC Channel 01 Transfer Destination Address Avoidance Register*/ - __I uint32_t C01XFSIZ; /*!< MDMAC Channel 01 Transfer Size Avoidance Register*/ - __I uint32_t C01DSADS; /*!< MDMAC Channel 01 Descriptor Address Avoidance Register*/ - __I uint32_t C01DSNUM; /*!< MDMAC Channel 01 Descriptor Number Avoidance Register*/ - uint32_t RESERVED4[2]; - __I uint32_t C02XFTYP; /*!< MDMAC Channel 02 Number Avoidance Register */ - __I uint32_t C02XFSAD; /*!< MDMAC Channel 02 Transfer Source Address Avoidance Register*/ - __I uint32_t C02XFDAD; /*!< MDMAC Channel 02 Transfer Destination Address Avoidance Register*/ - __I uint32_t C02XFSIZ; /*!< MDMAC Channel 02 Transfer Size Avoidance Register*/ - __I uint32_t C02DSADS; /*!< MDMAC Channel 02 Descriptor Address Avoidance Register*/ - __I uint32_t C02DSNUM; /*!< MDMAC Channel 02 Descriptor Number Avoidance Register*/ - uint32_t RESERVED5[2]; - __I uint32_t C03XFTYP; /*!< MDMAC Channel 03 Number Avoidance Register */ - __I uint32_t C03XFSAD; /*!< MDMAC Channel 03 Transfer Source Address Avoidance Register*/ - __I uint32_t C03XFDAD; /*!< MDMAC Channel 03 Transfer Destination Address Avoidance Register*/ - __I uint32_t C03XFSIZ; /*!< MDMAC Channel 03 Transfer Size Avoidance Register*/ - __I uint32_t C03DSADS; /*!< MDMAC Channel 03 Descriptor Address Avoidance Register*/ - __I uint32_t C03DSNUM; /*!< MDMAC Channel 03 Descriptor Number Avoidance Register*/ - uint32_t RESERVED6[2]; - __I uint32_t C04XFTYP; /*!< MDMAC Channel 04 Number Avoidance Register */ - __I uint32_t C04XFSAD; /*!< MDMAC Channel 04 Transfer Source Address Avoidance Register*/ - __I uint32_t C04XFDAD; /*!< MDMAC Channel 04 Transfer Destination Address Avoidance Register*/ - __I uint32_t C04XFSIZ; /*!< MDMAC Channel 04 Transfer Size Avoidance Register*/ - __I uint32_t C04DSADS; /*!< MDMAC Channel 04 Descriptor Address Avoidance Register*/ - __I uint32_t C04DSNUM; /*!< MDMAC Channel 04 Descriptor Number Avoidance Register*/ - uint32_t RESERVED7[2]; - __I uint32_t C05XFTYP; /*!< MDMAC Channel 05 Number Avoidance Register */ - __I uint32_t C05XFSAD; /*!< MDMAC Channel 05 Transfer Source Address Avoidance Register*/ - __I uint32_t C05XFDAD; /*!< MDMAC Channel 05 Transfer Destination Address Avoidance Register*/ - __I uint32_t C05XFSIZ; /*!< MDMAC Channel 05 Transfer Size Avoidance Register*/ - __I uint32_t C05DSADS; /*!< MDMAC Channel 05 Descriptor Address Avoidance Register*/ - __I uint32_t C05DSNUM; /*!< MDMAC Channel 05 Descriptor Number Avoidance Register*/ - uint32_t RESERVED8[2]; - __I uint32_t C06XFTYP; /*!< MDMAC Channel 06 Number Avoidance Register */ - __I uint32_t C06XFSAD; /*!< MDMAC Channel 06 Transfer Source Address Avoidance Register*/ - __I uint32_t C06XFDAD; /*!< MDMAC Channel 06 Transfer Destination Address Avoidance Register*/ - __I uint32_t C06XFSIZ; /*!< MDMAC Channel 06 Transfer Size Avoidance Register*/ - __I uint32_t C06DSADS; /*!< MDMAC Channel 06 Descriptor Address Avoidance Register*/ - __I uint32_t C06DSNUM; /*!< MDMAC Channel 06 Descriptor Number Avoidance Register*/ - uint32_t RESERVED9[2]; - __I uint32_t C07XFTYP; /*!< MDMAC Channel 07 Number Avoidance Register */ - __I uint32_t C07XFSAD; /*!< MDMAC Channel 07 Transfer Source Address Avoidance Register*/ - __I uint32_t C07XFDAD; /*!< MDMAC Channel 07 Transfer Destination Address Avoidance Register*/ - __I uint32_t C07XFSIZ; /*!< MDMAC Channel 07 Transfer Size Avoidance Register*/ - __I uint32_t C07DSADS; /*!< MDMAC Channel 07 Descriptor Address Avoidance Register*/ - __I uint32_t C07DSNUM; /*!< MDMAC Channel 07 Descriptor Number Avoidance Register*/ - uint32_t RESERVED10[2]; - __I uint32_t C08XFTYP; /*!< MDMAC Channel 08 Number Avoidance Register */ - __I uint32_t C08XFSAD; /*!< MDMAC Channel 08 Transfer Source Address Avoidance Register*/ - __I uint32_t C08XFDAD; /*!< MDMAC Channel 08 Transfer Destination Address Avoidance Register*/ - __I uint32_t C08XFSIZ; /*!< MDMAC Channel 08 Transfer Size Avoidance Register*/ - __I uint32_t C08DSADS; /*!< MDMAC Channel 08 Descriptor Address Avoidance Register*/ - __I uint32_t C08DSNUM; /*!< MDMAC Channel 08 Descriptor Number Avoidance Register*/ - uint32_t RESERVED11[2]; - __I uint32_t C09XFTYP; /*!< MDMAC Channel 09 Number Avoidance Register */ - __I uint32_t C09XFSAD; /*!< MDMAC Channel 09 Transfer Source Address Avoidance Register*/ - __I uint32_t C09XFDAD; /*!< MDMAC Channel 09 Transfer Destination Address Avoidance Register*/ - __I uint32_t C09XFSIZ; /*!< MDMAC Channel 09 Transfer Size Avoidance Register*/ - __I uint32_t C09DSADS; /*!< MDMAC Channel 09 Descriptor Address Avoidance Register*/ - __I uint32_t C09DSNUM; /*!< MDMAC Channel 09 Descriptor Number Avoidance Register*/ - uint32_t RESERVED12[2]; - __I uint32_t C10XFTYP; /*!< MDMAC Channel 10 Number Avoidance Register */ - __I uint32_t C10XFSAD; /*!< MDMAC Channel 10 Transfer Source Address Avoidance Register*/ - __I uint32_t C10XFDAD; /*!< MDMAC Channel 10 Transfer Destination Address Avoidance Register*/ - __I uint32_t C10XFSIZ; /*!< MDMAC Channel 10 Transfer Size Avoidance Register*/ - __I uint32_t C10DSADS; /*!< MDMAC Channel 10 Descriptor Address Avoidance Register*/ - __I uint32_t C10DSNUM; /*!< MDMAC Channel 10 Descriptor Number Avoidance Register*/ - uint32_t RESERVED13[2]; - __I uint32_t C11XFTYP; /*!< MDMAC Channel 11 Number Avoidance Register */ - __I uint32_t C11XFSAD; /*!< MDMAC Channel 11 Transfer Source Address Avoidance Register*/ - __I uint32_t C11XFDAD; /*!< MDMAC Channel 11 Transfer Destination Address Avoidance Register*/ - __I uint32_t C11XFSIZ; /*!< MDMAC Channel 11 Transfer Size Avoidance Register*/ - __I uint32_t C11DSADS; /*!< MDMAC Channel 11 Descriptor Address Avoidance Register*/ - __I uint32_t C11DSNUM; /*!< MDMAC Channel 11 Descriptor Number Avoidance Register*/ - uint32_t RESERVED14[2]; - __I uint32_t C12XFTYP; /*!< MDMAC Channel 12 Number Avoidance Register */ - __I uint32_t C12XFSAD; /*!< MDMAC Channel 12 Transfer Source Address Avoidance Register*/ - __I uint32_t C12XFDAD; /*!< MDMAC Channel 12 Transfer Destination Address Avoidance Register*/ - __I uint32_t C12XFSIZ; /*!< MDMAC Channel 12 Transfer Size Avoidance Register*/ - __I uint32_t C12DSADS; /*!< MDMAC Channel 12 Descriptor Address Avoidance Register*/ - __I uint32_t C12DSNUM; /*!< MDMAC Channel 12 Descriptor Number Avoidance Register*/ - uint32_t RESERVED15[2]; - __I uint32_t C13XFTYP; /*!< MDMAC Channel 13 Number Avoidance Register */ - __I uint32_t C13XFSAD; /*!< MDMAC Channel 13 Transfer Source Address Avoidance Register*/ - __I uint32_t C13XFDAD; /*!< MDMAC Channel 13 Transfer Destination Address Avoidance Register*/ - __I uint32_t C13XFSIZ; /*!< MDMAC Channel 13 Transfer Size Avoidance Register*/ - __I uint32_t C13DSADS; /*!< MDMAC Channel 13 Descriptor Address Avoidance Register*/ - __I uint32_t C13DSNUM; /*!< MDMAC Channel 13 Descriptor Number Avoidance Register*/ - uint32_t RESERVED16[2]; - __I uint32_t C14XFTYP; /*!< MDMAC Channel 14 Number Avoidance Register */ - __I uint32_t C14XFSAD; /*!< MDMAC Channel 14 Transfer Source Address Avoidance Register*/ - __I uint32_t C14XFDAD; /*!< MDMAC Channel 14 Transfer Destination Address Avoidance Register*/ - __I uint32_t C14XFSIZ; /*!< MDMAC Channel 14 Transfer Size Avoidance Register*/ - __I uint32_t C14DSADS; /*!< MDMAC Channel 14 Descriptor Address Avoidance Register*/ - __I uint32_t C14DSNUM; /*!< MDMAC Channel 14 Descriptor Number Avoidance Register*/ - uint32_t RESERVED17[2]; - __I uint32_t C15XFTYP; /*!< MDMAC Channel 15 Number Avoidance Register */ - __I uint32_t C15XFSAD; /*!< MDMAC Channel 15 Transfer Source Address Avoidance Register*/ - __I uint32_t C15XFDAD; /*!< MDMAC Channel 15 Transfer Destination Address Avoidance Register*/ - __I uint32_t C15XFSIZ; /*!< MDMAC Channel 15 Transfer Size Avoidance Register*/ - __I uint32_t C15DSADS; /*!< MDMAC Channel 15 Descriptor Address Avoidance Register*/ - __I uint32_t C15DSNUM; /*!< MDMAC Channel 15 Descriptor Number Avoidance Register*/ - uint32_t RESERVED18[2]; - __I uint32_t C16XFTYP; /*!< MDMAC Channel 16 Number Avoidance Register */ - __I uint32_t C16XFSAD; /*!< MDMAC Channel 16 Transfer Source Address Avoidance Register*/ - __I uint32_t C16XFDAD; /*!< MDMAC Channel 16 Transfer Destination Address Avoidance Register*/ - __I uint32_t C16XFSIZ; /*!< MDMAC Channel 16 Transfer Size Avoidance Register*/ - __I uint32_t C16DSADS; /*!< MDMAC Channel 16 Descriptor Address Avoidance Register*/ - __I uint32_t C16DSNUM; /*!< MDMAC Channel 16 Descriptor Number Avoidance Register*/ - uint32_t RESERVED19[2]; - __I uint32_t C17XFTYP; /*!< MDMAC Channel 17 Number Avoidance Register */ - __I uint32_t C17XFSAD; /*!< MDMAC Channel 17 Transfer Source Address Avoidance Register*/ - __I uint32_t C17XFDAD; /*!< MDMAC Channel 17 Transfer Destination Address Avoidance Register*/ - __I uint32_t C17XFSIZ; /*!< MDMAC Channel 17 Transfer Size Avoidance Register*/ - __I uint32_t C17DSADS; /*!< MDMAC Channel 17 Descriptor Address Avoidance Register*/ - __I uint32_t C17DSNUM; /*!< MDMAC Channel 17 Descriptor Number Avoidance Register*/ - uint32_t RESERVED20[2]; - __I uint32_t C18XFTYP; /*!< MDMAC Channel 18 Number Avoidance Register */ - __I uint32_t C18XFSAD; /*!< MDMAC Channel 18 Transfer Source Address Avoidance Register*/ - __I uint32_t C18XFDAD; /*!< MDMAC Channel 18 Transfer Destination Address Avoidance Register*/ - __I uint32_t C18XFSIZ; /*!< MDMAC Channel 18 Transfer Size Avoidance Register*/ - __I uint32_t C18DSADS; /*!< MDMAC Channel 18 Descriptor Address Avoidance Register*/ - __I uint32_t C18DSNUM; /*!< MDMAC Channel 18 Descriptor Number Avoidance Register*/ - uint32_t RESERVED21[2]; - __I uint32_t C19XFTYP; /*!< MDMAC Channel 19 Number Avoidance Register */ - __I uint32_t C19XFSAD; /*!< MDMAC Channel 19 Transfer Source Address Avoidance Register*/ - __I uint32_t C19XFDAD; /*!< MDMAC Channel 19 Transfer Destination Address Avoidance Register*/ - __I uint32_t C19XFSIZ; /*!< MDMAC Channel 19 Transfer Size Avoidance Register*/ - __I uint32_t C19DSADS; /*!< MDMAC Channel 19 Descriptor Address Avoidance Register*/ - __I uint32_t C19DSNUM; /*!< MDMAC Channel 19 Descriptor Number Avoidance Register*/ - uint32_t RESERVED22[2]; - __I uint32_t C20XFTYP; /*!< MDMAC Channel 20 Number Avoidance Register */ - __I uint32_t C20XFSAD; /*!< MDMAC Channel 20 Transfer Source Address Avoidance Register*/ - __I uint32_t C20XFDAD; /*!< MDMAC Channel 20 Transfer Destination Address Avoidance Register*/ - __I uint32_t C20XFSIZ; /*!< MDMAC Channel 20 Transfer Size Avoidance Register*/ - __I uint32_t C20DSADS; /*!< MDMAC Channel 20 Descriptor Address Avoidance Register*/ - __I uint32_t C20DSNUM; /*!< MDMAC Channel 20 Descriptor Number Avoidance Register*/ - uint32_t RESERVED23[2]; - __I uint32_t C21XFTYP; /*!< MDMAC Channel 21 Number Avoidance Register */ - __I uint32_t C21XFSAD; /*!< MDMAC Channel 21 Transfer Source Address Avoidance Register*/ - __I uint32_t C21XFDAD; /*!< MDMAC Channel 21 Transfer Destination Address Avoidance Register*/ - __I uint32_t C21XFSIZ; /*!< MDMAC Channel 21 Transfer Size Avoidance Register*/ - __I uint32_t C21DSADS; /*!< MDMAC Channel 21 Descriptor Address Avoidance Register*/ - __I uint32_t C21DSNUM; /*!< MDMAC Channel 21 Descriptor Number Avoidance Register*/ - uint32_t RESERVED24[2]; - __I uint32_t C22XFTYP; /*!< MDMAC Channel 22 Number Avoidance Register */ - __I uint32_t C22XFSAD; /*!< MDMAC Channel 22 Transfer Source Address Avoidance Register*/ - __I uint32_t C22XFDAD; /*!< MDMAC Channel 22 Transfer Destination Address Avoidance Register*/ - __I uint32_t C22XFSIZ; /*!< MDMAC Channel 22 Transfer Size Avoidance Register*/ - __I uint32_t C22DSADS; /*!< MDMAC Channel 22 Descriptor Address Avoidance Register*/ - __I uint32_t C22DSNUM; /*!< MDMAC Channel 22 Descriptor Number Avoidance Register*/ - uint32_t RESERVED25[2]; - __I uint32_t C23XFTYP; /*!< MDMAC Channel 23 Number Avoidance Register */ - __I uint32_t C23XFSAD; /*!< MDMAC Channel 23 Transfer Source Address Avoidance Register*/ - __I uint32_t C23XFDAD; /*!< MDMAC Channel 23 Transfer Destination Address Avoidance Register*/ - __I uint32_t C23XFSIZ; /*!< MDMAC Channel 23 Transfer Size Avoidance Register*/ - __I uint32_t C23DSADS; /*!< MDMAC Channel 23 Descriptor Address Avoidance Register*/ - __I uint32_t C23DSNUM; /*!< MDMAC Channel 23 Descriptor Number Avoidance Register*/ - uint32_t RESERVED26[2]; - __I uint32_t C24XFTYP; /*!< MDMAC Channel 24 Number Avoidance Register */ - __I uint32_t C24XFSAD; /*!< MDMAC Channel 24 Transfer Source Address Avoidance Register*/ - __I uint32_t C24XFDAD; /*!< MDMAC Channel 24 Transfer Destination Address Avoidance Register*/ - __I uint32_t C24XFSIZ; /*!< MDMAC Channel 24 Transfer Size Avoidance Register*/ - __I uint32_t C24DSADS; /*!< MDMAC Channel 24 Descriptor Address Avoidance Register*/ - __I uint32_t C24DSNUM; /*!< MDMAC Channel 24 Descriptor Number Avoidance Register*/ - uint32_t RESERVED27[2]; - __I uint32_t C25XFTYP; /*!< MDMAC Channel 25 Number Avoidance Register */ - __I uint32_t C25XFSAD; /*!< MDMAC Channel 25 Transfer Source Address Avoidance Register*/ - __I uint32_t C25XFDAD; /*!< MDMAC Channel 25 Transfer Destination Address Avoidance Register*/ - __I uint32_t C25XFSIZ; /*!< MDMAC Channel 25 Transfer Size Avoidance Register*/ - __I uint32_t C25DSADS; /*!< MDMAC Channel 25 Descriptor Address Avoidance Register*/ - __I uint32_t C25DSNUM; /*!< MDMAC Channel 25 Descriptor Number Avoidance Register*/ - uint32_t RESERVED28[2]; - __I uint32_t C26XFTYP; /*!< MDMAC Channel 26 Number Avoidance Register */ - __I uint32_t C26XFSAD; /*!< MDMAC Channel 26 Transfer Source Address Avoidance Register*/ - __I uint32_t C26XFDAD; /*!< MDMAC Channel 26 Transfer Destination Address Avoidance Register*/ - __I uint32_t C26XFSIZ; /*!< MDMAC Channel 26 Transfer Size Avoidance Register*/ - __I uint32_t C26DSADS; /*!< MDMAC Channel 26 Descriptor Address Avoidance Register*/ - __I uint32_t C26DSNUM; /*!< MDMAC Channel 26 Descriptor Number Avoidance Register*/ - uint32_t RESERVED29[2]; - __I uint32_t C27XFTYP; /*!< MDMAC Channel 27 Number Avoidance Register */ - __I uint32_t C27XFSAD; /*!< MDMAC Channel 27 Transfer Source Address Avoidance Register*/ - __I uint32_t C27XFDAD; /*!< MDMAC Channel 27 Transfer Destination Address Avoidance Register*/ - __I uint32_t C27XFSIZ; /*!< MDMAC Channel 27 Transfer Size Avoidance Register*/ - __I uint32_t C27DSADS; /*!< MDMAC Channel 27 Descriptor Address Avoidance Register*/ - __I uint32_t C27DSNUM; /*!< MDMAC Channel 27 Descriptor Number Avoidance Register*/ - uint32_t RESERVED30[2]; - __I uint32_t C28XFTYP; /*!< MDMAC Channel 28 Number Avoidance Register */ - __I uint32_t C28XFSAD; /*!< MDMAC Channel 28 Transfer Source Address Avoidance Register*/ - __I uint32_t C28XFDAD; /*!< MDMAC Channel 28 Transfer Destination Address Avoidance Register*/ - __I uint32_t C28XFSIZ; /*!< MDMAC Channel 28 Transfer Size Avoidance Register*/ - __I uint32_t C28DSADS; /*!< MDMAC Channel 28 Descriptor Address Avoidance Register*/ - __I uint32_t C28DSNUM; /*!< MDMAC Channel 28 Descriptor Number Avoidance Register*/ - uint32_t RESERVED31[2]; - __I uint32_t C29XFTYP; /*!< MDMAC Channel 29 Number Avoidance Register */ - __I uint32_t C29XFSAD; /*!< MDMAC Channel 29 Transfer Source Address Avoidance Register*/ - __I uint32_t C29XFDAD; /*!< MDMAC Channel 29 Transfer Destination Address Avoidance Register*/ - __I uint32_t C29XFSIZ; /*!< MDMAC Channel 29 Transfer Size Avoidance Register*/ - __I uint32_t C29DSADS; /*!< MDMAC Channel 29 Descriptor Address Avoidance Register*/ - __I uint32_t C29DSNUM; /*!< MDMAC Channel 29 Descriptor Number Avoidance Register*/ - uint32_t RESERVED32[2]; - __I uint32_t C30XFTYP; /*!< MDMAC Channel 30 Number Avoidance Register */ - __I uint32_t C30XFSAD; /*!< MDMAC Channel 30 Transfer Source Address Avoidance Register*/ - __I uint32_t C30XFDAD; /*!< MDMAC Channel 30 Transfer Destination Address Avoidance Register*/ - __I uint32_t C30XFSIZ; /*!< MDMAC Channel 30 Transfer Size Avoidance Register*/ - __I uint32_t C30DSADS; /*!< MDMAC Channel 30 Descriptor Address Avoidance Register*/ - __I uint32_t C30DSNUM; /*!< MDMAC Channel 30 Descriptor Number Avoidance Register*/ - uint32_t RESERVED33[2]; - __I uint32_t C31XFTYP; /*!< MDMAC Channel 31 Number Avoidance Register */ - __I uint32_t C31XFSAD; /*!< MDMAC Channel 31 Transfer Source Address Avoidance Register*/ - __I uint32_t C31XFDAD; /*!< MDMAC Channel 31 Transfer Destination Address Avoidance Register*/ - __I uint32_t C31XFSIZ; /*!< MDMAC Channel 31 Transfer Size Avoidance Register*/ - __I uint32_t C31DSADS; /*!< MDMAC Channel 31 Descriptor Address Avoidance Register*/ - __I uint32_t C31DSNUM; /*!< MDMAC Channel 31 Descriptor Number Avoidance Register*/ - uint32_t RESERVED34[238]; - __IO uint32_t MSK; /*!< MDMAC Mask Register */ -} TSB_MDMA_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief ARM Prime Cell PL011 - */ -typedef struct -{ - __IO uint32_t DR; /*!< Data Register */ -union { - __I uint32_t RSR; /*!< Receive Status Register */ - __O uint32_t ECR; /*!< Error Clear Register */ - }; - uint32_t RESERVED0[4]; - __I uint32_t FR; /*!< Flag Register */ - uint32_t RESERVED1; - __IO uint32_t ILPR; /*!< IrDA Low-power Counter register */ - __IO uint32_t BRD; /*!< Integer Baud Rate Register */ - __IO uint32_t FBRD; /*!< Fractional Baud Rate Register */ - __IO uint32_t LCR_H; /*!< Line Control Register */ - __IO uint32_t CR; /*!< Cntrol Register */ - __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select Register */ - __IO uint32_t IMSC; /*!< Interrupt Mask set/Clear Register */ - __I uint32_t RIS; /*!< Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Masked Interrupt Status Register */ - __O uint32_t ICR; /*!< Interrupt Clear Register */ - __IO uint32_t DMACR; /*!< DMA Control Register */ -} TSB_FURT_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - uint32_t RESERVED0; - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - __IO uint32_t CMPCR2; /*!< AD Conversion Monitor Function setting Register 2*/ - __IO uint32_t CMPCR3; /*!< AD Conversion Monitor Function setting Register 3*/ - __IO uint32_t CMP2; /*!< AD Conversion Result Comparison Register 2 */ - __IO uint32_t CMP3; /*!< AD Conversion Result Comparison Register 3 */ - uint32_t RESERVED1[30]; - __IO uint32_t EXAZSEL; /*!< AIN sampling period selection register */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED2[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief 16-bit Timer/Event Counter (TB) - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter Control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ - __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */ - __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter Control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ - __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */ - __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter Control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ - __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */ - __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ - __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software Reset Register */ - __IO uint32_t CR0; /*!< UART Control Register 0 */ - __IO uint32_t CR1; /*!< UART Control Register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control Register */ - __IO uint32_t BRD; /*!< UART Baud Rate Register */ - __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ - __IO uint32_t DR; /*!< UART Data Register */ - __IO uint32_t SR; /*!< UART Status Register */ - __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ - __IO uint32_t ERR; /*!< UART Error Register */ -} TSB_UART_TypeDef; - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< Interrupt Register */ - __IO uint32_t OP; /*!< Optiononal Function register */ - __I uint32_t PM; /*!< Bus Monitor register */ - __IO uint32_t AR2; /*!< Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port A Data Register */ - __IO uint32_t CR; /*!< Port A Output Control Register */ - __IO uint32_t FR1; /*!< Port A Function Register 1 */ - __IO uint32_t FR2; /*!< Port A Function Register 2 */ - __IO uint32_t FR3; /*!< Port A Function Register 3 */ - uint32_t RESERVED0; - __IO uint32_t FR5; /*!< Port A Function Register 5 */ - __IO uint32_t FR6; /*!< Port A Function Register 6 */ - __IO uint32_t FR7; /*!< Port A Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port A Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port A Input Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port B Data Register */ - __IO uint32_t CR; /*!< Port B Output Control Register */ - __IO uint32_t FR1; /*!< Port B Function Register 1 */ - __IO uint32_t FR2; /*!< Port B Function Register 2 */ - __IO uint32_t FR3; /*!< Port B Function Register 3 */ - uint32_t RESERVED0; - __IO uint32_t FR5; /*!< Port B Function Register 5 */ - __IO uint32_t FR6; /*!< Port B Function Register 6 */ - uint32_t RESERVED1[2]; - __IO uint32_t OD; /*!< Port B Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port B Input Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port C Data Register */ - __IO uint32_t CR; /*!< Port C Output Control Register */ - __IO uint32_t FR1; /*!< Port C Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< Port C Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port C Function Register 5 */ - uint32_t RESERVED2[3]; - __IO uint32_t OD; /*!< Port C Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port C Input Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port D Data Register */ - __IO uint32_t CR; /*!< Port D Output Control Register */ - __IO uint32_t FR1; /*!< Port D Function Register 1 */ - __IO uint32_t FR2; /*!< Port D Function Register 2 */ - __IO uint32_t FR3; /*!< Port D Function Register 3 */ - __IO uint32_t FR4; /*!< Port D Function Register 4 */ - __IO uint32_t FR5; /*!< Port D Function Register 5 */ - __IO uint32_t FR6; /*!< Port D Function Register 6 */ - __IO uint32_t FR7; /*!< Port D Function Register 7 */ - uint32_t RESERVED0; - __IO uint32_t OD; /*!< Port D Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< Port D Input Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port E Data Register */ - __IO uint32_t CR; /*!< Port E Output Control Register */ - __IO uint32_t FR1; /*!< Port E Function Register 1 */ - __IO uint32_t FR2; /*!< Port E Function Register 2 */ - __IO uint32_t FR3; /*!< Port E Function Register 3 */ - __IO uint32_t FR4; /*!< Port E Function Register 4 */ - __IO uint32_t FR5; /*!< Port E Function Register 5 */ - uint32_t RESERVED0; - __IO uint32_t FR7; /*!< Port E Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port E Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port E Input Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief Port F - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port F Data Register */ - __IO uint32_t CR; /*!< Port F Output Control Register */ - __IO uint32_t FR1; /*!< Port F Function Register 1 */ - uint32_t RESERVED0[5]; - __IO uint32_t FR7; /*!< Port F Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port F Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port F Input Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief Port G - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port G Data Register */ - __IO uint32_t CR; /*!< Port G Output Control Register */ - __IO uint32_t FR1; /*!< Port G Function Register 1 */ - __IO uint32_t FR2; /*!< Port G Function Register 2 */ - __IO uint32_t FR3; /*!< Port G Function Register 3 */ - __IO uint32_t FR4; /*!< Port G Function Register 4 */ - __IO uint32_t FR5; /*!< Port G Function Register 5 */ - uint32_t RESERVED0; - __IO uint32_t FR7; /*!< Port G Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port G Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port G Input Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief Port H - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port H Data Register */ - __IO uint32_t CR; /*!< Port H Output Control Register */ - __IO uint32_t FR1; /*!< Port H Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< Port H Function Register 3 */ - __IO uint32_t FR4; /*!< Port H Function Register 4 */ - __IO uint32_t FR5; /*!< Port H Function Register 5 */ - uint32_t RESERVED1[3]; - __IO uint32_t OD; /*!< Port H Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port H Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port H Input Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief Port J - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port J Data Register */ - __IO uint32_t CR; /*!< Port J Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port J Function Register 2 */ - __IO uint32_t FR3; /*!< Port J Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port J Function Register 5 */ - uint32_t RESERVED2; - __IO uint32_t FR7; /*!< Port J Function Register 7 */ - uint32_t RESERVED3; - __IO uint32_t OD; /*!< Port J Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ - uint32_t RESERVED4; - __IO uint32_t IE; /*!< Port J Input Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief Port K - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port K Data Register */ - __IO uint32_t CR; /*!< Port K Output Control Register */ - __IO uint32_t FR1; /*!< Port K Function Register 1 */ - __IO uint32_t FR2; /*!< Port K Function Register 2 */ - __IO uint32_t FR3; /*!< Port K Function Register 3 */ - __IO uint32_t FR4; /*!< Port K Function Register 4 */ - uint32_t RESERVED0; - __IO uint32_t FR6; /*!< Port K Function Register 6 */ - __IO uint32_t FR7; /*!< Port K Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port K Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port K Pull-up Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port K Input Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief Port L - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port L Data Register */ - __IO uint32_t CR; /*!< Port L Output Control Register */ - __IO uint32_t FR1; /*!< Port L Function Register 1 */ - __IO uint32_t FR2; /*!< Port L Function Register 2 */ - __IO uint32_t FR3; /*!< Port L Function Register 3 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR6; /*!< Port L Function Register 6 */ - __IO uint32_t FR7; /*!< Port L Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port L Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port L Input Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief Port M - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port M Data Register */ - __IO uint32_t CR; /*!< Port M Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port M Function Register 2 */ - __IO uint32_t FR3; /*!< Port M Function Register 3 */ - __IO uint32_t FR4; /*!< Port M Function Register 4 */ - __IO uint32_t FR5; /*!< Port M Function Register 5 */ - __IO uint32_t FR6; /*!< Port M Function Register 6 */ - __IO uint32_t FR7; /*!< Port M Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port M Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port M Pull-up Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port M Input Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief Port N - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port N Data Register */ - __IO uint32_t CR; /*!< Port N Output Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< Port N Opend Drain Control Register */ - __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< Port N Input Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief Port P - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port P Data Register */ - __IO uint32_t CR; /*!< Port P Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port P Function Register 2 */ - __IO uint32_t FR3; /*!< Port P Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port P Function Register 5 */ - uint32_t RESERVED2[3]; - __IO uint32_t OD; /*!< Port P Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port P Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port P Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port P Input Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief Port R - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port R Data Register */ - __IO uint32_t CR; /*!< Port R Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port R Function Register 2 */ - __IO uint32_t FR3; /*!< Port R Function Register 3 */ - uint32_t RESERVED1[5]; - __IO uint32_t OD; /*!< Port R Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port R Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port R Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port R Input Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief Port T - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port T Data Register */ - __IO uint32_t CR; /*!< Port T Output Control Register */ - __IO uint32_t FR1; /*!< Port T Function Register 1 */ - __IO uint32_t FR2; /*!< Port T Function Register 2 */ - __IO uint32_t FR3; /*!< Port T Function Register 3 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR6; /*!< Port T Function Register 6 */ - __IO uint32_t FR7; /*!< Port T Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port T Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port T Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port T Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port T Input Control Register */ -} TSB_PT_TypeDef; - -/** - * @brief Port U - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port U Data Register */ - __IO uint32_t CR; /*!< Port U Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port U Function Register 2 */ - __IO uint32_t FR3; /*!< Port U Function Register 3 */ - uint32_t RESERVED1[3]; - __IO uint32_t FR7; /*!< Port U Function Register 7 */ - uint32_t RESERVED2; - __IO uint32_t OD; /*!< Port U Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port U Input Control Register */ -} TSB_PU_TypeDef; - -/** - * @brief Port V - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port V Data Register */ - __IO uint32_t CR; /*!< Port V OutPut Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port V Function Register 2 */ - __IO uint32_t FR3; /*!< Port V Function Register 3 */ - __IO uint32_t FR4; /*!< Port V Function Register 4 */ - __IO uint32_t FR5; /*!< Port V Function Register 5 */ - __IO uint32_t FR6; /*!< Port V Function Register 6 */ - __IO uint32_t FR7; /*!< Port V Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port V Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port V InPut Control Register */ -} TSB_PV_TypeDef; - -/** - * @brief Port W - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port W Data Register */ - __IO uint32_t CR; /*!< Port W OutPut Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< Port W Function Register 3 */ - __IO uint32_t FR4; /*!< Port W Function Register 4 */ - __IO uint32_t FR5; /*!< Port W Function Register 5 */ - __IO uint32_t FR6; /*!< Port W Function Register 6 */ - __IO uint32_t FR7; /*!< Port W Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port W Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port W Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port W Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port W InPut Control Register */ -} TSB_PW_TypeDef; - -/** - * @brief Port Y - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port Y Data Register */ - __IO uint32_t CR; /*!< Port Y OutPut Control Register */ - __IO uint32_t FR1; /*!< Port Y Function Register 1 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR4; /*!< Port Y Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< Port Y Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port Y InPut Control Register */ -} TSB_PY_TypeDef; - -/** - * @brief Internal High-speed Oscillation Adjustment - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protection Register */ - __IO uint32_t OSCEN; /*!< TRM Enable Register */ - __I uint32_t OSCINIT; /*!< TRM Initial Trimming Level Monitor Register */ - __IO uint32_t OSCSET; /*!< TRM Trimming Level Setting Register */ -} TSB_TRM_TypeDef; - -/** - * @brief Oscillation Frequency Detector (OFD) - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief Real Time Clock (RTC) - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ - __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ -} TSB_RTC_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t EN; /*!< CEC Enable Register */ - __IO uint32_t ADD; /*!< CEC Logical Address Register */ - __O uint32_t RESET; /*!< CEC Software Reset Register */ - __IO uint32_t REN; /*!< CEC Receive Enable Register */ - __I uint32_t RBUF; /*!< CEC Receive Buffer Register */ - __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */ - __IO uint32_t TEN; /*!< CEC Transmit Enable Register */ - __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */ - __IO uint32_t TCR; /*!< CEC Transmit Control Register */ - __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */ - __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */ - __IO uint32_t FSSEL; /*!< CEC sampling clock selection Register */ -} TSB_CEC_TypeDef; - -/** - * @brief Remote Control Signal Preprocessor (RMC) - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ - __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ - __IO uint32_t RATE; /*!< PWM Frequency Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ - __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ - __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ - __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ - __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/ -} TSB_PMD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */ - __IO uint32_t CLKCR; /*!< Clock Control Register */ - __IO uint32_t OCR0; /*!< Output Control Register 0 */ - __IO uint32_t OCR1; /*!< Output Control Register 1 */ - __IO uint32_t ICR; /*!< Input Control Register */ - __IO uint32_t CR; /*!< Control Register */ - __I uint32_t BR; /*!< Buffer Register */ - __I uint32_t SR; /*!< Status Register */ - __IO uint32_t INTCR; /*!< interrupt Control Register */ -} TSB_ISD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3; - __I uint32_t PSR3; /*!< Flash Protect Status Register 3 */ - __I uint32_t PSR4; /*!< Flash Protect Status Register 4 */ - uint32_t RESERVED4; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED5; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED6; - __IO uint32_t PMR3; /*!< Flash Protect Mask Register 3 */ - __IO uint32_t PMR4; /*!< Flash Protect Mask Register 4 */ - uint32_t RESERVED7; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED8[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED9[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED10; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED11; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL) -#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL) -#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL) -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) -#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL) -#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL) -#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL) -#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL) -#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL) -#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL) -#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL) -#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL) -#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) -#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) -#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) -#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) -#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL) -#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL) -#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL) -#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) -#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL) -#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL) -#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL) -#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL) -#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL) -#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL) -#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL) -#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) -#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) -#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL) -#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL) -#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL) -#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL) -#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL) -#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL) -#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) -#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) -#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL) -#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL) -#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL) -#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) -#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL) -#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL) -#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE) -#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE) -#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE) -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) -#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) -#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) -#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE) -#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE) -#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE) -#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE) -#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) -#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE) -#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE) -#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) -#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) -#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE) -#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE) -#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE) -#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE) -#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE) -#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) -#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) -#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) -#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) -#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) -#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) -#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE) -#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE) -#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE) -#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - -/* DMA Controller */ -#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0))) -#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1))) -#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0))) -#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1))) -#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0))) -#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1))) -#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0))) -#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1))) -#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0))) -#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1))) -#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0))) -#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1))) -#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0))) -#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26))) -#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27))) -#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31))) -#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0))) -#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14))) -#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15))) -#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16))) -#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17))) -#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18))) -#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26))) -#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27))) -#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31))) -#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0))) -#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14))) -#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15))) -#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16))) -#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17))) -#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18))) - -#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0))) -#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1))) -#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0))) -#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1))) -#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0))) -#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1))) -#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0))) -#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1))) -#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0))) -#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1))) -#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0))) -#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1))) -#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0))) -#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26))) -#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27))) -#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31))) -#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0))) -#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14))) -#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15))) -#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16))) -#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17))) -#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18))) -#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26))) -#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27))) -#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31))) -#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0))) -#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14))) -#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15))) -#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16))) -#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17))) -#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18))) - - -/* */ -#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0))) -#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0))) -#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6))) -#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6))) -#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0))) -#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1))) -#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4))) -#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5))) -#define TSB_SMI0_INT_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0))) -#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0))) -#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1))) - - - - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) -#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) -#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) -#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) -#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) -#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) -#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) -#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) -#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) -#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) -#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) -#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) -#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) -#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) -#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) -#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) -#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) -#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) -#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) -#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) -#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) -#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) -#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) -#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) -#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) -#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) -#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) -#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) -#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) -#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) -#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) -#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) -#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) -#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) -#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) -#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) -#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) -#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) -#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) -#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) -#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) -#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) -#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) -#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) -#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) -#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) - - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - -#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) -#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) -#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) -#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) -#define TSB_TSPI2_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) -#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) -#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) -#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) -#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) -#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) -#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) -#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) -#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) -#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) -#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) -#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) -#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) -#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) -#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) -#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) -#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) -#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) -#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) -#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) -#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) -#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) -#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) -#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) -#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) -#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) -#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) -#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) -#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) -#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) -#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) -#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) -#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) - -#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) -#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) -#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) -#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) -#define TSB_TSPI3_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) -#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) -#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) -#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) -#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) -#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) -#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) -#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) -#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) -#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) -#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) -#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) -#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) -#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) -#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) -#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) -#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) -#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) -#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) -#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) -#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) -#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) -#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) -#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) -#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) -#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) -#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) -#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) -#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) -#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) -#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) -#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) -#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) - -#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) -#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) -#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) -#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) -#define TSB_TSPI4_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) -#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) -#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) -#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) -#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) -#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) -#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) -#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) -#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) -#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) -#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) -#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) -#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) -#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) -#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) -#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) -#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) -#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) -#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) -#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) -#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) -#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) -#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) -#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) -#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) -#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) -#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) -#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) -#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) -#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) -#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) -#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) -#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) - -#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0))) -#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12))) -#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13))) -#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14))) -#define TSB_TSPI5_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15))) -#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0))) -#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1))) -#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2))) -#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4))) -#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5))) -#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6))) -#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7))) -#define TSB_TSPI5_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,16))) -#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21))) -#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0))) -#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1))) -#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14))) -#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15))) -#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16))) -#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17))) -#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18))) -#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19))) -#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31))) -#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0))) -#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1))) -#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4))) -#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5))) -#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6))) -#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7))) -#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20))) -#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21))) -#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22))) -#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23))) -#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31))) -#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1))) -#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2))) -#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3))) - -#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0))) -#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12))) -#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13))) -#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14))) -#define TSB_TSPI6_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15))) -#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0))) -#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1))) -#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2))) -#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4))) -#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5))) -#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6))) -#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7))) -#define TSB_TSPI6_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,16))) -#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21))) -#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0))) -#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1))) -#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14))) -#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15))) -#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16))) -#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17))) -#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18))) -#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19))) -#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31))) -#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0))) -#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1))) -#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4))) -#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5))) -#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6))) -#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7))) -#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20))) -#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21))) -#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22))) -#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23))) -#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31))) -#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1))) -#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2))) -#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3))) - -#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0))) -#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12))) -#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13))) -#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14))) -#define TSB_TSPI7_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15))) -#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0))) -#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1))) -#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2))) -#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4))) -#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5))) -#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6))) -#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7))) -#define TSB_TSPI7_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,16))) -#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21))) -#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0))) -#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1))) -#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14))) -#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15))) -#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16))) -#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17))) -#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18))) -#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19))) -#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31))) -#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0))) -#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1))) -#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4))) -#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5))) -#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6))) -#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7))) -#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20))) -#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21))) -#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22))) -#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23))) -#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31))) -#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1))) -#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2))) -#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3))) - -#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0))) -#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12))) -#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13))) -#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14))) -#define TSB_TSPI8_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15))) -#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0))) -#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1))) -#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2))) -#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4))) -#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5))) -#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6))) -#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7))) -#define TSB_TSPI8_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,16))) -#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21))) -#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0))) -#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1))) -#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14))) -#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15))) -#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16))) -#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17))) -#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18))) -#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19))) -#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31))) -#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0))) -#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1))) -#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4))) -#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5))) -#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6))) -#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7))) -#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20))) -#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21))) -#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22))) -#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23))) -#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31))) -#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1))) -#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2))) -#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3))) - - -/* External Bus Interface(EXB) */ -#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0))) -#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0))) -#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12))) -#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13))) -#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0))) -#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12))) -#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13))) -#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0))) -#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12))) -#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13))) -#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0))) -#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12))) -#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13))) -#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0))) - - -/* Clock Generator (CG) */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) -#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) -#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) -#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) -#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) -#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) -#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) -#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) -#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) -#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) -#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) -#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) -#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) -#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13))) -#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14))) -#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15))) -#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) -#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) -#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18))) -#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) -#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) -#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) -#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) -#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) -#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) -#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) -#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) -#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27))) -#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) -#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) -#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) -#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) -#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) -#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) -#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) -#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) -#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) -#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) -#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) -#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) -#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) -#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) -#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) -#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) -#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) -#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) -#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) -#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) -#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) -#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) -#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18))) -#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19))) -#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20))) -#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21))) -#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22))) -#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23))) -#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24))) -#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28))) -#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) -#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) -#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) -#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) -#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) -#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0))) -#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1))) -#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2))) - - - -/* Interrupt Monitor Register */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) -#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4))) -#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5))) -#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6))) -#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7))) -#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8))) -#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9))) -#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10))) -#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11))) -#define TSB_IMN_FLG1_INT044FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,12))) -#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13))) -#define TSB_IMN_FLG1_INT046FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,14))) -#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18))) -#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19))) -#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20))) -#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21))) -#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22))) -#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23))) -#define TSB_IMN_FLG1_INT056FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,24))) -#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25))) -#define TSB_IMN_FLG1_INT058FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,26))) -#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27))) -#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28))) -#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29))) -#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30))) -#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31))) -#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17))) -#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18))) -#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19))) -#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20))) -#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21))) -#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22))) -#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23))) -#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24))) -#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) -#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) -#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) -#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) -#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) -#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) -#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) -#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) -#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) -#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) -#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) -#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) -#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) -#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) -#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) -#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) -#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) -#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) -#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) -#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) -#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) -#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) -#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) -#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) -#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) -#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) -#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) -#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) -#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) -#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) -#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) -#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) -#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) -#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) -#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) -#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) -#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) -#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) -#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) -#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) -#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) -#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) -#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) -#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) -#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) -#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) -#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) -#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) -#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) -#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31))) -#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0))) -#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1))) -#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2))) -#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3))) -#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4))) -#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5))) -#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6))) -#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7))) -#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8))) -#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9))) -#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10))) -#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11))) -#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12))) -#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13))) -#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14))) -#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15))) -#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16))) -#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17))) -#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18))) -#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19))) -#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20))) -#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21))) -#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22))) -#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23))) -#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24))) -#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25))) -#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26))) -#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27))) -#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28))) -#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29))) -#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30))) -#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31))) -#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0))) -#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1))) -#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2))) -#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3))) -#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4))) -#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5))) -#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6))) -#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7))) -#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8))) -#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9))) -#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10))) -#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - -#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) -#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) -#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) -#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) -#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) -#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) -#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) -#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) -#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) -#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) -#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) -#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) -#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) -#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) -#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) -#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) - - -/* Watchdog Timer (WD) */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) - - -/* NBD */ -#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) - - -/* Malti Porpose Direct Memory Accsess(MDMA) */ -#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16))) -#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24))) -#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8))) -#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16))) -#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24))) -#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8))) -#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16))) -#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24))) -#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8))) -#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16))) -#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24))) -#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8))) -#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16))) -#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24))) -#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8))) -#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16))) -#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24))) -#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8))) -#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16))) -#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24))) -#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8))) -#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16))) -#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24))) -#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8))) -#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16))) -#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24))) -#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8))) -#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16))) -#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24))) -#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8))) -#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16))) -#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24))) -#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8))) -#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16))) -#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24))) -#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8))) -#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16))) -#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24))) -#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8))) -#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16))) -#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24))) -#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8))) -#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16))) -#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24))) -#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8))) -#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16))) -#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24))) -#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8))) -#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16))) -#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24))) -#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8))) -#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16))) -#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24))) -#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8))) -#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16))) -#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24))) -#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8))) -#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16))) -#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24))) -#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8))) -#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16))) -#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24))) -#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8))) -#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16))) -#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24))) -#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8))) -#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16))) -#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24))) -#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8))) -#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16))) -#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24))) -#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8))) -#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16))) -#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24))) -#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8))) -#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16))) -#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24))) -#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8))) -#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16))) -#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24))) -#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8))) -#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16))) -#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24))) -#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8))) -#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16))) -#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24))) -#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8))) -#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16))) -#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24))) -#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8))) -#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16))) -#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24))) -#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8))) -#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16))) -#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24))) -#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8))) -#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16))) -#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24))) -#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8))) -#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0))) -#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1))) -#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2))) -#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3))) -#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4))) -#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5))) -#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6))) -#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7))) -#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8))) -#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9))) -#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10))) -#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11))) -#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12))) -#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13))) -#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14))) -#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15))) -#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16))) -#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17))) -#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18))) -#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19))) -#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20))) -#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21))) -#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22))) -#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23))) -#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24))) -#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25))) -#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26))) -#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27))) -#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28))) -#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29))) -#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30))) -#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31))) - - -/* ARM Prime Cell PL011 */ -#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8))) -#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9))) -#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10))) -#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11))) -#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0))) -#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1))) -#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2))) -#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3))) -#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0))) -#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3))) -#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4))) -#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5))) -#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6))) -#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7))) -#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0))) -#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1))) -#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2))) -#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3))) -#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4))) -#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7))) -#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0))) -#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1))) -#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2))) -#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8))) -#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9))) -#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14))) -#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15))) -#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4))) -#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5))) -#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6))) -#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7))) -#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8))) -#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9))) -#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10))) -#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4))) -#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5))) -#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6))) -#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7))) -#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8))) -#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9))) -#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10))) -#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4))) -#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5))) -#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6))) -#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7))) -#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8))) -#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9))) -#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10))) -#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4))) -#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5))) -#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6))) -#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7))) -#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8))) -#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9))) -#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10))) -#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0))) -#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1))) -#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2))) - -#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8))) -#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9))) -#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10))) -#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11))) -#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0))) -#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1))) -#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2))) -#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3))) -#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0))) -#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3))) -#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4))) -#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5))) -#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6))) -#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7))) -#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0))) -#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1))) -#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2))) -#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3))) -#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4))) -#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7))) -#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0))) -#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1))) -#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2))) -#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8))) -#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9))) -#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14))) -#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15))) -#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4))) -#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5))) -#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6))) -#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7))) -#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8))) -#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9))) -#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10))) -#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4))) -#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5))) -#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6))) -#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7))) -#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8))) -#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9))) -#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10))) -#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4))) -#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5))) -#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6))) -#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7))) -#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8))) -#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9))) -#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10))) -#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4))) -#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5))) -#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6))) -#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7))) -#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8))) -#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9))) -#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10))) -#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0))) -#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1))) -#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7))) -#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPEN_CMP2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,2))) -#define TSB_ADA_CMPEN_CMP3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,3))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_CMPCR2_ADBIG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,5))) -#define TSB_ADA_CMPCR2_CMPCND2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,6))) -#define TSB_ADA_CMPCR3_ADBIG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,5))) -#define TSB_ADA_CMPCR3_CMPCND3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,6))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0))) - -#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0))) - - -/* 16-bit Timer/Event Counter (TB) */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - -#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) -#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) -#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) -#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) -#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) -#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) -#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) -#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) -#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) -#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) -#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) -#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) -#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) -#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) -#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) -#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) -#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) -#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) -#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) -#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) -#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) -#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) -#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) -#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) -#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) -#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) -#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) -#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) -#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) -#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) -#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) -#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) -#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) -#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) -#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) -#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) -#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) -#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) -#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) -#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) -#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) -#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) -#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) -#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) -#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) -#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) -#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) -#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) -#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) -#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) -#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) -#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) -#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) -#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) - -#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) -#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) -#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) -#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) -#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) -#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) -#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) -#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) -#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) -#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) -#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) -#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) -#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) -#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) -#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) -#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) -#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) -#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) -#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) -#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) -#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) -#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) -#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) -#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) -#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) -#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) -#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) -#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) -#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) -#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) -#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) -#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) -#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) -#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) -#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) -#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) -#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) -#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) -#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) -#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) -#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) -#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) -#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) -#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) -#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) -#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) -#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) -#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) -#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) -#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) -#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) -#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) -#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) -#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) - -#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0))) -#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1))) -#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0))) -#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1))) -#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2))) -#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4))) -#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20))) -#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0))) -#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1))) -#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2))) -#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3))) -#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0))) -#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1))) -#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2))) -#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3))) -#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0))) -#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1))) -#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2))) -#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0))) -#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1))) -#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2))) -#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4))) -#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20))) -#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0))) -#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1))) -#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2))) -#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3))) -#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0))) -#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1))) -#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2))) -#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3))) -#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0))) -#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1))) -#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2))) -#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0))) -#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1))) -#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2))) -#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4))) -#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20))) -#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0))) -#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1))) -#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2))) -#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3))) -#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4))) -#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0))) -#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1))) -#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2))) -#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3))) -#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4))) -#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0))) -#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1))) -#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2))) -#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0))) -#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1))) - -#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0))) -#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1))) -#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0))) -#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1))) -#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2))) -#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4))) -#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20))) -#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0))) -#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1))) -#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2))) -#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3))) -#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0))) -#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1))) -#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2))) -#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3))) -#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0))) -#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1))) -#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2))) -#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0))) -#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1))) -#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2))) -#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4))) -#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20))) -#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0))) -#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1))) -#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2))) -#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3))) -#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0))) -#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1))) -#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2))) -#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3))) -#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0))) -#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1))) -#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2))) -#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0))) -#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1))) -#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2))) -#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4))) -#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20))) -#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0))) -#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1))) -#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2))) -#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3))) -#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4))) -#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0))) -#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1))) -#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2))) -#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3))) -#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4))) -#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0))) -#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1))) -#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2))) -#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0))) -#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1))) - -#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0))) -#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1))) -#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0))) -#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1))) -#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2))) -#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4))) -#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20))) -#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0))) -#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1))) -#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2))) -#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3))) -#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0))) -#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1))) -#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2))) -#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3))) -#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0))) -#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1))) -#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2))) -#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0))) -#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1))) -#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2))) -#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4))) -#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20))) -#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0))) -#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1))) -#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2))) -#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3))) -#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0))) -#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1))) -#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2))) -#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3))) -#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0))) -#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1))) -#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2))) -#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0))) -#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1))) -#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2))) -#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4))) -#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20))) -#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0))) -#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1))) -#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2))) -#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3))) -#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4))) -#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0))) -#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1))) -#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2))) -#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3))) -#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4))) -#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0))) -#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1))) -#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2))) -#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0))) -#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1))) - -#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0))) -#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1))) -#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0))) -#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1))) -#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2))) -#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4))) -#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20))) -#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0))) -#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1))) -#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2))) -#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3))) -#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0))) -#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1))) -#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2))) -#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3))) -#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0))) -#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1))) -#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2))) -#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0))) -#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1))) -#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2))) -#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4))) -#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20))) -#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0))) -#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1))) -#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2))) -#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3))) -#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0))) -#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1))) -#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2))) -#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3))) -#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0))) -#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1))) -#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2))) -#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0))) -#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1))) -#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2))) -#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4))) -#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20))) -#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0))) -#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1))) -#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2))) -#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3))) -#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4))) -#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0))) -#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1))) -#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2))) -#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3))) -#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4))) -#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0))) -#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1))) -#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2))) -#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0))) -#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1))) - -#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0))) -#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1))) -#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0))) -#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1))) -#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2))) -#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4))) -#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20))) -#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0))) -#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1))) -#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2))) -#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3))) -#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0))) -#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1))) -#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2))) -#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3))) -#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0))) -#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1))) -#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2))) -#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0))) -#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1))) -#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2))) -#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4))) -#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20))) -#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0))) -#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1))) -#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2))) -#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3))) -#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0))) -#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1))) -#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2))) -#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3))) -#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0))) -#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1))) -#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2))) -#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0))) -#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1))) -#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2))) -#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4))) -#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20))) -#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0))) -#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1))) -#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2))) -#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3))) -#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4))) -#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0))) -#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1))) -#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2))) -#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3))) -#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4))) -#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0))) -#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1))) -#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2))) -#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0))) -#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1))) - -#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0))) -#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1))) -#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0))) -#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1))) -#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2))) -#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4))) -#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20))) -#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0))) -#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1))) -#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2))) -#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3))) -#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0))) -#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1))) -#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2))) -#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3))) -#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0))) -#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1))) -#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2))) -#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0))) -#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1))) -#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2))) -#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4))) -#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20))) -#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0))) -#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1))) -#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2))) -#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3))) -#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0))) -#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1))) -#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2))) -#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3))) -#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0))) -#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1))) -#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2))) -#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0))) -#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1))) -#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2))) -#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4))) -#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20))) -#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0))) -#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1))) -#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2))) -#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3))) -#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4))) -#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0))) -#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1))) -#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2))) -#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3))) -#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4))) -#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0))) -#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1))) -#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2))) -#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0))) -#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - -#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) -#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) -#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) -#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) -#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) -#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) -#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) -#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) -#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) -#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) -#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) -#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) -#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) -#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) -#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) -#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) -#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) -#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) -#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) -#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) -#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) -#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) -#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) -#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) -#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) -#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) -#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) -#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) -#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) -#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) -#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) -#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) -#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) -#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) -#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) -#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) -#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) -#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) -#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) - -#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) -#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) -#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) -#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) -#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) -#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) -#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) -#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) -#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) -#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) -#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) -#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) -#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) -#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) -#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) -#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) -#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) -#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) -#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) -#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) -#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) -#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) -#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) -#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) -#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) -#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) -#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) -#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) -#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) -#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) -#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) -#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) -#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) -#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) -#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) -#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) -#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) -#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) -#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) - -#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) -#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) -#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) -#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) -#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) -#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) -#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) -#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) -#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) -#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) -#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) -#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) -#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) -#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) -#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) -#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) -#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) -#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) -#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) -#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) -#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) -#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) -#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) -#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) -#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) -#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) -#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) -#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) -#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) -#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) -#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) -#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) -#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) -#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) -#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) -#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) -#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) -#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) -#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - -#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) -#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) -#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) -#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) -#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) -#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) -#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) -#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) -#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) -#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) -#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) -#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) -#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) -#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) -#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) -#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) -#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) -#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) -#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) -#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) -#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) -#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) -#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) -#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) -#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) -#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) -#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) -#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) -#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) -#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) -#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) -#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) -#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) -#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) -#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) -#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) -#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) -#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) - -#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3))) -#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4))) -#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0))) -#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3))) -#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4))) -#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5))) -#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6))) -#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7))) -#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0))) -#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1))) -#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2))) -#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3))) -#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4))) -#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5))) -#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6))) -#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7))) -#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0))) -#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1))) -#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2))) -#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3))) -#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4))) -#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5))) -#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6))) -#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0))) -#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1))) -#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2))) -#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3))) -#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0))) -#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1))) -#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2))) -#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3))) -#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4))) -#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5))) -#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6))) -#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7))) -#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0))) -#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1))) -#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4))) -#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5))) -#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6))) -#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) -#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4))) -#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5))) -#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4))) -#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5))) -#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6))) -#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7))) -#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0))) -#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1))) -#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) -#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) -#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) -#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5))) -#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6))) -#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR1_PB6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6))) -#define TSB_PB_FR1_PB7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,7))) -#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0))) -#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1))) -#define TSB_PB_FR2_PB6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6))) -#define TSB_PB_FR2_PB7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,7))) -#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0))) -#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR3_PB7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,7))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4))) -#define TSB_PB_FR5_PB6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6))) -#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) -#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) -#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6))) -#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6))) -#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7))) -#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) -#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) -#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) -#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) -#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5))) -#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6))) -#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7))) -#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) -#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) -#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6))) -#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7))) -#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0))) -#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1))) -#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2))) -#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) -#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) -#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5))) -#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6))) -#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7))) -#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) -#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) -#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) -#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) -#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0))) -#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1))) -#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) -#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4))) -#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6))) -#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7))) -#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0))) -#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0))) -#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1))) -#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2))) -#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3))) -#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4))) -#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5))) -#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6))) -#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6))) -#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6))) -#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6))) -#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) -#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6))) -#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) -#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) -#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) -#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) -#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) -#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) -#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) -#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6))) -#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7))) -#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0))) -#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7))) -#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0))) -#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1))) -#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2))) -#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3))) -#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4))) -#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5))) -#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6))) -#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7))) -#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0))) -#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) -#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) -#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) -#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) -#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) -#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) -#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7))) -#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0))) -#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) -#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) -#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) -#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4))) -#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5))) -#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6))) -#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7))) -#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0))) -#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1))) -#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2))) -#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) -#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) -#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) -#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) -#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) -#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) -#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) -#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) -#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) -#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) -#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) -#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) -#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) -#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) -#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) -#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) -#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) -#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) -#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) -#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) -#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) -#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) -#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7))) -#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4))) -#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5))) -#define TSB_PG_FR3_PG0F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0))) -#define TSB_PG_FR3_PG1F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1))) -#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) -#define TSB_PG_FR3_PG3F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) -#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) -#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) -#define TSB_PG_FR4_PG3F4 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) -#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) -#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) -#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6))) -#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7))) -#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) -#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) -#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) -#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3))) -#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4))) -#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5))) -#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6))) -#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7))) -#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2))) -#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3))) -#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4))) -#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) -#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) -#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) -#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) -#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) -#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) -#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) -#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) -#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) -#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) -#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) -#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) -#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) -#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) -#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) -#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) -#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) -#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) -#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) -#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) -#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) -#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) -#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) -#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) -#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) -#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) -#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) -#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) -#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) -#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) -#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) -#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) -#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) -#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) -#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) -#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) -#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) -#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) -#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) -#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) -#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7))) -#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0))) -#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1))) -#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2))) -#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3))) -#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4))) -#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5))) -#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6))) -#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7))) -#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0))) -#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1))) -#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2))) -#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3))) -#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0))) -#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1))) -#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2))) -#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3))) -#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4))) -#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5))) -#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6))) -#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7))) -#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) -#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) -#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) -#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) -#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) -#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) -#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) -#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) -#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) -#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) -#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) -#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) -#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) -#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) -#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) -#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) -#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) -#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) -#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) -#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) -#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) -#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) -#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6))) -#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6))) -#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6))) -#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7))) -#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2))) -#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3))) -#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6))) -#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6))) -#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6))) -#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6))) -#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) -#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6))) -#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7))) - - -/* Port K */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5))) -#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6))) -#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7))) -#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0))) -#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5))) -#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6))) -#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7))) -#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2))) -#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3))) -#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4))) -#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5))) -#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6))) -#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7))) -#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* Port L */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) -#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4))) -#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5))) -#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) -#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) -#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) -#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) -#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0))) -#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3))) -#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0))) -#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1))) -#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2))) -#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) -#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) - - -/* Port M */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5))) -#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6))) -#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5))) -#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6))) -#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6))) -#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5))) -#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6))) -#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7))) -#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0))) -#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1))) -#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2))) -#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3))) -#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4))) -#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5))) -#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6))) -#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) -#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) - - -/* Port N */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6))) -#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6))) -#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6))) -#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6))) -#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6))) -#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) -#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6))) -#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7))) - - -/* Port P */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) -#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) -#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) -#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) -#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) -#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) -#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) -#define TSB_PP_FR2_PP0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) -#define TSB_PP_FR2_PP1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) -#define TSB_PP_FR2_PP2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) -#define TSB_PP_FR2_PP3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3))) -#define TSB_PP_FR2_PP4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4))) -#define TSB_PP_FR2_PP5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5))) -#define TSB_PP_FR2_PP6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) -#define TSB_PP_FR2_PP7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7))) -#define TSB_PP_FR3_PP0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR3_PP3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3))) -#define TSB_PP_FR3_PP4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4))) -#define TSB_PP_FR3_PP5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5))) -#define TSB_PP_FR3_PP6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) -#define TSB_PP_FR3_PP7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7))) -#define TSB_PP_FR5_PP0FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0))) -#define TSB_PP_FR5_PP1FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1))) -#define TSB_PP_FR5_PP2FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2))) -#define TSB_PP_FR5_PP3FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3))) -#define TSB_PP_FR5_PP4FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4))) -#define TSB_PP_FR5_PP5FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5))) -#define TSB_PP_FR5_PP6FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6))) -#define TSB_PP_FR5_PP7FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) -#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) -#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) -#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) -#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) -#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) -#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) -#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) -#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) -#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) -#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) -#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) -#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) -#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) - - -/* Port R */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) -#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) -#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) -#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) -#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) -#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) -#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) -#define TSB_PR_FR2_PR0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0))) -#define TSB_PR_FR2_PR1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1))) -#define TSB_PR_FR2_PR2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2))) -#define TSB_PR_FR2_PR3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3))) -#define TSB_PR_FR2_PR4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4))) -#define TSB_PR_FR2_PR5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5))) -#define TSB_PR_FR2_PR6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6))) -#define TSB_PR_FR2_PR7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7))) -#define TSB_PR_FR3_PR0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR3_PR3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3))) -#define TSB_PR_FR3_PR4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4))) -#define TSB_PR_FR3_PR5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5))) -#define TSB_PR_FR3_PR6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6))) -#define TSB_PR_FR3_PR7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) -#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) -#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) -#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) -#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) -#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) -#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) -#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) -#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) -#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) -#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) -#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) -#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) -#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) - - -/* Port T */ -#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) -#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) -#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) -#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) -#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) -#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) -#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) -#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) -#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) -#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) -#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) -#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) -#define TSB_PT_FR1_PT3FR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) -#define TSB_PT_FR2_PT3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3))) -#define TSB_PT_FR2_PT5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5))) -#define TSB_PT_FR3_PT3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) -#define TSB_PT_FR6_PT3FR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3))) -#define TSB_PT_FR7_PT2FR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2))) -#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) -#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) -#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) -#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) -#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) -#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) -#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) -#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) -#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) -#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) -#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) -#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) -#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) -#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) -#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) -#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) -#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) -#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) -#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) -#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) -#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) -#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) -#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) -#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) - - -/* Port U */ -#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) -#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) -#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) -#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) -#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) -#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) -#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) -#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) -#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) -#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) -#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) -#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) -#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) -#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) -#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) -#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) -#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) -#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) -#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2))) -#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3))) -#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4))) -#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) -#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) -#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7))) -#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) -#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2))) -#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3))) -#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4))) -#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5))) -#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6))) -#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) -#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) -#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2))) -#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3))) -#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4))) -#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5))) -#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6))) -#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) -#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) -#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) -#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) -#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) -#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) -#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) -#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) -#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) -#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) -#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) -#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) -#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) -#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) -#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) -#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) -#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) -#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) -#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) -#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) -#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) -#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) -#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) -#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) -#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) -#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) -#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) -#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) -#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) -#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) -#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) -#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) -#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) - - -/* Port V */ -#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) -#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) -#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) -#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) -#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) -#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) -#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) -#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) -#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) -#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) -#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) -#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) -#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) -#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) -#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) -#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) -#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) -#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) -#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2))) -#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3))) -#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4))) -#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5))) -#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) -#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) -#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0))) -#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1))) -#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2))) -#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5))) -#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6))) -#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4))) -#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5))) -#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6))) -#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7))) -#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0))) -#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1))) -#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2))) -#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3))) -#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4))) -#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5))) -#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6))) -#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7))) -#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0))) -#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1))) -#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2))) -#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3))) -#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4))) -#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5))) -#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7))) -#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0))) -#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1))) -#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2))) -#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3))) -#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4))) -#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5))) -#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6))) -#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7))) -#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) -#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) -#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) -#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) -#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) -#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) -#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) -#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) -#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) -#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) -#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) -#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) -#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) -#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) -#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) -#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) -#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) -#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) -#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) -#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) -#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) -#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) -#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) -#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) -#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) -#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) -#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) -#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) -#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) -#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) -#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) -#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) - - -/* Port W */ -#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0))) -#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1))) -#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2))) -#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3))) -#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4))) -#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5))) -#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6))) -#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7))) -#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0))) -#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1))) -#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2))) -#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3))) -#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4))) -#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5))) -#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6))) -#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7))) -#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4))) -#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7))) -#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0))) -#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1))) -#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2))) -#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3))) -#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0))) -#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1))) -#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2))) -#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3))) -#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4))) -#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5))) -#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6))) -#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7))) -#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0))) -#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1))) -#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2))) -#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4))) -#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5))) -#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6))) -#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7))) -#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0))) -#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1))) -#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2))) -#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3))) -#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4))) -#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5))) -#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6))) -#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7))) -#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0))) -#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1))) -#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2))) -#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3))) -#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4))) -#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5))) -#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6))) -#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7))) -#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0))) -#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1))) -#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2))) -#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3))) -#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4))) -#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5))) -#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6))) -#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7))) -#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0))) -#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1))) -#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2))) -#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3))) -#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4))) -#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5))) -#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6))) -#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7))) - - -/* Port Y */ -#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0))) -#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1))) -#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2))) -#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3))) -#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4))) -#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4))) -#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4))) -#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4))) -#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4))) -#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0))) -#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1))) -#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2))) -#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3))) -#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4))) -#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0))) -#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1))) -#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2))) -#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3))) -#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4))) -#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0))) -#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1))) -#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2))) -#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3))) -#define TSB_PY_IE_PY4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,4))) - - -/* Internal High-speed Oscillation Adjustment */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - -/* Oscillation Frequency Detector (OFD) */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - - -/* Consumer Electronics Control (CEC) */ -#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0))) -#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0))) -#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0))) -#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8))) -#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9))) -#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0))) -#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1))) -#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24))) -#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0))) -#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1))) -#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0))) -#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1))) -#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8))) -#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4))) -#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0))) -#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1))) -#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2))) -#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3))) -#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4))) -#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5))) -#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6))) -#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0))) -#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1))) -#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2))) -#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3))) -#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4))) -#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0))) - - -/* Remote Control Signal Preprocessor (RMC) */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8))) -#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - -#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0))) -#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0))) -#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24))) -#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25))) -#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29))) -#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30))) -#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31))) -#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15))) -#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7))) -#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7))) -#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8))) -#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11))) -#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12))) -#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13))) -#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14))) -#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15))) -#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) -#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) -#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) -#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) -#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) -#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) -#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) -#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) -#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) -#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) -#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) -#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) -#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) - - -/* */ -#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0))) -#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0))) -#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1))) -#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0))) -#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0))) -#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0))) -#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1))) -#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2))) -#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3))) -#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0))) -#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1))) -#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2))) -#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3))) -#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0))) - -#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0))) -#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0))) -#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1))) -#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0))) -#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0))) -#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0))) -#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1))) -#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2))) -#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3))) -#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0))) -#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1))) -#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2))) -#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3))) -#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0))) - -#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0))) -#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0))) -#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1))) -#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0))) -#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0))) -#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0))) -#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1))) -#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2))) -#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3))) -#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0))) -#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1))) -#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2))) -#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3))) -#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM4G9_H__ */ - -/** @} */ /* End of group TMPM4G9 */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S deleted file mode 100644 index 4483a37c88c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S +++ /dev/null @@ -1,533 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM4G9.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for the -; * TOSHIBA 'TMPM4G9' Device Series -; * @version V1.0.6.0 -; * $Date:: 2017-10-04 #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b - DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b - DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b - DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b - DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b - DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b - DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b - DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b - DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b - DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b - DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b - DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b - DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b - DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b - DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b - DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b - DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt - DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) - DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) - DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) - DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) - DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) - DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 - DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 - DCD INTLTTMR_IRQHandler ; 24: Long Term Timer Interrupt - DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) - DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) - DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) - DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) - DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) - DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt - DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt - DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) - DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) - DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) - DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) - DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) - DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) - DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) - DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) - DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) - DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) - DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) - DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) - DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) - DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt - DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) - DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) - DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) - DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt - DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt - DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt - DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt - DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt - DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt - DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt - DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt - DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt - DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished - DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt - DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt - DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt - DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt - DCD 0 ; 138: Reserved - DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) - DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTCEC0RX_IRQHandler [WEAK] - EXPORT INTCEC0TX_IRQHandler [WEAK] - EXPORT INTISDA_IRQHandler [WEAK] - EXPORT INTISDB_IRQHandler [WEAK] - EXPORT INTISDC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTRMC1_IRQHandler [WEAK] - EXPORT INTLTTMR_IRQHandler [WEAK] - EXPORT INTHDMAATC_IRQHandler [WEAK] - EXPORT INTHDMAAERR_IRQHandler [WEAK] - EXPORT INTHDMABTC_IRQHandler [WEAK] - EXPORT INTHDMABERR_IRQHandler [WEAK] - EXPORT INTMDMAATC_IRQHandler [WEAK] - EXPORT INTT32A00_A_CT_IRQHandler [WEAK] - EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A01_A_CT_IRQHandler [WEAK] - EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A02_A_CT_IRQHandler [WEAK] - EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A03_A_CT_IRQHandler [WEAK] - EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A04_A_CT_IRQHandler [WEAK] - EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A05_A_CT_IRQHandler [WEAK] - EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A06_A_CT_IRQHandler [WEAK] - EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A07_A_CT_IRQHandler [WEAK] - EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A08_A_CT_IRQHandler [WEAK] - EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A09_A_CT_IRQHandler [WEAK] - EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A10_A_CT_IRQHandler [WEAK] - EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A11_A_CT_IRQHandler [WEAK] - EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A12_A_CT_IRQHandler [WEAK] - EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A13_A_CT_IRQHandler [WEAK] - EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPWM0_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTT2RX_IRQHandler [WEAK] - EXPORT INTT2TX_IRQHandler [WEAK] - EXPORT INTT2ERR_IRQHandler [WEAK] - EXPORT INTT3RX_IRQHandler [WEAK] - EXPORT INTT3TX_IRQHandler [WEAK] - EXPORT INTT3ERR_IRQHandler [WEAK] - EXPORT INTT4RX_IRQHandler [WEAK] - EXPORT INTT4TX_IRQHandler [WEAK] - EXPORT INTT4ERR_IRQHandler [WEAK] - EXPORT INTT5RX_IRQHandler [WEAK] - EXPORT INTT5TX_IRQHandler [WEAK] - EXPORT INTT5ERR_IRQHandler [WEAK] - EXPORT INTT6RX_IRQHandler [WEAK] - EXPORT INTT6TX_IRQHandler [WEAK] - EXPORT INTT6ERR_IRQHandler [WEAK] - EXPORT INTT7RX_IRQHandler [WEAK] - EXPORT INTT7TX_IRQHandler [WEAK] - EXPORT INTT7ERR_IRQHandler [WEAK] - EXPORT INTT8RX_IRQHandler [WEAK] - EXPORT INTT8TX_IRQHandler [WEAK] - EXPORT INTT8ERR_IRQHandler [WEAK] - EXPORT INTSMI0_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTUART3RX_IRQHandler [WEAK] - EXPORT INTUART3TX_IRQHandler [WEAK] - EXPORT INTUART3ERR_IRQHandler [WEAK] - EXPORT INTUART4RX_IRQHandler [WEAK] - EXPORT INTUART4TX_IRQHandler [WEAK] - EXPORT INTUART4ERR_IRQHandler [WEAK] - EXPORT INTUART5RX_IRQHandler [WEAK] - EXPORT INTUART5TX_IRQHandler [WEAK] - EXPORT INTUART5ERR_IRQHandler [WEAK] - EXPORT INTFUART0_IRQHandler [WEAK] - EXPORT INTFUART1_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NACK_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NACK_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NACK_IRQHandler [WEAK] - EXPORT INTI2C3_IRQHandler [WEAK] - EXPORT INTI2C3AL_IRQHandler [WEAK] - EXPORT INTI2C3BF_IRQHandler [WEAK] - EXPORT INTI2C3NACK_IRQHandler [WEAK] - EXPORT INTI2C4_IRQHandler [WEAK] - EXPORT INTI2C4AL_IRQHandler [WEAK] - EXPORT INTI2C4BF_IRQHandler [WEAK] - EXPORT INTI2C4NACK_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTADAHP_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - EXPORT INTFLCRDY0_IRQHandler [WEAK] - EXPORT INTFLCRDY1_IRQHandler [WEAK] - EXPORT INTMDMAABERR_IRQHandler [WEAK] - EXPORT INTMDMAADERR_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INTRTC_IRQHandler -INTCEC0RX_IRQHandler -INTCEC0TX_IRQHandler -INTISDA_IRQHandler -INTISDB_IRQHandler -INTISDC_IRQHandler -INTRMC0_IRQHandler -INTRMC1_IRQHandler -INTLTTMR_IRQHandler -INTHDMAATC_IRQHandler -INTHDMAAERR_IRQHandler -INTHDMABTC_IRQHandler -INTHDMABERR_IRQHandler -INTMDMAATC_IRQHandler -INTT32A00_A_CT_IRQHandler -INTT32A00_B_C01_CPC_IRQHandler -INTT32A01_A_CT_IRQHandler -INTT32A01_B_C01_CPC_IRQHandler -INTT32A02_A_CT_IRQHandler -INTT32A02_B_C01_CPC_IRQHandler -INTT32A03_A_CT_IRQHandler -INTT32A03_B_C01_CPC_IRQHandler -INTT32A04_A_CT_IRQHandler -INTT32A04_B_C01_CPC_IRQHandler -INTT32A05_A_CT_IRQHandler -INTT32A05_B_C01_CPC_IRQHandler -INTT32A06_A_CT_IRQHandler -INTT32A06_B_C01_CPC_IRQHandler -INTT32A07_A_CT_IRQHandler -INTT32A07_B_C01_CPC_IRQHandler -INTT32A08_A_CT_IRQHandler -INTT32A08_B_C01_CPC_IRQHandler -INTT32A09_A_CT_IRQHandler -INTT32A09_B_C01_CPC_IRQHandler -INTT32A10_A_CT_IRQHandler -INTT32A10_B_C01_CPC_IRQHandler -INTT32A11_A_CT_IRQHandler -INTT32A11_B_C01_CPC_IRQHandler -INTT32A12_A_CT_IRQHandler -INTT32A12_B_C01_CPC_IRQHandler -INTT32A13_A_CT_IRQHandler -INTT32A13_B_C01_CPC_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPWM0_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTT2RX_IRQHandler -INTT2TX_IRQHandler -INTT2ERR_IRQHandler -INTT3RX_IRQHandler -INTT3TX_IRQHandler -INTT3ERR_IRQHandler -INTT4RX_IRQHandler -INTT4TX_IRQHandler -INTT4ERR_IRQHandler -INTT5RX_IRQHandler -INTT5TX_IRQHandler -INTT5ERR_IRQHandler -INTT6RX_IRQHandler -INTT6TX_IRQHandler -INTT6ERR_IRQHandler -INTT7RX_IRQHandler -INTT7TX_IRQHandler -INTT7ERR_IRQHandler -INTT8RX_IRQHandler -INTT8TX_IRQHandler -INTT8ERR_IRQHandler -INTSMI0_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTUART3RX_IRQHandler -INTUART3TX_IRQHandler -INTUART3ERR_IRQHandler -INTUART4RX_IRQHandler -INTUART4TX_IRQHandler -INTUART4ERR_IRQHandler -INTUART5RX_IRQHandler -INTUART5TX_IRQHandler -INTUART5ERR_IRQHandler -INTFUART0_IRQHandler -INTFUART1_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NACK_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NACK_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NACK_IRQHandler -INTI2C3_IRQHandler -INTI2C3AL_IRQHandler -INTI2C3BF_IRQHandler -INTI2C3NACK_IRQHandler -INTI2C4_IRQHandler -INTI2C4AL_IRQHandler -INTI2C4BF_IRQHandler -INTI2C4NACK_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTADAHP_IRQHandler -INTFLDRDY_IRQHandler -INTFLCRDY0_IRQHandler -INTFLCRDY1_IRQHandler -INTMDMAABERR_IRQHandler -INTMDMAADERR_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct deleted file mode 100644 index 74f7394e479..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E -I. --cpu Cortex-M4 -;; TMPM4G9F15FG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x000180000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; TMPM4G9: 1536 KB FLASH (0x180000) + 192 KB SRAM (0x30000) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region -{ - ER_IROM1 MBED_APP_START MBED_APP_SIZE - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x20000320 (0x30000 - 0x320 - Stack_Size) - { - tmpm4g9_fc.o (+RO) - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK (0x20000320+0x30000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S deleted file mode 100644 index b4c47bbb495..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S +++ /dev/null @@ -1,532 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM4G9.s - * @brief CMSIS Cortex-M4F Core Device Startup File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version - * @date - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long INT00_IRQHandler // 0: Interrupt pin 00a/00b - .long INT01_IRQHandler // 1: Interrupt pin 01a/00b - .long INT02_IRQHandler // 2: Interrupt pin 02a/00b - .long INT03_IRQHandler // 3: Interrupt pin 03a/03b - .long INT04_IRQHandler // 4: Interrupt pin 04a/04b - .long INT05_IRQHandler // 5: Interrupt pin 05a/05b - .long INT06_IRQHandler // 6: Interrupt pin 06a/06b - .long INT07_IRQHandler // 7: Interrupt pin 07a/07b - .long INT08_IRQHandler // 8: Interrupt pin 08a/08b - .long INT09_IRQHandler // 9: Interrupt pin 09a/09b - .long INT10_IRQHandler // 10: Interrupt pin 10a/10b - .long INT11_IRQHandler // 11: Interrupt pin 11a/11b - .long INT12_IRQHandler // 12: Interrupt pin 12a/12b - .long INT13_IRQHandler // 13: Interrupt pin 13a/13b - .long INT14_IRQHandler // 14: Interrupt pin 14a/14b - .long INT15_IRQHandler // 15: Interrupt pin 15a/15b - .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt - .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) - .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) - .long INTISDA_IRQHandler // 19: Interval Sensing Detector Interrupt (Unit A) - .long INTISDB_IRQHandler // 20: Interval Sensing Detector Interrupt (Unit B) - .long INTISDC_IRQHandler // 21: Interval Sensing Detector Interrupt (Unit C) - .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 - .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 - .long INTLTTMR_IRQHandler // 24: Long Term Timer Interrupt - .long INTHDMAATC_IRQHandler // 25: HDMA Complete of transfer(Unit A) - .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) - .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) - .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) - .long INTMDMAATC_IRQHandler // 29: MDMA Complete of transfer(Unit A) - .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA All Interrupt/Timer Interrupt C - .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA All Interrupt/Timer Interrupt C - .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA All Interrupt/Timer Interrupt C - .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA All Interrupt/Timer Interrupt C - .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA All Interrupt/Timer Interrupt C - .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA All Interrupt/Timer Interrupt C - .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA All Interrupt/Timer Interrupt C - .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA All Interrupt/Timer Interrupt C - .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA All Interrupt/Timer Interrupt C - .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA All Interrupt/Timer Interrupt C - .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA All Interrupt/Timer Interrupt C - .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA All Interrupt/Timer Interrupt C - .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA All Interrupt/Timer Interrupt C - .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA All Interrupt/Timer Interrupt C - .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt - .long INTPWM0_IRQHandler // 60: PMD0 interrupt - .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) - .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) - .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) - .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) - .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) - .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) - .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) - .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) - .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) - .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) - .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) - .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) - .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) - .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) - .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) - .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) - .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) - .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) - .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) - .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) - .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) - .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) - .long INTSMI0_IRQHandler // 88: Serial Memory Interface Interrupt - .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) - .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) - .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) - .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) - .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) - .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) - .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) - .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) - .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) - .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) - .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) - .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) - .long INTFUART0_IRQHandler // 107: FUART Interrupt(channel 0) - .long INTFUART1_IRQHandler // 108: FUART Interrupt(channel 1) - .long INTI2C0_IRQHandler // 109: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 110: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 111: I2C0 bus free interrupt - .long INTI2C0NACK_IRQHandler // 112: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 113: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 114: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 115: I2C1 bus free interrupt - .long INTI2C1NACK_IRQHandler // 116: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 117: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 118: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 119: I2C2 bus free interrupt - .long INTI2C2NACK_IRQHandler // 120: I2C2 no ack interrupt - .long INTI2C3_IRQHandler // 121: I2C3 transmission and reception interrupt - .long INTI2C3AL_IRQHandler // 122: I2C3 arbitration lost interrupt - .long INTI2C3BF_IRQHandler // 123: I2C3 bus free interrupt - .long INTI2C3NACK_IRQHandler // 124: I2C3 no ack interrupt - .long INTI2C4_IRQHandler // 125: I2C4 transmission and reception interrupt - .long INTI2C4AL_IRQHandler // 126: I2C4 arbitration lost interrupt - .long INTI2C4BF_IRQHandler // 127: I2C4 bus free interrupt - .long INTI2C4NACK_IRQHandler // 128: I2C4 no ack interrupt - .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 - .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 - .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished - .long INTADAHP_IRQHandler // 134: ADC High Priority AD conversion interrupt - .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt - .long INTFLCRDY0_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt - .long INTFLCRDY1_IRQHandler // 137: Code FLASH Area2 Ready interrupt - .long 0 // 138: Reserved - .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) - .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTCEC0RX_IRQHandler - def_irq_handler INTCEC0TX_IRQHandler - def_irq_handler INTISDA_IRQHandler - def_irq_handler INTISDB_IRQHandler - def_irq_handler INTISDC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTRMC1_IRQHandler - def_irq_handler INTLTTMR_IRQHandler - def_irq_handler INTHDMAATC_IRQHandler - def_irq_handler INTHDMAAERR_IRQHandler - def_irq_handler INTHDMABTC_IRQHandler - def_irq_handler INTHDMABERR_IRQHandler - def_irq_handler INTMDMAATC_IRQHandler - def_irq_handler INTT32A00_A_CT_IRQHandler - def_irq_handler INTT32A00_B_C01_CPC_IRQHandler - def_irq_handler INTT32A01_A_CT_IRQHandler - def_irq_handler INTT32A01_B_C01_CPC_IRQHandler - def_irq_handler INTT32A02_A_CT_IRQHandler - def_irq_handler INTT32A02_B_C01_CPC_IRQHandler - def_irq_handler INTT32A03_A_CT_IRQHandler - def_irq_handler INTT32A03_B_C01_CPC_IRQHandler - def_irq_handler INTT32A04_A_CT_IRQHandler - def_irq_handler INTT32A04_B_C01_CPC_IRQHandler - def_irq_handler INTT32A05_A_CT_IRQHandler - def_irq_handler INTT32A05_B_C01_CPC_IRQHandler - def_irq_handler INTT32A06_A_CT_IRQHandler - def_irq_handler INTT32A06_B_C01_CPC_IRQHandler - def_irq_handler INTT32A07_A_CT_IRQHandler - def_irq_handler INTT32A07_B_C01_CPC_IRQHandler - def_irq_handler INTT32A08_A_CT_IRQHandler - def_irq_handler INTT32A08_B_C01_CPC_IRQHandler - def_irq_handler INTT32A09_A_CT_IRQHandler - def_irq_handler INTT32A09_B_C01_CPC_IRQHandler - def_irq_handler INTT32A10_A_CT_IRQHandler - def_irq_handler INTT32A10_B_C01_CPC_IRQHandler - def_irq_handler INTT32A11_A_CT_IRQHandler - def_irq_handler INTT32A11_B_C01_CPC_IRQHandler - def_irq_handler INTT32A12_A_CT_IRQHandler - def_irq_handler INTT32A12_B_C01_CPC_IRQHandler - def_irq_handler INTT32A13_A_CT_IRQHandler - def_irq_handler INTT32A13_B_C01_CPC_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPWM0_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTT2RX_IRQHandler - def_irq_handler INTT2TX_IRQHandler - def_irq_handler INTT2ERR_IRQHandler - def_irq_handler INTT3RX_IRQHandler - def_irq_handler INTT3TX_IRQHandler - def_irq_handler INTT3ERR_IRQHandler - def_irq_handler INTT4RX_IRQHandler - def_irq_handler INTT4TX_IRQHandler - def_irq_handler INTT4ERR_IRQHandler - def_irq_handler INTT5RX_IRQHandler - def_irq_handler INTT5TX_IRQHandler - def_irq_handler INTT5ERR_IRQHandler - def_irq_handler INTT6RX_IRQHandler - def_irq_handler INTT6TX_IRQHandler - def_irq_handler INTT6ERR_IRQHandler - def_irq_handler INTT7RX_IRQHandler - def_irq_handler INTT7TX_IRQHandler - def_irq_handler INTT7ERR_IRQHandler - def_irq_handler INTT8RX_IRQHandler - def_irq_handler INTT8TX_IRQHandler - def_irq_handler INTT8ERR_IRQHandler - def_irq_handler INTSMI0_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTUART3RX_IRQHandler - def_irq_handler INTUART3TX_IRQHandler - def_irq_handler INTUART3ERR_IRQHandler - def_irq_handler INTUART4RX_IRQHandler - def_irq_handler INTUART4TX_IRQHandler - def_irq_handler INTUART4ERR_IRQHandler - def_irq_handler INTUART5RX_IRQHandler - def_irq_handler INTUART5TX_IRQHandler - def_irq_handler INTUART5ERR_IRQHandler - def_irq_handler INTFUART0_IRQHandler - def_irq_handler INTFUART1_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NACK_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NACK_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NACK_IRQHandler - def_irq_handler INTI2C3_IRQHandler - def_irq_handler INTI2C3AL_IRQHandler - def_irq_handler INTI2C3BF_IRQHandler - def_irq_handler INTI2C3NACK_IRQHandler - def_irq_handler INTI2C4_IRQHandler - def_irq_handler INTI2C4AL_IRQHandler - def_irq_handler INTI2C4BF_IRQHandler - def_irq_handler INTI2C4NACK_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTADAHP_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - def_irq_handler INTFLCRDY0_IRQHandler - def_irq_handler INTFLCRDY1_IRQHandler - //def_irq_handler 0 - def_irq_handler INTMDMAABERR_IRQHandler - def_irq_handler INTMDMAADERR_IRQHandler - - .end diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld deleted file mode 100644 index 3a3a846b764..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld +++ /dev/null @@ -1,214 +0,0 @@ -/* Linker script for Toshiba TMPM4G9 */ - -/* Linker script to configure memory regions. */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x180000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = 0x20000320, LENGTH = (192K - 0x320) -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - *(.ram_func*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S deleted file mode 100644 index ac05911602d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S +++ /dev/null @@ -1,952 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM4G9.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for the -; * TOSHIBA 'TMPM4G9' Device Series -; * @version V1.0.9.0 -; * $Date:: 2018-04-02 #$ -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2018 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b - DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b - DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b - DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b - DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b - DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b - DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b - DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b - DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b - DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b - DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b - DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b - DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b - DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b - DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b - DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b - DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt - DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) - DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) - DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) - DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) - DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) - DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 - DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 - DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) - DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) - DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) - DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) - DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) - DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) - DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt - DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt - DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) - DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) - DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) - DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) - DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) - DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) - DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) - DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) - DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) - DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) - DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) - DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) - DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) - DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt - DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) - DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) - DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) - DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt - DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt - DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt - DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt - DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt - DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt - DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt - DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt - DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt - DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished - DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt - DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt - DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt - DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt - DCD 0 ; 138: Reserved - DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) - DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTCEC0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTCEC0RX_IRQHandler - B INTCEC0RX_IRQHandler - - PUBWEAK INTCEC0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTCEC0TX_IRQHandler - B INTCEC0TX_IRQHandler - - PUBWEAK INTISDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDA_IRQHandler - B INTISDA_IRQHandler - - PUBWEAK INTISDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDB_IRQHandler - B INTISDB_IRQHandler - - PUBWEAK INTISDC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDC_IRQHandler - B INTISDC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTRMC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC1_IRQHandler - B INTRMC1_IRQHandler - - PUBWEAK INTLTTMR0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTLTTMR0_IRQHandler - B INTLTTMR0_IRQHandler - - PUBWEAK INTHDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMAATC_IRQHandler - B INTHDMAATC_IRQHandler - - PUBWEAK INTHDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMAAERR_IRQHandler - B INTHDMAAERR_IRQHandler - - PUBWEAK INTHDMABTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMABTC_IRQHandler - B INTHDMABTC_IRQHandler - - PUBWEAK INTHDMABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMABERR_IRQHandler - B INTHDMABERR_IRQHandler - - PUBWEAK INTMDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAATC_IRQHandler - B INTMDMAATC_IRQHandler - - PUBWEAK INTT32A00_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00_A_CT_IRQHandler - B INTT32A00_A_CT_IRQHandler - - PUBWEAK INTT32A00_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00_B_C01_CPC_IRQHandler - B INTT32A00_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A01_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01_A_CT_IRQHandler - B INTT32A01_A_CT_IRQHandler - - PUBWEAK INTT32A01_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01_B_C01_CPC_IRQHandler - B INTT32A01_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A02_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02_A_CT_IRQHandler - B INTT32A02_A_CT_IRQHandler - - PUBWEAK INTT32A02_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02_B_C01_CPC_IRQHandler - B INTT32A02_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A03_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03_A_CT_IRQHandler - B INTT32A03_A_CT_IRQHandler - - PUBWEAK INTT32A03_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03_B_C01_CPC_IRQHandler - B INTT32A03_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A04_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04_A_CT_IRQHandler - B INTT32A04_A_CT_IRQHandler - - PUBWEAK INTT32A04_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04_B_C01_CPC_IRQHandler - B INTT32A04_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A05_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05_A_CT_IRQHandler - B INTT32A05_A_CT_IRQHandler - - PUBWEAK INTT32A05_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05_B_C01_CPC_IRQHandler - B INTT32A05_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A06_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06_A_CT_IRQHandler - B INTT32A06_A_CT_IRQHandler - - PUBWEAK INTT32A06_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06_B_C01_CPC_IRQHandler - B INTT32A06_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A07_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07_A_CT_IRQHandler - B INTT32A07_A_CT_IRQHandler - - PUBWEAK INTT32A07_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07_B_C01_CPC_IRQHandler - B INTT32A07_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A08_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A08_A_CT_IRQHandler - B INTT32A08_A_CT_IRQHandler - - PUBWEAK INTT32A08_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A08_B_C01_CPC_IRQHandler - B INTT32A08_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A09_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A09_A_CT_IRQHandler - B INTT32A09_A_CT_IRQHandler - - PUBWEAK INTT32A09_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A09_B_C01_CPC_IRQHandler - B INTT32A09_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A10_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A10_A_CT_IRQHandler - B INTT32A10_A_CT_IRQHandler - - PUBWEAK INTT32A10_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A10_B_C01_CPC_IRQHandler - B INTT32A10_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A11_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A11_A_CT_IRQHandler - B INTT32A11_A_CT_IRQHandler - - PUBWEAK INTT32A11_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A11_B_C01_CPC_IRQHandler - B INTT32A11_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A12_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A12_A_CT_IRQHandler - B INTT32A12_A_CT_IRQHandler - - PUBWEAK INTT32A12_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A12_B_C01_CPC_IRQHandler - B INTT32A12_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A13_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A13_A_CT_IRQHandler - B INTT32A13_A_CT_IRQHandler - - PUBWEAK INTT32A13_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A13_B_C01_CPC_IRQHandler - B INTT32A13_B_C01_CPC_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPWM0_IRQHandler - B INTPWM0_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTT2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2RX_IRQHandler - B INTT2RX_IRQHandler - - PUBWEAK INTT2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2TX_IRQHandler - B INTT2TX_IRQHandler - - PUBWEAK INTT2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2ERR_IRQHandler - B INTT2ERR_IRQHandler - - PUBWEAK INTT3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3RX_IRQHandler - B INTT3RX_IRQHandler - - PUBWEAK INTT3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3TX_IRQHandler - B INTT3TX_IRQHandler - - PUBWEAK INTT3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3ERR_IRQHandler - B INTT3ERR_IRQHandler - - PUBWEAK INTT4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4RX_IRQHandler - B INTT4RX_IRQHandler - - PUBWEAK INTT4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4TX_IRQHandler - B INTT4TX_IRQHandler - - PUBWEAK INTT4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4ERR_IRQHandler - B INTT4ERR_IRQHandler - - PUBWEAK INTT5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5RX_IRQHandler - B INTT5RX_IRQHandler - - PUBWEAK INTT5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5TX_IRQHandler - B INTT5TX_IRQHandler - - PUBWEAK INTT5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5ERR_IRQHandler - B INTT5ERR_IRQHandler - - PUBWEAK INTT6RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6RX_IRQHandler - B INTT6RX_IRQHandler - - PUBWEAK INTT6TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6TX_IRQHandler - B INTT6TX_IRQHandler - - PUBWEAK INTT6ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6ERR_IRQHandler - B INTT6ERR_IRQHandler - - PUBWEAK INTT7RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7RX_IRQHandler - B INTT7RX_IRQHandler - - PUBWEAK INTT7TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7TX_IRQHandler - B INTT7TX_IRQHandler - - PUBWEAK INTT7ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7ERR_IRQHandler - B INTT7ERR_IRQHandler - - PUBWEAK INTT8RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8RX_IRQHandler - B INTT8RX_IRQHandler - - PUBWEAK INTT8TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8TX_IRQHandler - B INTT8TX_IRQHandler - - PUBWEAK INTT8ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8ERR_IRQHandler - B INTT8ERR_IRQHandler - - PUBWEAK INTSMI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTSMI0_IRQHandler - B INTSMI0_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTUART3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3RX_IRQHandler - B INTUART3RX_IRQHandler - - PUBWEAK INTUART3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3TX_IRQHandler - B INTUART3TX_IRQHandler - - PUBWEAK INTUART3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3ERR_IRQHandler - B INTUART3ERR_IRQHandler - - PUBWEAK INTUART4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4RX_IRQHandler - B INTUART4RX_IRQHandler - - PUBWEAK INTUART4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4TX_IRQHandler - B INTUART4TX_IRQHandler - - PUBWEAK INTUART4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4ERR_IRQHandler - B INTUART4ERR_IRQHandler - - PUBWEAK INTUART5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5RX_IRQHandler - B INTUART5RX_IRQHandler - - PUBWEAK INTUART5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5TX_IRQHandler - B INTUART5TX_IRQHandler - - PUBWEAK INTUART5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5ERR_IRQHandler - B INTUART5ERR_IRQHandler - - PUBWEAK INTFUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFUART0_IRQHandler - B INTFUART0_IRQHandler - - PUBWEAK INTFUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFUART1_IRQHandler - B INTFUART1_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NACK_IRQHandler - B INTI2C0NACK_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NACK_IRQHandler - B INTI2C1NACK_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NACK_IRQHandler - B INTI2C2NACK_IRQHandler - - PUBWEAK INTI2C3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3_IRQHandler - B INTI2C3_IRQHandler - - PUBWEAK INTI2C3AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3AL_IRQHandler - B INTI2C3AL_IRQHandler - - PUBWEAK INTI2C3BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3BF_IRQHandler - B INTI2C3BF_IRQHandler - - PUBWEAK INTI2C3NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3NACK_IRQHandler - B INTI2C3NACK_IRQHandler - - PUBWEAK INTI2C4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4_IRQHandler - B INTI2C4_IRQHandler - - PUBWEAK INTI2C4AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4AL_IRQHandler - B INTI2C4AL_IRQHandler - - PUBWEAK INTI2C4BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4BF_IRQHandler - B INTI2C4BF_IRQHandler - - PUBWEAK INTI2C4NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4NACK_IRQHandler - B INTI2C4NACK_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTADAHP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAHP_IRQHandler - B INTADAHP_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - PUBWEAK INTFLCRDY0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY0_IRQHandler - B INTFLCRDY0_IRQHandler - - PUBWEAK INTFLCRDY1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY1_IRQHandler - B INTFLCRDY1_IRQHandler - - PUBWEAK INTMDMAABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAABERR_IRQHandler - B INTMDMAABERR_IRQHandler - - PUBWEAK INTMDMAADERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAADERR_IRQHandler - B INTMDMAADERR_IRQHandler - - END diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf deleted file mode 100644 index e79c3b90b34..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x180000; } -define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000320; -define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_BRAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_BRAM_end__ = 0x200307FF; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x0400; -define symbol __ICFEDIT_size_heap__ = 0x6000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -initialize by copy { section RAMCODE }; - -/* Place both in a block */ -define block RamCode { section RAMCODE }; -define block RamCodeInit { section RAMCODE_init }; - -/* Place them in ROM and RAM */ -place in ROM_region { block RamCodeInit }; -place in RAM_region { block RamCode }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in ROM_region { readonly }; diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h deleted file mode 100644 index 6bcd9c1fb09..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h +++ /dev/null @@ -1,12 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM4G9 - * Copyright (C) 2011 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * A generic CMSIS include header, pulling in TMPM4G9 specifics - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM4G9.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h deleted file mode 100644 index 3b46a6c8810..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h +++ /dev/null @@ -1,28 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM4G9 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - - -#if defined(__ICCARM__) - #pragma section=".intvec" - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) -#elif defined(__CC_ARM) - extern uint32_t Load$$LR$$LR_IROM1$$Base[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) -#elif defined(__GNUC__) - extern uint32_t vectors[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) -#else - #error "Flash vector address not set for this toolchain" -#endif - - -#define NVIC_NUM_VECTORS (157) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c b/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c deleted file mode 100644 index d2208ec40c1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM4G9.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM4Gx' Device Series - * @version 1.0.0.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - ******************************************************************************* - */ - -#include "TMPM4G9.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ -#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ - -#define STBYCR_Val (0x00000000UL) - -#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ -#define CG_10M_MUL_16_FPLL (0x002E5020UL<<8U) /* fPLL = 10MHz * 16 */ -#define CG_12M_MUL_13_3125_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.3125 */ -#define CG_16M_MUL_10_FPLL (0x0048D014UL<<8U) /* fPLL = 16MHz * 10 */ -#define CG_20M_MUL_8_FPLL (0x005AD010UL<<8U) /* fPLL = 20MHz * 8 */ - -#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) -#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) -#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) -#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) - -#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) -#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) -#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) - -#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) -#define CG_OSCCR_EOSCEN_SET (0x00000002UL) -#define CG_OSCCR_OSCSEL_SET (0x00000100UL) - -#define CG_WUPHCR_WUON_START_SET (0x00000001UL) - -#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ - #define PLL0SEL_Ready CG_12M_MUL_13_3125_FPLL -#else - #define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ - #define PLL0SEL_Ready CG_12M_MUL_13_3125_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define EOSC_16M (16000000UL) -#define EOSC_20M (20000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ -#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ -#define EOSC_12M_DIV2_PLLON (159750000UL) /* 12.00MHz * 26.6250 / 2 */ -#define EOSC_16M_DIV2_PLLON (160000000UL) /* 16.00MHz * 20.0000 / 2 */ -#define EOSC_20M_DIV2_PLLON (160000000UL) /* 20.00MHz * 16.0000 / 2 */ -#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif - -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL)) - #define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) - #define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL) - #define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL) - #define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 16MHz */ - #elif (CORE_TALH == EOSC_20M) /* If input is 20MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL) - #define __CORE_CLK EOSC_20M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 20MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) - #define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ -uint32_t CoreClockInput = 0U; - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t regval = 0U; - - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - - CoreClockInput = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) { - CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { - CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL) { - CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL) { - CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_20M) { /* If input is 20MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL) { - CoreClockInput = EOSC_20M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { - CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - SystemCoreClock = CoreClockInput / 8U; - break; - case 4U: /* Gear -> fc/16 */ - SystemCoreClock = CoreClockInput / 16U; - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_GEAR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ - while((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) - != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))){ - ; - } - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - //TSB_RLM->LOSCCR = 0x03; - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h deleted file mode 100644 index 9ea28b81a03..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM4G9.h - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version V0.0.0.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM4G9_H -#define __SYSTEM_TMPM4G9_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c deleted file mode 100644 index f3e30e424a4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c +++ /dev/null @@ -1,130 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "mbed_critical.h" -#include "tmpm4g9_fc.h" - -#define PROGRAM_WIRTE_MAX (16U) // Page program could be written 16 bytes/4 words once -#define SECTOR_SIZE (0x8000) // 32KB each sectors or block -#define FLASH_CHIP_SIZE (0x00180000) // Flash chip size is 1536KByte -#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) - -#define SUCCESS (0U) -#define FAIL (-1) -// IHOSC1EN -#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask -#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable -#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable - -static void internal_hosc_enable(void); - -int32_t flash_init(flash_t *obj) -{ - obj->flash_inited = 0; - obj->flash_inited = 1; - internal_hosc_enable(); // Internal HOSC enable - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - obj->flash_inited = 0; - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - int status = FAIL; - - if (obj->flash_inited == 0) { - flash_init(obj); - } - - // We need to prevent flash accesses during erase operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) { - status = SUCCESS; - } else { - // Do nothing - } - - core_util_critical_section_exit(); - - return status; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - int status = SUCCESS; - - address &= MASK_CHIP_ID_FROM_ADD; - - // We need to prevent flash accesses during program operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) { - // Do nothing - } else { - status = FAIL; - } - - core_util_critical_section_exit(); - - return status; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { - return SECTOR_SIZE; - } else { - // Do nothing - } - - return MBED_FLASH_INVALID_SIZE; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return PROGRAM_WIRTE_MAX; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return FC_CODE_FLASH_ADDRESS_TOP; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return FLASH_CHIP_SIZE; -} - -static void internal_hosc_enable(void) -{ - uint32_t work; - work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); - TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c deleted file mode 100644 index c30f3f1f450..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define GPIO_DATA PIN_DATA(0, 2) -#define ALT_FUNC_GPIO 0U - -_gpio_t gpio_port_add = { - .p_pa_instance = TSB_PA, - .p_pb_instance = TSB_PB, - .p_pc_instance = TSB_PC, - .p_pd_instance = TSB_PD, - .p_pe_instance = TSB_PE, - .p_pf_instance = TSB_PF, - .p_pg_instance = TSB_PG, - .p_ph_instance = TSB_PH, - .p_pj_instance = TSB_PJ, - .p_pk_instance = TSB_PK, - .p_pl_instance = TSB_PL, - .p_pm_instance = TSB_PM, - .p_pn_instance = TSB_PN, - .p_pp_instance = TSB_PP, - .p_pr_instance = TSB_PR, - .p_pt_instance = TSB_PT, - .p_pu_instance = TSB_PU, - .p_pv_instance = TSB_PV, - .p_pw_instance = TSB_PW, - .p_py_instance = TSB_PY -}; - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - - // Return pin mask - return (1 << (pin & 0x07)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin != NC) { - obj->pin_num = PIN_POS(pin); - obj->mask = gpio_set(pin); - obj->port = (PortName) PIN_PORT(pin); - //Enable clock for particular port - TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2)); - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - // Set pin mode - pin_mode(obj->pin, mode); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_INOUT); - break; - default: - break; - } -} - -void gpio_write(gpio_t *obj, int value) -{ - // Write gpio object pin data - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); -} - -int gpio_read(gpio_t *obj) -{ - // Read gpio object pin data - gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable - gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); - return val; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c deleted file mode 100644 index a487732e502..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c +++ /dev/null @@ -1,281 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_critical.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define CHANNEL_NUM (16) -#define DISABLE (0) -#define ENABLE (1) -#define CLR_INT_FLAG (0xC0) - -const PinMap PinMap_GPIO_IRQ[] = { - {PK7, GPIO_IRQ_0, PIN_DATA(0, 0)}, - {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)}, - {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_3, PIN_DATA(0, 0)}, - {PB0, GPIO_IRQ_4, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_5, PIN_DATA(0, 0)}, - {PB6, GPIO_IRQ_6, PIN_DATA(0, 0)}, - {PB7, GPIO_IRQ_7, PIN_DATA(0, 0)}, - {PG0, GPIO_IRQ_8, PIN_DATA(0, 0)}, - {PG1, GPIO_IRQ_9, PIN_DATA(0, 0)}, - {PK0, GPIO_IRQ_A, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)}, - {PC0, GPIO_IRQ_C, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_D, PIN_DATA(0, 0)}, - {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)}, - {PC7, GPIO_IRQ_F, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -extern _gpio_t gpio_port_add; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static CG_INTActiveState CurrentState; - -static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); -static void INT_IRQHandler(PinName, uint32_t); - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PK7, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PL0, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PA0, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PA7, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PB0, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PB1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PB6, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PB7, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PG0, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PG1, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PK0, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PK1, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PC0, 12); -} -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PC1, 13); -} -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PC6, 14); -} -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PC7, 15); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - core_util_critical_section_enter(); - // Get GPIO port and pin num - obj->port = (PortName)PIN_PORT(pin); - obj->pin_num = PIN_POS(pin); - // Set pin level as LOW - gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - // Get GPIO irq source - obj->irq_src = (CG_INTSrc)obj->irq_id; - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - // Save irq id - channel_ids[obj->irq_src] = id; - // Initialize interrupt event as both edges detection - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Set interrupt event and enable INTx clear - CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); - core_util_critical_section_exit();; - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || - (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || - (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || - (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || - (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - if (obj->event != CG_INT_ACTIVE_STATE_INVALID ) { - // Set interrupt event and enable INTx clear - CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); - } else { - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); - } - // Clear interrupt request - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - PortName port; - gpio_pinstate_t data = GPIO_PIN_RESET; - uint8_t pin_num; - - pin_num = PIN_POS(pin); - port = (PortName)PIN_PORT(pin); - // Clear interrupt request - CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); - // Get pin value - gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); - // Enable interrupt request - CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); -} - -static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) -{ - uint8_t *ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2)); - //clear pending falling and rising edge bit - *ptr = CLR_INT_FLAG; - *ptr = (ActiveState | NewState); - { - uint8_t regval = *ptr; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h deleted file mode 100644 index c579368d239..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "txz_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - PortName port; - uint32_t pin_num; - uint32_t mask; -} gpio_t; - -typedef enum { - CG_INT_SRC_0 = 0U, - CG_INT_SRC_1, - CG_INT_SRC_2, - CG_INT_SRC_3, - CG_INT_SRC_4, - CG_INT_SRC_5, - CG_INT_SRC_6, - CG_INT_SRC_7, - CG_INT_SRC_8, - CG_INT_SRC_9, - CG_INT_SRC_A, - CG_INT_SRC_B, - CG_INT_SRC_C, - CG_INT_SRC_D, - CG_INT_SRC_E, - CG_INT_SRC_F -} CG_INTSrc; - -typedef enum { - CG_INT_ACTIVE_STATE_L = 0x00U, - CG_INT_ACTIVE_STATE_H = 0x02U, - CG_INT_ACTIVE_STATE_FALLING = 0x04U, - CG_INT_ACTIVE_STATE_RISING = 0x06U, - CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, - CG_INT_ACTIVE_STATE_INVALID = 0x0AU -} CG_INTActiveState; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin != (PinName)NC); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c deleted file mode 100644 index 57551473c97..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c +++ /dev/null @@ -1,216 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include -#include -#include -#include "mbed_error.h" -#include "txz_i2c_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define MAX_I2C_FREQ 1000000 - -static const PinMap PinMap_I2C_SDA[] = { - {PG2, I2C_0, PIN_DATA(7, 2)}, - {PF2, I2C_1, PIN_DATA(7, 2)}, - {PG4, I2C_2, PIN_DATA(7, 2)}, - {PJ6, I2C_3, PIN_DATA(7, 2)}, - {PJ3, I2C_4, PIN_DATA(7, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PG3, I2C_0, PIN_DATA(7, 2)}, - {PF3, I2C_1, PIN_DATA(7, 2)}, - {PG5, I2C_2, PIN_DATA(7, 2)}, - {PJ7, I2C_3, PIN_DATA(7, 2)}, - {PJ2, I2C_4, PIN_DATA(7, 2)}, - {NC, NC, 0} -}; - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - MBED_ASSERT(obj != NULL); - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch(i2c_name) { - case I2C_0: - // Enable clock for I2C_0 - TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; - //Enable clok for GPIO G - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C0; - obj->my_i2c.info.irqn = INTI2C0_IRQn; - break; - case I2C_1: - // Enable clock for I2C_1 - TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; - //Enable clok for GPIO F - TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C1; - obj->my_i2c.info.irqn = INTI2C1_IRQn; - break; - case I2C_2: - // Enable clock for I2C_2 - TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; - //Enable clok for GPIO G - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C2; - obj->my_i2c.info.irqn = INTI2C2_IRQn; - break; - case I2C_3: - // Enable clock for I2C_3 - TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; - //Enable clok for GPIO J - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C3; - obj->my_i2c.info.irqn = INTI2C3_IRQn; - break; - case I2C_4: - // Enable clock for I2C_4 - TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; - //Enable clok for GPIO J - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C4; - obj->my_i2c.info.irqn = INTI2C4_IRQn; - break; - default: - error("I2C is not available"); - break; - } - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - I2C_init(&obj->my_i2c.i2c); -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - if (hz <= MAX_I2C_FREQ) { - i2c_frequency_t(&obj->my_i2c, hz); - } else { - error("Failed : Max I2C frequency is 1000000"); - } -} - -int i2c_start(i2c_t *obj) -{ - i2c_start_t(&obj->my_i2c); - return TXZ_SUCCESS; -} - -int i2c_stop(i2c_t *obj) -{ - i2c_stop_t(&obj->my_i2c); - return TXZ_SUCCESS; -} - -void i2c_reset(i2c_t *obj) -{ - // Software reset - i2c_reset_t(&obj->my_i2c); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); - return count; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - int32_t data = i2c_byte_read_t(&obj->my_i2c, last); - return data; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - int32_t result = i2c_byte_write_t(&obj->my_i2c, data); - return result; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - i2c_slave_mode_t(&obj->my_i2c, enable_slave); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - i2c_slave_address_t(&obj->my_i2c, address); -} - -int i2c_slave_receive(i2c_t *obj) -{ - int32_t result = i2c_slave_receive_t(&obj->my_i2c); - return result; -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - int32_t count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length); - return count; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length); - return count; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/objects.h b/targets/TARGET_TT/TARGET_TT_M4G9/objects.h deleted file mode 100644 index d4f385074c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/objects.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "gpio_object.h" -#include "txz_gpio.h" -#include "txz_uart.h" -#include "txz_fuart.h" -#include "txz_tspi.h" -#include "txz_t32a.h" -#include "txz_cg.h" -#include "txz_driver_def.h" -#include "adc.h" -#include "txz_i2c_api.h" -#include "txz_i2c.h" -#include "txz_fuart_include.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct port_s { - PortName port; - uint32_t mask; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef *DACx; -}; - -struct serial_s { - uint32_t index; - uint32_t mode; - TSB_UART_TypeDef *UARTx; - TSB_FURT_TypeDef *FUARTx; - uart_boudrate_t boud_obj; - fuart_boudrate_t fboud_obj; -}; - -struct pwmout_s { - PinName pin; - uint32_t trailing_timing; - uint32_t leading_timing; - uint32_t divisor; - float period; - t32a_t p_t32a; - uint32_t type; -}; - -struct spi_s { - tspi_t p_obj; - SPIName module; - uint8_t bits; -}; - -struct gpio_irq_s { - PortName port; - uint8_t pin_num; - uint32_t irq_id; - CG_INTActiveState event; - CG_INTSrc irq_src; -}; - -struct flash_s { - int flash_inited; -}; - -struct analogin_s { - PinName pin; - adc_t p_adc; - adc_channel_setting_t param; - ADCName adc; -}; - -struct i2c_s { - uint32_t index; - int address; - _i2c_t my_i2c; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c b/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c deleted file mode 100644 index 0f612fb224b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "txz_gpio.h" - -#define PIN_FUNC_MAX 8 - -extern _gpio_t gpio_port_add; - -void pin_function(PinName pin, int function) -{ - uint32_t port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Calculate pin function and pin direction - func = PIN_FUNC(function); - dir = PIN_DIR(function); - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // find function is in range or not - if (func <= PIN_FUNC_MAX) { - // Set pin function and direction if direction is in range - switch (dir) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); - break; - default: - break; - } - } else { - // do nothing - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - uint32_t port = 0; - uint8_t bit = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Check if function is in range - if (mode > OpenDrain) { - return; - } - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // Set pin mode - switch (mode) { - case PullNone: - gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - break; - case PullUp: - gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - case PullDown: - gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - case OpenDrain: - gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - default: - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c deleted file mode 100644 index d1f687baca7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c +++ /dev/null @@ -1,140 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "mbed_assert.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "pinmap.h" - -#define PORT_PIN_NUM (8) -#define ALT_FUNC_GPIO (0U) - -extern _gpio_t gpio_port_add; -static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName)((port << 3) | pin_n); - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortY); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - //Enable the clock for particular port - _gpio_init(&gpio_port_add, obj->port); - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t i = 0; - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - for (i = 0; i < PORT_PIN_NUM; i++) { - // Set direction for masked pins - if (obj->mask & (1 << i)) { - gpio_pin_dir(obj, dir, i); - } - } -} - -void port_write(port_t *obj, int value) -{ - uint32_t port_data = 0; - uint32_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Get current data of port - gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); - - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - - // Write data to masked pins of the port - gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); -} - -int port_read(port_t *obj) -{ - uint32_t port_data = 0; - uint32_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Get current data of port - gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); - - // Calculate data of masked pins - data = port_data & obj->mask; - - return data; -} - -static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) -{ - switch (dir) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); - break; - default: - //error("Invalid direction\n"); - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c deleted file mode 100644 index 66224c7d7aa..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c +++ /dev/null @@ -1,225 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#include "pwmout_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define GPIO_CLK_OFFSET 2 -// Because Timer operating frequency is 2.5 MhZ -#define CALCULATE_RGC1_VAL 2.5 - -static const PinMap PinMap_PWM[] = { - {PA5, PWM_0, PIN_DATA(5, 1)}, - {PB2, PWM_1, PIN_DATA(5, 1)}, - {PB4, PWM_2, PIN_DATA(5, 1)}, - {PD2, PWM_3, PIN_DATA(5, 1)}, - {PD4, PWM_4, PIN_DATA(5, 1)}, - {PE1, PWM_5, PIN_DATA(5, 1)}, - {PE6, PWM_6, PIN_DATA(5, 1)}, - {PC2, PWM_7, PIN_DATA(5, 1)}, - {PL6, PWM_8, PIN_DATA(3, 1)}, - {PC4, PWM_9, PIN_DATA(5, 1)}, - {PM2, PWM_10, PIN_DATA(3, 1)}, - {PU0, PWM_11, PIN_DATA(3, 1)}, - {PU6, PWM_12, PIN_DATA(3, 1)}, - {NC, NC, 0} -}; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - // Determine the pwm channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - //Assert input is valid - MBED_ASSERT(pwm != (PWMName)NC); - switch (pwm) { - case PWM_0: - obj->p_t32a.p_instance = TSB_T32A1; - // Clock enable of T32A ch01 - TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE; - break; - case PWM_1: - obj->p_t32a.p_instance = TSB_T32A2; - // Clock enable of T32A ch02 - TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE; - break; - case PWM_2: - obj->p_t32a.p_instance = TSB_T32A3; - // Clock enable of T32A ch03 - TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE; - break; - case PWM_3: - obj->p_t32a.p_instance = TSB_T32A4; - // Clock enable of T32A ch04 - TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; - break; - case PWM_4: - obj->p_t32a.p_instance = TSB_T32A5; - // Clock enable of T32A ch05 - TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; - break; - case PWM_5: - obj->p_t32a.p_instance = TSB_T32A6; - // Clock enable of T32A ch06 - TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE; - break; - case PWM_6: - obj->p_t32a.p_instance = TSB_T32A7; - // Clock enable of T32A ch07 - TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE; - break; - case PWM_7: - obj->p_t32a.p_instance = TSB_T32A8; - // Clock enable of T32A ch08 - TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE; - break; - case PWM_8: - obj->p_t32a.p_instance = TSB_T32A9; - // Clock enable of T32A ch09 - TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE; - break; - case PWM_9: - obj->p_t32a.p_instance = TSB_T32A10; - // Clock enable of T32A ch10 - TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; - break; - case PWM_10: - obj->p_t32a.p_instance = TSB_T32A11; - // Clock enable of T32A ch11 - TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE; - break; - case PWM_11: - obj->p_t32a.p_instance = TSB_T32A12; - // Clock enable of T32A ch12 - TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE; - break; - case PWM_12: - obj->p_t32a.p_instance = TSB_T32A13; - // Clock enable of T32A ch13 - TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; - break; - default: - obj->p_t32a.p_instance = NULL; - break; - } - if(obj->p_t32a.p_instance == NULL) - return; - - // Enable clock for GPIO port. - TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET)); - - // Set pin function as PWM - pinmap_pinout(pin, PinMap_PWM); - - // Default to 20ms, 0% duty cycle - pwmout_period_ms(obj, 20); -} - -void pwmout_free(pwmout_t *obj) -{ - // Stop PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - obj->trailing_timing = TXZ_DISABLE; - obj->leading_timing = TXZ_DISABLE; - obj->p_t32a.p_instance = NULL; -} - -void pwmout_write(pwmout_t *obj, float value) -{ - // Stop PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - - if (value <= 0.0f) { - value = TXZ_DISABLE; - } else if (value >= 1.0f) { - value = TXZ_ENABLE; - } - - // Store the new leading_timing value - obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); - - // Setting T32A_RGA0 register - obj->p_t32a.p_instance->RGC0 = obj->leading_timing; - - // Start PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -float pwmout_read(pwmout_t *obj) -{ - float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; - return duty_cycle; -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, (ms * 1000)); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t *obj, int us) -{ - uint32_t prscl = 0; - float duty_cycle = 0; - float seconds = (float)((us) / 1000000.0f); - - obj->period = seconds; - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); - prscl = T32A_PRSCLx_32; - obj->trailing_timing = (us * CALCULATE_RGC1_VAL); - obj->leading_timing = ((obj->trailing_timing)- (obj->trailing_timing * duty_cycle)); - - obj->p_t32a.p_instance->MOD = T32A_MODE_32; - obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); - obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | - T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); - obj->p_t32a.p_instance->RGC0 = obj->leading_timing; - obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; - obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; - obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, (ms * 1000)); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c deleted file mode 100644 index 099a7cf7926..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c +++ /dev/null @@ -1,420 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_error.h" -#include "serial_api.h" -#include "pinmap.h" - -#define UART_NUM 8 -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) -#define FUART_ENABLE_RX ((uint32_t)0x00000200) -#define FUART_ENABLE_TX ((uint32_t)0x00000100) -#define BAUDRATE_DEFAULT (9600) -#define CLR_REGISTER (0x00) - -static const PinMap PinMap_UART_TX[] = { - {PE3, SERIAL_0, PIN_DATA(7, 1)}, - {PH1, SERIAL_1, PIN_DATA(3, 1)}, - {PG1, SERIAL_2, PIN_DATA(3, 1)}, - {PU7, SERIAL_3, PIN_DATA(7, 1)}, - {PU0, SERIAL_4, PIN_DATA(7, 1)}, - {PJ1, SERIAL_5, PIN_DATA(3, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PE2, SERIAL_0, PIN_DATA(7, 0)}, - {PH0, SERIAL_1, PIN_DATA(3, 0)}, - {PG0, SERIAL_2, PIN_DATA(3, 0)}, - {PU6, SERIAL_3, PIN_DATA(7, 0)}, - {PU1, SERIAL_4, PIN_DATA(7, 0)}, - {PJ0, SERIAL_5, PIN_DATA(3, 0)}, - {NC, NC, 0} -}; - -static int serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void uart_swreset(TSB_UART_TypeDef *UARTx); -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - obj->mode = 0; - cg_t paramCG; - paramCG.p_instance = TSB_CG; - uart_clock_t prescal = {0}; - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - // Initialize UART instance - switch (uart_name) { - case SERIAL_0: - obj->UARTx = TSB_UART0; - //Enable clock for UART0 and Port E - TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE; - break; - case SERIAL_1: - obj->UARTx = TSB_UART1; - //Enable clock for UART1 and Port H - TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB09 = TXZ_ENABLE; - break; - case SERIAL_2: - obj->UARTx = TSB_UART2; - //Enable clock for UART2 and Port G - TSB_CG_FSYSMENA_IPMENA25 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - break; - case SERIAL_3: - obj->UARTx = TSB_UART3; - //Enable clock for UART3 and Port U - TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; - break; - case SERIAL_4: - obj->UARTx = TSB_UART4; - //Enable clock for UART4 and Port U - TSB_CG_FSYSMENA_IPMENA27 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; - break; - case SERIAL_5: - obj->UARTx = TSB_UART5; - //Enable clock for UART5 and Port J - TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - break; - default: - break; - } - //Set alternate function - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC && rx != NC) { - obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->mode = UART_ENABLE_RX; - } - } - } - //software reset - uart_swreset(obj->UARTx); - //mbed default configurations - obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit - prescal.prsel = UART_PLESCALER_1; - uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); - obj->UARTx->BRD |=((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); - obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO - obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. - obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = CLR_REGISTER; - obj->UARTx->CR0 = CLR_REGISTER; - obj->UARTx->CR1 = CLR_REGISTER; - obj->UARTx = CLR_REGISTER; - uart_swreset(obj->UARTx); - obj->index = (uint32_t)NC; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - cg_t paramCG; - paramCG.p_instance = TSB_CG; - uart_clock_t prescal; - prescal.prsel = UART_PLESCALER_1; - uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); - obj->UARTx->BRD = CLR_REGISTER; //clear BRD register - obj->UARTx->BRD |=((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - uint32_t parity_check = 0; - uint32_t data_length = 0; - uint32_t tmp = 0; - uint32_t sblen = 0; - - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - parity_check = ((parity == ParityOdd) ? 1 :((parity == ParityEven) ? 3 : 0)); - data_length = (data_bits == 8 ? 1 :((data_bits == 7) ? 0 : 2)); - sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits - tmp = ((sblen << 4) |(parity_check << 2) | data_length); - obj->UARTx->CR0 = tmp; -} - -// INTERRUPT HANDLING -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART3RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); -} - -void INTUART3TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); -} - -void INTUART4RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); -} - -void INTUART4TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); -} - -void INTUART5RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); -} - -void INTUART5TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - case SERIAL_3: - if (irq == RxIrq) { - irq_n = INTUART3RX_IRQn; - } else { - irq_n = INTUART3TX_IRQn; - } - break; - case SERIAL_4: - if (irq == RxIrq) { - irq_n = INTUART4RX_IRQn; - } else { - irq_n = INTUART4TX_IRQn; - } - break; - case SERIAL_5: - if (irq == RxIrq) { - irq_n = INTUART5RX_IRQn; - } else { - irq_n = INTUART5TX_IRQn; - } - break; - default: - break; - } - - NVIC_ClearPendingIRQ(irq_n); - - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - //Read Data Register - data = (obj->UARTx->DR & 0xFFU); - obj->UARTx->SR |= (1U << 6); // clear RXEND flag - - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - // Do nothing - } - //Write Data Register - obj->UARTx->DR = (c & 0xFF); - while((obj->UARTx->SR & (1U << 14)) == 0) { - } - obj->UARTx->SR |= (1U << 14); // clear TXEND flag -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x000F) != 0) { - ret = 1; - } - - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x8000) == 0) { - ret = 1; - } - - return ret; -} - -// Pause transmission -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -// Switch to normal transmission -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -static void uart_swreset(TSB_UART_TypeDef *UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c b/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c deleted file mode 100644 index 565a00253f3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" - -// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16 -#define CG_WUODR_INT_5MS ((uint16_t)0x0C34) -#define CG_STBY_MODE_IDLE 0x0 -#define CG_STBY_MODE_STOP1 0x1 -#define EXTERNEL_OSC_MASK 0xFFFFFFF1 -#define SIWDT_DISABLE 0xB1 -#define WUPT_LOWER_MASK 0x000F -#define WUPT_UPPER_MASK 0xFFF0 - -static void external_losc_enable(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - - // Enter idle mode - __DSB(); - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t wupt_lower = 0U; - uint32_t wupt_upper = 0U; - uint32_t tmp = 0U; - - TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; - - TSB_SIWD0->EN = TXZ_DISABLE; - TSB_SIWD0->CR = SIWDT_DISABLE; - - - while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { - // Flash wait - } - - while (TSB_CG_WUPHCR_WUEF) { - // Wait for end of Warming-up for IHOSC1 - } - - TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; - wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); - wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); - TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; - - - while (TSB_CG_PLL0SEL_PLL0ST) { - // Wait for PLL status of fsys until off state(fosc=0) - } - - // Stop PLL of fsys - TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; - TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; - TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; - - while (TSB_CG_OSCCR_OSCF) { - // Wait for fosc status until IHOSC1 = 0 - } - - tmp = TSB_CG->OSCCR; - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - - - // Enter stop1 mode - __DSB(); - __WFI(); - - // Switch over from IHOSC to EHOSC - // After coming out off sleep mode, Restore the clock setting to EHOSC. - external_losc_enable(); -} - -static void external_losc_enable(void) -{ - uint32_t wupt_lower = 0U; - uint32_t wupt_upper = 0U; - - // Enable high-speed oscillator - TSB_CG->OSCCR |= (TXZ_ENABLE << 1); - - // Select internal(fIHOSC) as warm-up clock - wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); - wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); - TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); - - // Start warm-up - TSB_CG->WUPHCR |= TXZ_ENABLE; - - // Wait until EHOSC become stable - while ((TSB_CG->WUPHCR & 0x0002)) { - // Do nothing - } - - // Set fosc source - TSB_CG->OSCCR |= (1 << 8); - - // Wait for to become "1" - while (!((TSB_CG->OSCCR & 0x200)>> 9)) { - // Do nothing... - } - - // Stop IHOSC - TSB_CG->OSCCR &= ~TXZ_ENABLE; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c deleted file mode 100644 index 49292988401..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c +++ /dev/null @@ -1,341 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "spi_api.h" -#include "mbed_error.h" -#include "txz_tspi.h" -#include "pinmap.h" - -#define TIMEOUT (1000) -#define BAUDRATE_1MHZ_BRS (0xA) -#define BAUDRATE_1MHZ_BRCK (0x30) - -static const PinMap PinMap_SPI_SCLK[] = { - {PA1, SPI_0, PIN_DATA(7, 1)}, - {PL1, SPI_1, PIN_DATA(7, 1)}, - {PA6, SPI_2, PIN_DATA(7, 1)}, - {PK6, SPI_3, PIN_DATA(4, 1)}, - {PD1, SPI_4, PIN_DATA(4, 1)}, - {PM2, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PA3, SPI_0, PIN_DATA(7, 1)}, - {PL3, SPI_1, PIN_DATA(7, 1)}, - {PA4, SPI_2, PIN_DATA(7, 1)}, - {PK4, SPI_3, PIN_DATA(4, 1)}, - {PD3, SPI_4, PIN_DATA(4, 1)}, - {PM0, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA2, SPI_0, PIN_DATA(7, 0)}, - {PL2, SPI_1, PIN_DATA(7, 0)}, - {PA5, SPI_2, PIN_DATA(7, 0)}, - {PK5, SPI_3, PIN_DATA(4, 0)}, - {PD2, SPI_4, PIN_DATA(4, 0)}, - {PM1, SPI_5, PIN_DATA(6, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA0, SPI_0, PIN_DATA(7, 1)}, - {PL0, SPI_1, PIN_DATA(7, 1)}, - {PA7, SPI_2, PIN_DATA(7, 1)}, - {PK7, SPI_3, PIN_DATA(4, 1)}, - {PD0, SPI_4, PIN_DATA(4, 1)}, - {PM3, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk); - obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->module!= NC); - - // Identify SPI module to use - switch ((int)obj->module) { - case SPI_0: - obj->p_obj.p_instance = TSB_TSPI0; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; - break; - case SPI_1: - obj->p_obj.p_instance = TSB_TSPI1; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE; - break; - case SPI_2: - obj->p_obj.p_instance = TSB_TSPI2; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; - break; - case SPI_3: - obj->p_obj.p_instance = TSB_TSPI3; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE; - break; - case SPI_4: - obj->p_obj.p_instance = TSB_TSPI4; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE; - break; - case SPI_5: - obj->p_obj.p_instance = TSB_TSPI6; - //Enable clock for particular Port and SPI - TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; - break; - default: - obj->p_obj.p_instance = NULL; - obj->module = (SPIName)NC; - error("Cannot found SPI module corresponding with input pins."); - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - // Default configurations 8 bit, 1Mhz frequency - //Control 1 configurations - obj->p_obj.init.id = (uint32_t)obj->module; - obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled - obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication - obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode - obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation - obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) - obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid - obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time contineously - - //Control 2 configurations - obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; - obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low - obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_SET; - obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level - obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level - obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; - obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; - obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; - obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; - obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; - - //Control 3 configurations - obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear - obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear - - //baudrate settings - 1Mhz default - obj->p_obj.init.brd.brck = BAUDRATE_1MHZ_BRCK; - obj->p_obj.init.brd.brs = BAUDRATE_1MHZ_BRS; - - //Format Control 0 settings - obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first - obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; - obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; - - //Special control on polarity of signal and generation timing - obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; - obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; - obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; - obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; - - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; - obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; - obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; - - //Format Control 1 settings tspi_fmtr1_t - obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; - obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; - - obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; - - //initialize SPI - tspi_init(&obj->p_obj); -} - -void spi_free(spi_t *obj) -{ - tspi_deinit(&obj->p_obj); - obj->module = (SPIName)NC; -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - MBED_ASSERT((slave == 0U)); // 0: master mode, 1: slave mode - MBED_ASSERT((bits >= 8) && (bits <= 32)); - - obj->bits = bits; - obj->p_obj.init.fmr0.fl = (bits << 24); - - if((mode >> 1) & 0x1) { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; - } else { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - } - - if(mode & 0x1) { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; - } else { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - } - - tspi_init(&obj->p_obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - SystemCoreClockUpdate(); - uint8_t brs = 0, brck = 0; - uint16_t prsck = 1; - uint64_t fscl = 0, tmp_fscl = 0; - uint64_t fx = 0; - uint64_t tmpvar = SystemCoreClock / 2; - - for (prsck = 1; prsck <= 512; prsck *= 2) { - fx = ((uint64_t)tmpvar / prsck); - for (brs = 1; brs <= 16; brs++) { - fscl = fx /brs; - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - obj->p_obj.init.brd.brck = (brck << 4); - if(brs == 16) { - obj->p_obj.init.brd.brs = 0; - } else { - obj->p_obj.init.brd.brs = brs; - } - } - } - brck ++; - } - - tspi_init(&obj->p_obj); -} - -int spi_master_write(spi_t *obj, int value) -{ - uint8_t ret_value = 0; - - tspi_transmit_t send_obj; - tspi_receive_t rec_obj; - - // Transmit data - send_obj.tx8.p_data = (uint8_t *)&value; - send_obj.tx8.num = 1; - tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); - - // Read received data - rec_obj.rx8.p_data = &ret_value; - rec_obj.rx8.num = 1; - tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); - - return ret_value; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - int ret = 1; - uint32_t status; - tspi_get_status(&obj->p_obj, &status); - if((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { - ret = 0; - } - - return ret; -} - -uint8_t spi_get_module(spi_t *obj) -{ - return (uint8_t)(obj->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c b/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c deleted file mode 100644 index 38de88f50db..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "TMPM4G9.h" -#include "txz_t32a.h" - -#define CLR_TIMER_INT_FLAG (uint8_t)0x41 - -static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 2496094, - 32 - }; - return &info; -} - -// initialize us_ticker -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = 1; - - // Enable clock for T32A0 - TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; - - // T32A ch0 TimerC Reg Match/Over Flow/Under Flow - TSB_IB->IMC006 = TXZ_ENABLE; - - // Configure Timer T32A0 - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); -} - -uint32_t us_ticker_read(void) -{ - uint32_t ret_val = 0; - - if (!us_ticker_inited) { - us_ticker_init(); - } - - ret_val = (TSB_T32A0->TMRC); - return ret_val; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp ; - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts in NVIC - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_free(void) -{ - TSB_T32A0->RUNC = T32A_RUN_DISABLE; - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); - TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE; -} diff --git a/targets/TARGET_TT/mbed_rtx.h b/targets/TARGET_TT/mbed_rtx.h deleted file mode 100644 index 1f9bc5c3191..00000000000 --- a/targets/TARGET_TT/mbed_rtx.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - - -#if defined(TARGET_TT_M3HQ) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20010000UL) -#endif - -#endif - -#if defined(TARGET_TT_M4G9) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20030000UL) -#endif - - -#endif - -#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index b50531dc971..42a61119d91 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -14406,48 +14406,6 @@ "network-default-interface-type": "ETHERNET" } }, - "TT_M3HQ": { - "inherits": [ - "Target" - ], - "core": "Cortex-M3", - "is_disk_virtual": true, - "extra_labels": [ - "TT" - ], - "macros": [ - "__TT_M3HQ__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "USTICKER", - "ANALOGOUT", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "I2C", - "I2CSLAVE", - "STDIO_MESSAGES", - "MPU" - ], - "device_name": "TMPM3HQFDFG", - "detect_code": [ - "8012" - ], - "release_versions": [ - "5" - ] - }, "GD32_F450ZI": { "inherits": [ "GD32_Target" @@ -14531,50 +14489,6 @@ "5" ] }, - "TT_M4G9": { - "inherits": [ - "Target" - ], - "core": "Cortex-M4F", - "is_disk_virtual": true, - "extra_labels": [ - "TT" - ], - "macros": [ - "__TT_M4G9__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "ANALOGOUT", - "SERIAL", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SLEEP", - "SPI", - "STDIO_MESSAGES", - "FLASH", - "MPU" - ], - "device_name": "TMPM4G9F15FG", - "detect_code": [ - "8013" - ], - "release_versions": [ - "5" - ], - "bootloader_supported": true - }, "EP_AGORA": { "inherits": [ "MCU_NRF52840" From 32fab9bc0d7b74ddef5c31d1f3f881a750435dd9 Mon Sep 17 00:00:00 2001 From: MarceloSalazar Date: Tue, 7 Apr 2020 22:54:07 +0100 Subject: [PATCH 02/15] Remove Realtek targets --- .../TARGET_AMEBA/RTWInterface.cpp | 273 ---- .../TARGET_AMEBA/RTWInterface.h | 119 -- .../TARGET_MCU_RTL8195A/PeripheralPins.h | 54 - .../TARGET_RTL8195A/PeripheralNames.h | 42 - .../TARGET_RTL8195A/PeripheralPins.c | 182 --- .../TARGET_RTL8195A/PinNames.h | 238 --- .../TARGET_RTL8195A/PortNames.h | 38 - .../TARGET_MCU_RTL8195A/analogin_api.c | 211 --- .../TARGET_MCU_RTL8195A/analogin_ext.h | 31 - .../TARGET_MCU_RTL8195A/analogout_api.c | 197 --- .../TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h | 22 - .../lib_peripheral_mbed_arm.ar | Bin 300994 -> 0 bytes .../TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar | Bin 1172050 -> 0 bytes .../device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 78 - .../device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o | 648 -------- .../TOOLCHAIN_ARM_STD/rtl8195a_startup.S | 31 - .../lib_peripheral_mbed_gcc.a | Bin 980164 -> 0 bytes .../TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a | Bin 8317270 -> 0 bytes .../device/TOOLCHAIN_GCC_ARM/rtl8195a.ld | 232 --- .../device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h | 759 --------- .../TOOLCHAIN_GCC_ARM/rtl8195a_startup.S | 32 - .../TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a | Bin 392254 -> 0 bytes .../device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a | Bin 1308826 -> 0 bytes .../device/TOOLCHAIN_IAR/rtl8195a.icf | 216 --- .../device/TOOLCHAIN_IAR/rtl8195a_rom.h | 740 --------- .../device/TOOLCHAIN_IAR/rtl8195a_startup.S | 31 - .../TARGET_MCU_RTL8195A/device/cmsis.h | 26 - .../TARGET_MCU_RTL8195A/device/cmsis_nvic.h | 36 - .../TARGET_MCU_RTL8195A/device/diag.h | 850 ---------- .../device/platform_autoconf.h | 246 --- .../device/platform_opts.h | 599 ------- .../TARGET_MCU_RTL8195A/device/rand.h | 19 - .../TARGET_MCU_RTL8195A/device/rtl8195a_clk.h | 65 - .../device/rtl8195a_compiler.h | 64 - .../device/rtl8195a_crypto.h | 24 - .../device/rtl8195a_init.c | 387 ----- .../device/rtl8195a_misc.h | 32 - .../device/rtl8195a_platform.h | 27 - .../device/rtl8195a_trap.h | 80 - .../TARGET_MCU_RTL8195A/device/rtl_utility.h | 68 - .../TARGET_MCU_RTL8195A/device/strproc.h | 108 -- .../TARGET_MCU_RTL8195A/device/system_8195a.h | 77 - .../TARGET_MCU_RTL8195A/device/va_list.h | 40 - .../TARGET_MCU_RTL8195A/flash_api.c | 78 - .../TARGET_MCU_RTL8195A/flash_ext.c | 467 ------ .../TARGET_MCU_RTL8195A/flash_ext.h | 53 - .../TARGET_MCU_RTL8195A/gpio_api.c | 214 --- .../TARGET_MCU_RTL8195A/gpio_irq_api.c | 86 - .../TARGET_MCU_RTL8195A/i2c_api.c | 564 ------- .../TARGET_MCU_RTL8195A/log_uart_api.c | 502 ------ .../TARGET_MCU_RTL8195A/log_uart_api.h | 331 ---- .../TARGET_MCU_RTL8195A/objects.h | 214 --- .../TARGET_MCU_RTL8195A/ota_api.c | 176 --- .../TARGET_MCU_RTL8195A/ota_api.h | 83 - .../TARGET_MCU_RTL8195A/port_api.c | 219 --- .../TARGET_MCU_RTL8195A/pwmout_api.c | 133 -- .../TARGET_MCU_RTL8195A/rtc_api.c | 71 - .../TARGET_MCU_RTL8195A/serial_api.c | 541 ------- .../TARGET_MCU_RTL8195A/spi_api.c | 391 ----- .../TARGET_MCU_RTL8195A/spi_ex_api.h | 244 --- .../TARGET_MCU_RTL8195A/timer_api.c | 151 -- .../TARGET_MCU_RTL8195A/timer_api.h | 46 - .../TARGET_MCU_RTL8195A/trng_api.c | 77 - .../TARGET_MCU_RTL8195A/us_ticker.c | 126 -- .../TARGET_AMEBA/default_wifi_interface.cpp | 24 - .../TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp | 241 --- .../TARGET_Realtek/TARGET_AMEBA/rtw_emac.h | 164 -- .../sdk/common/api/platform/dlist.h | 279 ---- .../sdk/common/api/platform/platform_stdlib.h | 56 - .../api/platform/platform_stdlib_rtl8195a.h | 166 -- .../sdk/common/api/wifi/wifi_conf.h | 954 ----------- .../sdk/common/api/wifi/wifi_ind.h | 104 -- .../sdk/common/api/wifi/wifi_util.h | 94 -- .../drivers/wlan/realtek/include/autoconf.h | 702 --------- .../wlan/realtek/include/wifi_constants.h | 572 ------- .../wlan/realtek/include/wifi_structures.h | 266 ---- .../wlan/realtek/src/osdep/freertos/wrapper.h | 448 ------ .../wlan/realtek/src/osdep/lwip_intf.c | 279 ---- .../wlan/realtek/src/osdep/lwip_intf.h | 87 - .../drivers/wlan/realtek/src/osdep/skbuff.h | 72 - .../drivers/wlan/realtek/src/osdep/wireless.h | 1211 -------------- .../wlan/realtek/src/osdep/wlan_intf.h | 82 - .../sdk/os/cmsis_rtos/cmsis_rtos_service.c | 1231 --------------- .../sdk/os/cmsis_rtos/cmsis_rtos_service.h | 288 ---- .../TARGET_AMEBA/sdk/os/os_dep/device_lock.c | 64 - .../sdk/os/os_dep/include/device_lock.h | 27 - .../sdk/os/os_dep/include/osdep_service.h | 1404 ----------------- .../sdk/os/os_dep/include/tcm_heap.h | 66 - .../sdk/os/os_dep/osdep_service.c | 1331 ---------------- .../TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c | 370 ----- .../sdk/soc/realtek/8195a/fwlib/hal_adc.h | 343 ---- .../sdk/soc/realtek/8195a/fwlib/hal_api.h | 132 -- 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a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp deleted file mode 100644 index 30f589511c5..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp +++ /dev/null @@ -1,273 +0,0 @@ -/* Ameba implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed.h" -#include "rtos.h" - -#include "RTWInterface.h" -#include "mbed_interface.h" - -#include "rtw_emac.h" -#include "EMAC.h" -#include "wifi_constants.h" -#include "wifi_conf.h" - -#include "OnboardNetworkStack.h" -#include "EMACMemoryManager.h" -#include "osdep_service.h" - -typedef struct _wifi_scan_hdl { - _sema scan_sema; - nsapi_size_t ap_num; - nsapi_size_t scan_num; - WiFiAccessPoint *ap_details; -} wifi_scan_hdl; - -#define MAX_SCAN_TIMEOUT (15000) - -static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) -{ - wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data; - if (malloced_scan_result->scan_complete != RTW_TRUE) { - if (scan_handler->ap_details && scan_handler->scan_num > scan_handler->ap_num) { - nsapi_wifi_ap_t ap; - rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ - memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t)); - memcpy(ap.ssid, record->SSID.val, record->SSID.len); - memcpy(ap.bssid, record->BSSID.octet, 6); - switch (record->security) { - case RTW_SECURITY_OPEN: - ap.security = NSAPI_SECURITY_NONE; - break; - case RTW_SECURITY_WEP_PSK: - case RTW_SECURITY_WEP_SHARED: - ap.security = NSAPI_SECURITY_WEP; - break; - case RTW_SECURITY_WPA_TKIP_PSK: - case RTW_SECURITY_WPA_AES_PSK: - ap.security = NSAPI_SECURITY_WPA; - break; - case RTW_SECURITY_WPA2_AES_PSK: - case RTW_SECURITY_WPA2_TKIP_PSK: - case RTW_SECURITY_WPA2_MIXED_PSK: - ap.security = NSAPI_SECURITY_WPA2; - break; - case RTW_SECURITY_WPA_WPA2_MIXED: - ap.security = NSAPI_SECURITY_WPA_WPA2; - break; - default: - ap.security = NSAPI_SECURITY_UNKNOWN; - break; - } - ap.rssi = record->signal_strength; - ap.channel = record->channel; - scan_handler->ap_details[scan_handler->ap_num] = WiFiAccessPoint(ap); - } - scan_handler->ap_num++; - } else { - // scan done - rtw_up_sema(&scan_handler->scan_sema); - } - return RTW_SUCCESS; -} - -RTWInterface::RTWInterface(RTW_EMAC &get_rtw_emac, OnboardNetworkStack &get_rtw_obn_stack, bool debug) : - EMACInterface(get_rtw_emac, get_rtw_obn_stack), - rtw_emac(get_rtw_emac), - rtw_obn_stack(get_rtw_obn_stack) -{ - extern __u32 GlobalDebugEnable; - GlobalDebugEnable = debug?1:0; //Conditional statement: display debugging message - rtw_emac.power_up(); -} - -RTWInterface::~RTWInterface() -{ - rtw_emac.wlan_emac_link_change(false); - EMACInterface::disconnect(); -} - -/* - * we may call connect multiple times - */ -nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) -{ - _security = security; - // Check if ssid is empty - if (!ssid) { - return NSAPI_ERROR_PARAMETER; - } - - // Check if ssid is too long - int ssid_length = strlen(ssid); - - if (ssid_length > 0 && ssid_length <= SSID_MAX_LENGTH) { - memset(_ssid, 0, sizeof(_ssid)); - strncpy(_ssid, ssid, sizeof(_ssid)); - } else { - return NSAPI_ERROR_PARAMETER; - } - - // Check if it is an open access point - if (_security != NSAPI_SECURITY_NONE) { - // Check if passphase is empty - if (!pass) { - return NSAPI_ERROR_PARAMETER; - } - // Check if passphase too long - if (strlen(pass) >= PASSPHRASE_MIN_LENGTH && strlen(pass) <= PASSPHRASE_MAX_LENGTH ) { - memset(_pass, 0, sizeof(_pass)); - strncpy(_pass, pass, sizeof(_pass)); - } else { - return NSAPI_ERROR_PARAMETER; - } - } else { // It is an open access point - memset(_pass, 0, sizeof(_pass)); - } - return NSAPI_ERROR_OK; -} - -nsapi_error_t RTWInterface::connect() -{ - int ret; - rtw_security_t sec; - - // Check if the ssid is empty - if (strlen(_ssid) == 0) { - return NSAPI_ERROR_NO_SSID; - } - // Check the security is empty and the passphase is valid - if ((_security != NSAPI_SECURITY_NONE) && (strlen(_pass) < PASSPHRASE_MIN_LENGTH)) { - return NSAPI_ERROR_PARAMETER; - } - // Based on security type set, adapt to Ameba SDK format - switch (_security) { - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - sec = RTW_SECURITY_WPA_WPA2_MIXED; - break; - case NSAPI_SECURITY_WEP: - sec = RTW_SECURITY_WEP_PSK; - break; - case NSAPI_SECURITY_NONE: - sec = RTW_SECURITY_OPEN; - break; - default: - return NSAPI_ERROR_PARAMETER; - } - // Check if channel number is valid - if (_channel > 0 && _channel < 14) { - uint8_t pscan_config = PSCAN_ENABLE; - wifi_set_pscan_chan(&_channel, &pscan_config, 1); // Indicate which channel will be scanned - } - ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); // Join a WiFi network - // Check if the WiFi is connected. Return RTW_SUCCESS for succeful; Return RTW_ERROR for error - if (ret != RTW_SUCCESS) { - if(_ssid == "NULL"){ - return NSAPI_ERROR_PARAMETER; - } - else{ - printf("failed: %d\r\n", ret); - return NSAPI_ERROR_NO_CONNECTION; - } - } - rtw_emac.wlan_emac_link_change(true); - ret = EMACInterface::connect(); - return ret; -} - -nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count) -{ - static wifi_scan_hdl scan_handler; - scan_handler.ap_num = 0; - if (!scan_handler.scan_sema) { - rtw_init_sema(&scan_handler.scan_sema, 0); - } - scan_handler.scan_num = count; - scan_handler.ap_details = res; - if (wifi_scan_networks(scan_result_handler, (void *)&scan_handler) != RTW_SUCCESS) { - printf("wifi scan failed\n\r"); - return NSAPI_ERROR_DEVICE_ERROR; - } - if (rtw_down_timeout_sema( &scan_handler.scan_sema, MAX_SCAN_TIMEOUT ) == RTW_FALSE) { - printf("wifi scan timeout\r\n"); - return NSAPI_ERROR_DEVICE_ERROR; - } - if (count <= 0 || count > scan_handler.ap_num) { - count = scan_handler.ap_num; - } - return count; -} - -nsapi_error_t RTWInterface::set_channel(uint8_t channel) -{ - _channel = channel; - return NSAPI_ERROR_UNSUPPORTED; -} - -int8_t RTWInterface::get_rssi() -{ - int rssi = 0; - if (wifi_get_rssi(&rssi) == 0) { - return (int8_t)rssi; - } - return NSAPI_ERROR_OK; -} - -nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass, - nsapi_security_t security, uint8_t channel) -{ - set_channel(channel); - int err = set_credentials(ssid, pass, security); - if(err) { - return err; - } - return connect(); -} - -nsapi_error_t RTWInterface::disconnect() -{ - char essid[33]; - - rtw_emac.wlan_emac_link_change(false); - - EMACInterface::disconnect(); - - if (wifi_is_connected_to_ap() != RTW_SUCCESS) { - return NSAPI_ERROR_NO_CONNECTION; - } - if (wifi_disconnect()<0) { - return NSAPI_ERROR_DEVICE_ERROR; - } - while(1) { - if (wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) < 0) { - break; - } - } - return NSAPI_ERROR_OK; -} - -int RTWInterface::is_connected() -{ - return !wifi_is_connected_to_ap(); -} - -NetworkStack *RTWInterface::get_stack() -{ - return &rtw_obn_stack; -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h deleted file mode 100644 index 06a9328bdcd..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h +++ /dev/null @@ -1,119 +0,0 @@ -/* Ameba implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef RTW_INTERFACE_H -#define RTW_INTERFACE_H - -#include "netsocket/NetworkInterface.h" -#include "netsocket/WiFiInterface.h" -#include "nsapi.h" -#include "rtos.h" -#include "netif.h" -#include "rtw_emac.h" -#include "OnboardNetworkStack.h" -#include "EMACInterface.h" -#include "LWIPStack.h" - -// Forward declaration -class NetworkStack; - -/** Realtek Wlan (RTW) interface class - * Implementation of the NetworkStack for Ameba - */ -class RTWInterface: public WiFiInterface, public EMACInterface -{ -public: - /** RTWWlanInterface lifetime - */ - RTWInterface( - RTW_EMAC &rtw_emac = RTW_EMAC::get_instance(), - OnboardNetworkStack &rtw_lwip_stack = OnboardNetworkStack::get_default_instance(), bool debug=false); - - ~RTWInterface(); - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Start the interface - * - * Attempts to connect to a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t connect(const char *ssid, const char *pass, - nsapi_security_t security = NSAPI_SECURITY_NONE, - uint8_t channel = 0); - - /** Start the interface - * @return 0 on success, negative on failure - */ - virtual nsapi_error_t connect(); - - /** Stop the interface - * @return 0 on success, negative on failure - */ - virtual nsapi_error_t disconnect(); - virtual int is_connected(); - - /** Scan for available networks - * - * The scan will - * If the network interface is set to non-blocking mode, scan will attempt to scan - * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback - * is attached, the callback will be called when the operation has completed. - * @param ap Pointer to allocated array to store discovered AP - * @param count Size of allocated @a res array, or 0 to only count available AP - * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0) - * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error - * see @a nsapi_error - */ - virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count); - - virtual nsapi_error_t set_channel(uint8_t channel); - virtual int8_t get_rssi(); - - RTW_EMAC &get_emac() const { return rtw_emac; } - - virtual RTWInterface *rtwInterface() { return this; } - -protected: - /** Provide access to the underlying stack - * - * @return The underlying network stack - */ - virtual NetworkStack *get_stack(); - RTW_EMAC &rtw_emac; - OnboardNetworkStack &rtw_obn_stack; - char _ssid[256]; - char _pass[256]; - nsapi_security_t _security; - uint8_t _channel; - static const int SSID_MAX_LENGTH = 32; //The longest ssid - static const int PASSPHRASE_MAX_LENGTH = 63; //The longest passphrase - static const int PASSPHRASE_MIN_LENGTH = 8; // The shortest passphrase -}; -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h deleted file mode 100644 index 5231e92aa7c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "cmsis.h" -#include "pinmap.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// for spi_api.c -extern const PinMap PinMap_SSI_MOSI[]; -extern const PinMap PinMap_SSI_MISO[]; -extern const PinMap PinMap_SSI_SCLK[]; -extern const PinMap PinMap_SSI_SSEL[]; - -// for serial_api.c -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -// for pwmout_api.c -extern const PinMap PinMap_PWM[]; - -// for i2c_api.c -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -// for analogin_api.c -extern const PinMap PinMap_ADC[]; - -// for analogout_api.c -extern const PinMap PinMap_DAC[]; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h deleted file mode 100644 index aba42a11380..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UART_3 3 -#define STDIO_UART_TX PB_0 -#define STDIO_UART_RX PB_1 -#define STDIO_UART UART_3 - - -typedef enum { - DAC_0 = 0, - DAC_1 -} DACName; - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c deleted file mode 100644 index 2e1890ea32c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c +++ /dev/null @@ -1,182 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -// for spi_api.c -const PinMap PinMap_SSI_MOSI[] = { - {PE_2, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_2, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_1, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_6, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_6, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_2, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_6, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_2, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SSI_MISO[] = { - {PE_3, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_3, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_0, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_7, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_7, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_3, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_7, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_3, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_SSI_SCLK[] = { - {PC_1, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_SSI_SSEL[] = { - {PE_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_4, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PC_0, RTL_PIN_PERI(SPI0, 0, S0), /* Unused */ 0}, - {PA_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - - {NC, NC, 0} -}; - -// for serial_api.c -const PinMap PinMap_UART_TX[] = { - {PC_3, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_0, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_7, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_3, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_4, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_5, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_4, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_9, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_7, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_0, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PC_0, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_3, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_6, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_0, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_7, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_4, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_0, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_6, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_4, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_1, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; - -// for pwmout_api.c -const PinMap PinMap_PWM[] = { - {PB_4, RTL_PIN_PERI(PWM0, 0, S0), RTL_PIN_FUNC(PWM0, S0)}, - {PB_5, RTL_PIN_PERI(PWM1, 1, S0), RTL_PIN_FUNC(PWM1, S0)}, - {PB_6, RTL_PIN_PERI(PWM2, 2, S0), RTL_PIN_FUNC(PWM2, S0)}, - {PB_7, RTL_PIN_PERI(PWM3, 3, S0), RTL_PIN_FUNC(PWM3, S0)}, - - {PC_0, RTL_PIN_PERI(PWM0, 0, S1), RTL_PIN_FUNC(PWM0, S1)}, - {PC_1, RTL_PIN_PERI(PWM1, 1, S1), RTL_PIN_FUNC(PWM1, S1)}, - {PC_2, RTL_PIN_PERI(PWM2, 2, S1), RTL_PIN_FUNC(PWM2, S1)}, - {PC_3, RTL_PIN_PERI(PWM3, 3, S1), RTL_PIN_FUNC(PWM3, S1)}, - - {PD_3, RTL_PIN_PERI(PWM0, 0, S2), RTL_PIN_FUNC(PWM0, S2)}, - {PD_4, RTL_PIN_PERI(PWM1, 1, S2), RTL_PIN_FUNC(PWM1, S2)}, - {PD_5, RTL_PIN_PERI(PWM2, 2, S2), RTL_PIN_FUNC(PWM2, S2)}, - {PD_6, RTL_PIN_PERI(PWM3, 3, S2), RTL_PIN_FUNC(PWM3, S2)}, - - {PE_0, RTL_PIN_PERI(PWM0, 0, S3), RTL_PIN_FUNC(PWM0, S3)}, - {PE_1, RTL_PIN_PERI(PWM1, 1, S3), RTL_PIN_FUNC(PWM1, S3)}, - {PE_2, RTL_PIN_PERI(PWM2, 2, S3), RTL_PIN_FUNC(PWM2, S3)}, - {PE_3, RTL_PIN_PERI(PWM3, 3, S3), RTL_PIN_FUNC(PWM3, S3)}, - - {NC, NC, 0} -}; - -// for i2c_api.c -const PinMap PinMap_I2C_SDA[] = { - {PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_ADC[] = { - {A1, /* Unused */ 0, /* Unused */ 0}, - {A2, /* Unused */ 0, /* Unused */ 0}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_DAC[] = { - {DA_0, /* Unused */ 0, /* Unused */ 0}, - {DA_1, /* Unused */ 0, /* Unused */ 0}, - - {NC, NC, 0} -}; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h deleted file mode 100644 index 60895420ed9..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h +++ /dev/null @@ -1,238 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _PINNAMES_H_ -#define _PINNAMES_H_ - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PORT_A = 0, - PORT_B = 1, - PORT_C = 2, - PORT_D = 3, - PORT_E = 4, - PORT_F = 5, - PORT_G = 6, - PORT_H = 7, - PORT_I = 8, - PORT_J = 9, - PORT_K = 10, - - PORT_V = 11, - PORT_U = 12, - PORT_MAX -} GPIO_PORT; - -#define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL))) -#define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL))) -#define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F)) -#define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F)) - -typedef enum { - PIN_INPUT=0, - PIN_OUTPUT -} PinDirection; - - -typedef enum { - PA_0 = (PORT_A<<4|0), - PA_1 = (PORT_A<<4|1), - PA_2 = (PORT_A<<4|2), - PA_3 = (PORT_A<<4|3), - PA_4 = (PORT_A<<4|4), - PA_5 = (PORT_A<<4|5), - PA_6 = (PORT_A<<4|6), - PA_7 = (PORT_A<<4|7), - - PB_0 = (PORT_B<<4|0), - PB_1 = (PORT_B<<4|1), - PB_2 = (PORT_B<<4|2), - PB_3 = (PORT_B<<4|3), - PB_4 = (PORT_B<<4|4), - PB_5 = (PORT_B<<4|5), - PB_6 = (PORT_B<<4|6), - PB_7 = (PORT_B<<4|7), - - PC_0 = (PORT_C<<4|0), - PC_1 = (PORT_C<<4|1), - PC_2 = (PORT_C<<4|2), - PC_3 = (PORT_C<<4|3), - PC_4 = (PORT_C<<4|4), - PC_5 = (PORT_C<<4|5), - PC_6 = (PORT_C<<4|6), - PC_7 = (PORT_C<<4|7), - PC_8 = (PORT_C<<4|8), - PC_9 = (PORT_C<<4|9), - - PD_0 = (PORT_D<<4|0), - PD_1 = (PORT_D<<4|1), - PD_2 = (PORT_D<<4|2), - PD_3 = (PORT_D<<4|3), - PD_4 = (PORT_D<<4|4), - PD_5 = (PORT_D<<4|5), - PD_6 = (PORT_D<<4|6), - PD_7 = (PORT_D<<4|7), - PD_8 = (PORT_D<<4|8), - PD_9 = (PORT_D<<4|9), - - PE_0 = (PORT_E<<4|0), - PE_1 = (PORT_E<<4|1), - PE_2 = (PORT_E<<4|2), - PE_3 = (PORT_E<<4|3), - PE_4 = (PORT_E<<4|4), - PE_5 = (PORT_E<<4|5), - PE_6 = (PORT_E<<4|6), - PE_7 = (PORT_E<<4|7), - PE_8 = (PORT_E<<4|8), - PE_9 = (PORT_E<<4|9), - PE_A = (PORT_E<<4|10), - - PF_0 = (PORT_F<<4|0), - PF_1 = (PORT_F<<4|1), - PF_2 = (PORT_F<<4|2), - PF_3 = (PORT_F<<4|3), - PF_4 = (PORT_F<<4|4), - PF_5 = (PORT_F<<4|5), - /* unavailable pins */ -// PF_6 = (PORT_F<<4|6), -// PF_7 = (PORT_F<<4|7), - - PG_0 = (PORT_G<<4|0), - PG_1 = (PORT_G<<4|1), - PG_2 = (PORT_G<<4|2), - PG_3 = (PORT_G<<4|3), - PG_4 = (PORT_G<<4|4), - PG_5 = (PORT_G<<4|5), - PG_6 = (PORT_G<<4|6), - PG_7 = (PORT_G<<4|7), - - PH_0 = (PORT_H<<4|0), - PH_1 = (PORT_H<<4|1), - PH_2 = (PORT_H<<4|2), - PH_3 = (PORT_H<<4|3), - PH_4 = (PORT_H<<4|4), - PH_5 = (PORT_H<<4|5), - PH_6 = (PORT_H<<4|6), - PH_7 = (PORT_H<<4|7), - - PI_0 = (PORT_I<<4|0), - PI_1 = (PORT_I<<4|1), - PI_2 = (PORT_I<<4|2), - PI_3 = (PORT_I<<4|3), - PI_4 = (PORT_I<<4|4), - PI_5 = (PORT_I<<4|5), - PI_6 = (PORT_I<<4|6), - PI_7 = (PORT_I<<4|7), - - PJ_0 = (PORT_J<<4|0), - PJ_1 = (PORT_J<<4|1), - PJ_2 = (PORT_J<<4|2), - PJ_3 = (PORT_J<<4|3), - PJ_4 = (PORT_J<<4|4), - PJ_5 = (PORT_J<<4|5), - PJ_6 = (PORT_J<<4|6), - /* unavailable pins */ -// PJ_7 = (PORT_J<<4|7), - - PK_0 = (PORT_K<<4|0), - PK_1 = (PORT_K<<4|1), - PK_2 = (PORT_K<<4|2), - PK_3 = (PORT_K<<4|3), - PK_4 = (PORT_K<<4|4), - PK_5 = (PORT_K<<4|5), - PK_6 = (PORT_K<<4|6), - /* unavailable pins */ - // PK_7 = (PORT_K<<4|7), - - AD_1 = (PORT_V<<4|1), - AD_2 = (PORT_V<<4|2), - AD_3 = (PORT_V<<4|3), - - DA_0 = (PORT_U<<4|0), - DA_1 = (PORT_U<<4|1), - - // Not connected - NC = (int)0xFFFFFFFF, - - // Generic signals namings - /* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/ - LED1 = PB_4, - LED2 = PB_5, - LED3 = PB_6, - LED4 = PB_7, - SERIAL_TX = PA_7, - SERIAL_RX = PA_6, - USBTX = PB_0, - USBRX = PB_1, - I2C_SCL = PC_5, - I2C_SDA = PC_4, - SPI_MOSI = PC_2, - SPI_MISO = PC_3, - SPI_SCK = PC_1, - SPI_CS = PC_0, - PWM_OUT = PD_4, - - // Arduino connector namings - - A0 = AD_2,//A0 and A1 are connected - A1 = AD_2, - A2 = AD_3, - A3 = NC, - A4 = NC, - A5 = NC, - - D0 = PA_6, - D1 = PA_7, - D2 = PA_5, - D3 = PD_4, - D4 = PD_5, - D5 = PA_4, - D6 = PA_3, - D7 = PA_2, - D8 = PB_4, - D9 = PB_5, - D10 = PC_0, - D11 = PC_2, - D12 = PC_3, - D13 = PC_1, - D14 = PB_3, - D15 = PB_2, - D16 = PA_1, - D17 = PA_0, - D18 = PE_5 - -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - OpenDrain = 3, - PullDefault = PullNone -} PinMode; - -#define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF) -#define PIN_NUM(pin) ((uint32_t)(pin) & 0xF) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h deleted file mode 100644 index 29a53243712..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4, - PortF = 5, - PortG = 6, - PortH = 7, - PortI = 8 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c deleted file mode 100644 index 13ac03054c3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c +++ /dev/null @@ -1,211 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "PinNames.h" -#include "hal_adc.h" -#include "analogin_api.h" -#include "PeripheralPins.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -#if CONFIG_ADC_EN -#include "pinmap.h" - - -extern u32 ConfigDebugErr; -extern u32 ConfigDebuginfo; - - -void analogin_init (analogin_t *obj, PinName pin) -{ - uint32_t adc_idx; - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - HAL_ADC_INIT_DAT HalADCInitDataTmp; - PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp; - /* To backup user config first */ - -#if defined(CONFIG_MBED_ENABLED) - _memset(&(obj->HalADCInitData), 0, sizeof(HAL_ADC_INIT_DAT)); -#endif - - _memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); - _memset(obj, 0x00, sizeof(analogin_t)); - - ConfigDebugErr &= (~(_DBG_ADC_|_DBG_GDMA_)); - ConfigDebugInfo&= (~(_DBG_ADC_|_DBG_GDMA_)); - - adc_idx = pin & 0x0F; - - /* Get I2C device handler */ - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)&(obj->SalADCUserCBAdpt); - - /*To assign the rest pointers*/ - pSalADCMngtAdpt->pSalHndPriv = &(obj->SalADCHndPriv); - pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv); - - /* To assign the default (ROM) HAL OP initialization function */ - pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit; - - /* To assign the default (ROM) HAL GDMA OP initialization function */ - pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit; - - /* To assign the default (ROM) SAL interrupt function */ - pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle; - - /* To assign the default (ROM) SAL DMA TX interrupt function */ - pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle; - - /* To backup user config first */ - //_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); - - pSalADCMngtAdpt->pHalInitDat = &(obj->HalADCInitData); - pSalADCMngtAdpt->pHalOp = &(obj->HalADCOp); - pSalADCMngtAdpt->pIrqHnd = &(obj->ADCIrqHandleDat); - pSalADCMngtAdpt->pHalGdmaAdp = &(obj->HalADCGdmaAdpt); - pSalADCMngtAdpt->pHalGdmaOp = &(obj->HalADCGdmaOp); - pSalADCMngtAdpt->pIrqGdmaHnd = &(obj->ADCGdmaIrqHandleDat); - pSalADCMngtAdpt->pUserCB = &(obj->SalADCUserCB); - - /* Assign the private SAL handle to public SAL handle */ - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - - /* Assign the internal HAL initial data pointer to the SAL handle */ - pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat; - - /* Assign the internal user callback pointer to the SAL handle */ - pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB; - - /*To assign user callback pointers*/ - - pSalADCMngtAdpt->pUserCB->pRXCB = pSalADCUserCBAdpt; - pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+1); - pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+2); - pSalADCMngtAdpt->pUserCB->pIDMARXCCB= (pSalADCUserCBAdpt+3); - pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+4); - pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+5); - /* Set ADC Device Number */ - pSalADCHND->DevNum = adc_idx; - - /* Load ADC default value */ - RtkADCLoadDefault(pSalADCHND); - - /* Assign ADC Pin Mux */ - pSalADCHND->PinMux = 0; - pSalADCHND->OpType = ADC_RDREG_TYPE; - - /* Load user setting */ - if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) { - pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian; - } - - if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) { - pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn; - } - - /* Init ADC now */ - pSalADCHND->pInitDat->ADCBurstSz = 8; - pSalADCHND->pInitDat->ADCOneShotTD = 8; - RtkADCInit(pSalADCHND); -} - -float analogin_read(analogin_t *obj) -{ - float value; - uint32_t AnaloginTmp[2] = {0,0}; - uint32_t AnaloginDatMsk = 0xFFFF; - uint8_t AnaloginIdx = 0; - uint32_t AnalogDat = 0; - -#if defined(CONFIG_MBED_ENABLED) - //no auto-calibration implemented yet, uses hard coded calibrate - uint32_t Offset = 0x2980; - uint32_t AnalogDatFull = 0xAA00; -#else - uint32_t AnalogDatFull = 0; -#endif - - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - AnaloginIdx = pSalADCHND->DevNum; - RtkADCReceiveBuf(pSalADCHND,&AnaloginTmp[0]); - - AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); - AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; - AnalogDat = (AnalogDat & AnaloginDatMsk); - AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); - -#if defined(CONFIG_MBED_ENABLED) - AnalogDat -= Offset; -#else - AnalogDatFull = 0xCE80; -#endif - - value = (float)(AnalogDat) / (float)(AnalogDatFull); - return (float)value; -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t AnaloginTmp[2] = {0,0}; - uint32_t AnaloginDatMsk = 0xFFFF; - uint8_t AnaloginIdx = 0; - uint32_t AnalogDat = 0; - - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - AnaloginIdx = pSalADCHND->DevNum; - RtkADCRxManualRotate(pSalADCHND,&AnaloginTmp[0]); - - AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); - AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; - AnalogDat = (AnalogDat & AnaloginDatMsk); - AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); - - return (uint16_t)AnalogDat; -} - - -void analogin_deinit(analogin_t *obj) -{ - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - - /* To deinit analogin */ - RtkADCDeInit(pSalADCHND); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h deleted file mode 100644 index 83846aafd45..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ANALOGIN_EXT_H -#define MBED_ANALOGIN_EXT_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern void analogin_deinit(analogin_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c deleted file mode 100644 index 0a50d63e54f..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c +++ /dev/null @@ -1,197 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "objects.h" -#include "analogout_api.h" - - -#if CONFIG_DAC_EN - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include - -#define DAC_POSITIVE_FULL_SCALE 0x7E0 -#define DAC_NEGATIVE_FULL_SCALE 0x820 - -extern void HalDACPinMuxInit(void *Data); -extern void HalDACPinMuxDeInit(void *Data); - -/** \brief analogout_init:\n - * to initialize DAC - * - * This function is mainly to initialize a DAC channel. - * \para dac_t *: obj - * \para PinName: pin - */ -void analogout_init(dac_t *obj, PinName pin) -{ - uint32_t dac_idx; - uint32_t DacTemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - dac_idx = pin & 0x0F; - - /* Assign dac index */ - pHalDacInitData->DACIdx = dac_idx; - - pHalDacInitData->DACEn = DAC_DISABLE; - pHalDacInitData->DACDataRate = DAC_DATA_RATE_250K; - pHalDacInitData->DACEndian = DAC_DATA_ENDIAN_LITTLE; - pHalDacInitData->DACBurstSz = 10; - pHalDacInitData->DACDbgSel = DAC_DBG_SEL_DISABLE; - pHalDacInitData->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE; - pHalDacInitData->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE; - pHalDacInitData->DACDeltaSig = 0; - pHalDacInitData->DACAnaCtrl0 = 0; - pHalDacInitData->DACAnaCtrl1 = 0; - pHalDacInitData->DACIntrMSK = DAC_FEATURE_DISABLED; - - /* DAC Function and Clock Enable*/ - HalDACPinMuxInit(pHalDacInitData); - - HalDACInit8195a(pHalDacInitData); - - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, - (BIT_DAC_FIFO_FULL_EN | - BIT_DAC_FIFO_OVERFLOW_EN | - BIT_DAC_FIFO_STOP_EN | - BIT_DAC__WRITE_ERROR_EN | - BIT_DAC_DSC_OVERFLOW0_EN | - BIT_DAC_DSC_OVERFLOW1_EN)); - DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pHalDacInitData->DACIdx,REG_DAC_INTR_CTRL)); - - DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1); - DacTemp |= (BIT31); - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1, DacTemp); - DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1)); - - DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL); - DacTemp |= BIT3; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL, DacTemp); - DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp); - - pHalDacInitData->DACEn = DAC_ENABLE; - HalDACEnableRtl8195a(pHalDacInitData); - osDelay(6); //hardware needs some time to get ready -} - -/** \brief analogout_free:\n - * to free DAC - * - * This function is mainly to free a DAC channel. - * \para dac_t *: obj - */ -void analogout_free(dac_t *obj) -{ - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - HalDACPinMuxDeInit(pHalDacInitData); - - pHalDacInitData->DACEn = DAC_DISABLE; - HalDACEnableRtl8195a(pHalDacInitData); -} - -/** \brief analogout_write:\n - * to execute analogout_write - * - * This function is mainly to execute analog output and the value is a ratio. - * The upper/lower bound of DAC register input value is defined by - * DAC_XXXXX_FULL_SCALE. The parameter "value" of this function should be - * transfered to register value. - * - * \para dac_t * : obj - * \para float : value - */ -void analogout_write(dac_t *obj, float value) -{ - uint32_t dactemp; - uint16_t dacnegtemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - if (value < 0.0f) { - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, 0x00000000); - } else if (value > 1.0f) { - dactemp = (DAC_POSITIVE_FULL_SCALE<<16) | DAC_POSITIVE_FULL_SCALE; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } else { - if (value >= 0.5) { - dactemp = (uint32_t)((((value-0.5)/0.5) * (2^12)) * DAC_POSITIVE_FULL_SCALE); - dactemp = dactemp / (2^12); - dactemp = (dactemp<<16) | dactemp; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } else { - dacnegtemp = (DAC_NEGATIVE_FULL_SCALE & 0x7FF); - dacnegtemp = ((~dacnegtemp) + 1) & 0x7FF; - dactemp = (uint32_t)(((0.5-value)/0.5) * (2^12) * dacnegtemp); - dactemp = dactemp / (2^12); - dactemp = 0x1000 - dactemp; //change to 2's complement - dactemp = (dactemp<<16) | dactemp; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } - } -} - -/** \brief analogout_write_u16:\n - * to execute analogout_write_u16 - * - * The register value of DAC input is a format of 2's complement. - * The most maximum value of positive value drives DAC to output a voltage about 3.3V. - * The most mimimum value of negative value drives DAC to output a voltage about 0. - * And the middle value of 0x000 will drive DAC to output a voltage of half of max voltage. - * - * \para dac_t * : obj - * \para float : value - */ -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - uint32_t dactemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - /* To give a two point data */ - dactemp = (value << 16) | value; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); -} - -/** \brief analogout_read_u16:\n - * to read back analog output value in float format - * - * This function is NOT available in rtl8195a hardware design. - * It always returns a fixed value of 0.0; - * \para dac_t * : obj - */ -float analogout_read(dac_t *obj) -{ - return (float)0.0; -} - -/** \brief analogout_read_u16:\n - * to read back analog output register value - * - * This function is NOT available in rtl8195a hardware design. - * It always returns a fixed value of 0xFFFF; - * \para dac_t * : obj - */ -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)0xFFFF; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h deleted file mode 100644 index b4b1b8a4121..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h +++ /dev/null @@ -1,22 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar deleted file mode 100644 index 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HalSPI1PinCtrlRtl8195A -0x000010e5 T HalSPI2PinCtrlRtl8195A -0x000011b5 T HalSPI0MCSPinCtrlRtl8195A -0x00001275 T HalI2C0PinCtrlRtl8195A -0x00001381 T HalI2C1PinCtrlRtl8195A -0x00001459 T HalI2C2PinCtrlRtl8195A -0x00001529 T HalI2C3PinCtrlRtl8195A -0x00001639 T HalI2S0PinCtrlRtl8195A -0x0000176d T HalI2S1PinCtrlRtl8195A -0x00001845 T HalPCM0PinCtrlRtl8195A -0x00001949 T HalPCM1PinCtrlRtl8195A -0x00001a1d T HalSDIODPinCtrlRtl8195A -0x00001a6d T HalSDIOHPinCtrlRtl8195A -0x00001ab9 T HalMIIPinCtrlRtl8195A -0x00001b51 T HalWLLEDPinCtrlRtl8195A -0x00001c0d T HalWLANT0PinCtrlRtl8195A -0x00001c61 T HalWLANT1PinCtrlRtl8195A -0x00001cb5 T HalWLBTCOEXPinCtrlRtl8195A -0x00001d05 T HalWLBTCMDPinCtrlRtl8195A -0x00001d59 T HalNFCPinCtrlRtl8195A -0x00001da9 T HalPWM0PinCtrlRtl8195A -0x00001ead T HalPWM1PinCtrlRtl8195A -0x00001fb5 T HalPWM2PinCtrlRtl8195A -0x000020b1 T HalPWM3PinCtrlRtl8195A -0x000021b9 T HalETE0PinCtrlRtl8195A -0x000022c1 T HalETE1PinCtrlRtl8195A -0x000023c9 T HalETE2PinCtrlRtl8195A -0x000024d1 T HalETE3PinCtrlRtl8195A -0x000025d9 T HalEGTIMPinCtrlRtl8195A -0x00002679 T HalSPIFlashPinCtrlRtl8195A -0x00002725 T HalSDRPinCtrlRtl8195A -0x0000280d T HalJTAGPinCtrlRtl8195A -0x00002861 T HalTRACEPinCtrlRtl8195A -0x000028b9 T HalLOGUartPinCtrlRtl8195A -0x0000291d T HalLOGUartIRPinCtrlRtl8195A -0x00002981 T HalSICPinCtrlRtl8195A -0x000029d9 T HalEEPROMPinCtrlRtl8195A -0x00002a31 T HalDEBUGPinCtrlRtl8195A -0x00002b39 T HalPinCtrlRtl8195A -0x00002e5d T SpicRxCmdRtl8195A -0x00002ea5 T SpicWaitBusyDoneRtl8195A -0x00002eb5 T SpicGetFlashStatusRtl8195A -0x00002f55 T SpicWaitWipDoneRtl8195A -0x00002f6d T SpicTxCmdRtl8195A -0x00002fc1 T SpicSetFlashStatusRtl8195A -0x00003049 T SpicCmpDataForCalibrationRtl8195A -0x00003081 T SpicLoadInitParaFromClockRtl8195A -0x000030e5 T SpicInitRtl8195A -0x000031bd T SpicEraseFlashRtl8195A -0x00003279 T SpiFlashApp -0x000033b5 T HalPeripheralIntrHandle -0x00003439 T HalSysOnIntrHandle -0x00003485 T HalWdgIntrHandle -0x000034d5 T HalTimer0IntrHandle -0x00003525 T HalTimer1IntrHandle -0x00003575 T HalI2C3IntrHandle -0x000035c5 T HalTimer2To7IntrHandle -0x00003615 T HalSpi0IntrHandle -0x00003665 T HalGpioIntrHandle -0x000036b5 T HalUart0IntrHandle -0x00003705 T HalSpiFlashIntrHandle -0x00003755 T HalUsbOtgIntrHandle -0x000037a5 T HalSdioHostIntrHandle -0x000037f5 T HalI2s0OrPcm0IntrHandle -0x00003845 T HalI2s1OrPcm1IntrHandle -0x00003895 T HalWlDmaIntrHandle -0x000038e5 T HalWlProtocolIntrHandle -0x00003935 T HalCryptoIntrHandle -0x00003985 T HalGmacIntrHandle -0x000039d5 T HalGdma0Ch0IntrHandle -0x00003a25 T HalGdma0Ch1IntrHandle -0x00003a75 T HalGdma0Ch2IntrHandle; -0x00003ac5 T HalGdma0Ch3IntrHandle -0x00003b15 T HalGdma0Ch4IntrHandle -0x00003b65 T HalGdma0Ch5IntrHandle -0x00003bb5 T HalGdma1Ch0IntrHandle -0x00003c05 T HalGdma1Ch1IntrHandle -0x00003c55 T HalGdma1Ch2IntrHandle -0x00003ca5 T HalGdma1Ch3IntrHandle -0x00003cf5 T HalGdma1Ch4IntrHandle -0x00003d45 T HalGdma1Ch5IntrHandle -0x00003d95 T HalSdioDeviceIntrHandle -0x00003de5 T VectorTableInitRtl8195A -0x00004019 T VectorTableInitForOSRtl8195A -0x00004029 T VectorIrqRegisterRtl8195A -0x00004091 T VectorIrqUnRegisterRtl8195A -0x000040f1 T VectorIrqEnRtl8195A -0x0000418d T VectorIrqDisRtl8195A -0x0000422d T _UartRxDmaIrqHandle -0x00004281 T HalRuartPutCRtl8195a -0x0000429d T HalRuartGetCRtl8195a -0x000042bd T HalRuartRTSCtrlRtl8195a -0x000042e1 T HalRuartGetDebugValueRtl8195a -0x000043e1 T HalRuartGetIMRRtl8195a -0x0000442d T HalRuartSetIMRRtl8195a -0x00004465 T _UartIrqHandle -0x00004681 T HalRuartDmaInitRtl8195a -0x00004845 T HalRuartIntDisableRtl8195a -0x00004855 T HalRuartDeInitRtl8195a -0x00004985 T HalRuartIntEnableRtl8195a -0x00004995 T _UartTxDmaIrqHandle -0x000049d1 T HalRuartRegIrqRtl8195a -0x00004a4d T HalRuartAdapterLoadDefRtl8195a -0x00004add T HalRuartTxGdmaLoadDefRtl8195a -0x00004bc9 T HalRuartRxGdmaLoadDefRtl8195a -0x00004cc9 T RuartLock -0x00004ced T RuartUnLock -0x00004d09 T HalRuartIntSendRtl8195a -0x00004e35 T HalRuartDmaSendRtl8195a -0x00004f89 T HalRuartStopSendRtl8195a -0x0000504d T HalRuartIntRecvRtl8195a -0x000051ad T HalRuartDmaRecvRtl8195a -0x000052cd T HalRuartStopRecvRtl8195a -0x00005385 T RuartIsTimeout -0x000053b1 T HalRuartSendRtl8195a -0x00005599 T HalRuartRecvRtl8195a -0x00005751 T RuartResetRxFifoRtl8195a -0x00005775 T HalRuartResetRxFifoRtl8195a -0x00005829 T HalRuartInitRtl8195a -0x00005df1 T HalGdmaOnOffRtl8195a -0x00005e0d T HalGdmaChIsrEnAndDisRtl8195a -0x00005e51 T HalGdmaChEnRtl8195a -0x00005e6d T HalGdmaChDisRtl8195a -0x00005e91 T HalGdamChInitRtl8195a -0x00005ebd T HalGdmaChSetingRtl8195a -0x000060dd T HalGdmaChBlockSetingRtl8195a -0x00006419 T HalGdmaChIsrCleanRtl8195a -0x000064a1 T HalGdmaChCleanAutoSrcRtl8195a -0x00006501 T HalGdmaChCleanAutoDstRtl8195a -0x00006561 T HalEFUSEPowerSwitch8195AROM -0x000065f9 T HALEFUSEOneByteReadROM -0x00006699 T HALEFUSEOneByteWriteROM -0x0000681d T __rtl_memcmpb_v1_00 -0x00006861 T __rtl_random_v1_00 -0x00006881 T __rtl_align_to_be32_v1_00 -0x00006899 T __rtl_memsetw_v1_00 -0x000068ad T __rtl_memsetb_v1_00 -0x000068bd T __rtl_memcpyw_v1_00 -0x000068dd T __rtl_memcpyb_v1_00 -0x000068f5 T __rtl_memDump_v1_00 -0x00006901 T __rtl_AES_set_encrypt_key -0x00006c11 T __rtl_cryptoEngine_AES_set_decrypt_key -0x00006c95 T __rtl_cryptoEngine_set_security_mode_v1_00 -0x00006ea9 T __rtl_cryptoEngine_init_v1_00 -0x00007055 T __rtl_cryptoEngine_exit_v1_00 -0x000070b1 T __rtl_cryptoEngine_reset_v1_00 -0x000070ed T __rtl_cryptoEngine_v1_00 -0x00007c69 T __rtl_crypto_cipher_init_v1_00 -0x00007c89 T __rtl_crypto_cipher_encrypt_v1_00 -0x00007cad T __rtl_crypto_cipher_decrypt_v1_00 -0x00007cd5 T HalSsiPinmuxEnableRtl8195a -0x00007e45 T HalSsiEnableRtl8195a -0x00007ef9 T HalSsiDisableRtl8195a -0x00007fad T HalSsiLoadSettingRtl8195a -0x00008521 T HalSsiSetInterruptMaskRtl8195a -0x000085c9 T HalSsiGetInterruptMaskRtl8195a -0x0000863d T HalSsiSetSclkPolarityRtl8195a -0x00008715 T HalSsiSetSclkPhaseRtl8195a -0x000087e9 T HalSsiWriteRtl8195a -0x00008861 T HalSsiSetDeviceRoleRtl8195a -0x000088c9 T HalSsiSetRxFifoThresholdLevelRtl8195a -0x00008941 T HalSsiSetTxFifoThresholdLevelRtl8195a -0x000089b9 T HalSsiReadRtl8195a -0x00008a2d T HalSsiGetRxFifoLevelRtl8195a -0x00008aa5 T HalSsiGetTxFifoLevelRtl8195a -0x00008b1d T HalSsiGetStatusRtl8195a -0x00008b91 T HalSsiWriteableRtl8195a -0x00008c09 T HalSsiReadableRtl8195a -0x00008c81 T HalSsiBusyRtl8195a -0x00008cf9 T HalSsiReadInterruptRtl8195a -0x00008efd T HalSsiWriteInterruptRtl8195a -0x00009009 T HalSsiSetSlaveEnableRegisterRtl8195a -0x000090d9 T HalSsiGetInterruptStatusRtl8195a -0x0000914d T HalSsiInterruptEnableRtl8195a -0x00009299 T HalSsiInterruptDisableRtl8195a -0x000093e9 T HalSsiGetRawInterruptStatusRtl8195a -0x0000945d T HalSsiGetSlaveEnableRegisterRtl8195a -0x000094d1 T HalSsiInitRtl8195a -0x00009ba5 T _SsiReadInterrupt -0x00009db1 T _SsiWriteInterrupt -0x00009eb1 T _SsiIrqHandle -0x0000a061 T HalI2CWrite32 -0x0000a09d T HalI2CRead32 -0x0000a0dd T HalI2CDeInit8195a -0x0000a1f1 T HalI2CSendRtl8195a -0x0000a25d T HalI2CReceiveRtl8195a -0x0000a271 T HalI2CEnableRtl8195a -0x0000a389 T HalI2CIntrCtrl8195a -0x0000a3a1 T HalI2CReadRegRtl8195a -0x0000a3b1 T HalI2CWriteRegRtl8195a -0x0000a3c5 T HalI2CSetCLKRtl8195a -0x0000a6e9 T HalI2CMassSendRtl8195a -0x0000a749 T HalI2CClrIntrRtl8195a -0x0000a761 T HalI2CClrAllIntrRtl8195a -0x0000a775 T HalI2CInit8195a -0x0000aa31 T HalI2CDMACtrl8195a -0x0000aa61 T RtkI2CIoCtrl -0x0000aa65 T RtkI2CPowerCtrl -0x0000aa69 T HalI2COpInit -0x0000ac65 T I2CIsTimeout -0x0000b435 T I2CTXGDMAISRHandle -0x0000b4c1 T I2CRXGDMAISRHandle -0x0000b54d T RtkI2CIrqInit -0x0000b611 T RtkI2CIrqDeInit -0x0000b675 T RtkI2CPinMuxInit -0x0000b7c9 T RtkI2CPinMuxDeInit -0x0000b955 T RtkI2CDMAInit -0x0000bc95 T RtkI2CInit -0x0000bdad T RtkI2CDMADeInit -0x0000be4d T RtkI2CDeInit -0x0000bee5 T RtkI2CSendUserAddr -0x0000c07d T RtkI2CSend -0x0000ce51 T RtkI2CLoadDefault -0x0000cf21 T RtkSalI2COpInit -0x0000cf65 T HalI2SWrite32 -0x0000cf85 T HalI2SRead32 -0x0000cfa9 T HalI2SDeInitRtl8195a -0x0000cfc9 T HalI2STxRtl8195a -0x0000d011 T HalI2SRxRtl8195a -0x0000d05d T HalI2SEnableRtl8195a -0x0000d0b1 T HalI2SIntrCtrlRtl8195a -0x0000d0d1 T HalI2SReadRegRtl8195a -0x0000d0dd T HalI2SClrIntrRtl8195a -0x0000d0fd T HalI2SClrAllIntrRtl8195a -0x0000d11d T HalI2SInitRtl8195a -0x0000d2e5 T GPIO_GetIPPinName_8195a -0x0000d331 T GPIO_GetChipPinName_8195a -0x0000d39d T GPIO_PullCtrl_8195a -0x0000d421 T GPIO_FuncOn_8195a -0x0000d481 T GPIO_FuncOff_8195a -0x0000d4e9 T GPIO_Int_Mask_8195a -0x0000d511 T GPIO_Int_SetType_8195a -0x0000d5fd T HAL_GPIO_IrqHandler_8195a -0x0000d645 T HAL_GPIO_MbedIrqHandler_8195a -0x0000d6a1 T HAL_GPIO_UserIrqHandler_8195a -0x0000d6cd T HAL_GPIO_IntCtrl_8195a -0x0000d805 T HAL_GPIO_Init_8195a -0x0000dac1 T HAL_GPIO_DeInit_8195a -0x0000dbd1 T HAL_GPIO_ReadPin_8195a -0x0000dc91 T HAL_GPIO_WritePin_8195a -0x0000ddad T HAL_GPIO_RegIrq_8195a -0x0000ddf5 T HAL_GPIO_UnRegIrq_8195a -0x0000de15 T HAL_GPIO_UserRegIrq_8195a -0x0000def9 T HAL_GPIO_UserUnRegIrq_8195a -0x0000dfc1 T HAL_GPIO_MaskIrq_8195a -0x0000e061 T HAL_GPIO_UnMaskIrq_8195a -0x0000e101 T HAL_GPIO_IntDebounce_8195a -0x0000e1c1 T HAL_GPIO_GetIPPinName_8195a -0x0000e1c9 T HAL_GPIO_PullCtrl_8195a -0x0000e259 T DumpForOneBytes -0x0000e419 T CmdRomHelp -0x0000e491 T CmdWriteWord -0x0000e505 T CmdDumpHelfWord -0x0000e5f1 T CmdDumpWord -0x0000e6f5 T CmdDumpByte -0x0000e751 T CmdSpiFlashTool -0x0000e7a9 T GetRomCmdNum -0x0000e7ad T CmdWriteByte -0x0000e7ed T Isspace -0x0000e801 T Strtoul -0x0000e8b1 T ArrayInitialize -0x0000e8c9 T GetArgc -0x0000e8f9 T GetArgv -0x0000e95d T UartLogCmdExecute -0x0000e9fd T UartLogShowBackSpace -0x0000ea39 T UartLogRecallOldCmd -0x0000ea71 T UartLogHistoryCmd -0x0000eadd T UartLogCmdChk -0x0000ebf5 T UartLogIrqHandle -0x0000ecc5 T RtlConsolInit -0x0000ed49 T RtlConsolTaskRom -0x0000ed79 T RtlExitConsol -0x0000edcd T RtlConsolRom -0x0000ee0d T HalTimerOpInit -0x0000ee59 T HalTimerIrq2To7Handle -0x0000ef09 T HalGetTimerIdRtl8195a -0x0000ef3d T HalTimerInitRtl8195a -0x0000f069 T HalTimerDisRtl8195a -0x0000f089 T HalTimerEnRtl8195a -0x0000f0a9 T HalTimerReadCountRtl8195a -0x0000f0bd T HalTimerIrqClearRtl8195a -0x0000f0d1 T HalTimerDumpRegRtl8195a -0x0000f129 T VSprintf -0x0000f39d T DiagPrintf -0x0000f3b9 T DiagSPrintf -0x0000f3d1 T DiagSnPrintf -0x0000f3ed T prvDiagPrintf -0x0000f40d T prvDiagSPrintf -0x0000f429 T _memcmp -0x0000f465 T _memcpy -#0x0000f511 T _memset -0x0000f585 T Rand -0x0000f60d T _strncpy -0x0000f629 T _strcpy -0x0000f639 T prvStrCpy -0x0000f651 T _strlen -0x0000f669 T _strnlen -0x0000f699 T prvStrLen -0x0000f6b1 T _strcmp -0x0000f6d1 T _strncmp -0x0000f719 T prvStrCmp -0x0000f749 T StrUpr -0x0000f769 T prvAtoi -0x0000f7bd T prvStrStr -0x0000f7d5 T _strsep -0x0000f815 T skip_spaces -0x0000f831 T skip_atoi -0x0000f869 T _parse_integer_fixup_radix -0x0000f8bd T _parse_integer -0x0000f915 T simple_strtoull -0x0000f945 T simple_strtoll -0x0000f965 T simple_strtoul -0x0000f96d T simple_strtol -0x0000f985 T _vsscanf -0x0000ff71 T _sscanf -0x0000ff91 T div_u64 -0x0000ff99 T div_s64 -0x0000ffa1 T div_u64_rem -0x0000ffb1 T div_s64_rem -0x0000ffc1 T _strpbrk -0x0000ffed T _strchr -0x00010005 T aes_set_key -0x000103d1 T aes_encrypt -0x000114a5 T aes_decrypt -0x000125c9 T AES_WRAP -0x00012701 T AES_UnWRAP -0x00012861 T crc32_get -0x00012895 T arc4_byte -0x000128bd T rt_arc4_init -0x00012901 T rt_arc4_crypt -0x000131c1 T rt_md5_init -0x000131f5 T rt_md5_append -0x0001327d T rt_md5_final -0x000132d5 T rt_md5_hmac -0x00013449 T rtw_get_bit_value_from_ieee_value -0x00013475 T rtw_is_cckrates_included -0x000134b5 T rtw_is_cckratesonly_included -0x000134dd T rtw_check_network_type -0x0001350d T rtw_set_fixed_ie -0x0001352d T rtw_set_ie -0x0001355d T rtw_get_ie -0x00013591 T rtw_set_supported_rate -0x00013611 T rtw_get_rateset_len -0x0001362d T rtw_get_wpa_ie -0x000136c9 T rtw_get_wpa2_ie -0x00013701 T rtw_get_wpa_cipher_suite -0x00013769 T rtw_get_wpa2_cipher_suite -0x000137d1 T rtw_parse_wpa_ie -0x000138ad T rtw_parse_wpa2_ie -0x00013965 T rtw_get_sec_ie -0x00013a15 T rtw_get_wps_ie -0x00013a99 T rtw_get_wps_attr -0x00013b49 T rtw_get_wps_attr_content -0x00013b91 T rtw_ieee802_11_parse_elems -0x00013d9d T str_2char2num -0x00013db9 T key_2char2num -0x00013dd1 T convert_ip_addr -0x00013e9d T rom_psk_PasswordHash -0x00013ed5 T rom_psk_CalcGTK -0x00013f69 T rom_psk_CalcPTK -0x00014295 T wep_80211_encrypt -0x000142f5 T wep_80211_decrypt -0x00014389 T tkip_micappendbyte -0x000143d9 T rtw_secmicsetkey -0x00014419 T rtw_secmicappend -0x00014435 T rtw_secgetmic -0x0001449d T rtw_seccalctkipmic -0x000145a5 T tkip_phase1 -0x00014725 T tkip_phase2 -0x00014941 T tkip_80211_encrypt -0x000149d5 T tkip_80211_decrypt -0x00014a8d T aes1_encrypt -0x00014c65 T aesccmp_construct_mic_iv -0x00014ccd T aesccmp_construct_mic_header1 -0x00014d21 T aesccmp_construct_mic_header2 -0x00014db5 T aesccmp_construct_ctr_preload -0x00014e29 T aes_80211_encrypt -0x000151ad T aes_80211_decrypt -0x000155b9 T _sha1_process_message_block -0x00015749 T _sha1_pad_message -0x000157e5 T rt_sha1_init -0x00015831 T rt_sha1_update -0x000158a9 T rt_sha1_finish -0x00015909 T rt_hmac_sha1 -0x00015a65 T rom_aes_128_cbc_encrypt -0x00015ae1 T rom_aes_128_cbc_decrypt -0x00015b5d T rom_rijndaelKeySetupEnc -0x00015c39 T rom_aes_decrypt_init -0x00015d15 T rom_aes_internal_decrypt -0x00016071 T rom_aes_decrypt_deinit -0x00016085 T rom_aes_encrypt_init -0x0001609d T rom_aes_internal_encrypt -0x00016451 T rom_aes_encrypt_deinit -0x00017b35 T bignum_init -0x00017b61 T bignum_deinit -0x00017b81 T bignum_get_unsigned_bin_len -0x00017b85 T bignum_get_unsigned_bin -0x00017c21 T bignum_set_unsigned_bi -0x00017cd1 T bignum_cmp -0x00017cd5 T bignum_cmp_d -0x00017cfd T bignum_add -0x00017d0d T bignum_sub -0x00017d1d T bignum_mul -0x00017d2d T bignum_exptmod -0x00017d51 T WPS_realloc -0x00017d99 T os_zalloc -0x00017dc1 T rom_hmac_sha256_vector -0x00017ebd T rom_hmac_sha256 -0x00018009 T rom_sha256_vector -0x00018221 T phy_CalculateBitShift -0x00018239 T PHY_SetBBReg_8195A -0x00018279 T PHY_QueryBBReg_8195A -0x0001829d T ROM_odm_QueryRxPwrPercentage -0x000182bd T ROM_odm_EVMdbToPercentage -0x000182e5 T ROM_odm_SignalScaleMapping_8195A -0x000183cd T ROM_odm_FalseAlarmCounterStatistics -0x00018721 T ROM_odm_SetEDCCAThreshold -0x00018749 T ROM_odm_SetTRxMux -0x00018771 T ROM_odm_SetCrystalCap -0x000187d5 T ROM_odm_GetDefaultCrytaltalCap -0x000187e9 T ROM_ODM_CfoTrackingReset -0x00018811 T ROM_odm_CfoTrackingFlow -0x0001965d T curve25519_donna -0x0001a391 T aes_test_alignment_detection -0x0001a3ed T aes_mode_reset -0x0001a3f9 T aes_ecb_encrypt -0x0001a431 T aes_ecb_decrypt -0x0001a469 T aes_cbc_encrypt -0x0001a579 T aes_cbc_decrypt -0x0001a701 T aes_cfb_encrypt -0x0001a9e5 T aes_cfb_decrypt -0x0001acc9 T aes_ofb_crypt -0x0001af7d T aes_ctr_crypt -0x0001b289 T aes_encrypt_key128 -0x0001b2a5 T aes_encrypt_key192 -0x0001b2c1 T aes_encrypt_key256 -0x0001b2e1 T aes_encrypt_key -0x0001b351 T aes_decrypt_key128 -0x0001b36d T aes_decrypt_key192 -0x0001b389 T aes_decrypt_key256 -0x0001b3a9 T aes_decrypt_key -0x0001b419 T aes_init -0x0001b41d T CRYPTO_chacha_20 -0x0001bc25 T CRYPTO_poly1305_init -0x0001bd09 T CRYPTO_poly1305_update -0x0001bd8d T CRYPTO_poly1305_finish -0x0001ceb5 T rom_sha512_starts -0x0001d009 T rom_sha512_update -0x0001d011 T rom_sha512_finish -0x0001d261 T rom_sha512 -0x0001d299 T rom_sha512_hmac_starts -0x0001d35d T rom_sha512_hmac_update -0x0001d365 T rom_sha512_hmac_finish -0x0001d3b5 T rom_sha512_hmac_reset -0x0001d3d1 T rom_sha512_hmac -0x0001d40d T rom_sha512_hkdf -0x0001d501 T rom_ed25519_gen_keypair -0x0001d505 T rom_ed25519_gen_signature -0x0001d51d T rom_ed25519_verify_signature -0x0001d521 T rom_ed25519_crypto_sign_seed_keypair -0x0001d579 T rom_ed25519_crypto_sign_detached -0x0001d655 T rom_ed25519_crypto_sign_verify_detached -0x0001f86d T rom_ed25519_ge_double_scalarmult_vartime -0x0001fc35 T rom_ed25519_ge_frombytes_negate_vartime -0x000207d5 T rom_ed25519_ge_p3_tobytes -0x00020821 T rom_ed25519_ge_scalarmult_base -0x000209e1 T rom_ed25519_ge_tobytes -0x00020a2d T rom_ed25519_sc_muladd -0x0002603d T rom_ed25519_sc_reduce -0x00028a4d T __rtl_memchr_v1_00 -0x00028ae1 T __rtl_memcmp_v1_00 -0x00028b49 T __rtl_memcpy_v1_00 -0x00028bed T __rtl_memmove_v1_00 -0x00028cb5 T __rtl_memset_v1_00 -0x00028d49 T __rtl_strcat_v1_00 -0x00028d91 T __rtl_strchr_v1_00 -0x00028e55 T __rtl_strcmp_v1_00 -0x00028ec9 T __rtl_strcpy_v1_00 -0x00028f15 T __rtl_strlen_v1_00 -0x00028f69 T __rtl_strncat_v1_00 -0x00028fc5 T __rtl_strncmp_v1_00 -0x0002907d T __rtl_strncpy_v1_00 -0x000293cd T __rtl_strstr_v1_00 -0x0002960d T __rtl_strsep_v1_00 -0x00029619 T __rtl_strtok_v1_00 -0x0002962d T __rtl__strtok_r_v1_00 -0x00029691 T __rtl_strtok_r_v1_00 -0x00029699 T __rtl_close_v1_00 -0x000296ad T __rtl_fstat_v1_00 -0x000296c1 T __rtl_isatty_v1_00 -0x000296d5 T __rtl_lseek_v1_00 -0x000296e9 T __rtl_open_v1_00 -0x000296fd T __rtl_read_v1_00 -0x00029711 T __rtl_write_v1_00 -0x00029725 T __rtl_sbrk_v1_00 -0x000297bd T __rtl_ltoa_v1_00 -0x00029855 T __rtl_ultoa_v1_00 -0x000298c5 T __rtl_dtoi_v1_00 -0x00029945 T __rtl_dtoi64_v1_00 -0x000299dd T __rtl_dtoui_v1_00 -0x000299e5 T __rtl_ftol_v1_00 -0x00029a51 T __rtl_itof_v1_00 -0x00029ae9 T __rtl_itod_v1_00 -0x00029b79 T __rtl_i64tod_v1_00 -0x00029c55 T __rtl_uitod_v1_00 -0x00029d2d T __rtl_ftod_v1_00 -0x00029de9 T __rtl_dtof_v1_00 -0x00029e89 T __rtl_uitof_v1_00 -0x00029f65 T __rtl_fadd_v1_00 -0x0002a261 T __rtl_fsub_v1_00 -0x0002a559 T __rtl_fmul_v1_00 -0x0002a695 T __rtl_fdiv_v1_00 -0x0002a825 T __rtl_dadd_v1_00 -0x0002aed9 T __rtl_dsub_v1_00 -0x0002b555 T __rtl_dmul_v1_00 -0x0002b8ad T __rtl_ddiv_v1_00 -0x0002be4d T __rtl_dcmpeq_v1_00 -0x0002bebd T __rtl_dcmplt_v1_00 -0x0002bf51 T __rtl_dcmpgt_v1_00 -0x0002c049 T __rtl_dcmple_v1_00 -0x0002c139 T __rtl_fcmplt_v1_00 -0x0002c195 T __rtl_fcmpgt_v1_00 -0x0002c229 T __rtl_cos_f32_v1_00 -0x0002c435 T __rtl_sin_f32_v1_00 -0x0002c639 T __rtl_fabs_v1_00 -0x0002c641 T __rtl_fabsf_v1_00 -0x0002c77d T __rtl_dtoa_r_v1_00 -0x0002d7d1 T __rom_mallocr_init_v1_00 -0x0002d841 T __rtl_free_r_v1_00 -0x0002da31 T __rtl_malloc_r_v1_00 -0x0002df55 T __rtl_realloc_r_v1_00 -0x0002e331 T __rtl_memalign_r_v1_00 -0x0002e421 T __rtl_valloc_r_v1_00 -0x0002e42d T __rtl_pvalloc_r_v1_00 -0x0002e441 T __rtl_calloc_r_v1_00 -0x0002e4a9 T __rtl_cfree_r_v1_00 -0x0002e515 T __rtl_Balloc_v1_00 -0x0002e571 T __rtl_Bfree_v1_00 -0x0002e585 T __rtl_i2b_v1_00 -0x0002e599 T __rtl_multadd_v1_00 -0x0002e629 T __rtl_mult_v1_00 -0x0002e769 T __rtl_pow5mult_v1_00 -0x0002e809 T __rtl_hi0bits_v1_00 -0x0002e845 T __rtl_d2b_v1_00 -0x0002e901 T __rtl_lshift_v1_00 -0x0002e9bd T __rtl_cmp_v1_00 -0x0002ea01 T __rtl_diff_v1_00 -0x0002eae9 T __rtl_sread_v1_00 -0x0002eb39 T __rtl_seofread_v1_00 -0x0002eb3d T __rtl_swrite_v1_00 -0x0002ebc1 T __rtl_sseek_v1_00 -0x0002ec11 T __rtl_sclose_v1_00 -0x0002ec41 T __rtl_sbrk_r_v1_00 -0x0002ef8d T __rtl_fflush_r_v1_00 -0x0002f661 T __rtl_vfprintf_r_v1_00 -0x00030c15 T __rtl_fpclassifyd -0x00030c68 D CpkClkTbl -0x00030c80 D ROM_IMG1_VALID_PATTEN -0x00030c88 D SpicCalibrationPattern -0x00030c98 D SpicInitCPUCLK -0x00030ca8 D BAUDRATE -0x00030d1c D OVSR -0x00030d90 D DIV -0x00030e04 D OVSR_ADJ -0x00030e78 D __AES_rcon -0x00030ea0 D __AES_Te4 -0x000312a0 D I2CDmaChNo -0x000316a0 D UartLogRomCmdTable -0x00031700 D _HalRuartOp -0x00031760 D _HalGdmaOp -0x0003540c D RTW_WPA_OUI_TYPE -0x00035410 D WPA_CIPHER_SUITE_NONE -0x00035414 D WPA_CIPHER_SUITE_WEP40 -0x00035418 D WPA_CIPHER_SUITE_TKIP -0x0003541c D WPA_CIPHER_SUITE_CCMP -0x00035420 D WPA_CIPHER_SUITE_WEP104 -0x00035424 D RSN_CIPHER_SUITE_NONE -0x00035428 D RSN_CIPHER_SUITE_WEP40 -0x0003542c D RSN_CIPHER_SUITE_TKIP -0x00035430 D RSN_CIPHER_SUITE_CCMP -0x00035434 D RSN_CIPHER_SUITE_WEP104 -0x00035444 D RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X -0x00035448 D RSN_AUTH_KEY_MGMT_UNSPEC_802_1X -0x0003544c D RSN_VERSION_BSD -0x00035988 D rom_wps_Te0 -0x00035d88 D rom_wps_rcons -0x00035d94 D rom_wps_Td4s -0x00035e94 D rom_wps_Td0 -0x10000000 D NewVectorTable -0x10000100 D UserIrqFunTable -0x10000200 D UserIrqDataTable -0x10000300 D __rom_bss_start__ -0x10000300 D CfgSysDebugWarn -0x10000304 D CfgSysDebugInfo -0x10000308 D CfgSysDebugErr -0x1000030c D ConfigDebugWarn -0x10000310 D ConfigDebugInfo -0x10000314 D ConfigDebugErr -0x10000318 D HalTimerOp -0x10000334 D GPIOState -0x1000034c D gTimerRecord -0x10000350 D SSI_DBG_CONFIG -0x10000354 D _pHAL_Gpio_Adapter -0x10000358 D Timer2To7VectorTable -#0x10000384 D pUartLogCtl -#0x10000388 D UartLogBuf -#0x10000408 D UartLogCtl -#0x10000430 D UartLogHistoryBuf -#0x100006ac D ArgvArray -0x100006d4 D rom_wlan_ram_map -0x100006e0 D FalseAlmCnt -0x10000720 D ROMInfo -0x10000738 D DM_CfoTrack -0x10000760 D rom_libgloss_ram_map -0x10000bc4 D __rtl_errno -0x10000bc8 D __ram_table_start__ -0x10000bc8 D __rom_bss_end__ -0x10001c60 D _rtl_impure_ptr -0X10006000 D __image2_entry_func__ -0x10006000 D __image2_start__ -0x30000000 D __image3_start__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S deleted file mode 100644 index c184bdff725..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S +++ /dev/null @@ -1,31 +0,0 @@ -; -; Copyright (c) 2017 Realtek Semiconductor Corp. -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - - PRESERVE8 - THUMB - - AREA |i.PLAT_Start|, CODE, READONLY - -PLAT_Start PROC - - EXPORT PLAT_Start - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - IMPORT PLAT_Init - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =PLAT_Init - BX R0 - ENDP - ALIGN - END diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a deleted file mode 100644 index 7b2963eb35695ba42699858f22125e6beff2dcd4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 980164 zcmeFa34C2e**|{Hy;*M3CiiA(o0D!gO-j?!q*=N`fhIRen{G*ylolx5rpav+nkFF& zEsIe0#SIh{waAVu3YGezf})~UMQs5U1Qn525Cn^YltudgerKLJ_uQKVL|=V*|3A;? z-uccv^UO2*oH=vmIa9Q>eW0W3_{@3X#H(^a^^)r9`3n~>35P3`m)8u3D=Vuj7ApGY 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