diff --git a/TESTS/events/queue/main.cpp b/TESTS/events/queue/main.cpp index 4bde3c8e230..f52cf70665a 100644 --- a/TESTS/events/queue/main.cpp +++ b/TESTS/events/queue/main.cpp @@ -22,7 +22,7 @@ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -357,3 +357,4 @@ int main() return !Harness::run(specification); } +#endif // !DEVICE_USTICKER diff --git a/TESTS/events/timing/main.cpp b/TESTS/events/timing/main.cpp index adc001640b2..146d5de7642 100644 --- a/TESTS/events/timing/main.cpp +++ b/TESTS/events/timing/main.cpp @@ -26,7 +26,7 @@ using namespace utest::v1; #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else // Test delay #ifndef TEST_EVENTS_TIMING_TIME @@ -148,3 +148,4 @@ int main() return !Harness::run(specification); } +#endif // !DEVICE_USTICKER diff --git a/TESTS/lorawan/loraradio/main.cpp b/TESTS/lorawan/loraradio/main.cpp index 0d88d4e6e6f..f5daaa13089 100644 --- a/TESTS/lorawan/loraradio/main.cpp +++ b/TESTS/lorawan/loraradio/main.cpp @@ -36,6 +36,7 @@ #error [NOT_SUPPORTED] Requires parameters from application config file. #endif +#if (MBED_CONF_APP_LORA_RADIO == SX1272) || (MBED_CONF_APP_LORA_RADIO == SX1276) using namespace utest::v1; using namespace mbed; @@ -281,3 +282,5 @@ int main() { return !Harness::run(specification); } + +#endif // (MBED_CONF_APP_LORA_RADIO == SX1272) || (MBED_CONF_APP_LORA_RADIO == SX1276) diff --git a/TESTS/mbed-crypto/sanity/main.cpp b/TESTS/mbed-crypto/sanity/main.cpp index 73d5eb0b6f2..27269195237 100644 --- a/TESTS/mbed-crypto/sanity/main.cpp +++ b/TESTS/mbed-crypto/sanity/main.cpp @@ -19,7 +19,7 @@ #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. -#endif +#else #include #include "mbed.h" @@ -460,3 +460,4 @@ int main(void) { return !Harness::run(specification); } +#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) diff --git a/TESTS/mbed_drivers/flashiap/main.cpp b/TESTS/mbed_drivers/flashiap/main.cpp index 28249eeaf22..6f7991bcc24 100644 --- a/TESTS/mbed_drivers/flashiap/main.cpp +++ b/TESTS/mbed_drivers/flashiap/main.cpp @@ -17,7 +17,7 @@ #if !DEVICE_FLASH #error [NOT_SUPPORTED] Flash API not supported for this target -#endif +#else #include "utest/utest.h" #include "utest/utest_serial.h" @@ -328,3 +328,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_FLASH diff --git a/TESTS/mbed_drivers/lp_ticker/main.cpp b/TESTS/mbed_drivers/lp_ticker/main.cpp index 425c5b9a38a..cf10dbac7a7 100644 --- a/TESTS/mbed_drivers/lp_ticker/main.cpp +++ b/TESTS/mbed_drivers/lp_ticker/main.cpp @@ -21,7 +21,7 @@ #if !DEVICE_LPTICKER #error [NOT_SUPPORTED] Low power ticker not supported for this target -#endif +#else using utest::v1::Case; @@ -228,3 +228,5 @@ int main() { utest::v1::Harness::run(specification); } + +#endif // !DEVICE_LPTICKER diff --git a/TESTS/mbed_drivers/lp_timeout/main.cpp b/TESTS/mbed_drivers/lp_timeout/main.cpp index ffeecde1f3e..6eb8c142040 100644 --- a/TESTS/mbed_drivers/lp_timeout/main.cpp +++ b/TESTS/mbed_drivers/lp_timeout/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_LPTICKER #error [NOT_SUPPORTED] Low power timer not supported for this target -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -93,3 +93,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_LPTICKER diff --git a/TESTS/mbed_drivers/lp_timer/main.cpp b/TESTS/mbed_drivers/lp_timer/main.cpp index d41fd806aff..390c6e23376 100644 --- a/TESTS/mbed_drivers/lp_timer/main.cpp +++ b/TESTS/mbed_drivers/lp_timer/main.cpp @@ -24,7 +24,7 @@ #if !DEVICE_LPTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -350,3 +350,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_LPTICKER diff --git a/TESTS/mbed_drivers/mem_trace/main.cpp b/TESTS/mbed_drivers/mem_trace/main.cpp index 9eac2684443..3018ca3172a 100644 --- a/TESTS/mbed_drivers/mem_trace/main.cpp +++ b/TESTS/mbed_drivers/mem_trace/main.cpp @@ -26,7 +26,7 @@ #ifndef MBED_MEM_TRACING_ENABLED #error [NOT_SUPPORTED] test not supported -#endif +#else using utest::v1::Case; @@ -427,3 +427,5 @@ int main() return !utest::v1::Harness::run(specification); } + +#endif // MBED_MEM_TRACING_ENABLED diff --git a/TESTS/mbed_drivers/race_test/main.cpp b/TESTS/mbed_drivers/race_test/main.cpp index 059313e5eaf..8f896e25187 100644 --- a/TESTS/mbed_drivers/race_test/main.cpp +++ b/TESTS/mbed_drivers/race_test/main.cpp @@ -22,13 +22,9 @@ #include "SingletonPtr.h" #include -#ifdef MBED_RTOS_SINGLE_THREAD -#error [NOT_SUPPORTED] test not supported for single threaded enviroment -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER +#error [NOT_SUPPORTED] Test not supported for single threaded enviroment. UsTicker need to be enabled for this test. +#else using namespace utest::v1; @@ -135,3 +131,5 @@ int main() { Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/reset_reason/main.cpp b/TESTS/mbed_drivers/reset_reason/main.cpp index 626fccc6487..f9c59d70958 100644 --- a/TESTS/mbed_drivers/reset_reason/main.cpp +++ b/TESTS/mbed_drivers/reset_reason/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_RESET_REASON #error [NOT_SUPPORTED] Reset reason API not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -141,3 +141,5 @@ int main() test_reset_reason(); // The result of this test suite is reported by the host side. GREENTEA_TESTSUITE_RESULT(0); // Fail on any error. } + +#endif // !DEVICE_RESET_REASON diff --git a/TESTS/mbed_drivers/rtc/main.cpp b/TESTS/mbed_drivers/rtc/main.cpp index 460785b1203..8cdb54581c5 100644 --- a/TESTS/mbed_drivers/rtc/main.cpp +++ b/TESTS/mbed_drivers/rtc/main.cpp @@ -23,7 +23,7 @@ #if !DEVICE_RTC || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -494,3 +494,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_RTC || !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/sleep_lock/main.cpp b/TESTS/mbed_drivers/sleep_lock/main.cpp index 7986845f578..8bf77fa7167 100644 --- a/TESTS/mbed_drivers/sleep_lock/main.cpp +++ b/TESTS/mbed_drivers/sleep_lock/main.cpp @@ -17,7 +17,7 @@ #if !DEVICE_SLEEP #error [NOT_SUPPORTED] Sleep not supported for this target -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -132,3 +132,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_SLEEP diff --git a/TESTS/mbed_drivers/ticker/main.cpp b/TESTS/mbed_drivers/ticker/main.cpp index b324f35674d..02ec415feb4 100644 --- a/TESTS/mbed_drivers/ticker/main.cpp +++ b/TESTS/mbed_drivers/ticker/main.cpp @@ -20,7 +20,7 @@ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using utest::v1::Case; @@ -354,3 +354,5 @@ int main() { utest::v1::Harness::run(specification); } + +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/timeout/main.cpp b/TESTS/mbed_drivers/timeout/main.cpp index 48feba4d914..3f3706e5a0b 100644 --- a/TESTS/mbed_drivers/timeout/main.cpp +++ b/TESTS/mbed_drivers/timeout/main.cpp @@ -21,7 +21,7 @@ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] usticker not supported for this target. -#endif +#else using namespace utest::v1; @@ -87,3 +87,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/timer/main.cpp b/TESTS/mbed_drivers/timer/main.cpp index d04cd54e76e..317ce916f20 100644 --- a/TESTS/mbed_drivers/timer/main.cpp +++ b/TESTS/mbed_drivers/timer/main.cpp @@ -24,7 +24,7 @@ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -789,3 +789,4 @@ int main() return !Harness::run(specification); } +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/timerevent/main.cpp b/TESTS/mbed_drivers/timerevent/main.cpp index 7228b8bb16e..f23dfb1a5de 100644 --- a/TESTS/mbed_drivers/timerevent/main.cpp +++ b/TESTS/mbed_drivers/timerevent/main.cpp @@ -15,7 +15,7 @@ */ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] usticker not supported for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -27,10 +27,6 @@ using namespace utest::v1; -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif - #define TEST_DELAY_US 50000ULL #define DELTA 2 @@ -246,3 +242,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_drivers/watchdog/main.cpp b/TESTS/mbed_drivers/watchdog/main.cpp index e89fe282fbe..db42107bf28 100644 --- a/TESTS/mbed_drivers/watchdog/main.cpp +++ b/TESTS/mbed_drivers/watchdog/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_WATCHDOG #error [NOT_SUPPORTED] Watchdog not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -282,3 +282,5 @@ int main() // Harness will start with a test case index provided by host script. return !Harness::run(specification); } + +#endif // !DEVICE_WATCHDOG diff --git a/TESTS/mbed_drivers/watchdog_reset/main.cpp b/TESTS/mbed_drivers/watchdog_reset/main.cpp index 5025a43d769..3f6e3d9a0fe 100644 --- a/TESTS/mbed_drivers/watchdog_reset/main.cpp +++ b/TESTS/mbed_drivers/watchdog_reset/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_WATCHDOG #error [NOT_SUPPORTED] Watchdog not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "utest/utest.h" @@ -319,3 +319,4 @@ int main() // Harness will start with a test case index provided by host script. return !Harness::run(specification); } +#endif // !DEVICE_WATCHDOG diff --git a/TESTS/mbed_hal/common_tickers/main.cpp b/TESTS/mbed_hal/common_tickers/main.cpp index e1a26dc79e1..4b2f4c41c96 100644 --- a/TESTS/mbed_hal/common_tickers/main.cpp +++ b/TESTS/mbed_hal/common_tickers/main.cpp @@ -32,7 +32,7 @@ extern "C" { #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else #define US_PER_S 1000000 @@ -605,3 +605,4 @@ int main() { return !Harness::run(specification); } +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_hal/common_tickers_freq/main.cpp b/TESTS/mbed_hal/common_tickers_freq/main.cpp index e00c2a242d7..a91abf86d72 100644 --- a/TESTS/mbed_hal/common_tickers_freq/main.cpp +++ b/TESTS/mbed_hal/common_tickers_freq/main.cpp @@ -30,13 +30,9 @@ #include "hal/lp_ticker_api.h" #include "hal/mbed_lp_ticker_wrapper.h" -#if defined(SKIP_TIME_DRIFT_TESTS) +#if defined(SKIP_TIME_DRIFT_TESTS) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #define US_PER_S 1000000 @@ -208,3 +204,5 @@ int main() { Harness::run(specification); } + +#endif // defined(SKIP_TIME_DRIFT_TESTS) || !DEVICE_USTICKER diff --git a/TESTS/mbed_hal/crc/main.cpp b/TESTS/mbed_hal/crc/main.cpp index c233c120d60..597605920a0 100644 --- a/TESTS/mbed_hal/crc/main.cpp +++ b/TESTS/mbed_hal/crc/main.cpp @@ -22,7 +22,7 @@ #if !DEVICE_CRC #error [NOT_SUPPORTED] CRC not supported for this target -#endif +#else using namespace utest::v1; @@ -280,3 +280,5 @@ int main() Harness::run(specification); } + +#endif // !DEVICE_CRC diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index e79a16a53dd..0ec95b5e545 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_FLASH #error [NOT_SUPPORTED] Flash API not supported for this target -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -280,3 +280,5 @@ int main() { Harness::run(specification); } + +#endif !DEVICE_FLASH diff --git a/TESTS/mbed_hal/lp_ticker/main.cpp b/TESTS/mbed_hal/lp_ticker/main.cpp index 58ff4acf7f1..1d56bda276b 100644 --- a/TESTS/mbed_hal/lp_ticker/main.cpp +++ b/TESTS/mbed_hal/lp_ticker/main.cpp @@ -24,7 +24,7 @@ #if !DEVICE_LPTICKER #error [NOT_SUPPORTED] Low power timer not supported for this target -#endif +#else using namespace utest::v1; @@ -204,3 +204,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_LPTICKER diff --git a/TESTS/mbed_hal/mpu/main.cpp b/TESTS/mbed_hal/mpu/main.cpp index 09da6397175..a479d5c48a1 100644 --- a/TESTS/mbed_hal/mpu/main.cpp +++ b/TESTS/mbed_hal/mpu/main.cpp @@ -26,7 +26,7 @@ #if !DEVICE_MPU #error [NOT_SUPPORTED] MPU API not supported for this target -#endif +#else using namespace utest::v1; @@ -197,3 +197,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_MPU diff --git a/TESTS/mbed_hal/qspi/main.cpp b/TESTS/mbed_hal/qspi/main.cpp index 33515daa804..0c772327f03 100644 --- a/TESTS/mbed_hal/qspi/main.cpp +++ b/TESTS/mbed_hal/qspi/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_QSPI #error [NOT_SUPPORTED] QSPI not supported for this target -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -30,7 +30,7 @@ #if !defined(QSPI_FLASH_CHIP_STRING) #error [NOT_SUPPORTED] QSPI test not supported for this target -#endif +#else using namespace utest::v1; @@ -602,3 +602,5 @@ int main() Harness::run(specification); } +#endif // !defined(QSPI_FLASH_CHIP_STRING) +#endif // !DEVICE_QSPI diff --git a/TESTS/mbed_hal/reset_reason/main.cpp b/TESTS/mbed_hal/reset_reason/main.cpp index e604a4c6ad2..99f5d7ace12 100644 --- a/TESTS/mbed_hal/reset_reason/main.cpp +++ b/TESTS/mbed_hal/reset_reason/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_RESET_REASON #error [NOT_SUPPORTED] Reset reason API not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -148,3 +148,5 @@ int main() test_reset_reason(); // The result of this test suite is reported by the host side. GREENTEA_TESTSUITE_RESULT(0); // Fail on any error. } + +#endif //!DEVICE_RESET_REASON diff --git a/TESTS/mbed_hal/rtc/main.cpp b/TESTS/mbed_hal/rtc/main.cpp index bd65e38cd4f..89d560b90a6 100644 --- a/TESTS/mbed_hal/rtc/main.cpp +++ b/TESTS/mbed_hal/rtc/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_RTC #error [NOT_SUPPORTED] RTC API not supported for this target -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -258,3 +258,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_RTC diff --git a/TESTS/mbed_hal/rtc_reset/main.cpp b/TESTS/mbed_hal/rtc_reset/main.cpp index de9fdf85c6a..8d44df14dab 100644 --- a/TESTS/mbed_hal/rtc_reset/main.cpp +++ b/TESTS/mbed_hal/rtc_reset/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_RTC #error [NOT_SUPPORTED] RTC API not supported for this target -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -100,3 +100,5 @@ int main() { rtc_reset_test(); } + +#endif // !DEVICE_RTC diff --git a/TESTS/mbed_hal/sleep/main.cpp b/TESTS/mbed_hal/sleep/main.cpp index a61e0660234..c0730c5eb97 100644 --- a/TESTS/mbed_hal/sleep/main.cpp +++ b/TESTS/mbed_hal/sleep/main.cpp @@ -16,7 +16,7 @@ #if !DEVICE_SLEEP #error [NOT_SUPPORTED] sleep not supported for this target -#endif +#else #include "mbed.h" @@ -260,3 +260,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_SLEEP diff --git a/TESTS/mbed_hal/sleep_manager/main.cpp b/TESTS/mbed_hal/sleep_manager/main.cpp index 7e7cca03d0e..14a2e6e9007 100644 --- a/TESTS/mbed_hal/sleep_manager/main.cpp +++ b/TESTS/mbed_hal/sleep_manager/main.cpp @@ -24,7 +24,7 @@ #if !DEVICE_SLEEP #error [NOT_SUPPORTED] test not supported -#endif +#else #define SLEEP_DURATION_US 20000ULL #define DEEP_SLEEP_TEST_CHECK_WAIT_US 2000 @@ -333,3 +333,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_SLEEP diff --git a/TESTS/mbed_hal/sleep_manager_racecondition/main.cpp b/TESTS/mbed_hal/sleep_manager_racecondition/main.cpp index 86f2aaeeeaf..6f5cd877cd7 100644 --- a/TESTS/mbed_hal/sleep_manager_racecondition/main.cpp +++ b/TESTS/mbed_hal/sleep_manager_racecondition/main.cpp @@ -19,13 +19,9 @@ #include "mbed.h" #include "sleep_manager_api_racecondition_tests.h" -#if !DEVICE_SLEEP +#if !DEVICE_SLEEP || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -105,3 +101,5 @@ int main() { Harness::run(specification); } + +#endif // !DEVICE_SLEEP || !DEVICE_USTICKER diff --git a/TESTS/mbed_hal/spm/main.cpp b/TESTS/mbed_hal/spm/main.cpp index 5b16dcc5066..cdf8b27757d 100644 --- a/TESTS/mbed_hal/spm/main.cpp +++ b/TESTS/mbed_hal/spm/main.cpp @@ -17,15 +17,15 @@ #if !defined(COMPONENT_PSA_SRV_IPC) #error [NOT_SUPPORTED] Test supported only on PSA targets -#endif +#else #if (defined( __CC_ARM ) || defined(__ARMCC_VERSION) || defined( __ICCARM__ )) #error [NOT_SUPPORTED] this test is supported on GCC only -#endif +#else #if DOMAIN_NS == 1 #error [NOT_SUPPORTED] Cannot run on M23/M33 core as SecureFault is implemented in secure-side and cant be remapped -#endif +#else #include "utest/utest.h" #include "unity/unity.h" @@ -156,3 +156,7 @@ int main() { Harness::run(specification); } + +#endif // DOMAIN_NS == 1 +#endif // (defined( __CC_ARM ) || defined(__ARMCC_VERSION) || defined( __ICCARM__ )) +#endif // !defined(COMPONENT_PSA_SRV_IPC) diff --git a/TESTS/mbed_hal/stack_size_unification/main.cpp b/TESTS/mbed_hal/stack_size_unification/main.cpp index 230ade73d69..377cd1eb750 100644 --- a/TESTS/mbed_hal/stack_size_unification/main.cpp +++ b/TESTS/mbed_hal/stack_size_unification/main.cpp @@ -22,7 +22,7 @@ #ifdef TARGET_RENESAS #error [NOT_SUPPORTED] Cortex-A target not supported for this test -#endif +#else using namespace utest::v1; @@ -74,3 +74,5 @@ int main() { return !Harness::run(specification); } + +#endif // TARGET_RENESAS diff --git a/TESTS/mbed_hal/trng/main.cpp b/TESTS/mbed_hal/trng/main.cpp index 6166219888e..38c228a2a49 100644 --- a/TESTS/mbed_hal/trng/main.cpp +++ b/TESTS/mbed_hal/trng/main.cpp @@ -48,7 +48,7 @@ #if !DEVICE_TRNG #error [NOT_SUPPORTED] TRNG API not supported for this target -#endif +#else #define MSG_VALUE_DUMMY "0" #define MSG_VALUE_LEN 64 @@ -284,5 +284,5 @@ int main() return ret; } - +#endif // !DEVICE_TRNG diff --git a/TESTS/mbed_hal/us_ticker/main.cpp b/TESTS/mbed_hal/us_ticker/main.cpp index 7df5f80bfc0..09789791293 100644 --- a/TESTS/mbed_hal/us_ticker/main.cpp +++ b/TESTS/mbed_hal/us_ticker/main.cpp @@ -22,7 +22,7 @@ #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -57,3 +57,5 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_USTICKER diff --git a/TESTS/mbed_hal/watchdog/main.cpp b/TESTS/mbed_hal/watchdog/main.cpp index 2b8d58b4af8..7df1efb55e7 100644 --- a/TESTS/mbed_hal/watchdog/main.cpp +++ b/TESTS/mbed_hal/watchdog/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_WATCHDOG #error [NOT_SUPPORTED] Watchdog not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "hal/watchdog_api.h" @@ -283,3 +283,5 @@ int main() // Harness will start with a test case index provided by host script. return !Harness::run(specification); } + +#endif // !DEVICE_WATCHDOG diff --git a/TESTS/mbed_hal/watchdog_reset/main.cpp b/TESTS/mbed_hal/watchdog_reset/main.cpp index dddd3121863..1c94a91b3f1 100644 --- a/TESTS/mbed_hal/watchdog_reset/main.cpp +++ b/TESTS/mbed_hal/watchdog_reset/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_WATCHDOG #error [NOT_SUPPORTED] Watchdog not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "utest/utest.h" @@ -305,3 +305,5 @@ int main() // Harness will start with a test case index provided by host script. return !Harness::run(specification); } + +#endif // !DEVICE_WATCHDOG diff --git a/TESTS/mbed_hal/watchdog_timing/main.cpp b/TESTS/mbed_hal/watchdog_timing/main.cpp index a5d75783411..816fb889e77 100644 --- a/TESTS/mbed_hal/watchdog_timing/main.cpp +++ b/TESTS/mbed_hal/watchdog_timing/main.cpp @@ -16,7 +16,7 @@ */ #if !DEVICE_WATCHDOG #error [NOT_SUPPORTED] Watchdog not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "hal/watchdog_api.h" @@ -160,3 +160,5 @@ int main() // Harness will start with a test case index provided by host script. return !Harness::run(specification); } + +#endif // !DEVICE_WATCHDOG diff --git a/TESTS/mbed_platform/atomic/main.cpp b/TESTS/mbed_platform/atomic/main.cpp index 3a2f99d0eb9..4d8856da809 100644 --- a/TESTS/mbed_platform/atomic/main.cpp +++ b/TESTS/mbed_platform/atomic/main.cpp @@ -20,7 +20,7 @@ #if !MBED_CONF_RTOS_PRESENT #error [NOT_SUPPORTED] test not supported -#endif +#else #define THREAD_STACK 512 @@ -183,3 +183,5 @@ int main() { return !utest::v1::Harness::run(specification); } + +#endif // !MBED_CONF_RTOS_PRESENT diff --git a/TESTS/mbed_platform/crash_reporting/main.cpp b/TESTS/mbed_platform/crash_reporting/main.cpp index d971099c854..3f3260b5f2e 100644 --- a/TESTS/mbed_platform/crash_reporting/main.cpp +++ b/TESTS/mbed_platform/crash_reporting/main.cpp @@ -21,7 +21,7 @@ #if !MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED #error [NOT_SUPPORTED] crash_reporting test not supported -#endif +#else #define MSG_VALUE_DUMMY "0" #define MSG_VALUE_LEN 32 @@ -78,3 +78,5 @@ int main(void) return 0; } + +#endif // !MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED diff --git a/TESTS/mbed_platform/stats_cpu/main.cpp b/TESTS/mbed_platform/stats_cpu/main.cpp index f4c77526fd6..348da308213 100644 --- a/TESTS/mbed_platform/stats_cpu/main.cpp +++ b/TESTS/mbed_platform/stats_cpu/main.cpp @@ -23,7 +23,7 @@ #if !defined(MBED_CPU_STATS_ENABLED) || !DEVICE_LPTICKER || !DEVICE_SLEEP #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -110,3 +110,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(MBED_CPU_STATS_ENABLED) || !DEVICE_LPTICKER || !DEVICE_SLEEP diff --git a/TESTS/mbed_platform/stats_heap/main.cpp b/TESTS/mbed_platform/stats_heap/main.cpp index 163ff20d6cc..2e7dc98e811 100644 --- a/TESTS/mbed_platform/stats_heap/main.cpp +++ b/TESTS/mbed_platform/stats_heap/main.cpp @@ -24,7 +24,7 @@ #if !defined(MBED_HEAP_STATS_ENABLED) #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -207,3 +207,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(MBED_HEAP_STATS_ENABLED) diff --git a/TESTS/mbed_platform/stats_sys/main.cpp b/TESTS/mbed_platform/stats_sys/main.cpp index 0fdbe3849ec..d0f58cc9c79 100644 --- a/TESTS/mbed_platform/stats_sys/main.cpp +++ b/TESTS/mbed_platform/stats_sys/main.cpp @@ -23,7 +23,7 @@ #if !defined(MBED_SYS_STATS_ENABLED) #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -105,3 +105,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(MBED_SYS_STATS_ENABLED) diff --git a/TESTS/mbed_platform/stats_thread/main.cpp b/TESTS/mbed_platform/stats_thread/main.cpp index 2a9f62d8f9d..648e45bf1f6 100644 --- a/TESTS/mbed_platform/stats_thread/main.cpp +++ b/TESTS/mbed_platform/stats_thread/main.cpp @@ -23,7 +23,7 @@ #if !defined(MBED_THREAD_STATS_ENABLED) #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -174,3 +174,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(MBED_THREAD_STATS_ENABLED) diff --git a/TESTS/mbed_platform/wait_ns/main.cpp b/TESTS/mbed_platform/wait_ns/main.cpp index 61af4afeaef..9d8743b0338 100644 --- a/TESTS/mbed_platform/wait_ns/main.cpp +++ b/TESTS/mbed_platform/wait_ns/main.cpp @@ -26,7 +26,7 @@ //FastModels not support timing test #if defined(TARGET_ARM_FM) #error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -99,3 +99,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(TARGET_ARM_FM) diff --git a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp index e9e3bbf4c05..13c131feff4 100644 --- a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp @@ -19,17 +19,9 @@ #include "utest/utest.h" #include "unity/unity.h" -#if defined(SKIP_TIME_DRIFT_TESTS) +#if defined(SKIP_TIME_DRIFT_TESTS) || defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if defined(MBED_RTOS_SINGLE_THREAD) -#error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using utest::v1::Case; @@ -123,3 +115,5 @@ int main() { utest::v1::Harness::run(specification); } + +#endif // defined(SKIP_TIME_DRIFT_TESTS) || defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp b/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp index 3592f0a93ec..0f96013d2db 100644 --- a/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp @@ -19,13 +19,9 @@ #include "utest.h" #include "rtos.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -188,3 +184,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp index fd57ca98e1f..2ee4d760e36 100644 --- a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp @@ -22,13 +22,9 @@ using utest::v1::Case; -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #if defined(__CORTEX_M23) || defined(__CORTEX_M33) #define THREAD_STACK_SIZE 512 @@ -374,3 +370,5 @@ int main() { return !utest::v1::Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp index c0f6f4cf351..9fd9829fdf9 100644 --- a/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp @@ -15,13 +15,9 @@ * limitations under the License. */ -#if defined(TARGET_CORTEX_A) +#if defined(TARGET_CORTEX_A) || !DEVICE_USTICKER #error [NOT_SUPPORTED] This function not supported for this target -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #include #include @@ -266,3 +262,5 @@ int main() { return !utest::v1::Harness::run(specification); } + +#endif // defined(TARGET_CORTEX_A) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp index 1046d1d2491..cfcec0fa780 100644 --- a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp @@ -19,13 +19,9 @@ #include "utest.h" #include "rtos.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -512,3 +508,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp index 1a3891ce198..b2c650f6781 100644 --- a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp @@ -19,13 +19,9 @@ #include "unity/unity.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using utest::v1::Case; @@ -221,3 +217,5 @@ int main() { return !utest::v1::Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp b/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp index c3cfd3d6515..6a6e4c2bf02 100644 --- a/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp @@ -19,13 +19,9 @@ #include "utest.h" #include "rtos.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -308,3 +304,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp index 286630bb773..1293f9c3c17 100644 --- a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp @@ -19,13 +19,9 @@ #include "utest.h" #include "rtos.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else using namespace utest::v1; @@ -348,3 +344,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp index e184575fa8f..024eb475184 100644 --- a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp @@ -28,11 +28,11 @@ using namespace utest::v1; #if RESTART_DELAY_MS >= DELAY_MS #error invalid RESTART_DELAY_MS value -#endif +#else #if !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif +#else class Stopwatch: public Timer { private: @@ -357,3 +357,6 @@ int main() { return !Harness::run(specification); } + +#endif // !DEVICE_USTICKER +#endif // RESTART_DELAY_MS >= DELAY_MS diff --git a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp index 80580ef5ee2..49a806c6e04 100644 --- a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp @@ -21,13 +21,9 @@ using namespace utest::v1; -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #define THREAD_DELAY 30 #define SEMAPHORE_SLOTS 2 @@ -249,3 +245,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/signals/main.cpp b/TESTS/mbedmicro-rtos-mbed/signals/main.cpp index 092d9cd1787..6fd39b23d68 100644 --- a/TESTS/mbedmicro-rtos-mbed/signals/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/signals/main.cpp @@ -20,13 +20,9 @@ using utest::v1::Case; -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #define TEST_STACK_SIZE 512 #define MAX_FLAG_POS 30 @@ -396,3 +392,5 @@ int main() { return !utest::v1::Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp index 0d3764b7fd2..470a9f081fc 100644 --- a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp @@ -21,13 +21,9 @@ #include "SynchronizedIntegral.h" #include "LockGuard.h" -#if defined(MBED_RTOS_SINGLE_THREAD) +#if defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER #error [NOT_SUPPORTED] test not supported -#endif - -#if !DEVICE_USTICKER -#error [NOT_SUPPORTED] test not supported -#endif +#else #define THREAD_STACK_SIZE 512 #if defined(__CORTEX_A9) @@ -854,3 +850,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(MBED_RTOS_SINGLE_THREAD) || !DEVICE_USTICKER diff --git a/TESTS/netsocket/dns/main.cpp b/TESTS/netsocket/dns/main.cpp index 20e594885a1..949a418b21b 100644 --- a/TESTS/netsocket/dns/main.cpp +++ b/TESTS/netsocket/dns/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -199,3 +199,5 @@ int main() { return !Harness::run(specification); } + +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/netsocket/tcp/main.cpp b/TESTS/netsocket/tcp/main.cpp index 2be8adc724a..2f41109d863 100644 --- a/TESTS/netsocket/tcp/main.cpp +++ b/TESTS/netsocket/tcp/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -30,7 +30,7 @@ #ifndef ECHO_SERVER_ADDR #error [NOT_SUPPORTED] Requires parameters for echo server -#endif +#else using namespace utest::v1; @@ -237,3 +237,6 @@ int main() { return !Harness::run(specification); } + +#endif // ECHO_SERVER_ADDR +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/netsocket/tls/main.cpp b/TESTS/netsocket/tls/main.cpp index 03eb057436d..f7ae2253578 100644 --- a/TESTS/netsocket/tls/main.cpp +++ b/TESTS/netsocket/tls/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -30,7 +30,7 @@ #ifndef ECHO_SERVER_ADDR #error [NOT_SUPPORTED] Requires parameters for echo server -#endif +#else #if defined(MBEDTLS_SSL_CLI_C) || defined(DOXYGEN_ONLY) @@ -276,3 +276,6 @@ int main() #else #error [NOT_SUPPORTED] This device does not support SSL library #endif // defined(MBEDTLS_SSL_CLI_C) || defined(DOXYGEN_ONLY) + +#endif // ECHO_SERVER_ADDR +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/netsocket/udp/main.cpp b/TESTS/netsocket/udp/main.cpp index d85e2ce85d7..38ae7a203f9 100644 --- a/TESTS/netsocket/udp/main.cpp +++ b/TESTS/netsocket/udp/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -30,7 +30,7 @@ #ifndef ECHO_SERVER_ADDR #error [NOT_SUPPORTED] Requires parameters for echo server -#endif +#else using namespace utest::v1; @@ -201,3 +201,6 @@ int main() { return !Harness::run(specification); } + +#endif // ECHO_SERVER_ADDR +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index ffe7343d245..593d944fda5 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -19,7 +19,7 @@ !defined(MBED_CONF_APP_ECHO_SERVER_TRACE) || \ !defined(MBED_CONF_APP_WIFI_SCAN) #error [NOT_SUPPORTED] Requires parameters from mbed_app.json -#endif +#else #define ETHERNET 1 #define WIFI 2 @@ -27,10 +27,10 @@ #if MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != ETHERNET && \ MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI #error [NOT_SUPPORTED] Either wifi or ethernet testing need to be enabled -#endif +#else -#if MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI -#if !defined(TARGET_UBLOX_EVK_ODIN_W2) && \ +#if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \ + !defined(TARGET_UBLOX_EVK_ODIN_W2) && \ !defined(TARGET_REALTEK_RTL8195AM) && \ !defined(TARGET_MTB_ADV_WISE_1530) && \ !defined(TARGET_MTB_USI_WM_BN_BM_22) && \ @@ -38,8 +38,9 @@ !defined(TARGET_MTB_UBLOX_ODIN_W2) && \ !defined(TARGET_UNO_91H) #error [NOT_SUPPORTED] Wifi tests are not valid for the target -#endif -#endif +#else + + #include "greentea-client/test_env.h" #include "unity.h" @@ -82,3 +83,14 @@ int main() return !Harness::run(specification); } +#endif // (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \ +!defined(TARGET_UBLOX_EVK_ODIN_W2) && \ +!defined(TARGET_REALTEK_RTL8195AM) && \ +!defined(TARGET_MTB_ADV_WISE_1530) && \ +!defined(TARGET_MTB_USI_WM_BN_BM_22) && \ +!defined(TARGET_MTB_MXCHIP_EMW3166) && \ +!defined(TARGET_MTB_UBLOX_ODIN_W2) && \ +!defined(TARGET_UNO_91H) + +#endif // MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != ETHERNET && MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI +#endif // !defined(MBED_CONF_APP_ECHO_SERVER) || !defined(MBED_CONF_APP_ECHO_SERVER_TRACE) || !defined(MBED_CONF_APP_WIFI_SCAN) diff --git a/TESTS/network/interface/main.cpp b/TESTS/network/interface/main.cpp index 48d3f734e36..123bcf9bc51 100644 --- a/TESTS/network/interface/main.cpp +++ b/TESTS/network/interface/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -54,3 +54,5 @@ int main() { return !Harness::run(specification); } + +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/network/multihoming/main.cpp b/TESTS/network/multihoming/main.cpp index b645ff54307..6f6e41e48df 100644 --- a/TESTS/network/multihoming/main.cpp +++ b/TESTS/network/multihoming/main.cpp @@ -19,15 +19,15 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #ifndef MBED_CONF_APP_ECHO_SERVER_ADDR #error [NOT_SUPPORTED] Requires parameters from mbed_app.json -#endif +#else #if !defined(DEVICE_EMAC) || \ (!defined(MBED_CONF_APP_WIFI_SECURE_SSID) && !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID)) #error [NOT_SUPPORTED] Both Wifi and Ethernet devices are required for multihoming tests. -#endif +#else #define STRING_VERIFY(str) (str != NULL ? str : "not supported") @@ -164,3 +164,7 @@ int main() { return !Harness::run(specification); } + +#endif // !defined(DEVICE_EMAC) || (!defined(MBED_CONF_APP_WIFI_SECURE_SSID) && !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID)) +#endif // MBED_CONF_APP_ECHO_SERVER_ADDR +#endif // !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI && !defined(MBED_CONF_NSAPI_DEFAULT_WIFI_SSID)) diff --git a/TESTS/network/wifi/get_interface.cpp b/TESTS/network/wifi/get_interface.cpp index ed60ff7226f..d23e06c377b 100644 --- a/TESTS/network/wifi/get_interface.cpp +++ b/TESTS/network/wifi/get_interface.cpp @@ -19,10 +19,10 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #if !defined(MBED_CONF_APP_WIFI_SECURE_SSID) && !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) #error [NOT_SUPPORTED] Requires parameters from mbed_app.json -#endif +#else #include "mbed.h" #include "WiFiInterface.h" @@ -40,3 +40,5 @@ WiFiInterface *get_interface() return interface; } +#endif //!defined(MBED_CONF_APP_WIFI_SECURE_SSID) && !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) +#endif //!defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index 12bf3d766f5..074a233d178 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -19,7 +19,7 @@ #if !defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || \ MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI #error [NOT_SUPPORTED] No network configuration found for this target. -#endif +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -28,25 +28,24 @@ #include "wifi_tests.h" // Test for parameters -#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) -#if !defined(MBED_CONF_APP_AP_MAC_SECURE) || \ +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) && \ + (!defined(MBED_CONF_APP_AP_MAC_SECURE) || \ !defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ !defined(MBED_CONF_APP_WIFI_CH_SECURE) || \ !defined(MBED_CONF_APP_WIFI_PASSWORD) || \ !defined(MBED_CONF_APP_WIFI_SECURE_SSID) || \ - !defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL + !defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL) #error [NOT_SUPPORTED] Requires parameters from mbed_app.json (for secure connections) -#endif -#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) +#else -#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) -#if !defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) && \ + !defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ !defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ !defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) #error [NOT_SUPPORTED] Requires parameters from mbed_app.json (for unsecure connections) -#endif -#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) +#else + using namespace utest::v1; @@ -93,3 +92,18 @@ int main() { return !Harness::run(specification); } +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) && \ +!defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ +!defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ +!defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ +!defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) && \ +(!defined(MBED_CONF_APP_AP_MAC_SECURE) || \ +!defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ +!defined(MBED_CONF_APP_WIFI_CH_SECURE) || \ +!defined(MBED_CONF_APP_WIFI_PASSWORD) || \ +!defined(MBED_CONF_APP_WIFI_SECURE_SSID) || \ +!defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL) + +#endif //!defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI diff --git a/TESTS/nfc/eeprom/main.cpp b/TESTS/nfc/eeprom/main.cpp index 4f25ce74830..c8d40a012d5 100644 --- a/TESTS/nfc/eeprom/main.cpp +++ b/TESTS/nfc/eeprom/main.cpp @@ -25,7 +25,7 @@ #if !MBED_CONF_NFCEEPROM #error [NOT_SUPPORTED] NFC EEPROM not supported for this target -#endif +#else using namespace utest::v1; using namespace mbed::nfc; @@ -497,3 +497,5 @@ int main() { return !Harness::run(specification); } + +#endif // !MBED_CONF_NFCEEPROM diff --git a/TESTS/psa/attestation/main.cpp b/TESTS/psa/attestation/main.cpp index 90113daa1f0..d4dbb054f7b 100755 --- a/TESTS/psa/attestation/main.cpp +++ b/TESTS/psa/attestation/main.cpp @@ -20,7 +20,7 @@ #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. -#endif // TARGET_PSA +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -156,3 +156,5 @@ int main() { return !Harness::run(specification); } + +#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) diff --git a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp index ca848e85afd..ef45ab43816 100644 --- a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp @@ -19,7 +19,7 @@ #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C)) || (!defined(COMPONENT_PSA_SRV_IPC))) #error [NOT_SUPPORTED] These tests can run only on SPM-enabled targets and where Mbed Crypto is ON - skipping. -#endif +#else #include #include "mbed.h" @@ -594,3 +594,5 @@ int main(void) { return !Harness::run(specification); } + +#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C)) || (!defined(COMPONENT_PSA_SRV_IPC))) diff --git a/TESTS/psa/crypto_init/main.cpp b/TESTS/psa/crypto_init/main.cpp index b057cd501e3..c5854499276 100644 --- a/TESTS/psa/crypto_init/main.cpp +++ b/TESTS/psa/crypto_init/main.cpp @@ -20,7 +20,7 @@ #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. -#endif // TARGET_PSA +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -112,3 +112,5 @@ int main() #endif return !Harness::run(specification); } + +#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) diff --git a/TESTS/psa/entropy_inject/main.cpp b/TESTS/psa/entropy_inject/main.cpp index da3898c7d9f..a27562e9432 100644 --- a/TESTS/psa/entropy_inject/main.cpp +++ b/TESTS/psa/entropy_inject/main.cpp @@ -18,7 +18,7 @@ #if ((!defined(TARGET_PSA) || (!defined(COMPONENT_PSA_SRV_IPC)) && !defined(MBEDTLS_ENTROPY_NV_SEED))) #error [NOT_SUPPORTED] PSA entropy injection tests can run only on PSA-enabled targets. -#endif // TARGET_PSA +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -182,3 +182,5 @@ int main() { return !Harness::run(specification); } + +#endif // ((!defined(TARGET_PSA) || (!defined(COMPONENT_PSA_SRV_IPC)) && !defined(MBEDTLS_ENTROPY_NV_SEED))) diff --git a/TESTS/psa/its_ps/main.cpp b/TESTS/psa/its_ps/main.cpp index 7aab27ad64a..b3a2e57411e 100644 --- a/TESTS/psa/its_ps/main.cpp +++ b/TESTS/psa/its_ps/main.cpp @@ -18,7 +18,7 @@ #ifndef TARGET_PSA #error [NOT_SUPPORTED] ITS/PS tests can run only on PSA-enabled targets. -#endif // TARGET_PSA +#else #include "greentea-client/test_env.h" #include "unity/unity.h" @@ -196,3 +196,5 @@ int main() { return !Harness::run(specification); } + +#endif // TARGET_PSA diff --git a/TESTS/psa/spm_client/COMPONENT_NSPE/main.cpp b/TESTS/psa/spm_client/COMPONENT_NSPE/main.cpp index 535cb3c3388..edf613627f0 100644 --- a/TESTS/psa/spm_client/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/spm_client/COMPONENT_NSPE/main.cpp @@ -17,7 +17,7 @@ #ifndef COMPONENT_PSA_SRV_IPC #error [NOT_SUPPORTED] SPM tests can run only on SPM-enabled targets -#endif // COMPONENT_PSA_SRV_IPC +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -486,3 +486,5 @@ int main() Harness::run(specification); return 0; } + +#endif // COMPONENT_PSA_SRV_IPC diff --git a/TESTS/psa/spm_server/COMPONENT_NSPE/main.cpp b/TESTS/psa/spm_server/COMPONENT_NSPE/main.cpp index 1a47cbea6bc..33b920f6e14 100644 --- a/TESTS/psa/spm_server/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/spm_server/COMPONENT_NSPE/main.cpp @@ -17,7 +17,7 @@ #ifndef COMPONENT_PSA_SRV_IPC #error [NOT_SUPPORTED] SPM tests can run only on SPM-enabled targets -#endif // COMPONENT_PSA_SRV_IPC +#else #include "mbed.h" #include "greentea-client/test_env.h" @@ -275,3 +275,5 @@ int main(int, char **) Harness::run(specification); return 0; } + +#endif // COMPONENT_PSA_SRV_IPC diff --git a/TESTS/psa/spm_smoke/COMPONENT_NSPE/main.cpp b/TESTS/psa/spm_smoke/COMPONENT_NSPE/main.cpp index d3130eeecd7..be6ff6833f5 100644 --- a/TESTS/psa/spm_smoke/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/spm_smoke/COMPONENT_NSPE/main.cpp @@ -18,7 +18,7 @@ #ifndef COMPONENT_PSA_SRV_IPC #error [NOT_SUPPORTED] SPM tests can run only on SPM-enabled targets -#endif // COMPONENT_PSA_SRV_IPC +#else /* -------------------------------------- Includes ----------------------------------- */ @@ -91,3 +91,5 @@ int main(int, char **) Harness::run(specification); return 0; } + +#endif // COMPONENT_PSA_SRV_IPC diff --git a/TESTS/usb_device/basic/main.cpp b/TESTS/usb_device/basic/main.cpp index 533a9be9a68..09e4e1f7196 100644 --- a/TESTS/usb_device/basic/main.cpp +++ b/TESTS/usb_device/basic/main.cpp @@ -40,7 +40,7 @@ #if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE #error [NOT_SUPPORTED] USB Device not supported for this target -#endif +#else using namespace utest::v1; @@ -658,3 +658,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE diff --git a/TESTS/usb_device/hid/main.cpp b/TESTS/usb_device/hid/main.cpp index 44aa1ea83c7..e8816b99fa3 100644 --- a/TESTS/usb_device/hid/main.cpp +++ b/TESTS/usb_device/hid/main.cpp @@ -16,7 +16,7 @@ */ #if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE #error [NOT_SUPPORTED] USB Device not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "utest/utest.h" @@ -382,3 +382,5 @@ int main() { return !Harness::run(specification); } + +#endif // !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE diff --git a/TESTS/usb_device/msd/main.cpp b/TESTS/usb_device/msd/main.cpp index a6349588028..3942573ef34 100644 --- a/TESTS/usb_device/msd/main.cpp +++ b/TESTS/usb_device/msd/main.cpp @@ -31,7 +31,7 @@ #if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE #error [NOT_SUPPORTED] USB Device not supported for this target -#endif +#else #define OS_WINDOWS 1 @@ -480,3 +480,5 @@ int main() { Harness::run(specification); } + +#endif // !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE diff --git a/TESTS/usb_device/serial/main.cpp b/TESTS/usb_device/serial/main.cpp index c6c804a1912..b84819bff97 100644 --- a/TESTS/usb_device/serial/main.cpp +++ b/TESTS/usb_device/serial/main.cpp @@ -16,7 +16,7 @@ */ #if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE #error [NOT_SUPPORTED] USB Device not supported for this target -#endif +#else #include "greentea-client/test_env.h" #include "utest/utest.h" @@ -845,3 +845,5 @@ int main() { return !Harness::run(specification); } + +#endif // !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake index 8a8910cfb71..1236082eb2e 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake @@ -42,4 +42,5 @@ set(unittest-test-sources stubs/UARTSerial_stub.cpp stubs/SerialBase_stub.cpp stubs/CellularContext_stub.cpp + stubs/SocketAddress_stub.cpp ) diff --git a/UNITTESTS/stubs/AT_CellularContext_stub.cpp b/UNITTESTS/stubs/AT_CellularContext_stub.cpp index 87bc66765be..4f89449efaa 100644 --- a/UNITTESTS/stubs/AT_CellularContext_stub.cpp +++ b/UNITTESTS/stubs/AT_CellularContext_stub.cpp @@ -287,3 +287,8 @@ void AT_CellularContext::do_connect_with_retry() { } + +char *AT_CellularContext::get_interface_name(char *interface_name) +{ + return NULL; +} diff --git a/UNITTESTS/target_h/platform/mbed_assert.h b/UNITTESTS/target_h/platform/mbed_assert.h index c52a0173e2e..3d7a8a24d86 100644 --- a/UNITTESTS/target_h/platform/mbed_assert.h +++ b/UNITTESTS/target_h/platform/mbed_assert.h @@ -39,7 +39,12 @@ extern "C" { * @param file File where assertation failed. * @param line Failing assertation line number. */ -MBED_NORETURN void mbed_assert_internal(const char *expr, const char *file, int line); +// mbed_assert_internal UT stub only prints an assert trace and returns, so therefore +// MBED_NORETURN must not be defined for UTs. +#ifndef UNITTEST +MBED_NORETURN +#endif +void mbed_assert_internal(const char *expr, const char *file, int line); #ifdef __cplusplus } @@ -132,4 +137,3 @@ do { \ /**@}*/ /**@}*/ - diff --git a/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp b/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp index bc8093d1642..c2f5dfb7efd 100644 --- a/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp +++ b/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp @@ -68,7 +68,9 @@ using namespace utest::v1; * <<< lines removed >>> */ -#if DEVICE_SPI && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED)) +#if !(DEVICE_SPI && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED))) +#error [NOT_SUPPORTED] DEVICE_SPI need to be enabled for this test. SDcard need to be installed for this test. +#else static char fsfat_fopen_utest_msg_g[FSFAT_UTEST_MSG_BUF_SIZE]; #define FSFAT_FOPEN_TEST_MOUNT_PT_NAME "sd" #define FSFAT_FOPEN_TEST_MOUNT_PT_PATH "/" FSFAT_FOPEN_TEST_MOUNT_PT_NAME @@ -1553,54 +1555,6 @@ control_t fsfat_fopen_test_16(const size_t call_count) return CaseNext; } - -#else - -#define FSFAT_FOPEN_TEST_00 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_01 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_02 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_03 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_04 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_05 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_06 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_07 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_08 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_09 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_10 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_11 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_12 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_13 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_14 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_15 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_16 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_17 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_18 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_19 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_20 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_21 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_22 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_23 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_24 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_25 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_26 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_27 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_28 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_29 fsfat_fopen_test_dummy -#define FSFAT_FOPEN_TEST_30 fsfat_fopen_test_dummy - -/** @brief fsfat_fopen_test_dummy Dummy test case for testing when platform doesnt have an SDCard installed. - * - * @return success always - */ -static control_t fsfat_fopen_test_dummy() -{ - printf("Null test\n"); - return CaseNext; -} - -#endif - - /// @cond FSFAT_DOXYGEN_DISABLE utest::v1::status_t greentea_setup(const size_t number_of_cases) { @@ -1641,3 +1595,4 @@ int main() return !Harness::run(specification); } /// @endcond +#endif // !(DEVICE_SPI && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED))) diff --git a/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.cpp index 08822766490..29c407bd15d 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.cpp @@ -21,6 +21,7 @@ #include "mbed_wait_api.h" #include "mbed_trace.h" +#include "mbed_debug.h" #define TRACE_GROUP "SPIF" using namespace mbed; @@ -106,7 +107,8 @@ static unsigned int local_math_power(int base, int exp); //*********************** SPIFBlockDevice::SPIFBlockDevice( PinName mosi, PinName miso, PinName sclk, PinName csel, int freq) - : _spi(mosi, miso, sclk), _cs(csel), _device_size_bytes(0), _is_initialized(false), _init_ref_count(0) + : _spi(mosi, miso, sclk), _cs(csel), _read_instruction(0), _prog_instruction(0), _erase_instruction(0), + _erase4k_inst(0), _page_size_bytes(0), _device_size_bytes(0), _init_ref_count(0), _is_initialized(false) { _address_size = SPIF_ADDR_SIZE_3_BYTES; // Initial SFDP read tables are read with 8 dummy cycles @@ -154,6 +156,8 @@ int SPIFBlockDevice::init() tr_error("init - Unable to initialize flash memory, tests failed"); status = SPIF_BD_ERROR_DEVICE_ERROR; goto exit_point; + } else { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Initialize flash memory OK\n"); } /* Read Manufacturer ID (1byte), and Device ID (2bytes)*/ @@ -202,6 +206,8 @@ int SPIFBlockDevice::init() _region_high_boundary[0] = _device_size_bytes - 1; if ((sector_map_table_addr != 0) && (0 != sector_map_table_size)) { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: init - Parsing Sector Map Table - addr: 0x%" PRIx32 "h, Size: %d", sector_map_table_addr, + sector_map_table_size); if (0 != _sfdp_parse_sector_map_table(sector_map_table_addr, sector_map_table_size)) { tr_error("init - Parse Sector Map Table Failed"); status = SPIF_BD_ERROR_PARSING_FAILED; @@ -265,6 +271,7 @@ int SPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) } int status = SPIF_BD_ERROR_OK; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG Read - Inst: 0x%xh", _read_instruction); _mutex->lock(); // Set Dummy Cycles for Specific Read Command Mode @@ -290,6 +297,8 @@ int SPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size) uint32_t offset = 0; uint32_t chunk = 0; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: program - Buff: 0x%" PRIx32 "h, addr: %llu, size: %llu", (uint32_t)buffer, addr, size); + while (size > 0) { // Write on _page_size_bytes boundaries (Default 256 bytes a page) @@ -344,9 +353,15 @@ int SPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size) int status = SPIF_BD_ERROR_OK; // Find region of erased address int region = _utils_find_addr_region(addr); + if (region < 0) { + tr_error("no region found for address %llu", addr); + return SPIF_BD_ERROR_INVALID_ERASE_PARAMS; + } // Erase Types of selected region uint8_t bitfield = _region_erase_types_bitfield[region]; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: erase - addr: %llu, in_size: %llu", addr, in_size); + if ((addr + in_size) > _device_size_bytes) { tr_error("erase exceeds flash device size"); return SPIF_BD_ERROR_INVALID_ERASE_PARAMS; @@ -367,6 +382,11 @@ int SPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size) offset = addr % _erase_type_size_arr[type]; chunk = ((offset + size) < _erase_type_size_arr[type]) ? size : (_erase_type_size_arr[type] - offset); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: erase - addr: %llu, size:%d, Inst: 0x%xh, chunk: %" PRIu32 " , ", + addr, size, cur_erase_inst, chunk); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: erase - Region: %d, Type:%d", + region, type); + _mutex->lock(); if (_set_write_enable() != 0) { @@ -424,7 +444,7 @@ bd_size_t SPIFBlockDevice::get_erase_size() const } // Find minimal erase size supported by the region to which the address belongs to -bd_size_t SPIFBlockDevice::get_erase_size(bd_addr_t addr) +bd_size_t SPIFBlockDevice::get_erase_size(bd_addr_t addr) const { // Find region of current address int region = _utils_find_addr_region(addr); @@ -550,6 +570,7 @@ spif_bd_error SPIFBlockDevice::_spi_send_program_command(int prog_inst, const vo spif_bd_error SPIFBlockDevice::_spi_send_erase_command(int erase_inst, bd_addr_t addr, bd_size_t size) { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Erase Inst: 0x%xh, addr: %llu, size: %llu", erase_inst, addr, size); addr = (((int)addr) & 0xFFFFF000); _spi_send_general_command(erase_inst, addr, NULL, 0, NULL, 0); return SPIF_BD_ERROR_OK; @@ -677,7 +698,7 @@ int SPIFBlockDevice::_sfdp_parse_basic_param_table(uint32_t basic_table_addr, si (param_table[5] << 8) | param_table[4]); _device_size_bytes = (density_bits + 1) / 8; - tr_debug("Density bits: %ld , device size: %llu bytes", density_bits, _device_size_bytes); + tr_debug("Density bits: %" PRIu32 " , device size: %llu bytes", density_bits, _device_size_bytes); // Set Default read/program/erase Instructions _read_instruction = SPIF_READ; @@ -722,10 +743,13 @@ int SPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_t if (!(memcmp(&sfdp_header[0], "SFDP", 4) == 0 && sfdp_header[5] == 1)) { tr_error("init - _verify SFDP signature and version Failed"); return -1; + } else { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: init - verified SFDP Signature and version Successfully"); } // Discover Number of Parameter Headers int number_of_param_headers = (int)(sfdp_header[6]) + 1; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: number of Param Headers: %d", number_of_param_headers); addr += SPIF_SFDP_HEADER_SIZE; data_length = SPIF_PARAM_HEADER_SIZE; @@ -748,12 +772,14 @@ int SPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_t if ((param_header[0] == 0) && (param_header[7] == 0xFF)) { // Found Basic Params Table: LSB=0x00, MSB=0xFF + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Found Basic Param Table at Table: %d", i_ind + 1); basic_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4])); // Supporting up to 64 Bytes Table (16 DWORDS) basic_table_size = ((param_header[3] * 4) < SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES) ? (param_header[3] * 4) : 64; } else if ((param_header[0] == 81) && (param_header[7] == 0xFF)) { // Found Sector Map Table: LSB=0x81, MSB=0xFF + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Found Sector Map Table at Table: %d", i_ind + 1); sector_map_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4])); sector_map_table_size = param_header[3] * 4; @@ -772,6 +798,9 @@ unsigned int SPIFBlockDevice::_sfdp_detect_page_size(uint8_t *basic_param_table_ // Page Size is specified by 4 Bits (N), calculated by 2^N int page_to_power_size = ((int)basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE]) >> 4; page_size = local_math_power(2, page_to_power_size); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Detected Page Size: %d", page_size); + } else { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Using Default Page Size: %d", page_size); } return page_size; } @@ -793,6 +822,8 @@ int SPIFBlockDevice::_sfdp_detect_erase_types_inst_and_size(uint8_t *basic_param erase_type_inst_arr[i_ind] = 0xff; //0xFF default for unsupported type erase_type_size_arr[i_ind] = local_math_power(2, basic_param_table_ptr[SPIF_BASIC_PARAM_ERASE_TYPE_1_SIZE_BYTE + 2 * i_ind]); // Size given as 2^N + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Erase Type(A) %d - Inst: 0x%xh, Size: %d", (i_ind + 1), erase_type_inst_arr[i_ind], + erase_type_size_arr[i_ind]); if (erase_type_size_arr[i_ind] > 1) { // if size==1 type is not supported erase_type_inst_arr[i_ind] = basic_param_table_ptr[SPIF_BASIC_PARAM_ERASE_TYPE_1_BYTE + 2 * i_ind]; @@ -814,7 +845,8 @@ int SPIFBlockDevice::_sfdp_detect_erase_types_inst_and_size(uint8_t *basic_param } _region_erase_types_bitfield[0] |= bitfield; // If there's no region map, set region "0" types bitfield as defualt; } - + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "INFO: Erase Type %d - Inst: 0x%xh, Size: %d", (i_ind + 1), + erase_type_inst_arr[i_ind], erase_type_size_arr[i_ind]); bitfield = bitfield << 1; } } @@ -841,6 +873,7 @@ int SPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ read_inst = basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE]; _read_dummy_and_mode_cycles = (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5) + (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "\nDEBUG: Read Bus Mode set to 2-2-2, Instruction: 0x%xh", read_inst); break; } } @@ -850,6 +883,7 @@ int SPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ read_inst = basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE]; _read_dummy_and_mode_cycles = (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5) + (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "\nDEBUG: Read Bus Mode set to 1-2-2, Instruction: 0x%xh", read_inst); break; } if (examined_byte & 0x01) { @@ -857,10 +891,12 @@ int SPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ read_inst = basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE]; _read_dummy_and_mode_cycles = (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5) + (basic_param_table_ptr[SPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F); + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "\nDEBUG: Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction); break; } */ _read_dummy_and_mode_cycles = 0; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "\nDEBUG: Read Bus Mode set to 1-1-1, Instruction: 0x%xh", read_inst); } while (false); return 0; @@ -871,10 +907,13 @@ int SPIFBlockDevice::_reset_flash_mem() // Perform Soft Reset of the Device prior to initialization int status = 0; char status_value[2] = {0}; + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "INFO: _reset_flash_mem:\n"); //Read the Status Register from device if (SPIF_BD_ERROR_OK == _spi_send_general_command(SPIF_RDSR, SPI_NO_ADDRESS_COMMAND, NULL, 0, status_value, 1)) { // store received values in status_value + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Reading Status Register Success: value = 0x%x\n", (int)status_value[0]); } else { + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "ERROR: Reading Status Register failed\n"); status = -1; } @@ -882,6 +921,7 @@ int SPIFBlockDevice::_reset_flash_mem() //Send Reset Enable if (SPIF_BD_ERROR_OK == _spi_send_general_command(SPIF_RSTEN, SPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) { // store received values in status_value + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Sending RSTEN Success\n"); } else { tr_error("Sending RSTEN failed"); status = -1; @@ -891,6 +931,7 @@ int SPIFBlockDevice::_reset_flash_mem() //Send Reset if (SPIF_BD_ERROR_OK == _spi_send_general_command(SPIF_RST, SPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) { // store received values in status_value + debug_if(MBED_CONF_SPIF_DRIVER_DEBUG, "DEBUG: Sending RST Success\n"); } else { tr_error("Sending RST failed"); status = -1; @@ -962,7 +1003,7 @@ int SPIFBlockDevice::_set_write_enable() /*********************************************/ /************* Utility Functions *************/ /*********************************************/ -int SPIFBlockDevice::_utils_find_addr_region(bd_size_t offset) +int SPIFBlockDevice::_utils_find_addr_region(bd_size_t offset) const { //Find the region to which the given offset belong to if ((offset > _device_size_bytes) || (_regions_count == 0)) { diff --git a/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.h b/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.h index e0e68c15e31..c7ab3b3987a 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.h +++ b/components/storage/blockdevice/COMPONENT_SPIF/SPIFBlockDevice.h @@ -170,7 +170,7 @@ class SPIFBlockDevice : public mbed::BlockDevice { * @return Size of minimal erase sector size, in given address region, in bytes * @note Must be a multiple of the program size */ - virtual mbed::bd_size_t get_erase_size(mbed::bd_addr_t addr); + virtual mbed::bd_size_t get_erase_size(mbed::bd_addr_t addr) const; /** Get the value of storage byte after it was erased * @@ -227,7 +227,7 @@ class SPIFBlockDevice : public mbed::BlockDevice { /* Utilities Functions */ /***********************/ // Find the region to which the given offset belongs to - int _utils_find_addr_region(bd_size_t offset); + int _utils_find_addr_region(bd_size_t offset) const; // Iterate on all supported Erase Types of the Region to which the offset belongs to. // Iterates from highest type to lowest diff --git a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index 51b8c7eace2..b0b4d7b5984 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -5,7 +5,12 @@ "SPI_MISO": "SPI_MISO", "SPI_CLK": "SPI_SCK", "SPI_CS": "SPI_CS", - "SPI_FREQ": "40000000" + "SPI_FREQ": "40000000", + "debug": { + "help": "Enable debug logs. [0/1]", + "options" : [0, 1], + "value": 0 + } }, "target_overrides": { "LPC54114": { diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/TESTS/cordio_hci/transport/main.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/TESTS/cordio_hci/transport/main.cpp index e5ee4bc235f..67067b83fbf 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/TESTS/cordio_hci/transport/main.cpp +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/TESTS/cordio_hci/transport/main.cpp @@ -31,26 +31,29 @@ using namespace utest::v1; using ble::vendor::cordio::CordioHCIDriver; using ble::vendor::cordio::CordioHCITransportDriver; -extern ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver(); +extern ble::vendor::cordio::CordioHCIDriver &ble_cordio_get_hci_driver(); #if CORDIO_ZERO_COPY_HCI #error [NOT_SUPPORTED] Test not relevant for zero copy hci. -#endif +#else namespace ble { namespace vendor { namespace cordio { struct CordioHCIHook { - static CordioHCIDriver& get_driver() { + static CordioHCIDriver &get_driver() + { return ble_cordio_get_hci_driver(); } - static CordioHCITransportDriver& get_transport_driver() { + static CordioHCITransportDriver &get_transport_driver() + { return get_driver()._transport_driver; } - static void set_data_received_handler(void (*handler)(uint8_t*, uint8_t)) { + static void set_data_received_handler(void (*handler)(uint8_t *, uint8_t)) + { get_transport_driver().set_data_received_handler(handler); } }; @@ -75,22 +78,24 @@ static const uint32_t WAITING_FLAGS = static rtos::EventFlags event_channel; -static void signal_flag(uint32_t flag) { +static void signal_flag(uint32_t flag) +{ if (!(event_channel.get() & flag)) { event_channel.set(flag); } } -uint32_t wait_for_event() { +uint32_t wait_for_event() +{ // clear reception flags uint32_t flags = event_channel.get(); event_channel.clear(flags & ~RESET_RECEIVED_FLAG); return event_channel.wait_any( - WAITING_FLAGS, - /* timeout */ RESET_COMMAND_TIMEOUT, - /* clear */ false - ); + WAITING_FLAGS, + /* timeout */ RESET_COMMAND_TIMEOUT, + /* clear */ false + ); } // @@ -104,7 +109,8 @@ uint32_t wait_for_event() { #define RESET_PACKET_LENGTH (1 + HCI_EVT_HDR_LEN + RESET_PARAMETER_LENGTH) #define RESET_STATUS_INDEX 6 -static bool is_reset_event(const uint8_t* data, uint16_t len) { +static bool is_reset_event(const uint8_t *data, uint16_t len) +{ if (len != RESET_PACKET_LENGTH) { return false; } @@ -135,7 +141,8 @@ static bool is_reset_event(const uint8_t* data, uint16_t len) { return true; } -static void hci_driver_rx_reset_handler(uint8_t* data, uint8_t len) { +static void hci_driver_rx_reset_handler(uint8_t *data, uint8_t len) +{ enum packet_state_t { WAITING_FOR_PACKET_TYPE, WAITING_FOR_HEADER_COMPLETE, @@ -166,19 +173,20 @@ static void hci_driver_rx_reset_handler(uint8_t* data, uint8_t len) { case WAITING_FOR_HEADER_COMPLETE: case WAITING_FOR_DATA_COMPLETE: { - uint16_t step = std::min((uint16_t) len, (uint16_t) (packet_length - position)); + uint16_t step = std::min((uint16_t) len, (uint16_t)(packet_length - position)); memcpy(packet + position, data, step); - position+= step; + position += step; data += step; len -= step; if (reception_state == WAITING_FOR_HEADER_COMPLETE && - position == packet_length - ) { + position == packet_length + ) { reception_state = WAITING_FOR_DATA_COMPLETE; packet_length += packet[HCI_EVT_HDR_LEN]; } - } break; + } + break; // dead end; we never exit from the error state; just asignal it again. @@ -192,7 +200,7 @@ static void hci_driver_rx_reset_handler(uint8_t* data, uint8_t len) { } bool packet_complete = (reception_state == WAITING_FOR_DATA_COMPLETE) && - (position == packet_length); + (position == packet_length); if (packet_complete) { if (is_reset_event(packet, packet_length)) { @@ -217,9 +225,10 @@ static uint8_t reset_cmd[] = { 0 // parameter length }; -void test_reset_command() { - CordioHCIDriver& driver = CordioHCIHook::get_driver(); - CordioHCITransportDriver& transport_driver = CordioHCIHook::get_transport_driver(); +void test_reset_command() +{ + CordioHCIDriver &driver = CordioHCIHook::get_driver(); + CordioHCITransportDriver &transport_driver = CordioHCIHook::get_transport_driver(); driver.initialize(); @@ -235,9 +244,10 @@ void test_reset_command() { #define EXPECTED_CONSECUTIVE_RESET 10 -void test_multiple_reset_command() { - CordioHCIDriver& driver = CordioHCIHook::get_driver(); - CordioHCITransportDriver& transport_driver = CordioHCIHook::get_transport_driver(); +void test_multiple_reset_command() +{ + CordioHCIDriver &driver = CordioHCIHook::get_driver(); + CordioHCITransportDriver &transport_driver = CordioHCIHook::get_transport_driver(); driver.initialize(); @@ -260,13 +270,16 @@ Case cases[] = { Case("Test multiple reset commands", test_multiple_reset_command) }; -utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ GREENTEA_SETUP(15, "default_auto"); return verbose_test_setup_handler(number_of_cases); } Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); -int main() { +int main() +{ return !Harness::run(specification); } +#endif // CORDIO_ZERO_COPY_HCI diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/include/audio_board.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/include/audio_board.h index 0deee771ddf..05cb6ce0852 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/include/audio_board.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/include/audio_board.h @@ -24,7 +24,7 @@ #ifndef AUDIOBOARD_H #define AUDIOBOARD_H -#include "pal_types.h" +#include "stack/platform/include/pal_types.h" #include "nrf_gpio.h" #ifdef __cplusplus diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb.c index 8e84ba45a7e..f9ed39323a4 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb.c @@ -21,9 +21,8 @@ */ /*************************************************************************************************/ -#include "pal_types.h" -#include "pal_bb.h" -#include "pal_bb.h" +#include "stack/platform/include/pal_types.h" +#include "stack/platform/include/pal_bb.h" #include "nrf.h" #include "nrf_timer.h" #include diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble.c index e5f24196194..1f262043102 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble.c @@ -43,13 +43,12 @@ * */ -#include "pal_types.h" -#include "pal_bb.h" -#include "pal_rtc.h" -#include "pal_bb.h" -#include "pal_led.h" -#include "pal_bb_ble.h" -#include "pal_radio.h" +#include "stack/platform/include/pal_types.h" +#include "stack/platform/include/pal_bb.h" +#include "stack/platform/include/pal_rtc.h" +#include "stack/platform/include/pal_led.h" +#include "stack/platform/include/pal_bb_ble.h" +#include "stack/platform/include/pal_radio.h" #include "ll_defs.h" #include "boards.h" #include "nrf.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_cfg.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_cfg.c index 749fc5a78b2..f03c5e4c74d 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_cfg.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_cfg.c @@ -21,7 +21,7 @@ */ /*************************************************************************************************/ -#include "pal_cfg.h" +#include "stack/platform/include/pal_cfg.h" #include "nrf.h" /************************************************************************************************** diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_crypto.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_crypto.c index adf87e670d0..c230adc5eff 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_crypto.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_crypto.c @@ -21,8 +21,8 @@ */ /*************************************************************************************************/ -#include "pal_types.h" -#include "pal_bb_ble.h" +#include "stack/platform/include/pal_types.h" +#include "stack/platform/include/pal_bb_ble.h" #if defined(NRF52840_XXAA) && defined(FEATURE_CRYPTOCELL310) && MBED_CONF_CORDIO_LL_NRF52840_CRYPTOCELL310_ACCELERATION #include "crys_rsa_kg.h" #include "crys_dh.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_led.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_led.c index 450c342913e..5b6da04d845 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_led.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_led.c @@ -21,9 +21,9 @@ */ /*************************************************************************************************/ -#include "pal_led.h" +#include "stack/platform/include/pal_led.h" #include "boards.h" -#include "pal_types.h" +#include "stack/platform/include/pal_types.h" /************************************************************************************************** Macros diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_nvm.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_nvm.c index 1bbc8ad9e1b..4baca509674 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_nvm.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_nvm.c @@ -22,7 +22,7 @@ /*************************************************************************************************/ #include -#include "pal_nvm.h" +#include "stack/platform/include/pal_nvm.h" #include "sdk_config.h" #if defined(NRF52840_XXAA) #include "nrfx_qspi.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_rtc.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_rtc.c index 30427e9b2a7..ebdf3d95f5f 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_rtc.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_rtc.c @@ -22,7 +22,7 @@ /*************************************************************************************************/ #include "nrf.h" -#include "pal_rtc.h" +#include "stack/platform/include/pal_rtc.h" /*************************************************************************************************/ /*! diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_sys.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_sys.c index 1f53dd3bb41..10235e70c4b 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_sys.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_sys.c @@ -22,10 +22,10 @@ /*************************************************************************************************/ #include "nrf.h" -#include "pal_bb.h" -#include "pal_rtc.h" -#include "pal_sys.h" -#include "pal_led.h" +#include "stack/platform/include/pal_bb.h" +#include "stack/platform/include/pal_rtc.h" +#include "stack/platform/include/pal_sys.h" +#include "stack/platform/include/pal_led.h" #include "platform/mbed_power_mgmt.h" #include diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_timer.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_timer.c index c00ae9c106b..f59d4ec1eb4 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_timer.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_timer.c @@ -34,7 +34,7 @@ */ #include "nrf.h" -#include "pal_timer.h" +#include "stack/platform/include/pal_timer.h" #include "nrf_gpio.h" /************************************************************************************************** diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_twi.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_twi.c index b11ef1071b3..5f30efd882f 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_twi.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_twi.c @@ -22,7 +22,7 @@ /*************************************************************************************************/ #include -#include "pal_twi.h" +#include "stack/platform/include/pal_twi.h" #include "nrfx_twim.h" #include "nrf_twim.h" #include "app_util_platform.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_uart.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_uart.c index 034cbc7fc91..60f845db8c3 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_uart.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_uart.c @@ -21,7 +21,7 @@ */ /*************************************************************************************************/ -#include "pal_uart.h" +#include "stack/platform/include/pal_uart.h" #include "sdk_config.h" #include "nrfx_uarte.h" #include "boards.h" diff --git a/features/cellular/TESTS/api/cellular_device/main.cpp b/features/cellular/TESTS/api/cellular_device/main.cpp index bc925cc86a4..d471f176136 100644 --- a/features/cellular/TESTS/api/cellular_device/main.cpp +++ b/features/cellular/TESTS/api/cellular_device/main.cpp @@ -15,13 +15,10 @@ * limitations under the License. */ -#if !defined(MBED_CONF_NSAPI_PRESENT) -#error [NOT_SUPPORTED] A json configuration file is needed. Skipping this build. -#endif +#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) +#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. +#else -#ifndef MBED_CONF_APP_CELLULAR_SIM_PIN -#error [NOT_SUPPORTED] SIM pin code is needed. Skipping this build. -#endif #include "greentea-client/test_env.h" #include "unity.h" @@ -221,3 +218,4 @@ int main() return ret; } +#endif !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_information/main.cpp b/features/cellular/TESTS/api/cellular_information/main.cpp index 64052d29fcb..29897823291 100644 --- a/features/cellular/TESTS/api/cellular_information/main.cpp +++ b/features/cellular/TESTS/api/cellular_information/main.cpp @@ -16,16 +16,12 @@ */ -#if !defined(MBED_CONF_NSAPI_PRESENT) -#error [NOT_SUPPORTED] A json configuration file is needed. Skipping this build. -#endif +#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) +#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. +#else #include "CellularUtil.h" // for CELLULAR_ helper macros -#ifndef MBED_CONF_APP_CELLULAR_SIM_PIN -#error [NOT_SUPPORTED] SIM pin code is needed. Skipping this build. -#endif - #include "greentea-client/test_env.h" #include "unity.h" #include "utest.h" @@ -118,3 +114,4 @@ int main() #endif return ret; } +#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_network/main.cpp b/features/cellular/TESTS/api/cellular_network/main.cpp index 050b2ab1199..b21c44c9261 100644 --- a/features/cellular/TESTS/api/cellular_network/main.cpp +++ b/features/cellular/TESTS/api/cellular_network/main.cpp @@ -16,13 +16,9 @@ */ -#if !defined(MBED_CONF_NSAPI_PRESENT) -#error [NOT_SUPPORTED] A json configuration file is needed. Skipping this build. -#endif - -#ifndef MBED_CONF_APP_CELLULAR_SIM_PIN -#error [NOT_SUPPORTED] SIM pin code is needed. Skipping this build. -#endif +#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) +#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. +#else #include "greentea-client/test_env.h" #include "unity.h" @@ -252,3 +248,4 @@ int main() #endif return ret; } +#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_sms/main.cpp b/features/cellular/TESTS/api/cellular_sms/main.cpp index 79390bc0d6b..c1e7656c7a5 100644 --- a/features/cellular/TESTS/api/cellular_sms/main.cpp +++ b/features/cellular/TESTS/api/cellular_sms/main.cpp @@ -16,17 +16,13 @@ */ -#if !defined(MBED_CONF_NSAPI_PRESENT) -#error [NOT_SUPPORTED] A json configuration file is needed. Skipping this build. -#endif - -#ifndef MBED_CONF_APP_CELLULAR_SIM_PIN -#error [NOT_SUPPORTED] SIM pin code is needed. Skipping this build. -#endif +#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) +#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. +#else #if defined(TARGET_ADV_WISE_1570) || defined(TARGET_MTB_ADV_WISE_1570) #error [NOT_SUPPORTED] target MTB_ADV_WISE_1570 does not have SMS functionality -#endif +#else #include "greentea-client/test_env.h" #include "unity.h" @@ -260,3 +256,6 @@ int main() #endif return ret; } + +#endif //defined(TARGET_ADV_WISE_1570) || defined(TARGET_MTB_ADV_WISE_1570) +#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/socket/udp/main.cpp b/features/cellular/TESTS/socket/udp/main.cpp index 9a9c67ea387..3efd3814cd8 100644 --- a/features/cellular/TESTS/socket/udp/main.cpp +++ b/features/cellular/TESTS/socket/udp/main.cpp @@ -15,16 +15,12 @@ * limitations under the License. */ -#if !defined(MBED_CONF_NSAPI_PRESENT) -#error [NOT_SUPPORTED] A json configuration file is needed. Skipping this build. -#endif +#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) +#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. +#else #include "CellularUtil.h" // for CELLULAR_ helper macros -#ifndef MBED_CONF_APP_CELLULAR_SIM_PIN -#error [NOT_SUPPORTED] SIM pin code is needed. Skipping this build. -#endif - #include "greentea-client/test_env.h" #include "unity.h" #include "utest.h" @@ -218,3 +214,4 @@ int main() #endif return ret; } +#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index 40ddbeaf571..e7039283e07 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -238,6 +238,16 @@ const char *AT_CellularContext::get_ip_address() #endif } +char *AT_CellularContext::get_interface_name(char *interface_name) +{ + if (_cid < 0) { + return NULL; + } + MBED_ASSERT(interface_name); + sprintf(interface_name, "ce%02d", _cid); + return interface_name; +} + void AT_CellularContext::attach(Callback status_cb) { _status_cb = status_cb; @@ -469,7 +479,30 @@ nsapi_error_t AT_CellularContext::do_activate_context() nsapi_error_t AT_CellularContext::activate_ip_context() { - return find_and_activate_context(); + nsapi_error_t ret = find_and_activate_context(); +#if !NSAPI_PPP_AVAILABLE + if (ret == NSAPI_ERROR_OK) { + pdpContextList_t params_list; + if (get_pdpcontext_params(params_list) == NSAPI_ERROR_OK) { + pdpcontext_params_t *pdp = params_list.get_head(); + while (pdp) { + SocketAddress addr; + if (addr.set_ip_address(pdp->dns_secondary_addr)) { + tr_info("DNS secondary %s", pdp->dns_secondary_addr); + char ifn[5]; // "ce" + two digit _cid + zero + add_dns_server(addr, get_interface_name(ifn)); + } + if (addr.set_ip_address(pdp->dns_primary_addr)) { + tr_info("DNS primary %s", pdp->dns_primary_addr); + char ifn[5]; // "ce" + two digit _cid + zero + add_dns_server(addr, get_interface_name(ifn)); + } + pdp = pdp->next; + } + } + } +#endif + return ret; } nsapi_error_t AT_CellularContext::activate_non_ip_context() diff --git a/features/cellular/framework/AT/AT_CellularContext.h b/features/cellular/framework/AT/AT_CellularContext.h index a5da94daa99..9831d9b9fab 100644 --- a/features/cellular/framework/AT/AT_CellularContext.h +++ b/features/cellular/framework/AT/AT_CellularContext.h @@ -36,6 +36,7 @@ class AT_CellularContext : public CellularContext, public AT_CellularBase { virtual nsapi_error_t set_blocking(bool blocking); virtual NetworkStack *get_stack(); virtual const char *get_ip_address(); + virtual char *get_interface_name(char *interface_name); virtual void attach(mbed::Callback status_cb); virtual nsapi_error_t connect(); virtual nsapi_error_t disconnect(); diff --git a/features/cellular/framework/device/CellularDevice.cpp b/features/cellular/framework/device/CellularDevice.cpp index d9055a65de0..8326864cdb0 100644 --- a/features/cellular/framework/device/CellularDevice.cpp +++ b/features/cellular/framework/device/CellularDevice.cpp @@ -124,13 +124,6 @@ nsapi_error_t CellularDevice::create_state_machine() _nw->attach(callback(this, &CellularDevice::stm_callback)); _state_machine = new CellularStateMachine(*this, *get_queue(), *_nw); _state_machine->set_cellular_callback(callback(this, &CellularDevice::stm_callback)); - err = _state_machine->start_dispatch(); - if (err) { - tr_error("Start state machine failed."); - delete _state_machine; - _state_machine = NULL; - } - if (strlen(_plmn)) { _state_machine->set_plmn(_plmn); } @@ -138,6 +131,13 @@ nsapi_error_t CellularDevice::create_state_machine() _state_machine->set_sim_pin(_sim_pin); } } + err = _state_machine->start_dispatch(); + if (err) { + tr_error("Start state machine failed."); + delete _state_machine; + _state_machine = NULL; + return err; + } return err; } diff --git a/features/cellular/framework/device/CellularStateMachine.cpp b/features/cellular/framework/device/CellularStateMachine.cpp index deafc391cae..3af35d48c2c 100644 --- a/features/cellular/framework/device/CellularStateMachine.cpp +++ b/features/cellular/framework/device/CellularStateMachine.cpp @@ -103,7 +103,6 @@ void CellularStateMachine::stop() { tr_debug("CellularStateMachine stop"); if (_queue_thread) { - _queue.break_dispatch(); _queue_thread->terminate(); delete _queue_thread; _queue_thread = NULL; @@ -366,6 +365,9 @@ void CellularStateMachine::state_device_ready() _status = 0; enter_to_state(STATE_SIM_PIN); } + } else { + _status = 0; + enter_to_state(STATE_INIT); } } if (_cb_data.error != NSAPI_ERROR_OK) { @@ -546,7 +548,7 @@ bool CellularStateMachine::get_current_status(CellularStateMachine::CellularStat void CellularStateMachine::event() { // Don't send Signal quality when in signal quality state or it can confuse callback functions when running retry logic - if (_state != STATE_SIGNAL_QUALITY) { + if (_state > STATE_SIGNAL_QUALITY) { _cb_data.error = _network.get_signal_quality(_signal_quality.rssi, &_signal_quality.ber); _cb_data.data = &_signal_quality; @@ -624,15 +626,21 @@ void CellularStateMachine::event() nsapi_error_t CellularStateMachine::start_dispatch() { - MBED_ASSERT(!_queue_thread); + if (!_queue_thread) { + _queue_thread = new rtos::Thread(osPriorityNormal, 2048, NULL, "stm_queue"); + _event_id = STM_STOPPED; + } - _queue_thread = new rtos::Thread(osPriorityNormal, 2048, NULL, "stm_queue"); - if (_queue_thread->start(callback(&_queue, &events::EventQueue::dispatch_forever)) != osOK) { - report_failure("Failed to start thread."); - stop(); - return NSAPI_ERROR_NO_MEMORY; + if (_event_id == STM_STOPPED) { + if (_queue_thread->start(callback(&_queue, &events::EventQueue::dispatch_forever)) != osOK) { + report_failure("Failed to start thread."); + stop(); + return NSAPI_ERROR_NO_MEMORY; + } } + _event_id = -1; + return NSAPI_ERROR_OK; } diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index b7c3743b7dd..9782361c721 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -111,31 +111,36 @@ nsapi_error_t QUECTEL_BG96::hard_power_on() nsapi_error_t QUECTEL_BG96::soft_power_on() { - if (_rst.is_connected()) { - tr_info("Reset modem"); - _rst = !_active_high; - ThisThread::sleep_for(100); - _rst = _active_high; - ThisThread::sleep_for(150 + 460); // RESET_N timeout from BG96_Hardware_Design_V1.1 - _rst = !_active_high; - ThisThread::sleep_for(500); + if (!_rst.is_connected()) { + return NSAPI_ERROR_OK; + } - // wait for RDY - _at->lock(); - _at->set_at_timeout(10 * 1000); - _at->resp_start(); - _at->set_stop_tag("RDY"); - bool rdy = _at->consume_to_stop_tag(); - _at->set_stop_tag(OK); - _at->restore_at_timeout(); - _at->unlock(); + tr_info("Reset modem"); + _rst = !_active_high; + ThisThread::sleep_for(100); + _rst = _active_high; + ThisThread::sleep_for(150 + 460); // RESET_N timeout from BG96_Hardware_Design_V1.1 + _rst = !_active_high; + ThisThread::sleep_for(500); - if (!rdy) { - return NSAPI_ERROR_DEVICE_ERROR; - } + // wait for RDY + _at->lock(); + _at->set_at_timeout(10 * 1000); + _at->resp_start(); + _at->set_stop_tag("RDY"); + bool rdy = _at->consume_to_stop_tag(); + _at->set_stop_tag(OK); + _at->restore_at_timeout(); + + if (!rdy) { + // check if modem was silently powered on + _at->clear_error(); + _at->set_at_timeout(100); + _at->cmd_start("AT"); + _at->cmd_stop_read_resp(); + _at->restore_at_timeout(); } - - return NSAPI_ERROR_OK; + return _at->unlock_return_error(); } nsapi_error_t QUECTEL_BG96::hard_power_off() @@ -162,26 +167,22 @@ nsapi_error_t QUECTEL_BG96::init() _at->cmd_start("AT+CMEE=1"); // verbose responses _at->cmd_stop_read_resp(); - if (_at->get_last_error() == NSAPI_ERROR_OK) { - do { - _at->cmd_start("AT+CFUN=1"); // set full functionality - _at->cmd_stop_read_resp(); - - // CFUN executed ok - if (_at->get_last_error() != NSAPI_ERROR_OK) { - // wait some time that modem gets ready for CFUN command, and try again - retry++; - _at->flush(); - ThisThread::sleep_for(64); // experimental value - } else { - // yes continue - break; - } - - /* code */ - } while ((retry < 3)); + if (_at->get_last_error() != NSAPI_ERROR_OK) { + return _at->unlock_return_error(); } + do { + _at->clear_error(); + _at->cmd_start("AT+CFUN=1"); // set full functionality + _at->cmd_stop_read_resp(); + if (_at->get_last_error() == NSAPI_ERROR_OK) { + break; + } + // wait some time that modem gets ready for CFUN command, and try again + retry++; + ThisThread::sleep_for(64); // experimental value + } while (retry < 3); + return _at->unlock_return_error(); } diff --git a/features/device_key/TESTS/device_key/functionality/main.cpp b/features/device_key/TESTS/device_key/functionality/main.cpp index 7be7afabf8f..a0cd524c117 100644 --- a/features/device_key/TESTS/device_key/functionality/main.cpp +++ b/features/device_key/TESTS/device_key/functionality/main.cpp @@ -29,7 +29,7 @@ using namespace mbed; #if !DEVICEKEY_ENABLED #error [NOT_SUPPORTED] DeviceKey needs to be enabled for this test -#endif +#else #define MSG_VALUE_DUMMY "0" #define MSG_VALUE_LEN 32 @@ -499,3 +499,4 @@ int main() return ret; } +#endif // !DEVICEKEY_ENABLED diff --git a/features/frameworks/greentea-client/greentea-client/greentea_serial.h b/features/frameworks/greentea-client/greentea-client/greentea_serial.h index 111204c3266..ff0901cbfe8 100644 --- a/features/frameworks/greentea-client/greentea-client/greentea_serial.h +++ b/features/frameworks/greentea-client/greentea-client/greentea_serial.h @@ -4,6 +4,8 @@ #ifndef GREENTEA_SERIAL_H #define GREENTEA_SERIAL_H +#if DEVICE_SERIAL + #include "RawSerial.h" #include "SingletonPtr.h" @@ -16,3 +18,4 @@ extern SingletonPtr greentea_serial; #endif /** @}*/ +#endif \ No newline at end of file diff --git a/features/frameworks/greentea-client/source/greentea_serial.cpp b/features/frameworks/greentea-client/source/greentea_serial.cpp index 3a4b8053f82..6f80a69a1db 100644 --- a/features/frameworks/greentea-client/source/greentea_serial.cpp +++ b/features/frameworks/greentea-client/source/greentea_serial.cpp @@ -1,5 +1,7 @@ #include "greentea-client/greentea_serial.h" +#if DEVICE_SERIAL + /** * Macros for setting console flow control. */ @@ -21,3 +23,5 @@ GreenteaSerial::GreenteaSerial() : mbed::RawSerial(USBTX, USBRX, MBED_CONF_PLATF set_flow_control(SerialBase::RTSCTS, STDIO_UART_RTS, STDIO_UART_CTS); #endif } + +#endif \ No newline at end of file diff --git a/features/frameworks/greentea-client/source/greentea_test_env.cpp b/features/frameworks/greentea-client/source/greentea_test_env.cpp index 89ee51c39c8..e909c29ce7c 100644 --- a/features/frameworks/greentea-client/source/greentea_test_env.cpp +++ b/features/frameworks/greentea-client/source/greentea_test_env.cpp @@ -15,6 +15,8 @@ * limitations under the License. */ +#if DEVICE_SERIAL + #include #include #include @@ -780,3 +782,5 @@ static int HandleKV(char *out_key, getNextToken(0, 0); return 0; } + +#endif \ No newline at end of file diff --git a/features/frameworks/utest/source/unity_handler.cpp b/features/frameworks/utest/source/unity_handler.cpp index b11454acd3a..2b9b52000b2 100644 --- a/features/frameworks/utest/source/unity_handler.cpp +++ b/features/frameworks/utest/source/unity_handler.cpp @@ -19,7 +19,10 @@ #include "utest/utest_harness.h" #include "utest/utest_stack_trace.h" #include "utest/unity_handler.h" + +#if DEVICE_SERIAL #include "greentea-client/greentea_serial.h" +#endif void utest_unity_assert_failure(void) { @@ -33,9 +36,10 @@ void utest_unity_ignore_failure(void) utest::v1::Harness::raise_failure(utest::v1::failure_reason_t(utest::v1::REASON_ASSERTION | utest::v1::REASON_IGNORE)); } +#if DEVICE_SERIAL void utest_safe_putc(int chr) { greentea_serial->putc(chr); } - +#endif diff --git a/features/frameworks/utest/source/utest_default_handlers.cpp b/features/frameworks/utest/source/utest_default_handlers.cpp index f487e2dcea6..63171e87488 100644 --- a/features/frameworks/utest/source/utest_default_handlers.cpp +++ b/features/frameworks/utest/source/utest_default_handlers.cpp @@ -16,6 +16,8 @@ **************************************************************************** */ +#if DEVICE_SERIAL + #include "utest/utest_default_handlers.h" #include "utest/utest_case.h" #include "utest/utest_stack_trace.h" @@ -102,3 +104,5 @@ utest::v1::status_t utest::v1::verbose_case_failure_handler(const Case *const /* if (failure.reason & REASON_IGNORE) return STATUS_IGNORE; return STATUS_CONTINUE; } + +#endif \ No newline at end of file diff --git a/features/frameworks/utest/utest/utest_serial.h b/features/frameworks/utest/utest/utest_serial.h index 640577181c2..8d94e21a3bc 100644 --- a/features/frameworks/utest/utest/utest_serial.h +++ b/features/frameworks/utest/utest/utest_serial.h @@ -19,6 +19,8 @@ **************************************************************************** */ +#if DEVICE_SERIAL + #ifndef UTEST_SERIAL_H #define UTEST_SERIAL_H @@ -29,3 +31,5 @@ #endif // UTEST_SERIAL_H /** @}*/ + +#endif \ No newline at end of file diff --git a/features/lwipstack/mbed_lib.json b/features/lwipstack/mbed_lib.json index 1ccdbcddc21..0480acc9fcb 100644 --- a/features/lwipstack/mbed_lib.json +++ b/features/lwipstack/mbed_lib.json @@ -217,6 +217,20 @@ "pbuf-pool-size": 48, "mem-size": 65536 }, + "CY8CKIT_062S2_43012": { + "tcpip-thread-stacksize": 8192, + "default-thread-stacksize": 640, + "ppp-thread-stacksize": 896, + "memp-num-tcp-seg": 24, + "tcp-socket-max": 10, + "udp-socket-max":10, + "socket-max":18, + "tcp-mss": 1540, + "tcp-snd-buf": "(6 * TCP_MSS)", + "tcp-wnd": "(TCP_MSS * 6)", + "pbuf-pool-size": 96, + "mem-size": 92610 + }, "MIMXRT1050_EVK": { "mem-size": 36560 }, diff --git a/features/nanostack/coap-service/source/coap_message_handler.c b/features/nanostack/coap-service/source/coap_message_handler.c index a40f138b6b4..d4cef6a5ea7 100644 --- a/features/nanostack/coap-service/source/coap_message_handler.c +++ b/features/nanostack/coap-service/source/coap_message_handler.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Arm Limited and affiliates. + * Copyright (c) 2015-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -192,14 +192,16 @@ static int8_t coap_rx_function(sn_coap_hdr_s *resp_ptr, sn_nsdl_addr_s *address_ coap_transaction_t *this = NULL; (void)param; - if (resp_ptr->coap_status == COAP_STATUS_BUILDER_BLOCK_SENDING_DONE) { - return 0; + if (!resp_ptr || !address_ptr) { + return -1; } tr_warn("transaction was not handled %d", resp_ptr->msg_id); - if (!resp_ptr || !address_ptr) { - return -1; + + if (resp_ptr->coap_status == COAP_STATUS_BUILDER_BLOCK_SENDING_DONE) { + return 0; } + if (resp_ptr->token_ptr) { this = transaction_find_client_by_token(resp_ptr->token_ptr, resp_ptr->token_len, address_ptr->addr_ptr, address_ptr->port); } diff --git a/features/nanostack/sal-stack-nanostack/Makefile b/features/nanostack/sal-stack-nanostack/Makefile index 67d9d854d1f..17a7f5512b7 100644 --- a/features/nanostack/sal-stack-nanostack/Makefile +++ b/features/nanostack/sal-stack-nanostack/Makefile @@ -65,6 +65,7 @@ $(TESTDIRS): $(CLEANTESTDIRS): @make -C $(@:clean-%=%) clean + @rm -fr results .PHONY: release release: diff --git a/features/nanostack/sal-stack-nanostack/nanostack/fhss_config.h b/features/nanostack/sal-stack-nanostack/nanostack/fhss_config.h index debb62503f7..a388f5643f4 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/fhss_config.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/fhss_config.h @@ -183,6 +183,12 @@ typedef struct fhss_statistics { /** FHSS synchronization lost counter. */ uint32_t fhss_synch_lost; + + /** FHSS TX to unknown neighbour counter. */ + uint32_t fhss_unknown_neighbor; + + /** FHSS channel retry counter. */ + uint32_t fhss_channel_retry; } fhss_statistics_t; /** diff --git a/features/nanostack/sal-stack-nanostack/nanostack/net_fhss.h b/features/nanostack/sal-stack-nanostack/nanostack/net_fhss.h index b201420e14f..6d6003c9861 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/net_fhss.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/net_fhss.h @@ -76,6 +76,14 @@ extern int ns_fhss_ws_configuration_set(const fhss_api_t *fhss_api, const fhss_w */ extern int ns_fhss_delete(fhss_api_t *fhss_api); +/** + * @brief Starts collecting FHSS statistics. + * @param fhss_api FHSS instance. + * @param fhss_statistics Pointer to stored statistics. + * @return 0 on success, -1 on fail. + */ +extern int ns_fhss_statistics_start(const fhss_api_t *fhss_api, fhss_statistics_t *fhss_statistics); + #ifdef __cplusplus } diff --git a/features/nanostack/sal-stack-nanostack/nanostack/ns_conf.h b/features/nanostack/sal-stack-nanostack/nanostack/ns_conf.h new file mode 100644 index 00000000000..c8e6d506023 --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/nanostack/ns_conf.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _NS_CONF_H_ +#define _NS_CONF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \file ns_conf.h + * \brief Nanostack configuration API. + */ + +/** + * \brief Set threshold for memory garbage collection. + * + * Nanostack heap usage is monitored in regular intervals. If too much memory has been used then garbage collection (GC) + * is triggered. GC has two adjustable thresholds: HIGH and CRITICAL. HIGH threshold is lower one and once exceeded + * a GC will try to release memory that is used for caching. When CRITTICAL threshold is exceeded them GC will try to release + * memory more aggressiveliy. + * + * Nanostack memory monitoring can only work if memory statistics are enabled in nsdynmemLIB. + + * + * \param percentage_high Percentage of total heap when garbage collection is first time triggered + * \param percentage_critical Percentage of total heap when critical garbage collection is triggered + * + * \return 0 in success, negative value in case of error. + * + */ +int ns_conf_gc_threshold_set(uint8_t percentage_high, uint8_t percentage_critical); + +/** + * \brief Limit amount of incoming packets if system does not have enough free memory. + * Memory statistics must been initialized in nsdynmemLIB to get this feature working. + * + * \param free_heap_percentage Percentage of free heap that must be available when packet arrives to MAC layer. + * \return 0 in case of success, <0 otherwise. + */ +int ns_conf_packet_ingress_rate_limit_by_mem(uint8_t free_heap_percentage); + +#ifdef __cplusplus +} +#endif + +#endif /* _NS_CONF_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/nanostack/ns_file_system.h b/features/nanostack/sal-stack-nanostack/nanostack/ns_file_system.h index 8fac78ccef3..00ce97eb320 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/ns_file_system.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/ns_file_system.h @@ -18,6 +18,10 @@ #ifndef _NS_FILE_SYSTEM_H_ #define _NS_FILE_SYSTEM_H_ +#ifdef __cplusplus +extern "C" { +#endif + /** * \file ns_file_system.h * \brief Nanostack file system API. @@ -35,9 +39,7 @@ * \return 0 in success, negative value in case of error. * */ -#ifdef __cplusplus -extern "C" { -#endif + int ns_file_system_set_root_path(const char *root_path); /** @@ -47,6 +49,7 @@ int ns_file_system_set_root_path(const char *root_path); * */ char *ns_file_system_get_root_path(void); + #ifdef __cplusplus } #endif diff --git a/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h b/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h index 3ebbd152775..000f53c73ba 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, Arm Limited and affiliates. + * Copyright (c) 2016-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -81,6 +81,13 @@ extern struct fhss_api *ns_sw_mac_get_fhss_api(struct mac_api_s *mac_api); */ extern int ns_sw_mac_statistics_start(struct mac_api_s *mac_api, struct mac_statistics_s *mac_statistics); +/** + * @brief Read current timestamp. + * @param mac_api MAC instance. + * @return Current timestamp in us + */ +extern uint32_t ns_sw_mac_read_current_timestamp(struct mac_api_s *mac_api); + #ifdef __cplusplus } #endif diff --git a/features/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h b/features/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h index a52809d0a45..604de467f0d 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h @@ -77,6 +77,7 @@ extern "C" { #define NETWORK_SIZE_AUTOMATIC 0x00 #define NETWORK_SIZE_SMALL 0x01 +#define NETWORK_SIZE_MEDIUM 0x08 #define NETWORK_SIZE_LARGE 0x10 @@ -85,6 +86,16 @@ extern "C" { */ #define WS_MANAGEMENT_API_VER_2 +/** + * \brief Struct ws_statistics defines the Wi-SUN statistics storage structure. + */ +typedef struct ws_statistics { + /** Asynch TX counter */ + uint32_t asynch_tx_count; + /** Asynch RX counter */ + uint32_t asynch_rx_count; +} ws_statistics_t; + /** * Initialize Wi-SUN stack. * @@ -255,6 +266,30 @@ int ws_management_fhss_broadcast_channel_function_configure( uint8_t dwell_interval, uint32_t broadcast_interval); +/** + * Start collecting Wi-SUN statistics. + * + * \param interface_id Network interface ID. + * \param stats_ptr Pointer to stored statistics. + * + * \return 0 Success. + * \return <0 Failure. + */ +int ws_statistics_start( + int8_t interface_id, + ws_statistics_t *stats_ptr); + +/** + * Stop collecting Wi-SUN statistics. + * + * \param interface_id Network interface ID. + * + * \return 0 Success. + * \return <0 Failure. + */ +int ws_statistics_stop( + int8_t interface_id); + #ifdef __cplusplus } #endif diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c index 5f3f17beccb..e6b009e500a 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c @@ -1605,7 +1605,7 @@ static void lowpan_neighbor_entry_remove_notify(mac_neighbor_table_entry_t *entr protocol_6lowpan_release_short_link_address_from_neighcache(cur_interface, entry_ptr->mac16); protocol_6lowpan_release_long_link_address_from_neighcache(cur_interface, entry_ptr->mac64); } - mac_helper_devicetable_remove(cur_interface->mac_api, entry_ptr->index); + mac_helper_devicetable_remove(cur_interface->mac_api, entry_ptr->index, entry_ptr->mac64); //Removes ETX neighbor etx_neighbor_remove(cur_interface->id, entry_ptr->index); //Remove MLE frame counter info diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c index 5bc8ee417f6..177113f46e3 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c @@ -866,7 +866,7 @@ int8_t mac_helper_link_frame_counter_set(int8_t interface_id, uint32_t seq_ptr) return 0; } -void mac_helper_devicetable_remove(mac_api_t *mac_api, uint8_t attribute_index) +void mac_helper_devicetable_remove(mac_api_t *mac_api, uint8_t attribute_index, uint8_t *mac64) { if (!mac_api) { return; @@ -880,7 +880,7 @@ void mac_helper_devicetable_remove(mac_api_t *mac_api, uint8_t attribute_index) set_req.attr_index = attribute_index; set_req.value_pointer = (void *)&device_desc; set_req.value_size = sizeof(mlme_device_descriptor_t); - tr_debug("unRegister Device"); + tr_debug("Unregister Device %u, mac64: %s", attribute_index, trace_array(mac64, 8)); mac_api->mlme_req(mac_api, MLME_SET, &set_req); } @@ -910,7 +910,7 @@ void mac_helper_devicetable_set(const mlme_device_descriptor_t *device_desc, pro set_req.attr_index = attribute_index; set_req.value_pointer = (void *)device_desc; set_req.value_size = sizeof(mlme_device_descriptor_t); - tr_debug("Register Device"); + tr_debug("Register Device %u, mac16 %x mac64: %s, %"PRIu32, attribute_index, device_desc->ShortAddress, trace_array(device_desc->ExtAddress, 8), device_desc->FrameCounter); cur->mac_api->mlme_req(cur->mac_api, MLME_SET, &set_req); } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h index 8435328a539..025df0313b1 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h @@ -115,7 +115,7 @@ int8_t mac_helper_link_frame_counter_read(int8_t interface_id, uint32_t *seq_ptr int8_t mac_helper_link_frame_counter_set(int8_t interface_id, uint32_t seq_ptr); -void mac_helper_devicetable_remove(struct mac_api_s *mac_api, uint8_t attribute_index); +void mac_helper_devicetable_remove(struct mac_api_s *mac_api, uint8_t attribute_index, uint8_t *mac64); void mac_helper_device_description_write(struct protocol_interface_info_entry *cur, mlme_device_descriptor_t *device_desc, uint8_t *mac64, uint16_t mac16, uint32_t frame_counter, bool exempt); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c index 9c8f50351f2..c397bfa66c8 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c @@ -855,8 +855,14 @@ static void nd_update_registration(protocol_interface_info_entry_t *cur_interfac */ mac_neighbor_table_entry_t *entry = mac_neighbor_table_address_discover(mac_neighbor_info(cur_interface), ipv6_neighbour_eui64(&cur_interface->ipv6_neighbour_cache, neigh), ADDR_802_15_4_LONG); - if (entry && !entry->ffd_device) { - rpl_control_publish_host_address(protocol_6lowpan_rpl_domain, neigh->ip_address, neigh->lifetime); + if (entry) { + if (ws_info(cur_interface)) { + ws_common_etx_validate(cur_interface, entry); + } + + if (!entry->ffd_device) { + rpl_control_publish_host_address(protocol_6lowpan_rpl_domain, neigh->ip_address, neigh->lifetime); + } } protocol_6lowpan_neighbor_address_state_synch(cur_interface, aro->eui64, neigh->ip_address + 8); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c index 953f0390912..36c3171b1be 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c @@ -2015,7 +2015,7 @@ void thread_reset_neighbour_info(protocol_interface_info_entry_t *cur, mac_neigh thread_routing_remove_link(cur, neighbour->mac16); thread_router_bootstrap_reset_child_info(cur, neighbour); protocol_6lowpan_release_long_link_address_from_neighcache(cur, neighbour->mac64); - mac_helper_devicetable_remove(cur->mac_api, neighbour->index); + mac_helper_devicetable_remove(cur->mac_api, neighbour->index, neighbour->mac64); thread_neighbor_class_entry_remove(&cur->thread_info->neighbor_class, neighbour->index); } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c index 2cabf92da23..12328fc57b0 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c @@ -40,25 +40,31 @@ #include "ws_bbr_api.h" -#define TRACE_GROUP "wsbs" +#define TRACE_GROUP "BBRw" #define RPL_INSTANCE_ID 1 #ifdef HAVE_WS_BORDER_ROUTER +#define WS_ULA_LIFETIME 24*3600 +#define WS_ROUTE_LIFETIME WS_ULA_LIFETIME +#define WS_DHCP_ADDRESS_LIFETIME 2*3600 +#define BBR_CHECK_INTERVAL 60 +#define BBR_BACKUP_ULA_DELAY 300 /* when creating BBR make ULA dodag ID always and when network becomes available add prefix to DHCP * * */ static int8_t backbone_interface_id = -1; // BBR backbone information -static uint16_t configuration = BBR_ULA_C | BBR_GUA_C | BBR_GUA_ROUTE; +static uint16_t configuration = 0; static uint8_t static_dodag_prefix[8] = {0xfd, 0x00, 0x61, 0x72, 0x6d}; -static uint8_t static_ula_address[16] = {0}; -static uint8_t static_dodag_id[16] = {0}; -static uint8_t global_dodag_id[16] = {0}; -static uint32_t bbr_delay_timer = 20; // initial delay. +static uint8_t current_dodag_id[16] = {0}; +static uint8_t current_local_prefix[8] = {0}; +static uint8_t current_global_prefix[8] = {0}; +static uint32_t bbr_delay_timer = BBR_CHECK_INTERVAL; // initial delay. +static uint32_t global_prefix_unavailable_timer = 0; // initial delay. static rpl_dodag_conf_t rpl_conf = { // Lifetime values @@ -68,7 +74,7 @@ static rpl_dodag_conf_t rpl_conf = { .authentication = 0, .path_control_size = 7, .dag_max_rank_increase = 2048, - .min_hop_rank_increase = 256, + .min_hop_rank_increase = 196, // DIO configuration .dio_interval_min = WS_RPL_DIO_IMIN, .dio_interval_doublings = WS_RPL_DIO_DOUBLING, @@ -115,31 +121,20 @@ static void ws_bbr_rpl_root_start(uint8_t *dodag_id) } // RPL memory limits set larger for Border router rpl_control_set_memory_limits(64 * 1024, 0); - // Save configured static id to check for changes later - memcpy(static_dodag_id, dodag_id, 16); } static void ws_bbr_rpl_root_stop(void) { tr_info("RPL root stop"); - rpl_control_delete_dodag_root(protocol_6lowpan_rpl_domain, protocol_6lowpan_rpl_root_dodag); - protocol_6lowpan_rpl_root_dodag = NULL; - memset(static_ula_address, 0, 16); - memset(static_dodag_id, 0, 16); - memset(global_dodag_id, 0, 16); -} - -static void ws_bbr_ula_prefix_enable(uint8_t *dodag_id) -{ - tr_info("RPL ula prefix start"); - - uint8_t t_flags = PIO_A; - - rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, dodag_id, 64, t_flags, 7200, 7200, false); - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, dodag_id, 64, 0x18, 7200, false); + if (protocol_6lowpan_rpl_root_dodag) { + rpl_control_delete_dodag_root(protocol_6lowpan_rpl_domain, protocol_6lowpan_rpl_root_dodag); + protocol_6lowpan_rpl_root_dodag = NULL; + } + memset(current_local_prefix, 0, 8); + memset(current_global_prefix, 0, 8); + memset(current_dodag_id, 0, 16); } - static int ws_border_router_proxy_validate(int8_t interface_id, uint8_t *address) { @@ -163,29 +158,24 @@ int ws_border_router_proxy_state_update(int8_t caller_interface_id, int8_t handl return -1; } - if (status) { - tr_debug("Border router Backhaul link ready"); - } else { - tr_debug("Border router Backhaul link down"); - } + tr_debug("Border router Backhaul link %s", status ? "ready" : "down"); return 0; } -static int ws_bbr_static_ula_create(protocol_interface_info_entry_t *cur) +static int ws_bbr_static_dodagid_create(protocol_interface_info_entry_t *cur) { - if (memcmp(static_ula_address, ADDR_UNSPECIFIED, 16) != 0) { + if (memcmp(current_dodag_id, ADDR_UNSPECIFIED, 16) != 0) { // address generated return 0; } - tr_info("BBR generate ula prefix"); - // This address is only used if no other address available. if_address_entry_t *add_entry = icmpv6_slaac_address_add(cur, static_dodag_prefix, 64, 0xffffffff, 0xffffffff, true, SLAAC_IID_FIXED); if (!add_entry) { + tr_err("dodagid create failed"); return -1; } - memcpy(static_ula_address, add_entry->address, 16); - tr_info("BBR generate ula prefix addr %s", trace_ipv6(static_ula_address)); + memcpy(current_dodag_id, add_entry->address, 16); + tr_info("BBR generate DODAGID %s", trace_ipv6(current_dodag_id)); addr_policy_table_add_entry(static_dodag_prefix, 64, 2, WS_NON_PREFFRED_LABEL); return 0; @@ -195,61 +185,53 @@ static int ws_bbr_static_ula_create(protocol_interface_info_entry_t *cur) * 0 static non rooted self generated own address * 1 static address with backbone connectivity */ -static int ws_bbr_static_dodag_get(protocol_interface_info_entry_t *cur, uint8_t *dodag_id_ptr) +static void ws_bbr_bb_static_prefix_get(uint8_t *dodag_id_ptr) { + /* Get static ULA prefix if we have configuration in backbone and there is address we use that. + * + * If there is no address we can use our own generated ULA as a backup ULA + */ + protocol_interface_info_entry_t *bb_interface = protocol_stack_interface_info_get_by_id(backbone_interface_id); if (bb_interface && bb_interface->ipv6_configure->ipv6_stack_mode == NET_IPV6_BOOTSTRAP_STATIC) { - // static configuration for ethernet available - ns_list_foreach(if_address_entry_t, add_entry, &cur->ip_addresses) { - if (memcmp(add_entry->address, bb_interface->ipv6_configure->static_prefix64, 8) == 0) { - //tr_info("BBR static config available"); - if (dodag_id_ptr) { - memcpy(dodag_id_ptr, add_entry->address, 16); - } - return 1; - } + if (protocol_address_prefix_cmp(bb_interface, bb_interface->ipv6_configure->static_prefix64, 64)) { + memcpy(dodag_id_ptr, bb_interface->ipv6_configure->static_prefix64, 8); } } - ws_bbr_static_ula_create(cur); - - // only own generated prefix available - if (dodag_id_ptr) { - memcpy(dodag_id_ptr, static_ula_address, 16); - } - - return 0; + return; } -static int ws_bbr_dodag_get(protocol_interface_info_entry_t *cur, uint8_t *static_dodag_id_ptr, uint8_t *dodag_id_ptr) +static void ws_bbr_dodag_get(uint8_t *local_prefix_ptr, uint8_t *global_prefix_ptr) { uint8_t global_address[16]; - if (static_dodag_id_ptr) { - memset(static_dodag_id_ptr, 0, 16); - } - - if (dodag_id_ptr) { - memset(dodag_id_ptr, 0, 16); - } + memset(global_prefix_ptr, 0, 8); - if (ws_bbr_static_dodag_get(cur, static_dodag_id_ptr) < 0) { - // no static configuration available - return -1; - } + // By default static dodagID prefix is used as local prefix + memcpy(local_prefix_ptr, current_dodag_id, 8); + ws_bbr_bb_static_prefix_get(local_prefix_ptr); if (arm_net_address_get(backbone_interface_id, ADDR_IPV6_GP, global_address) != 0) { // No global prefix available - return 0; + return; } - if (memcmp(global_address, dodag_id_ptr, 8) == 0) { - // static address is same - return 0; + protocol_interface_info_entry_t *bb_interface = protocol_stack_interface_info_get_by_id(backbone_interface_id); + if_address_entry_t *addr_entry = addr_get_entry(bb_interface, global_address); + + if (!addr_entry || addr_entry->preferred_lifetime == 0) { + return; } - memcpy(dodag_id_ptr, global_address, 16); - return 0; + //tr_debug("BBR address %s lifetime %d pref %d", trace_ipv6(addr_entry->address), addr_entry->valid_lifetime, addr_entry->preferred_lifetime); + + if (memcmp(global_address, local_prefix_ptr, 8) == 0) { + // static prefix is same + return; + } + memcpy(global_prefix_ptr, global_address, 8); + return; } static void wisun_bbr_na_send(int8_t interface_id, const uint8_t target[static 16]) { @@ -284,7 +266,7 @@ static void ws_bbr_dhcp_server_start(protocol_interface_info_entry_t *cur, uint8 memcpy(&ll[8], cur->mac, 8); ll[8] ^= 2; - tr_debug("DHCP server activate %s", trace_ipv6(global_id)); + tr_debug("DHCP server activate %s", trace_ipv6_prefix(global_id, 64)); if (DHCPv6_server_service_init(cur->id, global_id, cur->mac, DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE) != 0) { tr_error("DHCPv6 Server create fail"); @@ -293,7 +275,7 @@ static void ws_bbr_dhcp_server_start(protocol_interface_info_entry_t *cur, uint8 DHCPv6_server_service_callback_set(cur->id, global_id, NULL, wisun_dhcp_address_add_cb); DHCPv6_server_service_set_address_autonous_flag(cur->id, global_id, true); - DHCPv6_server_service_set_address_validlifetime(cur->id, global_id, 7200); + DHCPv6_server_service_set_address_validlifetime(cur->id, global_id, WS_DHCP_ADDRESS_LIFETIME); ws_dhcp_client_address_request(cur, global_id, ll); } @@ -307,86 +289,136 @@ static void ws_bbr_dhcp_server_stop(protocol_interface_info_entry_t *cur, uint8_ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) { - uint8_t static_id[16] = {0}; - uint8_t global_id[16] = {0}; + uint8_t local_prefix[8] = {0}; + uint8_t global_prefix[8] = {0}; //tr_info("BBR status check"); - ws_bbr_dodag_get(cur, static_id, global_id); + /* + * Start RPL Root + */ + if (!protocol_6lowpan_rpl_root_dodag) { + // Generate DODAGID + if (ws_bbr_static_dodagid_create(cur) == 0) { + ws_bbr_rpl_root_start(current_dodag_id); + } + } + + if (!protocol_6lowpan_rpl_root_dodag) { + // Failed to start + tr_info("BBR failed to start"); + return; + } + + /* + * Check that DODAGID is still valid + */ + if (protocol_interface_address_compare(current_dodag_id) != 0) { + //DODAGID is lost need to restart + tr_err("DODAGID lost restart RPL"); + memset(current_dodag_id, 0, 16); + ws_bbr_rpl_root_stop(); + return; + } - // Check if we need to wait for Global ID - if (configuration & BBR_GUA_WAIT) { - if (memcmp(global_dodag_id, ADDR_UNSPECIFIED, 16) == 0 && - memcmp(global_id, ADDR_UNSPECIFIED, 16) == 0) { - // We need to wait for Global connectivity to start anything - return; + ws_bbr_dodag_get(local_prefix, global_prefix); + tr_debug("BBR global %s, local %s", trace_ipv6_prefix(global_prefix, 64), trace_ipv6_prefix(local_prefix, 64)); + + /* + * Add default route to RPL + */ + rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, NULL, 0, 0, WS_ROUTE_LIFETIME, false); + + /* + * Create static ULA configuration or modify if needed + */ + if ((configuration & BBR_ULA_C) && + memcmp(current_local_prefix, local_prefix, 8) != 0) { + // Generate Static ULA + // Start static ULA prefix and routing always + if (memcmp(current_local_prefix, ADDR_UNSPECIFIED, 8) != 0) { + // Remove Old ULA prefix + rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, current_local_prefix, 64, PIO_A, 0, 0, true); + } + if (memcmp(local_prefix, ADDR_UNSPECIFIED, 8) != 0) { + tr_info("RPL Local prefix activate %s", trace_ipv6_prefix(local_prefix, 64)); + rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, local_prefix, 64, PIO_A, WS_ULA_LIFETIME, WS_ULA_LIFETIME, false); + memcpy(current_local_prefix, local_prefix, 8); } } - if (memcmp(static_dodag_id, static_id, 16) != 0) { - // Static id updated or first setup - ws_bbr_rpl_root_start(static_id); - if (configuration & BBR_ULA_C) { - // Start static ULA prefix and routing always - ws_bbr_ula_prefix_enable(static_id); + /* + * Check if backup ULA prefix is needed + */ + if (memcmp(global_prefix, ADDR_UNSPECIFIED, 8) == 0) { + //Global prefix not available count if backup ULA should be created + global_prefix_unavailable_timer += BBR_CHECK_INTERVAL; + tr_debug("Check for backup prefix %"PRIu32"", global_prefix_unavailable_timer); + if (global_prefix_unavailable_timer >= BBR_BACKUP_ULA_DELAY) { + if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) == 0) { + tr_info("start using backup prefix %s", trace_ipv6_prefix(local_prefix, 64)); + } + memcpy(global_prefix, local_prefix, 8); } + } else { + //Global connection OK + global_prefix_unavailable_timer = 0; } - if (memcmp(global_dodag_id, global_id, 16) != 0) { + /* + * Check for Global prefix + */ + if (memcmp(current_global_prefix, global_prefix, 8) != 0) { // Global prefix changed - if (memcmp(global_dodag_id, ADDR_UNSPECIFIED, 16) != 0) { + if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) != 0) { // TODO remove old global prefix - tr_info("RPL GUA deactivate %s", trace_ipv6(global_dodag_id)); + tr_info("RPL global prefix deactivate %s", trace_ipv6_prefix(current_global_prefix, 64)); // Old backbone information is deleted after 120 seconds - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, NULL, 0, 0, 0, true); - rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, global_dodag_id, 64, 0, 0, 0, true); - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, global_dodag_id, 64, 0, 0, true); - ipv6_route_add_with_info(global_dodag_id, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 120, 0); + rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, current_global_prefix, 64, 0, 0, 0, true); + if (configuration & BBR_GUA_ROUTE) { + rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, current_global_prefix, 64, 0, 0, true); + } + ipv6_route_add_with_info(current_global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 120, 0); - ws_bbr_dhcp_server_stop(cur, global_dodag_id); + ws_bbr_dhcp_server_stop(cur, current_global_prefix); } // TODO add global prefix - if (memcmp(global_id, ADDR_UNSPECIFIED, 16) != 0) { - //DHCPv6 Server flags set 0 by default - uint8_t t_flags = 0; + if (memcmp(global_prefix, ADDR_UNSPECIFIED, 8) != 0) { + tr_info("RPL global prefix activate %s", trace_ipv6_prefix(global_prefix, 64)); // Add default route to RPL - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, NULL, 0, 0, 7200, false); // Enable default routing to backbone - ipv6_route_add_with_info(global_id, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 0xffffffff, 0); - - if (configuration & BBR_GUA_SLAAC) { - // GUA prefix is using SLAAC so no DHCP started and set correct flags for prefix - t_flags = PIO_A; - icmpv6_slaac_address_add(cur, global_id, 64, 0xffffffff, 0xffffffff, true, SLAAC_IID_FIXED); - } else { - ws_bbr_dhcp_server_start(cur, global_id); + if (ipv6_route_add_with_info(global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 0xffffffff, 0) == NULL) { + tr_err("global route add failed"); + return; } + ws_bbr_dhcp_server_start(cur, global_prefix); + rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, global_prefix, 64, 0, 0, 0, false); + // no check for failure should have - if (configuration & BBR_GUA_C) { - // Add also global prefix and route to RPL - uint32_t valid_lifetime; - if (t_flags & PIO_A) { - valid_lifetime = 7200; - } else { - valid_lifetime = 0; - } - - rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, global_id, 64, t_flags, valid_lifetime, valid_lifetime, false); - - } if (configuration & BBR_GUA_ROUTE) { // Add also global prefix and route to RPL - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, global_id, 64, 0, 7200, false); + rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, global_prefix, 64, 0, WS_ROUTE_LIFETIME, false); } } - memcpy(global_dodag_id, global_id, 16); + memcpy(current_global_prefix, global_prefix, 8); rpl_control_increment_dodag_version(protocol_6lowpan_rpl_root_dodag); nd_proxy_downstream_interface_register(cur->id, ws_border_router_proxy_validate, ws_border_router_proxy_state_update); + } else if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) != 0) { + /* + * This is a keep alive validation RPL is updated to hold the real info. + * There is no status checks on prefix adds so this makes sure they are not lost + * DHCP validation should be done also + */ + rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, current_global_prefix, 64, 0, 0, 0, false); + + if (configuration & BBR_GUA_ROUTE) { + // Add also global prefix and route to RPL + rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, current_global_prefix, 64, 0, WS_ROUTE_LIFETIME, false); + } } - } void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) @@ -408,7 +440,7 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds if (bbr_delay_timer > seconds) { bbr_delay_timer -= seconds; } else { - bbr_delay_timer = 20; // 20 second interval between status checks + bbr_delay_timer = BBR_CHECK_INTERVAL; // 20 second interval between status checks // prequisists // Wi-SUN network configuration started without RPL @@ -425,16 +457,6 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds // 2. if GUA prefix becomes available in backend add new prefix to DODAG // 3. if GUA prefix is removed remove the prefix. - if (protocol_6lowpan_rpl_root_dodag) { - // Border router is active - if (0 != protocol_interface_address_compare(static_dodag_id)) { - // Dodag has become invalid need to delete - tr_info("RPL static dodag not valid anymore %s", trace_ipv6(static_dodag_id)); - ws_bbr_rpl_root_stop(); - } else { - - } - } ws_bbr_rpl_status_check(cur); } @@ -445,7 +467,7 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds } else { // Border router has timed out tr_debug("Border router version number update"); - cur->ws_info->pan_version_timer = PAN_VERSION_LIFETIME; + cur->ws_info->pan_version_timer = ws_common_version_lifetime_get(cur->ws_info->network_size_config); cur->ws_info->pan_information.pan_version++; // Inconsistent for border router to make information distribute faster ws_bootstrap_configuration_trickle_reset(cur); @@ -455,8 +477,8 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds } // We update the RPL version in same time to allow nodes to reselect parent // As configuration is made so that devices cant move downward in dodag this allows it - // TODO think the correct rate for this - if (cur->ws_info->pan_information.pan_version && cur->ws_info->pan_information.pan_version % RPL_VERSION_LIFETIME / PAN_VERSION_LIFETIME == 0) { + // Version number update is only done if DoDAG MAX Rank Increase parameter is 0 + if (rpl_conf.dag_max_rank_increase == 0 && cur->ws_info->pan_information.pan_version && cur->ws_info->pan_information.pan_version % RPL_VERSION_LIFETIME / cur->ws_info->pan_version_timer == 0) { // Third the rate of configuration version change at default 5 hours rpl_control_increment_dodag_version(protocol_6lowpan_rpl_root_dodag); } @@ -476,13 +498,12 @@ uint16_t ws_bbr_pan_size(protocol_interface_info_entry_t *cur) } // const uint8_t *prefix_ptr; - if ((configuration & (BBR_ULA_C | BBR_GUA_C)) == BBR_GUA_C) { - //Use just GUA Prefix - prefix_ptr = global_dodag_id; - + if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) != 0) { + //Use GUA Prefix + prefix_ptr = current_global_prefix; } else { //Use ULA for indentifier - prefix_ptr = static_dodag_id; + prefix_ptr = current_local_prefix; } rpl_control_get_instance_dao_target_count(cur->rpl_domain, RPL_INSTANCE_ID, NULL, prefix_ptr, &result); @@ -598,3 +619,4 @@ int ws_bbr_node_access_revoke_start(int8_t interface_id) return -1; #endif } + diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c index 2193e6eae86..6ab4c793bcc 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c @@ -53,6 +53,7 @@ #include "6LoWPAN/ws/ws_llc.h" #include "6LoWPAN/ws/ws_neighbor_class.h" #include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_stats.h" #include "6LoWPAN/lowpan_adaptation_interface.h" #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" @@ -80,7 +81,7 @@ static void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp static bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *cur); static int8_t ws_bootsrap_event_trig(ws_bootsrap_event_type_e event_type, int8_t interface_id, arm_library_event_priority_e priority, void *event_data); -static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new); +static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new, bool multicast); static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entry_t *cur); static uint16_t ws_bootstrap_rank_get(protocol_interface_info_entry_t *cur); static uint16_t ws_bootstrap_min_rank_inc_get(protocol_interface_info_entry_t *cur); @@ -90,10 +91,12 @@ static void ws_bootstrap_nw_key_set(protocol_interface_info_entry_t *cur, uint8_ static void ws_bootstrap_nw_key_clear(protocol_interface_info_entry_t *cur, uint8_t slot); static void ws_bootstrap_nw_key_index_set(protocol_interface_info_entry_t *cur, uint8_t index); static void ws_bootstrap_nw_frame_counter_set(protocol_interface_info_entry_t *cur, uint32_t counter); +static void ws_bootstrap_nw_frame_counter_read(protocol_interface_info_entry_t *cur, uint32_t *counter); static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_t *cur, bool success); static void ws_bootstrap_pan_version_increment(protocol_interface_info_entry_t *cur); static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry_t *cur, void *neighbor); static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *entry_ptr); +static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data); typedef enum { WS_PARENT_SOFT_SYNCH = 0, /**< let FHSS make decision if synchronization is needed*/ @@ -101,6 +104,13 @@ typedef enum { WS_EAPOL_PARENT_SYNCH, /**< Broadcast synch with EAPOL parent*/ } ws_parent_synch_e; +static void ws_bootsrap_create_ll_address(uint8_t *ll_address, const uint8_t *mac64) +{ + memcpy(ll_address, ADDR_LINK_LOCAL_PREFIX, 8); + memcpy(ll_address + 8, mac64, 8); + ll_address[8] ^= 2; +} + mac_neighbor_table_entry_t *ws_bootstrap_mac_neighbor_add(struct protocol_interface_info_entry *interface, const uint8_t *src64) { @@ -123,11 +133,11 @@ mac_neighbor_table_entry_t *ws_bootstrap_mac_neighbor_add(struct protocol_interf return neighbor; } -static void ws_bootstrap_neighbor_delete(struct protocol_interface_info_entry *interface, uint8_t attribute_index) +static void ws_bootstrap_neighbor_delete(struct protocol_interface_info_entry *interface, mac_neighbor_table_entry_t *entry_ptr) { - mac_helper_devicetable_remove(interface->mac_api, attribute_index); - etx_neighbor_remove(interface->id, attribute_index); - ws_neighbor_class_entry_remove(&interface->ws_info->neighbor_storage, attribute_index); + mac_helper_devicetable_remove(interface->mac_api, entry_ptr->index, entry_ptr->mac64); + etx_neighbor_remove(interface->id, entry_ptr->index); + ws_neighbor_class_entry_remove(&interface->ws_info->neighbor_storage, entry_ptr->index); } static void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entry *interface) @@ -144,8 +154,9 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ } if (reason == ADDR_CALLBACK_DAD_COMPLETE) { //Trig Address Registartion only when Bootstrap is ready - if (interface->nwk_bootstrap_state == ER_BOOTSRAP_DONE || addr->source == ADDR_SOURCE_DHCP) { - ws_bootsrap_event_trig(WS_ADDRESS_ADDED, interface->bootStrapId, ARM_LIB_LOW_PRIORITY_EVENT, (void *)addr); + if (interface->nwk_bootstrap_state == ER_BOOTSRAP_DONE && addr->source != ADDR_SOURCE_DHCP) { + tr_debug("Address registration %s", trace_ipv6(addr->address)); + rpl_control_register_address(interface, addr->address); } if (addr_ipv6_scope(addr->address, interface) > IPV6_SCOPE_LINK_LOCAL) { // at least ula address available inside mesh. @@ -155,6 +166,12 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ } else if (reason == ADDR_CALLBACK_DELETED) { // What to do? // Go through address list and check if there is global address still available + if (addr->source == ADDR_SOURCE_DHCP) { + //Deprecate dhcpv address + uint8_t address[16]; + memcpy(address, addr->address, 16); + dhcp_client_global_address_delete(interface->id, NULL, address); + } //Discover prefix policy addr_policy_remove_by_label(WS_NON_PREFFRED_LABEL); @@ -167,12 +184,10 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ } } } else if (reason == ADDR_CALLBACK_TIMER) { - tr_debug("Address Re registration %s", trace_ipv6(addr->address)); - - if (!interface->ws_info->address_registration_event_active) { - interface->ws_info->address_registration_event_active = true; - tr_info("Register ARO"); - ws_bootsrap_event_trig(WS_ADDRESS_ADDED, interface->bootStrapId, ARM_LIB_LOW_PRIORITY_EVENT, NULL); + if (addr->source != ADDR_SOURCE_DHCP) { + tr_debug("Address Re registration %s", trace_ipv6(addr->address)); + //Register + rpl_control_register_address(interface, addr->address); } } } @@ -304,9 +319,7 @@ static bool ws_nud_message_build(protocol_interface_info_entry_t *cur, mac_neigh { //Send NS uint8_t ll_target[16]; - memcpy(ll_target, ADDR_LINK_LOCAL_PREFIX, 8); - memcpy(ll_target + 8, neighbor->mac64, 8); - ll_target[8] ^= 2; + ws_bootsrap_create_ll_address(ll_target, neighbor->mac64); tr_info("NUD generate NS %u", neighbor->index); buffer_t *buffer = icmpv6_build_ns(cur, ll_target, NULL, true, false, NULL); if (buffer) { @@ -321,6 +334,8 @@ void ws_nud_active_timer(protocol_interface_info_entry_t *cur, uint16_t ticks) //Convert TICKS to real milliseconds if (ticks > 0xffff / 100) { ticks = 0xffff; + } else if (ticks == 0) { + ticks = 1; } else { ticks *= 100; } @@ -649,10 +664,7 @@ uint16_t ws_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr if (!ws_neighbour || !etx_entry || etx_entry->etx_samples < 1 /*|| !ws_neighbour->candidate_parent*/) { // if RSL value is not good enough candidate parent flag is removed and device not accepted as parent - //tr_debug("ws_etx_read not valid parent"); - if (etx_entry && etx_entry->etx_samples) { - tr_debug("ws_etx_read not valid %u RSL IN(%u), %u RSL out(%u)", ws_neighbor_class_rsl_in_get(ws_neighbour), ws_neighbour->rsl_in, ws_neighbor_class_rsl_out_get(ws_neighbour), ws_neighbour->rsl_out); - } + tr_debug("ws_etx_read not valid params"); return 0xffff; } @@ -680,6 +692,21 @@ uint16_t ws_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr //tr_debug("ws_etx_read etx:%d", etx); return etx; } +bool ws_bootstrap_nd_ns_transmit(protocol_interface_info_entry_t *cur, ipv6_neighbour_t *entry, bool unicast, uint8_t seq) +{ + (void)cur; + (void)seq; + + if (unicast) { + // Unicast NS is OK + return false; + } + // Fail the resolution + tr_warn("Link address lost for %s", trace_ipv6(entry->ip_address)); + ipv6_neighbour_entry_remove(&cur->ipv6_neighbour_cache, entry); + // True means we skip the message sending + return true; +} static int8_t ws_bootstrap_up(protocol_interface_info_entry_t *cur) { @@ -698,8 +725,6 @@ static int8_t ws_bootstrap_up(protocol_interface_info_entry_t *cur) return -3; } - //Enable Power bootup timer setup - cur->ws_info->power_up_setup = true; // Save FHSS api cur->ws_info->fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); @@ -725,6 +750,9 @@ static int8_t ws_bootstrap_up(protocol_interface_info_entry_t *cur) /* Disable NUD Probes */ cur->ipv6_neighbour_cache.send_nud_probes = false; cur->ipv6_neighbour_cache.probe_avoided_routers = true; + /*Replace NS handler to disable multicast address queries */ + cur->if_ns_transmit = ws_bootstrap_nd_ns_transmit; + dhcp_client_init(cur->id); dhcp_client_configure(cur->id, true, true, true); //RENEW uses SOLICIT, Interface will use 1 instance for address get, IAID address hint is not used. dhcp_client_solicit_timeout_set(cur->id, WS_DHCP_SOLICIT_TIMEOUT, WS_DHCP_SOLICIT_MAX_RT, WS_DHCP_SOLICIT_MAX_RC); @@ -833,17 +861,18 @@ static void ws_bootstrap_pan_advertisement_analyse_active(struct protocol_interf * * A consistent transmission is defined as a PAN Advertisement received by a node with PAN ID and * NETNAME-IE / Network Name matching that of the receiving node, and with a PAN-IE / Routing Cost - * the same or better than (less than or equal to) that of the receiving node. + * the same or worse than (bigger than or equal to) that of the receiving node. * * Inconsistent: - * PAN Advertisement solicit + * + * Received Routing Cost is smaller than stored one * * A PAN Advertisement received by a node with PAN ID and NETNAME-IE / Network name matching - * that of the receiving node, and PAN-IE / Routing Cost worse than (greater than) that of the receiving node. + * that of the receiving node, and PAN-IE / Routing Cost better than (smaller than) that of the receiving node. * */ - if (pan_information->routing_cost <= cur->ws_info->pan_information.routing_cost) { + if (pan_information->routing_cost >= cur->ws_info->pan_information.routing_cost) { trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); } else { trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); @@ -897,7 +926,7 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf // Save route cost for all neighbours llc_neighbour_req_t neighbor_info; neighbor_info.neighbor = NULL; - if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false, false)) { neighbor_info.ws_neighbor->routing_cost = pan_information.routing_cost; } @@ -911,13 +940,13 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf if (memcmp(cur->ws_info->parent_info.addr, ADDR_UNSPECIFIED, 8) != 0) { // if we dont have higher than threshold signal only signal level decides parent - if (ws_neighbor_class_rssi_from_dbm_calculate(cur->ws_info->parent_info.signal_dbm) < (CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS) && - ws_neighbor_class_rssi_from_dbm_calculate(data->signal_dbm) > ws_neighbor_class_rssi_from_dbm_calculate(cur->ws_info->parent_info.signal_dbm)) { + if (ws_neighbor_class_rsl_from_dbm_calculate(cur->ws_info->parent_info.signal_dbm) < (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS) && + ws_neighbor_class_rsl_from_dbm_calculate(data->signal_dbm) > ws_neighbor_class_rsl_from_dbm_calculate(cur->ws_info->parent_info.signal_dbm)) { // automatically select the best quality link from the below threshold goto parent_selected; } // Drop if signal quality is not good enough - if (ws_neighbor_class_rssi_from_dbm_calculate(data->signal_dbm) < (CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS)) { + if (ws_neighbor_class_rsl_from_dbm_calculate(data->signal_dbm) < (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS)) { tr_info("EAPOL target dropped Link quality too low"); return; } @@ -936,14 +965,6 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf tr_info("EAPOL target dropped Lower link quality %u < %u current", data->signal_dbm, cur->ws_info->parent_info.signal_dbm); return; } - - } else { - // First advertise heard - - if (ws_neighbor_class_rssi_from_dbm_calculate(data->signal_dbm) < (CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS)) { - // First neighbor is too low we need to wait one extra trickle - cur->bootsrap_state_machine_cnt += cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; - } } parent_selected: @@ -974,8 +995,10 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf // Learn latest network information if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && neighbor_info.neighbor) { + uint8_t ll_address[16]; + ws_bootsrap_create_ll_address(ll_address, neighbor_info.neighbor->mac64); - if (neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + if (rpl_control_is_dodag_parent(cur, ll_address, true)) { cur->ws_info->pan_information.pan_size = pan_information.pan_size; cur->ws_info->pan_information.routing_cost = pan_information.routing_cost; cur->ws_info->pan_information.rpl_routing_method = pan_information.rpl_routing_method; @@ -1055,23 +1078,34 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry return; } llc_neighbour_req_t neighbor_info; - if (!ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, true)) { - return; + bool neighbour_pointer_valid; + + if (cur->ws_info->configuration_learned || cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //If we are border router or learned configuration we only update already learned neighbours. + neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false, true); + + } else { + neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, true, true); + if (!neighbour_pointer_valid) { + return; + } } - etx_lqi_dbm_update(cur->id, data->mpduLinkQuality, data->signal_dbm, neighbor_info.neighbor->index); - //Update Neighbor Broadcast and Unicast Parameters - ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp); - ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us); - ws_neighbor_class_neighbor_broadcast_time_info_update(neighbor_info.ws_neighbor, &ws_bt_ie, data->timestamp); - ws_neighbor_class_neighbor_broadcast_schedule_set(neighbor_info.ws_neighbor, &ws_bs_ie); + if (neighbour_pointer_valid) { + etx_lqi_dbm_update(cur->id, data->mpduLinkQuality, data->signal_dbm, neighbor_info.neighbor->index); + //Update Neighbor Broadcast and Unicast Parameters + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp); + ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us); + ws_neighbor_class_neighbor_broadcast_time_info_update(neighbor_info.ws_neighbor, &ws_bt_ie, data->timestamp); + ws_neighbor_class_neighbor_broadcast_schedule_set(neighbor_info.ws_neighbor, &ws_bs_ie); + } if (cur->ws_info->configuration_learned) { tr_info("PAN Config analyse own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); if (cur->ws_info->pan_information.pan_version == pan_version) { // Same version heard so it is consistent trickle_consistent_heard(&cur->ws_info->trickle_pan_config); - if (neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_SOFT_SYNCH); } // no need to process more @@ -1079,7 +1113,7 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry } else { // received version is different so we need to reset the trickle trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); - if (neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_HARD_SYNCH); } if (common_serial_number_greater_16(cur->ws_info->pan_information.pan_version, pan_version)) { @@ -1100,7 +1134,7 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry tr_info("Updated PAN configuration own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); // restart PAN version timer - cur->ws_info->pan_version_timeout_timer = PAN_VERSION_TIMEOUT; + cur->ws_info->pan_version_timeout_timer = ws_common_version_timeout_get(cur->ws_info->network_size_config); cur->ws_info->pan_information.pan_version = pan_version; ws_pae_controller_gtk_hash_update(cur, gtkhash_ptr); @@ -1138,7 +1172,7 @@ static void ws_bootstrap_pan_config_solicit_analyse(struct protocol_interface_in */ llc_neighbour_req_t neighbor_info; - if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false, false)) { etx_lqi_dbm_update(cur->id, data->mpduLinkQuality, data->signal_dbm, neighbor_info.neighbor->index); ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp); ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us); @@ -1220,7 +1254,7 @@ static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, c default: return; } - + ws_stats_update(cur, STATS_WS_ASYNCH_RX, 1); //UTT-IE and US-IE are mandatory for all Asynch Messages ws_utt_ie_t ws_utt; if (!ws_wh_utt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_utt)) { @@ -1273,9 +1307,21 @@ static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, c static void ws_bootstrap_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) { + ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); (void)interface; (void)asynch_message; } + +uint32_t ws_time_from_last_unicast_traffic(uint32_t current_time_stamp, ws_neighbor_class_entry_t *ws_neighbor) +{ + uint32_t time_from_last_unicast_shedule = current_time_stamp; + + //Time from last RX unicast in us + time_from_last_unicast_shedule -= ws_neighbor->fhss_data.uc_timing_info.utt_rx_timestamp; + time_from_last_unicast_shedule /= 1000000; //Convert to seconds + return time_from_last_unicast_shedule; +} + static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_entry *interface) { uint8_t ll_target[16]; @@ -1286,14 +1332,22 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent } memcpy(ll_target, ADDR_LINK_LOCAL_PREFIX, 8); + uint32_t current_time_stamp = ns_sw_mac_read_current_timestamp(interface->mac_api); + mac_neighbor_table_entry_t *neighbor_entry_ptr = NULL; ns_list_foreach_safe(mac_neighbor_table_entry_t, cur, &mac_neighbor_info(interface)->neighbour_list) { + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, cur->index); if (cur->link_role == PRIORITY_PARENT_NEIGHBOUR) { //This is our primary parent we cannot delete continue; } + if (cur->nud_active || ws_neighbor->accelerated_etx_probe || ws_neighbor->negative_aro_send) { + //If NUD process is active do not trig + continue; + } + if (neighbor_entry_ptr && neighbor_entry_ptr->lifetime < cur->lifetime) { // We have already shorter link entry found this cannot replace it continue; @@ -1309,20 +1363,35 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent memcpy(ll_target + 8, cur->mac64, 8); ll_target[8] ^= 2; - if (rpl_control_is_dodag_parent(interface, ll_target)) { + if (rpl_control_is_dodag_parent(interface, ll_target, true)) { // Possible parent is limited to 3 by default? continue; } } + uint32_t link_min_timeout; + //Read current timestamp + uint32_t time_from_last_unicast_shedule = ws_time_from_last_unicast_traffic(current_time_stamp, ws_neighbor); if (cur->trusted_device) { - neighbor_entry_ptr = cur; + link_min_timeout = WS_NEIGHBOR_TRUSTED_LINK_MIN_TIMEOUT; } else { - if (cur->link_lifetime - cur->lifetime > WS_NEIGHBOR_NOT_TRUSTED_LINK_TIMEOUT) { - //Accept only Enough Old not trusted Device + + link_min_timeout = WS_NEIGHBOR_NOT_TRUSTED_LINK_MIN_TIMEOUT; + } + + if (time_from_last_unicast_shedule > link_min_timeout || !ws_neighbor->unicast_data_rx) { + //Accept only Enough Old Device + if (!neighbor_entry_ptr) { + //Accept first compare neighbor_entry_ptr = cur; + } else { + uint32_t compare_neigh_time = ws_time_from_last_unicast_traffic(current_time_stamp, ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbor_entry_ptr->index)); + if (compare_neigh_time < time_from_last_unicast_shedule) { + //Accept older RX timeout allways + neighbor_entry_ptr = cur; + } } } } @@ -1333,7 +1402,7 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent } -static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new) +static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new, bool multicast) { neighbor_buffer->neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(interface), mac_64, ADDR_802_15_4_LONG); if (neighbor_buffer->neighbor) { @@ -1346,17 +1415,36 @@ static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_en if (!request_new) { return false; } - uint8_t ll_target[16]; - memcpy(ll_target, ADDR_LINK_LOCAL_PREFIX, 8); - memcpy(ll_target + 8, mac_64, 8); - ll_target[8] ^= 2; + uint8_t ll_target[16]; + ws_bootsrap_create_ll_address(ll_target, mac_64); if (blacklist_reject(ll_target)) { // Rejected by blacklist return false; } + if (multicast) { + //for multicast neighbour we must limit if we have already enough information + if (interface->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //Border router never allocate neighbors by multicast + return false; + } + + uint16_t parent_candidate_size = rpl_control_parent_candidate_list_size(interface, false); + + //if we have enough candidates at list do not accept new multicast neighbours + if (parent_candidate_size >= 4) { + return false; + } + + parent_candidate_size = rpl_control_parent_candidate_list_size(interface, true); + //If we have already enough parent selected Candidates count is bigger tahn 4 + if (parent_candidate_size >= 2) { + return false; + } + } + ws_bootstrap_neighbor_table_clean(interface); neighbor_buffer->neighbor = ws_bootstrap_mac_neighbor_add(interface, mac_64); @@ -1394,7 +1482,7 @@ static void ws_neighbor_entry_remove_notify(mac_neighbor_table_entry_t *entry_pt //NUD Process Clear Here ws_nud_entry_remove(cur, entry_ptr); - ws_bootstrap_neighbor_delete(cur, entry_ptr->index); + ws_bootstrap_neighbor_delete(cur, entry_ptr); } static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data) @@ -1406,7 +1494,7 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&cur->ws_info->neighbor_storage, entry_ptr->index); etx_storage_t *etx_entry = etx_storage_entry_get(cur->id, entry_ptr->index); - if (!entry_ptr->trusted_device || !ws_neighbor || !etx_entry) { + if (!entry_ptr->trusted_device || !ws_neighbor || !etx_entry || ws_neighbor->negative_aro_send) { return false; } @@ -1426,17 +1514,37 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, //ETX Sample 0: random 1-8 //ETX Sample 1: random 2-16 //ETX Sample 2: random 4-32 - uint32_t probe_period = WS_PROBE_INIT_BASE_SECONDS << etx_entry->etx_samples; - uint32_t time_block = 1 << etx_entry->etx_samples; - if (time_from_start >= probe_period) { - tr_debug("Link Probe test %u Sample trig", etx_entry->etx_samples); + if (etx_entry->etx_samples == 0 && ws_neighbor->accelerated_etx_probe) { + //Accept quick Probe for init ETX activate_nud = true; - } else if (time_from_start > time_block) { - uint16_t switch_prob = randLIB_get_random_in_range(0, probe_period - 1); - //Take Random from time WS_NEIGHBOR_NUD_TIMEOUT - WS_NEIGHBOR_NUD_TIMEOUT*1.5 - if (switch_prob < 2) { - tr_debug("Link Probe test with jitter %"PRIu32", sample %u", time_from_start, etx_entry->etx_samples); + } else { + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + if (etx_entry->etx_samples || !ws_neighbor->unicast_data_rx) { + //Border router just need 1 sample for ETX + return false; + } + } else { + uint8_t ll_address[16]; + ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); + if (!rpl_control_is_dodag_parent(cur, ll_address, false)) { + if (etx_entry->etx_samples || !ws_neighbor->unicast_data_rx) { + return 0; + } + } + } + + uint32_t probe_period = WS_PROBE_INIT_BASE_SECONDS << etx_entry->etx_samples; + uint32_t time_block = 1 << etx_entry->etx_samples; + if (time_from_start >= probe_period) { + //tr_debug("Link Probe test %u Sample trig", etx_entry->etx_samples); activate_nud = true; + } else if (time_from_start > time_block) { + uint16_t switch_prob = randLIB_get_random_in_range(0, probe_period - 1); + //Take Random from time WS_NEIGHBOR_NUD_TIMEOUT - WS_NEIGHBOR_NUD_TIMEOUT*1.5 + if (switch_prob < 2) { + //tr_debug("Link Probe test with jitter %"PRIu32", sample %u", time_from_start, etx_entry->etx_samples); + activate_nud = true; + } } } } @@ -1450,6 +1558,10 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, return false; } entry->neighbor_info = entry_ptr; + if (ws_neighbor->accelerated_etx_probe) { + ws_neighbor->accelerated_etx_probe = false; + entry->timer = 1; + } if (etx_entry->etx_samples >= WS_NEIGBOR_ETX_SAMPLE_MAX) { entry->nud_process = true; @@ -1554,7 +1666,7 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) ret_val = -4; goto init_fail; } - if (ws_pae_controller_cb_register(cur, &ws_bootstrap_authentication_completed, &ws_bootstrap_nw_key_set, &ws_bootstrap_nw_key_clear, &ws_bootstrap_nw_key_index_set, &ws_bootstrap_nw_frame_counter_set, &ws_bootstrap_pan_version_increment) < 0) { + if (ws_pae_controller_cb_register(cur, &ws_bootstrap_authentication_completed, &ws_bootstrap_nw_key_set, &ws_bootstrap_nw_key_clear, &ws_bootstrap_nw_key_index_set, &ws_bootstrap_nw_frame_counter_set, &ws_bootstrap_nw_frame_counter_read, &ws_bootstrap_pan_version_increment) < 0) { ret_val = -4; goto init_fail; } @@ -1778,11 +1890,8 @@ static void ws_set_fhss_hop(protocol_interface_info_entry_t *cur) static void ws_address_registration_update(protocol_interface_info_entry_t *interface) { - if (!interface->ws_info->address_registration_event_active) { - interface->ws_info->address_registration_event_active = true; - tr_info("RPL parent update ... register ARO"); - ws_bootsrap_event_trig(WS_ADDRESS_ADDED, interface->bootStrapId, ARM_LIB_LOW_PRIORITY_EVENT, NULL); - } + rpl_control_register_address(interface, NULL); + tr_info("RPL parent update ... register ARO"); } static void ws_bootstrap_rpl_callback(rpl_event_t event, void *handle) @@ -1835,7 +1944,13 @@ static void ws_dhcp_client_global_adress_cb(int8_t interface, uint8_t dhcp_addr[ (void)prefix; (void)interface; //TODO add handler for negative status - tr_debug("DHCPv6 %s status %u", trace_ipv6(dhcp_addr), register_status); + tr_debug("DHCPv6 %s status %u with link %s", trace_ipv6(prefix), register_status, trace_ipv6(dhcp_addr)); + if (register_status) { + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); + if (cur) { + rpl_control_register_address(cur, prefix); + } + } } @@ -1907,6 +2022,7 @@ static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) rpl_control_set_callback(protocol_6lowpan_rpl_domain, ws_bootstrap_rpl_callback, ws_rpl_prefix_callback, cur); // If i am router I Do this rpl_control_force_leaf(protocol_6lowpan_rpl_domain, leaf); + rpl_control_request_parent_link_confirmation(true); cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event } @@ -1966,16 +2082,6 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) // New network scan started old addresses not assumed valid anymore ws_bootstrap_ip_stack_addr_clear(cur); - // Reset advertisement solicit trickle to start discovering network - cur->ws_info->trickle_pas_running = true; - trickle_start(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); - if (cur->ws_info->power_up_setup) { - cur->ws_info->power_up_setup = false; - tr_debug("PAS init I %u and t %u", cur->ws_info->trickle_pan_advertisement_solicit.I, cur->ws_info->trickle_pan_advertisement_solicit.t); - } else { - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); - } - if ((cur->lowpan_info & INTERFACE_NWK_BOOTSRAP_ACTIVE) != INTERFACE_NWK_BOOTSRAP_ACTIVE) { // we have sent bootstrap ready event and now // restarted discovery so bootstrap down event is sent @@ -1983,8 +2089,24 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) ws_nwk_event_post(cur, ARM_NWK_NWK_CONNECTION_DOWN); } - // Discovery statemachine is checkked after two trickle interval - cur->bootsrap_state_machine_cnt = 2 * cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; + // Start advertisement solicit trickle and calculate when we are checking the status + cur->ws_info->trickle_pas_running = true; + if (cur->ws_info->trickle_pan_advertisement_solicit.I != cur->ws_info->trickle_params_pan_discovery.Imin) { + // Trickle not reseted so starting a new interval + trickle_start(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); + } + + // Discovery statemachine is checkked after we have sent the Solicit + uint16_t time_to_solicit = 0; + if (cur->ws_info->trickle_pan_advertisement_solicit.t > cur->ws_info->trickle_pan_advertisement_solicit.now) { + time_to_solicit = cur->ws_info->trickle_pan_advertisement_solicit.t - cur->ws_info->trickle_pan_advertisement_solicit.now; + } + + tr_debug("Disc params imin %u, imax %u, expirations %u, k %u PAS Trickle I %u t %u, now %u, c %u", + cur->ws_info->trickle_params_pan_discovery.Imin, cur->ws_info->trickle_params_pan_discovery.Imax, cur->ws_info->trickle_params_pan_discovery.TimerExpirations, cur->ws_info->trickle_params_pan_discovery.k, + cur->ws_info->trickle_pan_advertisement_solicit.I, cur->ws_info->trickle_pan_advertisement_solicit.t, cur->ws_info->trickle_pan_advertisement_solicit.now, cur->ws_info->trickle_pan_advertisement_solicit.c); + + cur->bootsrap_state_machine_cnt = time_to_solicit + cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; } // Start authentication @@ -2024,6 +2146,12 @@ static void ws_bootstrap_nw_frame_counter_set(protocol_interface_info_entry_t *c mac_helper_link_frame_counter_set(cur->id, counter); } +static void ws_bootstrap_nw_frame_counter_read(protocol_interface_info_entry_t *cur, uint32_t *counter) +{ + // Read frame counter + mac_helper_link_frame_counter_read(cur->id, counter); +} + static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_t *cur, bool success) { if (success) { @@ -2032,6 +2160,8 @@ static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_ } else { tr_debug("authentication failed"); // What else to do to start over again... + // Trickle is reseted when entering to discovery from state 2 + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); ws_bootstrap_event_discovery_start(cur); } } @@ -2244,17 +2374,6 @@ static void ws_bootstrap_pan_config(protocol_interface_info_entry_t *cur) ws_llc_asynch_request(cur, &async_req); } -static bool ws_bootstrap_address_registration_ongoing(protocol_interface_info_entry_t *cur) -{ - ns_list_foreach(if_address_entry_t, addr, &cur->ip_addresses) { - if (addr->addr_reg_pend != 0) { - return true; - } - } - - return false; -} - static void ws_bootstrap_event_handler(arm_event_s *event) { ws_bootsrap_event_type_e event_type; @@ -2301,7 +2420,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); ws_llc_set_gtkhash(cur, gtkhash); - cur->ws_info->pan_version_timer = PAN_VERSION_LIFETIME; + cur->ws_info->pan_version_timer = ws_common_version_lifetime_get(cur->ws_info->network_size_config); // Set default parameters for FHSS when starting a discovery ws_fhss_border_router_configure(cur); @@ -2378,12 +2497,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) ws_bootstrap_advertise_start(cur); ws_bootstrap_state_change(cur, ER_BOOTSRAP_DONE); break; - case WS_ADDRESS_ADDED: - cur->ws_info->address_registration_event_active = false; - if (!ws_bootstrap_address_registration_ongoing(cur)) { - rpl_control_register_address(cur, (if_address_entry_t *) event->data_ptr); - } - break; + default: tr_err("Invalid event received"); break; @@ -2407,7 +2521,7 @@ void ws_bootstrap_network_scan_process(protocol_interface_info_entry_t *cur) // Add EAPOL neighbour llc_neighbour_req_t neighbor_info; - if (!ws_bootstrap_neighbor_info_request(cur, cur->ws_info->parent_info.addr, &neighbor_info, true)) { + if (!ws_bootstrap_neighbor_info_request(cur, cur->ws_info->parent_info.addr, &neighbor_info, true, false)) { return; } @@ -2515,9 +2629,6 @@ void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur) break; case ER_PANA_AUTH: tr_info("authentication start"); - // only advert sol stopped as we might be doing re authentication - cur->ws_info->trickle_pas_running = false; - //Add Test ecurity key and security level's // Advertisements stopped during the EAPOL cur->ws_info->trickle_pa_running = false; cur->ws_info->trickle_pc_running = false; @@ -2557,6 +2668,8 @@ void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t t // Remove network keys from MAC ws_pae_controller_nw_keys_remove(cur); + // Trickle is reseted when entering to discovery from state 3 + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); ws_bootstrap_event_discovery_start(cur); return; } @@ -2601,9 +2714,7 @@ void ws_primary_parent_update(protocol_interface_info_entry_t *interface, mac_ne neighbor_info.ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbor->index); ws_bootstrap_primary_parent_set(interface, &neighbor_info, WS_PARENT_HARD_SYNCH); uint8_t link_local_address[16]; - memcpy(link_local_address, ADDR_LINK_LOCAL_PREFIX, 8); - memcpy(link_local_address + 8, neighbor->mac64, 8); - link_local_address[8] ^= 2; + ws_bootsrap_create_ll_address(link_local_address, neighbor->mac64); dhcp_client_server_address_update(interface->id, NULL, link_local_address); ws_secondary_parent_update(interface); @@ -2615,11 +2726,30 @@ void ws_secondary_parent_update(protocol_interface_info_entry_t *interface) if (interface->ws_info) { ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { if (!addr_is_ipv6_link_local(address->address)) { - address->addr_reg_done = 0; ws_address_registration_update(interface); } } } } +void ws_bootstrap_etx_accelerate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh) +{ + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neigh->index); + //Enable Faster ETX probing + ws_neighbor->accelerated_etx_probe = true; + //Move Neighbor to first to for accelerate Process + mac_neighbor_table_t *table_class = mac_neighbor_info(interface); + ns_list_remove(&table_class->neighbour_list, neigh); + ns_list_add_to_start(&table_class->neighbour_list, neigh); + //Try to Generate Active NUD Immediately + if (!ws_neighbor_entry_nud_notify(neigh, interface)) { + return;//Return if NUD active is full + } + table_class->active_nud_process++; + neigh->nud_active = true; + //Push NS to send + ws_nud_active_timer(interface, 0); + +} + #endif //HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h index 789279e0fc0..9d7f5524659 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h @@ -24,8 +24,7 @@ typedef enum { WS_DISCOVERY_START, /**< discovery start*/ WS_CONFIGURATION_START, /**< configuration learn start*/ WS_OPERATION_START, /**< active operation start*/ - WS_ROUTING_READY, /**< RPL routing connected to BR*/ - WS_ADDRESS_ADDED /**< Address added to IF*/ + WS_ROUTING_READY /**< RPL routing connected to BR*/ } ws_bootsrap_event_type_e; #ifdef HAVE_WS @@ -77,6 +76,8 @@ bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur); void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); +void ws_bootstrap_etx_accelerate(struct protocol_interface_info_entry *cur, mac_neighbor_table_entry_t *neigh); + #else #define ws_bootstrap_init(interface_id, bootstrap_mode) (-1) @@ -86,6 +87,7 @@ void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, #define ws_bootstrap_aro_failure(cur, ll_address) #define ws_primary_parent_update(interface, neighbor) #define ws_secondary_parent_update(interface) +#define ws_bootstrap_etx_accelerate(cur, neigh) ((void) 0) #endif //HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c index 5478366ec5f..e020bee7c6d 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c @@ -27,6 +27,7 @@ #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" #include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" #include "Service_Libs/blacklist/blacklist.h" #include "ws_management_api.h" @@ -35,7 +36,9 @@ #ifdef HAVE_WS #define TRACE_GROUP "wscm" -int8_t DEVICE_MIN_SENS = -93; +// estimated sensitivity -93 dbm converted to Wi-SUN RSL range +// This provides a range of -174 (0) to +80 (254) dBm +uint8_t DEVICE_MIN_SENS = 174 - 93; #define TRICKLE_IMIN_60_SECS (60 * 10) #define TRICKLE_IMIN_30_SECS (30 * 10) @@ -50,7 +53,7 @@ static const trickle_params_t trickle_params_pan_discovery_large = { static const trickle_params_t trickle_params_pan_discovery_medium = { .Imin = TRICKLE_IMIN_30_SECS, /* 30 second; ticks are 1s */ - .Imax = TRICKLE_IMIN_30_SECS << 3, /* 240 seconds 4 min*/ + .Imax = TRICKLE_IMIN_30_SECS << 5, /* 960 seconds 16 min*/ .k = 1, /* 1 */ .TimerExpirations = TRICKLE_EXPIRATIONS_INFINITE }; @@ -274,8 +277,8 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) cur->ws_info->hopping_schdule.operating_mode = OPERATING_MODE_3; cur->ws_info->hopping_schdule.operating_class = 2; ws_common_regulatory_domain_config(cur); - cur->ws_info->network_size_config = NETWORK_SIZE_AUTOMATIC; - ws_common_network_size_configure(cur, 10); // defaults to small network size + cur->ws_info->network_size_config = NETWORK_SIZE_MEDIUM; + ws_common_network_size_configure(cur, 200); // defaults to medium network size // Set defaults for the device. user can modify these. cur->ws_info->fhss_uc_fixed_channel = 0xffff; @@ -314,17 +317,17 @@ void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint cur->ws_info->trickle_params_pan_discovery = trickle_params_pan_discovery_medium; // Something in between // imin: 15 (32s) - // doublings:3 (262s) - // redundancy; 7 - ws_bbr_rpl_config(15, 3, 7); + // doublings:5 (960s) + // redundancy; 10 + ws_bbr_rpl_config(15, 5, 10); } else { // Configure the Wi-SUN discovery trickle parameters cur->ws_info->trickle_params_pan_discovery = trickle_params_pan_discovery_large; // Wi-SUN Large network parameters // imin: 19 (524s, 9 min) // doublings:1 (1048s, 17 min) - // redundancy; 1 Really heavy redundancy - ws_bbr_rpl_config(19, 1, 1); + // redundancy; 10 May need some tuning still + ws_bbr_rpl_config(19, 1, 10); } return; } @@ -396,6 +399,58 @@ bool ws_common_allow_child_registration(protocol_interface_info_entry_t *interfa return true; } +bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, const uint8_t *eui64) +{ + mac_neighbor_table_entry_t *neighbour = mac_neighbor_table_address_discover(mac_neighbor_info(interface), eui64, ADDR_802_15_4_LONG); + if (!neighbour) { + return false; + } + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbour->index); + ws_neighbor->negative_aro_send = true; + neighbour->lifetime = WS_NEIGHBOR_NOT_TRUSTED_LINK_MIN_TIMEOUT; //Remove anyway if Packet is freed before MAC push + return true; +} + +void ws_common_etx_validate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh) +{ + etx_storage_t *etx_entry = etx_storage_entry_get(interface->id, neigh->index); + + if (neigh->nud_active || !neigh->trusted_device || !etx_entry || etx_entry->etx_samples) { + return; //Do not trig Second NS if Active NUD already, not trusted or ETX samples already done + } + + ws_bootstrap_etx_accelerate(interface, neigh); +} + +uint32_t ws_common_version_lifetime_get(uint8_t config) +{ + uint32_t lifetime; + if (config == NETWORK_SIZE_SMALL) { + lifetime = PAN_VERSION_SMALL_NETWORK_LIFETIME; + } else if (config == NETWORK_SIZE_MEDIUM) { + lifetime = PAN_VERSION_MEDIUM_NETWORK_LIFETIME; + } else { + lifetime = PAN_VERSION_LARGE_NETWORK_LIFETIME; + } + + return lifetime; + +} + +uint32_t ws_common_version_timeout_get(uint8_t config) +{ + uint32_t lifetime; + if (config == NETWORK_SIZE_SMALL) { + lifetime = PAN_VERSION_SMALL_NETWORK_TIMEOUT; + } else if (config == NETWORK_SIZE_MEDIUM) { + lifetime = PAN_VERSION_MEDIUM_NETWORK_TIMEOUT; + } else { + lifetime = PAN_VERSION_LARGE_NETWORK_TIMEOUT; + } + + return lifetime; +} + #endif // HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h index 3c1d220cc7b..510f3d96816 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h @@ -73,13 +73,11 @@ typedef struct ws_info_s { uint32_t pan_version_timer; /**< border router version udate timeout */ uint32_t pan_version_timeout_timer; /**< routers will fallback to previous state after this */ uint8_t gtkhash[32]; - bool address_registration_event_active : 1; bool configuration_learned: 1; bool trickle_pas_running: 1; bool trickle_pa_running: 1; bool trickle_pcs_running: 1; bool trickle_pc_running: 1; - bool power_up_setup: 1; // default fhss parameters for this device uint8_t fhss_uc_dwell_interval; uint8_t fhss_bc_dwell_interval; @@ -94,6 +92,7 @@ typedef struct ws_info_s { ws_nud_table_list_t free_nud_entries; struct ws_pan_information_s pan_information; ws_hopping_schedule_t hopping_schdule; + struct ws_statistics *stored_stats_ptr; struct ws_neighbor_class_s neighbor_storage; struct fhss_timer *fhss_timer_ptr; // Platform adaptation for FHSS timers. struct fhss_api *fhss_api; @@ -123,6 +122,15 @@ void ws_common_neighbor_remove(protocol_interface_info_entry_t *cur, const uint8 bool ws_common_allow_child_registration(protocol_interface_info_entry_t *cur, const uint8_t *eui64); +void ws_common_etx_validate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh); + +bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, const uint8_t *eui64); + + +uint32_t ws_common_version_lifetime_get(uint8_t config); + +uint32_t ws_common_version_timeout_get(uint8_t config); + #define ws_info(cur) ((cur)->ws_info) #else #define ws_info(cur) ((ws_info_t *) NULL) @@ -132,6 +140,8 @@ bool ws_common_allow_child_registration(protocol_interface_info_entry_t *cur, co #define ws_common_neighbor_remove(cur, ll_address) #define ws_common_fast_timer(cur, ticks) ((void) 0) #define ws_common_allow_child_registration(cur, eui64) (false) +#define ws_common_etx_validate(interface, neigh) ((void) 0) +#define ws_common_negative_aro_mark(interface, eui64)(false) #endif //HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h index 4df0dd641f5..4e796f4fd97 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h @@ -186,7 +186,8 @@ typedef struct ws_bs_ie { #define WS_FAN_VERSION_1_0 1 #define WS_NEIGHBOR_LINK_TIMEOUT 2200 -#define WS_NEIGHBOR_NOT_TRUSTED_LINK_TIMEOUT 60 +#define WS_NEIGHBOR_NOT_TRUSTED_LINK_MIN_TIMEOUT 60 +#define WS_NEIGHBOR_TRUSTED_LINK_MIN_TIMEOUT 15 #define WS_NEIGHBOR_NUD_TIMEOUT WS_NEIGHBOR_LINK_TIMEOUT / 2 #define WS_NEIGBOR_ETX_SAMPLE_MAX 3 diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h index f7eecaa201f..0d63c67c6b9 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h @@ -37,7 +37,9 @@ * Minimum interval at which a Border Router shall increment its PAN Version value. */ -#define PAN_VERSION_LIFETIME 240 +#define PAN_VERSION_SMALL_NETWORK_LIFETIME 4*60 +#define PAN_VERSION_MEDIUM_NETWORK_LIFETIME 15*60 +#define PAN_VERSION_LARGE_NETWORK_LIFETIME 30*60 //30min #define RPL_VERSION_LIFETIME 5*3600 @@ -50,7 +52,11 @@ * */ -#define PAN_VERSION_TIMEOUT 1920 +#define PAN_VERSION_SMALL_NETWORK_TIMEOUT 32*60 + +#define PAN_VERSION_MEDIUM_NETWORK_TIMEOUT 64*60 + +#define PAN_VERSION_LARGE_NETWORK_TIMEOUT 90*60 /* Routing Cost Weighting factor */ @@ -68,7 +74,7 @@ * * Default value for us is -93 */ -extern int8_t DEVICE_MIN_SENS; +extern uint8_t DEVICE_MIN_SENS; /* Candidate parent Threshold */ @@ -96,7 +102,7 @@ extern int8_t DEVICE_MIN_SENS; * */ #define WS_DHCP_SOLICIT_TIMEOUT 60 -#define WS_DHCP_SOLICIT_MAX_RT 3600 +#define WS_DHCP_SOLICIT_MAX_RT 900 #define WS_DHCP_SOLICIT_MAX_RC 0 @@ -120,5 +126,11 @@ extern int8_t DEVICE_MIN_SENS; #define WS_BLACKLIST_PURGE_NBR 3 #define WS_BLACKLIST_PURGE_TIMER_TIMEOUT 60 +/* + * MAC frame counter NVM storing configuration + */ +#define FRAME_COUNTER_STORE_INTERVAL 60 // Time interval (on seconds) between frame counter store operations +#define FRAME_COUNTER_INCREMENT 1000 // How much frame counter is incremented on start up +#define FRAME_COUNTER_STORE_THRESHOLD 800 // How much frame counter must increment before it is stored #endif /* WS_CONFIG_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c index 0881574e92f..487af5e151f 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c @@ -189,4 +189,17 @@ int ws_test_next_gtk_set(int8_t interface_id, uint8_t *gtk[4]) return -1; } +int ws_statistics_start(int8_t interface_id, ws_statistics_t *stats_ptr) +{ + (void) interface_id; + (void) stats_ptr; + return -1; +} + +int ws_statistics_stop(int8_t interface_id) +{ + (void) interface_id; + return -1; +} + #endif // no HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c index 92b95bce68d..a3aa0d93a65 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c @@ -111,10 +111,10 @@ uint8_t *ws_wh_fc_write(uint8_t *ptr, uint8_t flow_ctrl) return ptr; } -uint8_t *ws_wh_rsl_write(uint8_t *ptr, int8_t rssi) +uint8_t *ws_wh_rsl_write(uint8_t *ptr, uint8_t rsl) { ptr = ws_wh_header_base_write(ptr, 1, WH_IE_RSL_TYPE); - *ptr++ = rssi; + *ptr++ = rsl; return ptr; } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h index e992b09fd26..1beadcd898b 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h @@ -36,7 +36,7 @@ typedef struct ws_wp_network_name { uint8_t *ws_wh_utt_write(uint8_t *ptr, uint8_t message_type); uint8_t *ws_wh_bt_write(uint8_t *ptr); uint8_t *ws_wh_fc_write(uint8_t *ptr, uint8_t flow_ctrl); -uint8_t *ws_wh_rsl_write(uint8_t *ptr, int8_t rssi); +uint8_t *ws_wh_rsl_write(uint8_t *ptr, uint8_t rsl); uint8_t *ws_wh_vh_write(uint8_t *ptr, uint8_t *vendor_header, uint8_t vendor_header_length); uint8_t *ws_wh_ea_write(uint8_t *ptr, uint8_t *eui64); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h index a1dab61bffd..1104431e70c 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h @@ -99,11 +99,12 @@ typedef void ws_asynch_confirm(struct protocol_interface_info_entry *interface, * @param mac_64 Neighbor 64-bit address * @param neighbor_buffer Buffer where neighbor infor is buffered * @param request_new true if is possible to allocate new entry + * @param multicast true if packet is multicast * * @return true when neighbor info is available * @return false when no neighbor info */ -typedef bool ws_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new); +typedef bool ws_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new, bool multicast); /** * @brief ws_llc_create ws LLC module create diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c index 9c9192bb1b0..53b2a9e9e93 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c @@ -395,7 +395,7 @@ static void ws_llc_mac_confirm_cb(const mac_api_t *api, const mcps_data_conf_t * success = true; } - if (message->dst_address_type == MAC_ADDR_MODE_64_BIT && base->ws_neighbor_info_request_cb(interface, message->dst_address, &neighbor_info, false)) { + if (message->dst_address_type == MAC_ADDR_MODE_64_BIT && base->ws_neighbor_info_request_cb(interface, message->dst_address, &neighbor_info, false, false)) { etx_transm_attempts_update(interface->id, 1 + data->tx_retries, success, neighbor_info.neighbor->index); //TODO discover RSL from Enchanced ACK Header IE elements ws_utt_ie_t ws_utt; @@ -463,8 +463,7 @@ static void ws_llc_ack_data_req_ext(const mac_api_t *api, mcps_ack_data_payload_ //Write Data to block uint8_t *ptr = base->ws_enhanced_ack_elements; ptr = ws_wh_utt_write(ptr, WS_FT_ACK); - uint8_t rsl = ws_neighbor_class_rssi_from_dbm_calculate(rssi); - ws_wh_rsl_write(ptr, rsl); + ws_wh_rsl_write(ptr, ws_neighbor_class_rsl_from_dbm_calculate(rssi)); } /** WS LLC MAC data extension indication */ @@ -494,6 +493,7 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t return; } + mpx_user_t *user_cb; mac_payload_IE_t mpx_ie; mpx_ie.id = MAC_PAYLOAD_MPX_IE_GROUP_ID; if (mac_ie_payload_discover(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &mpx_ie) < 1) { @@ -522,12 +522,24 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t } llc_neighbour_req_t neighbor_info; + bool multicast; + if (data->DstAddrMode == ADDR_802_15_4_LONG) { + multicast = false; + } else { + multicast = true; + } - if (!base->ws_neighbor_info_request_cb(interface, data->SrcAddr, &neighbor_info, us_ie_inline)) { - tr_debug("Drop message no neighbor"); - return; + if (!base->ws_neighbor_info_request_cb(interface, data->SrcAddr, &neighbor_info, us_ie_inline, multicast)) { + if (!multicast || ws_utt.message_type == WS_FT_EAPOL) { + tr_debug("Drop message no neighbor"); + return; + } else { + goto mpx_data_ind; + } } + multicast = false; + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, &ws_utt, data->timestamp); if (us_ie_inline) { ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, &us_ie); @@ -557,9 +569,9 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t } } - //Refresh Neighbor if unicast + //Refresh Neighbor ETX if unicast if (ws_utt.message_type == WS_FT_DATA && data->DstAddrMode == ADDR_802_15_4_LONG) { - neighbor_info.neighbor->lifetime = neighbor_info.neighbor->link_lifetime; + neighbor_info.ws_neighbor->unicast_data_rx = true; etx_lqi_dbm_update(interface->id, data->mpduLinkQuality, data->signal_dbm, neighbor_info.neighbor->index); } if (ws_utt.message_type == WS_FT_DATA) { @@ -572,10 +584,15 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t } } + +mpx_data_ind: // Discover MPX - mpx_user_t *user_cb = ws_llc_mpx_user_discover(&base->mpx_data_base, mpx_frame.multiplex_id); + user_cb = ws_llc_mpx_user_discover(&base->mpx_data_base, mpx_frame.multiplex_id); if (user_cb && user_cb->data_ind) { mcps_data_ind_t data_ind = *data; + if (multicast) { + data_ind.Key.SecurityLevel = 0; //Mark unknow device + } data_ind.msdu_ptr = mpx_frame.frame_ptr; data_ind.msduLength = mpx_frame.frame_length; user_cb->data_ind(&base->mpx_data_base.mpx_api, &data_ind); @@ -618,7 +635,7 @@ static uint16_t ws_mpx_header_size_get(llc_data_base_t *base, uint16_t user_id) } //Dynamic length - header_size += 2 + WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + ws_wp_nested_hopping_schedule_length(base->ie_params.hopping_schedule, true); + header_size += 2 + WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + ws_wp_nested_hopping_schedule_length(base->ie_params.hopping_schedule, true) + ws_wp_nested_hopping_schedule_length(base->ie_params.hopping_schedule, false); } else if (MPX_KEY_MANAGEMENT_ENC_USER_ID) { header_size += 7 + 5 + 2; @@ -687,6 +704,11 @@ static void ws_llc_mpx_data_request(const mpx_api_t *api, const struct mcps_data if (base->ie_params.vendor_payload_length) { nested_wp_id.vp_ie = true; } + + if (!data->TxAckReq) { + nested_wp_id.bs_ie = true; + } + } else if (user_id == MPX_KEY_MANAGEMENT_ENC_USER_ID) { ie_header_mask.bt_ie = ws_eapol_relay_state_active(base->interface_ptr); ie_header_mask.ea_ie = ws_eapol_handshake_first_msg(data->msdu, data->msduLength, base->interface_ptr); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c index e733080d8de..e302b7bd7ab 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c @@ -118,6 +118,8 @@ int ws_management_network_size_set( if (network_size == NETWORK_SIZE_LARGE) { ws_common_network_size_configure(cur, 5000); + } else if (network_size == NETWORK_SIZE_MEDIUM) { + ws_common_network_size_configure(cur, 200); } else { ws_common_network_size_configure(cur, 10); } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c index 79036b8375d..8eda4fcc63a 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c @@ -134,13 +134,22 @@ void ws_neighbor_class_neighbor_broadcast_schedule_set(ws_neighbor_class_entry_t ws_neighbor->fhss_data.bc_timing_info.broadcast_schedule_id = ws_bs_ie->broadcast_schedule_identifier; } -uint8_t ws_neighbor_class_rssi_from_dbm_calculate(int8_t dbm_heard) +void ws_neighbor_class_rf_sensitivity_calculate(uint8_t rsl_heard) { - if (DEVICE_MIN_SENS > dbm_heard) { + if (DEVICE_MIN_SENS > rsl_heard) { // We are hearing packet with lower than min_sens dynamically learn the sensitivity - DEVICE_MIN_SENS = dbm_heard; + DEVICE_MIN_SENS = rsl_heard; } - return dbm_heard - DEVICE_MIN_SENS; +} + +uint8_t ws_neighbor_class_rsl_from_dbm_calculate(int8_t dbm_heard) +{ + /* RSL MUST be calculated as the received signal level relative to standard + * thermal noise (290oK) at 1 Hz bandwidth or 174 dBm. + * This provides a range of -174 (0) to +80 (254) dBm. + */ + + return dbm_heard + 174; } static void ws_neighbor_class_parent_set_analyze(ws_neighbor_class_entry_t *ws_neighbor) @@ -151,24 +160,26 @@ static void ws_neighbor_class_parent_set_analyze(ws_neighbor_class_entry_t *ws_n return; } - if (ws_neighbor_class_rsl_in_get(ws_neighbor) < (CAND_PARENT_THRESHOLD - CAND_PARENT_HYSTERISIS) && - ws_neighbor_class_rsl_out_get(ws_neighbor) < (CAND_PARENT_THRESHOLD - CAND_PARENT_HYSTERISIS)) { + if (ws_neighbor_class_rsl_in_get(ws_neighbor) < (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD - CAND_PARENT_HYSTERISIS) && + ws_neighbor_class_rsl_out_get(ws_neighbor) < (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD - CAND_PARENT_HYSTERISIS)) { ws_neighbor->candidate_parent = false; } - if (ws_neighbor_class_rsl_in_get(ws_neighbor) > (CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS) && - ws_neighbor_class_rsl_out_get(ws_neighbor) > (CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS)) { + if (ws_neighbor_class_rsl_in_get(ws_neighbor) > (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS) && + ws_neighbor_class_rsl_out_get(ws_neighbor) > (DEVICE_MIN_SENS + CAND_PARENT_THRESHOLD + CAND_PARENT_HYSTERISIS)) { ws_neighbor->candidate_parent = true; } } void ws_neighbor_class_rsl_in_calculate(ws_neighbor_class_entry_t *ws_neighbor, int8_t dbm_heard) { - uint8_t rssi = ws_neighbor_class_rssi_from_dbm_calculate(dbm_heard); + uint8_t rsl = ws_neighbor_class_rsl_from_dbm_calculate(dbm_heard); + // Calculate minimum sensitivity from heard packets. + ws_neighbor_class_rf_sensitivity_calculate(rsl); if (ws_neighbor->rsl_in == RSL_UNITITIALIZED) { - ws_neighbor->rsl_in = rssi << WS_RSL_SCALING; + ws_neighbor->rsl_in = rsl << WS_RSL_SCALING; } - ws_neighbor->rsl_in = ws_neighbor->rsl_in + rssi - (ws_neighbor->rsl_in >> WS_RSL_SCALING); + ws_neighbor->rsl_in = ws_neighbor->rsl_in + rsl - (ws_neighbor->rsl_in >> WS_RSL_SCALING); ws_neighbor_class_parent_set_analyze(ws_neighbor); return; } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h index bc86ab70f8c..7fa0c9b6957 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h @@ -32,6 +32,9 @@ typedef struct ws_neighbor_class_entry { bool broadcast_timing_info_stored: 1; bool broadcast_shedule_info_stored: 1; bool synch_done : 1; + bool accelerated_etx_probe : 1; + bool negative_aro_send : 1; + bool unicast_data_rx : 1; } ws_neighbor_class_entry_t; /** @@ -134,15 +137,26 @@ void ws_neighbor_class_neighbor_broadcast_time_info_update(ws_neighbor_class_ent void ws_neighbor_class_neighbor_broadcast_schedule_set(ws_neighbor_class_entry_t *ws_neighbor, ws_bs_ie_t *ws_bs_ie); /** - * ws_neighbor_class_rssi_from_dbm_calculate + * ws_neighbor_class_rf_sensitivity_calculate * - * Calculates rssi value from dbm heard taking into account min sensitivity of radio - * dynamically adjusts min sensitivity if value is not properly set + * Calculates minimum heard RSL value from all packets. + * This will dynamically adjusts min sensitivity if value is not properly set + * + * \param rsl_heard; rsl_heard heard from Radio + * + */ +void ws_neighbor_class_rf_sensitivity_calculate(uint8_t rsl_heard); + +/** + * ws_neighbor_class_rsl_from_dbm_calculate + * + * Calculates rsl value from dbm heard. + * This provides a range of -174 (0) to +80 (254) dBm. * * \param dbm_heard; dbm heard from the neighbour * */ -uint8_t ws_neighbor_class_rssi_from_dbm_calculate(int8_t dbm_heard); +uint8_t ws_neighbor_class_rsl_from_dbm_calculate(int8_t dbm_heard); /** Helper macros to read RSL values from neighbour class. * diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c index 78f559696f6..ada62670909 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c @@ -332,7 +332,7 @@ int8_t ws_pae_auth_node_keys_remove(protocol_interface_info_entry_t *interface_p sec_prot_keys_pmk_delete(&supp->sec_keys); sec_prot_keys_ptk_delete(&supp->sec_keys); supp->access_revoked = true; - tr_info("Access revoked; keys removed, eui-64: %s", trace_array(kmp_address_eui_64_get(supp->addr), 8)); + tr_info("Access revoked; keys removed, eui-64: %s", trace_array(supp->addr.eui_64, 8)); return 0; } @@ -340,7 +340,7 @@ int8_t ws_pae_auth_node_keys_remove(protocol_interface_info_entry_t *interface_p supp = ws_pae_lib_supp_list_entry_eui_64_get(&pae_auth->inactive_supp_list, eui_64); if (supp) { // Deletes supplicant - tr_info("Access revoked; deleted, eui-64: %s", trace_array(kmp_address_eui_64_get(supp->addr), 8)); + tr_info("Access revoked; deleted, eui-64: %s", trace_array(supp->addr.eui_64, 8)); ws_pae_lib_supp_list_remove(&pae_auth->inactive_supp_list, supp); return 0; } @@ -720,8 +720,8 @@ static void ws_pae_auth_kmp_service_addr_get(kmp_service_t *service, kmp_api_t * // Get supplicant address supp_entry_t *entry = kmp_api_data_get(kmp); - if (entry && entry->addr) { - kmp_address_copy(remote_addr, entry->addr); + if (entry) { + kmp_address_copy(remote_addr, &entry->addr); } } @@ -767,7 +767,7 @@ static kmp_api_t *ws_pae_auth_kmp_incoming_ind(kmp_service_t *service, kmp_type_ sec_prot_keys_ptk_eui_64_write(&supp_entry->sec_keys, kmp_address_eui_64_get(addr)); } else { // Updates relay address - kmp_address_copy(supp_entry->addr, addr); + kmp_address_copy(&supp_entry->addr, addr); } // Increases waiting time for supplicant authentication @@ -788,7 +788,7 @@ static kmp_api_t *ws_pae_auth_kmp_incoming_ind(kmp_service_t *service, kmp_type_ kmp_api_data_set(kmp, supp_entry); // Sets address to KMP - kmp_api_addr_set(kmp, supp_entry->addr); + kmp_api_addr_set(kmp, &supp_entry->addr); // Sets security keys to KMP kmp_api_sec_keys_set(kmp, &supp_entry->sec_keys); @@ -862,6 +862,11 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup if (next_type == KMP_TYPE_NONE) { // All done return; + } else { + if (ws_pae_lib_kmp_list_type_get(&supp_entry->kmp_list, next_type) != NULL) { + tr_info("KMP already ongoing; ignored, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); + return; + } } // Increases waiting time for supplicant authentication @@ -877,7 +882,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup uint16_t ongoing_eap_tls_cnt = ws_pae_lib_supp_list_kmp_count(&pae_auth->active_supp_list, IEEE_802_1X_MKA); if (ongoing_eap_tls_cnt >= MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS) { supp_entry->retry_ticks = EAP_TLS_NEGOTIATION_TRIGGER_TIMEOUT; - tr_info("EAP-TLS max ongoing reached, count %i, delayed: eui-64: %s", ongoing_eap_tls_cnt, trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("EAP-TLS max ongoing reached, count %i, delayed: eui-64: %s", ongoing_eap_tls_cnt, trace_array(supp_entry->addr.eui_64, 8)); return; } } @@ -902,7 +907,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup } } - kmp_api_create_request(new_kmp, next_type, supp_entry->addr, &supp_entry->sec_keys); + kmp_api_create_request(new_kmp, next_type, &supp_entry->addr, &supp_entry->sec_keys); } static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry) @@ -915,11 +920,11 @@ static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry) sec_keys->ptk_mismatch = true; // start EAP-TLS towards supplicant next_type = IEEE_802_1X_MKA; - tr_info("PAE start EAP-TLS, eui-64: %s", trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("PAE start EAP-TLS, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); } else if (sec_keys->ptk_mismatch) { // start 4WH towards supplicant next_type = IEEE_802_11_4WH; - tr_info("PAE start 4WH, eui-64: %s", trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("PAE start 4WH, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); } int8_t gtk_index = -1; @@ -937,14 +942,14 @@ static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry) if (next_type == KMP_TYPE_NONE && gtk_index >= 0) { // Update just GTK next_type = IEEE_802_11_GKH; - tr_info("PAE start GKH, eui-64: %s", trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("PAE start GKH, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); } - tr_info("PAE update GTK index: %i, eui-64: %s", gtk_index, trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("PAE update GTK index: %i, eui-64: %s", gtk_index, trace_array(supp_entry->addr.eui_64, 8)); } if (next_type == KMP_TYPE_NONE) { - tr_info("PAE authenticated, eui-64: %s", trace_array(kmp_address_eui_64_get(supp_entry->addr), 8)); + tr_info("PAE authenticated, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); } return next_type; @@ -1004,7 +1009,7 @@ static void ws_pae_auth_kmp_api_finished(kmp_api_t *kmp) ws_pae_lib_kmp_list_delete(&supp_entry->kmp_list, kmp); if (retry_supp) { - tr_info("PAE next KMP trigger, eui-64: %s", trace_array(kmp_address_eui_64_get(retry_supp->addr), 8)); + tr_info("PAE next KMP trigger, eui-64: %s", trace_array(retry_supp->addr.eui_64, 8)); ws_pae_auth_next_kmp_trigger(pae_auth, retry_supp); } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c index a00dbd3b717..c001c2364a6 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c @@ -31,6 +31,8 @@ #include "6LoWPAN/ws/ws_pae_timers.h" #include "6LoWPAN/ws/ws_pae_supp.h" #include "6LoWPAN/ws/ws_pae_auth.h" +#include "6LoWPAN/ws/ws_pae_nvm_store.h" +#include "6LoWPAN/ws/ws_pae_nvm_data.h" #include "mbedtls/sha256.h" #ifdef HAVE_WS @@ -51,6 +53,13 @@ typedef struct { bool fresh : 1; /**< Key is fresh i.e. not used on sending */ } nw_key_t; +typedef struct { + uint8_t hash[8]; /**< GTK hash for the frame counter */ + uint32_t frame_counter; /**< Frame counter */ + uint8_t index; /**< Index */ + bool set : 1; /**< Value has been set */ +} stored_frame_counter_t; + typedef struct { ns_list_link_t link; /**< Link */ uint8_t target_eui_64[8]; /**< EAPOL target */ @@ -63,6 +72,8 @@ typedef struct { sec_prot_certs_t certs; /**< Certificates */ nw_key_t nw_key[4]; /**< Currently active network keys (on MAC) */ char *network_name; /**< Network name for GAK generation */ + uint16_t frame_cnt_store_timer; /**< Timer for storing frame counter value */ + stored_frame_counter_t stored_frame_counter; /**< Stored frame counter */ timer_settings_t timer_settings; /**< Timer settings */ protocol_interface_info_entry_t *interface_ptr; /**< List link entry */ ws_pae_controller_auth_completed *auth_completed; /**< Authentication completed callback, continue bootstrap */ @@ -70,6 +81,7 @@ typedef struct { ws_pae_controller_nw_key_clear *nw_key_clear; /**< Key clear callback */ ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set; /**< Send key index set callback */ ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set; /**< Frame counter set callback */ + ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read; /**< Frame counter read callback */ ws_pae_controller_pan_ver_increment *pan_ver_increment; /**< PAN version increment callback */ ws_pae_delete *pae_delete; /**< PAE delete callback */ ws_pae_timer *pae_fast_timer; /**< PAE fast timer callback */ @@ -79,12 +91,17 @@ typedef struct { ws_pae_gtks_updated *pae_gtks_updated; /**< PAE GTKs updated */ ws_pae_gtk_hash_update *pae_gtk_hash_update; /**< PAE GTK HASH update */ ws_pae_nw_key_index_update *pae_nw_key_index_update; /**< PAE NW key index update */ + nvm_tlv_entry_t *pae_nvm_buffer; /**< Buffer For PAE NVM write operation*/ bool gtks_set : 1; /**< GTKs are set */ bool gtkhash_set : 1; /**< GTK hashes are set */ bool key_index_set : 1; /**< NW key index is set */ } pae_controller_t; static pae_controller_t *ws_pae_controller_get(protocol_interface_info_entry_t *interface_ptr); +static void ws_pae_controller_frame_counter_timer(uint16_t seconds, pae_controller_t *entry); +static void ws_pae_controller_frame_counter_store(pae_controller_t *entry); +static void ws_pae_controller_nvm_frame_counter_write(nvm_tlv_entry_t *tlv_entry); +static int8_t ws_pae_controller_nvm_frame_counter_read(uint8_t *index, uint8_t *hash, uint32_t *frame_counter); static pae_controller_t *ws_pae_controller_get_or_create(int8_t interface_id); static void ws_pae_controller_gtk_hash_set(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash); static int8_t ws_pae_controller_nw_key_check_and_insert(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks); @@ -93,6 +110,12 @@ static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t static int8_t ws_pae_controller_gak_from_gtk(uint8_t *gak, uint8_t *gtk, char *network_name); static void ws_pae_controller_nw_key_index_check_and_set(protocol_interface_info_entry_t *interface_ptr, uint8_t index); static void ws_pae_controller_data_init(pae_controller_t *controller); +static void ws_pae_controller_frame_counter_read(pae_controller_t *controller); +static void ws_pae_controller_frame_counter_reset(stored_frame_counter_t *counter); +static uint32_t ws_pae_controller_frame_counter_get(stored_frame_counter_t *counter, uint8_t index, uint8_t *key_hash); +static void ws_pae_controller_frame_counter_write(pae_controller_t *controller, uint8_t index, uint8_t *key_hash, uint32_t curr_counter); + +static const char *FRAME_COUNTER_FILE = FRAME_COUNTER_FILE_NAME; static NS_LIST_DEFINE(pae_controller_list, pae_controller_t, link); @@ -188,7 +211,7 @@ int8_t ws_pae_controller_authenticator_start(protocol_interface_info_entry_t *in return 0; } -int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_pan_ver_increment *pan_ver_increment) +int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read, ws_pae_controller_pan_ver_increment *pan_ver_increment) { if (!interface_ptr) { return -1; @@ -204,6 +227,7 @@ int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ controller->nw_key_clear = nw_key_clear; controller->nw_send_key_index_set = nw_send_key_index_set; controller->nw_frame_counter_set = nw_frame_counter_set; + controller->nw_frame_counter_read = nw_frame_counter_read; controller->pan_ver_increment = pan_ver_increment; return 0; @@ -422,7 +446,12 @@ static void ws_pae_controller_nw_key_index_check_and_set(protocol_interface_info if (controller->nw_send_key_index_set) { tr_info("NW send key index set: %i", index + 1); controller->nw_send_key_index_set(interface_ptr, index); - controller->nw_frame_counter_set(interface_ptr, 0); + controller->gtk_index = index; + + uint32_t frame_counter = ws_pae_controller_frame_counter_get(&controller->stored_frame_counter, index, controller->nw_key[index].hash); + controller->nw_frame_counter_set(interface_ptr, frame_counter); + tr_info("NW frame counter set: %"PRIu32"", frame_counter); + ws_pae_controller_frame_counter_write(controller, index, controller->nw_key[index].hash, frame_counter); } // Do not update PAN version for initial key index set @@ -444,10 +473,14 @@ static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t if (controller->nw_send_key_index_set) { controller->nw_send_key_index_set(controller->interface_ptr, index); + tr_info("NW send key index set: %i", index + 1); - // If index has changed and the key for the index is fresh reset frame counter + // If index has changed and the key for the index is fresh get frame counter if (controller->gtk_index != index && controller->nw_key[index].fresh) { - controller->nw_frame_counter_set(cur, 0); + uint32_t frame_counter = ws_pae_controller_frame_counter_get(&controller->stored_frame_counter, index, controller->nw_key[index].hash); + controller->nw_frame_counter_set(cur, frame_counter); + tr_info("NW frame counter set: %"PRIu32"", frame_counter); + ws_pae_controller_frame_counter_write(controller, index, controller->nw_key[index].hash, frame_counter); } controller->gtk_index = index; @@ -466,7 +499,11 @@ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) } pae_controller_t *controller = ns_dyn_mem_alloc(sizeof(pae_controller_t)); - if (!controller) { + void *pae_nvm_buffer = ws_pae_buffer_allocate(); + + if (!controller || !pae_nvm_buffer) { + ns_dyn_mem_free(controller); + ns_dyn_mem_free(pae_nvm_buffer); return -1; } @@ -477,6 +514,7 @@ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) controller->nw_send_key_index_set = NULL; controller->nw_frame_counter_set = NULL; controller->pan_ver_increment = NULL; + controller->pae_nvm_buffer = pae_nvm_buffer; ws_pae_controller_data_init(controller); @@ -510,12 +548,62 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) controller->key_index_set = false; controller->gtk_index = -1; controller->network_name = NULL; + controller->frame_cnt_store_timer = FRAME_COUNTER_STORE_INTERVAL; + ws_pae_controller_frame_counter_reset(&controller->stored_frame_counter); sec_prot_keys_gtks_init(&controller->gtks); sec_prot_keys_gtks_init(&controller->next_gtks); sec_prot_certs_init(&controller->certs); ws_pae_timers_settings_init(&controller->timer_settings); } +static void ws_pae_controller_frame_counter_read(pae_controller_t *controller) +{ + stored_frame_counter_t *counter = &controller->stored_frame_counter; + // If not already, read frame counter and check if index and hash matches + if (!counter->set && ws_pae_controller_nvm_frame_counter_read(&counter->index, counter->hash, &counter->frame_counter) >= 0) { + counter->frame_counter += FRAME_COUNTER_INCREMENT; + counter->set = true; + tr_debug("Read frame counter: %"PRIu32", index %i, hash %s, system time: %"PRIu32"", counter->frame_counter, counter->index, trace_array(counter->hash, 8), protocol_core_monotonic_time / 10); + // Write incremented frame counter + ws_pae_nvm_store_frame_counter_tlv_create(controller->pae_nvm_buffer, counter->index, counter->hash, counter->frame_counter); + ws_pae_controller_nvm_frame_counter_write(controller->pae_nvm_buffer); + } +} + +static void ws_pae_controller_frame_counter_reset(stored_frame_counter_t *counter) +{ + memset(counter->hash, 0, GTK_HASH_LEN); + counter->frame_counter = 0; + counter->index = -1; + counter->set = false; +} + +static uint32_t ws_pae_controller_frame_counter_get(stored_frame_counter_t *counter, uint8_t index, uint8_t *key_hash) +{ + uint32_t frame_counter = 0; + // If both index and hash matches uses the stored frame counter + if (counter->set && counter->index == index && memcmp(counter->hash, key_hash, GTK_HASH_LEN) == 0) { + frame_counter = counter->frame_counter; + } + + return frame_counter; +} + +static void ws_pae_controller_frame_counter_write(pae_controller_t *controller, uint8_t index, uint8_t *key_hash, uint32_t curr_frame_counter) +{ + stored_frame_counter_t *counter = &controller->stored_frame_counter; + // If index or hash changes, or frame counter has been incremented by the threshold updates frame counter + if (!counter->set || counter->index != index || memcmp(key_hash, counter->hash, 8) != 0 || curr_frame_counter > counter->frame_counter + FRAME_COUNTER_STORE_THRESHOLD) { + ws_pae_nvm_store_frame_counter_tlv_create(controller->pae_nvm_buffer, index, key_hash, curr_frame_counter); + ws_pae_controller_nvm_frame_counter_write(controller->pae_nvm_buffer); + counter->index = index; + counter->frame_counter = curr_frame_counter; + memcpy(counter->hash, key_hash, GTK_HASH_LEN); + counter->set = true; + tr_debug("Stored frame counter: %"PRIu32", index %i, hash %s, system time: %"PRIu32"", curr_frame_counter, index, trace_array(key_hash, 8), protocol_core_monotonic_time / 10); + } +} + int8_t ws_pae_controller_supp_init(protocol_interface_info_entry_t *interface_ptr) { pae_controller_t *controller = ws_pae_controller_get(interface_ptr); @@ -537,6 +625,8 @@ int8_t ws_pae_controller_supp_init(protocol_interface_info_entry_t *interface_pt ws_pae_supp_cb_register(controller->interface_ptr, controller->auth_completed, ws_pae_controller_nw_key_check_and_insert, ws_pae_controller_active_nw_key_set); + ws_pae_controller_frame_counter_read(controller); + return 0; } @@ -557,8 +647,11 @@ int8_t ws_pae_controller_auth_init(protocol_interface_info_entry_t *interface_pt controller->pae_gtks_updated = ws_pae_auth_gtks_updated; controller->pae_nw_key_index_update = ws_pae_auth_nw_key_index_update; + ws_pae_controller_frame_counter_read(controller); + return 0; } + int8_t ws_pae_controller_stop(protocol_interface_info_entry_t *interface_ptr) { pae_controller_t *controller = ws_pae_controller_get(interface_ptr); @@ -566,6 +659,9 @@ int8_t ws_pae_controller_stop(protocol_interface_info_entry_t *interface_ptr) return -1; } + // Stores frame counter + ws_pae_controller_frame_counter_store(controller); + // If PAE has been initialized, deletes it if (controller->pae_delete) { controller->pae_delete(interface_ptr); @@ -594,6 +690,7 @@ int8_t ws_pae_controller_delete(protocol_interface_info_entry_t *interface_ptr) } ns_list_remove(&pae_controller_list, controller); + ns_dyn_mem_free(controller->pae_nvm_buffer); ns_dyn_mem_free(controller); return 0; @@ -959,9 +1056,58 @@ void ws_pae_controller_slow_timer(uint16_t seconds) if (entry->pae_slow_timer) { entry->pae_slow_timer(seconds); } + + ws_pae_controller_frame_counter_timer(seconds, entry); } } +static void ws_pae_controller_frame_counter_timer(uint16_t seconds, pae_controller_t *entry) +{ + if (entry->frame_cnt_store_timer > seconds) { + entry->frame_cnt_store_timer -= seconds; + } else { + entry->frame_cnt_store_timer = FRAME_COUNTER_STORE_INTERVAL; + ws_pae_controller_frame_counter_store(entry); + } +} + +static void ws_pae_controller_frame_counter_store(pae_controller_t *entry) +{ + // Gets index of active GTK + int8_t active_index = entry->gtk_index; + + if (active_index >= 0) { + // Gets hash of the key + uint8_t *hash = entry->nw_key[active_index].hash; + + uint32_t curr_frame_counter; + entry->nw_frame_counter_read(entry->interface_ptr, &curr_frame_counter); + ws_pae_controller_frame_counter_write(entry, active_index, hash, curr_frame_counter); + } +} + + +static int8_t ws_pae_controller_nvm_frame_counter_read(uint8_t *index, uint8_t *hash, uint32_t *frame_counter) +{ + nvm_tlv_list_t tlv_list; + ns_list_init(&tlv_list); + + if (ws_pae_nvm_store_tlv_file_read(FRAME_COUNTER_FILE, &tlv_list) < 0) { + return -1; + } + + int8_t result = -1; + ns_list_foreach_safe(nvm_tlv_entry_t, entry, &tlv_list) { + if (ws_pae_nvm_store_frame_counter_tlv_read(entry, index, hash, frame_counter) >= 0) { + result = 0; + } + ns_list_remove(&tlv_list, entry); + ns_dyn_mem_free(entry); + } + + return result; +} + static pae_controller_t *ws_pae_controller_get(protocol_interface_info_entry_t *interface_ptr) { ns_list_foreach(pae_controller_t, entry, &pae_controller_list) { @@ -992,5 +1138,24 @@ static pae_controller_t *ws_pae_controller_get_or_create(int8_t interface_id) return controller; } +nvm_tlv_entry_t *ws_pae_controller_nvm_tlv_get(protocol_interface_info_entry_t *interface_ptr) +{ + pae_controller_t *controller = ws_pae_controller_get(interface_ptr); + if (!controller) { + return NULL; + } + + return controller->pae_nvm_buffer; +} + +static void ws_pae_controller_nvm_frame_counter_write(nvm_tlv_entry_t *tlv_entry) +{ + nvm_tlv_list_t tlv_list; + ns_list_init(&tlv_list); + ns_list_add_to_end(&tlv_list, tlv_entry); + ws_pae_nvm_store_tlv_file_write(FRAME_COUNTER_FILE, &tlv_list); + +} + #endif /* HAVE_WS */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h index c7d75d36100..2f1b6ce0502 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h @@ -20,6 +20,7 @@ #ifdef HAVE_WS +struct nvm_tlv_entry; /** * ws_pae_controller_set_target sets EAPOL target for PAE supplicant * @@ -384,6 +385,15 @@ typedef void ws_pae_controller_nw_send_key_index_set(protocol_interface_info_ent */ typedef void ws_pae_controller_nw_frame_counter_set(protocol_interface_info_entry_t *interface_ptr, uint32_t counter); +/** + * ws_pae_controller_nw_frame_counter_read network frame counter read callback + * + * \param interface_ptr interface + * \param counter frame counter + * + */ +typedef void ws_pae_controller_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter); + /** * ws_pae_controller_auth_completed authentication completed callback * @@ -410,13 +420,14 @@ typedef void ws_pae_controller_pan_ver_increment(protocol_interface_info_entry_t * \param nw_key_clear network key clear callback * \param nw_send_key_index_set network send key index set callback * \param nw_frame_counter_set network frame counter set callback + * \param nw_frame_counter_read network frame counter read callback * \param pan_ver_increment PAN version increment callback * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_pan_ver_increment *pan_ver_increment); +int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read, ws_pae_controller_pan_ver_increment *pan_ver_increment); /** * ws_pae_controller_fast_timer PAE controller fast timer call @@ -435,6 +446,8 @@ void ws_pae_controller_fast_timer(uint16_t ticks); */ void ws_pae_controller_slow_timer(uint16_t seconds); +struct nvm_tlv_entry *ws_pae_controller_nvm_tlv_get(protocol_interface_info_entry_t *interface_ptr); + #else #define ws_pae_controller_set_target(interface_ptr, target_pan_id, target_dest_eui_64) @@ -455,6 +468,7 @@ void ws_pae_controller_slow_timer(uint16_t seconds); #define ws_pae_controller_stop(interface_ptr) #define ws_pae_controller_delete(interface_ptr) #define ws_pae_controller_cb_register(interface_ptr, completed, nw_key_set, nw_key_clear, nw_send_key_index_set, pan_ver_increment) 1 +#define ws_pae_controller_nvm_tlv_get(interface_ptr) NULL #endif diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c index 13d311f8f48..6886a71408e 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c @@ -156,9 +156,9 @@ supp_entry_t *ws_pae_lib_supp_list_add(supp_list_t *supp_list, const kmp_addr_t } ws_pae_lib_supp_init(entry); - - entry->addr = kmp_address_create(KMP_ADDR_EUI_64_AND_IP, 0); - kmp_address_copy(entry->addr, addr); + memset(&entry->addr, 0, sizeof(kmp_addr_t)); + entry->addr.type = KMP_ADDR_EUI_64_AND_IP; + kmp_address_copy(&entry->addr, addr); ns_list_add_to_end(supp_list, entry); @@ -178,7 +178,7 @@ int8_t ws_pae_lib_supp_list_remove(supp_list_t *supp_list, supp_entry_t *supp) supp_entry_t *ws_pae_lib_supp_list_entry_eui_64_get(const supp_list_t *supp_list, const uint8_t *eui_64) { ns_list_foreach(supp_entry_t, cur, supp_list) { - if (memcmp(kmp_address_eui_64_get(cur->addr), eui_64, 8) == 0) { + if (memcmp(cur->addr.eui_64, eui_64, 8) == 0) { return cur; } } @@ -213,10 +213,10 @@ void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, timer_settin { ns_list_foreach(supp_entry_t, entry, supp_list) { if (sec_prot_keys_pmk_lifetime_decrement(&entry->sec_keys, timer_settings->pmk_lifetime, seconds)) { - tr_info("PMK and PTK expired, eui-64: %s, system time: %"PRIu32"", trace_array(kmp_address_eui_64_get(entry->addr), 8), protocol_core_monotonic_time / 10); + tr_info("PMK and PTK expired, eui-64: %s, system time: %"PRIu32"", trace_array(entry->addr.eui_64, 8), protocol_core_monotonic_time / 10); } if (sec_prot_keys_ptk_lifetime_decrement(&entry->sec_keys, timer_settings->ptk_lifetime, seconds)) { - tr_info("PTK expired, eui-64: %s, system time: %"PRIu32"", trace_array(kmp_address_eui_64_get(entry->addr), 8), protocol_core_monotonic_time / 10); + tr_info("PTK expired, eui-64: %s, system time: %"PRIu32"", trace_array(entry->addr.eui_64, 8), protocol_core_monotonic_time / 10); } } @@ -225,7 +225,7 @@ void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, timer_settin void ws_pae_lib_supp_init(supp_entry_t *entry) { ws_pae_lib_kmp_list_init(&entry->kmp_list); - entry->addr = 0; + memset(&entry->addr, 0, sizeof(kmp_addr_t)); memset(&entry->sec_keys, 0, sizeof(sec_prot_keys_t)); entry->ticks = 0; entry->retry_ticks = 0; @@ -236,7 +236,6 @@ void ws_pae_lib_supp_init(supp_entry_t *entry) void ws_pae_lib_supp_delete(supp_entry_t *entry) { ws_pae_lib_kmp_list_free(&entry->kmp_list); - kmp_address_delete(entry->addr); } bool ws_pae_lib_supp_timer_update(supp_entry_t *entry, uint16_t ticks, ws_pae_lib_kmp_timer_timeout timeout) @@ -260,7 +259,7 @@ bool ws_pae_lib_supp_timer_update(supp_entry_t *entry, uint16_t ticks, ws_pae_li entry->retry_ticks -= ticks; } else { if (entry->retry_ticks > 0) { - tr_info("EAP-TLS max ongoing delay timeout eui-64: %s", trace_array(kmp_address_eui_64_get(entry->addr), 8)); + tr_info("EAP-TLS max ongoing delay timeout eui-64: %s", trace_array(entry->addr.eui_64, 8)); } entry->retry_ticks = 0; } @@ -279,7 +278,7 @@ void ws_pae_lib_supp_list_to_active(supp_list_t *active_supp_list, supp_list_t * return; } - tr_debug("PAE: to active, eui-64: %s", trace_array(kmp_address_eui_64_get(entry->addr), 8)); + tr_debug("PAE: to active, eui-64: %s", trace_array(entry->addr.eui_64, 8)); ns_list_remove(inactive_supp_list, entry); ns_list_add_to_start(active_supp_list, entry); @@ -288,9 +287,7 @@ void ws_pae_lib_supp_list_to_active(supp_list_t *active_supp_list, supp_list_t * entry->ticks = 0; // Adds relay address data - kmp_addr_t *addr = kmp_address_create(KMP_ADDR_EUI_64_AND_IP, kmp_address_eui_64_get(entry->addr)); - kmp_address_delete(entry->addr); - entry->addr = addr; + entry->addr.type = KMP_ADDR_EUI_64_AND_IP; } void ws_pae_lib_supp_list_to_inactive(supp_list_t *active_supp_list, supp_list_t *inactive_supp_list, supp_entry_t *entry) @@ -299,10 +296,10 @@ void ws_pae_lib_supp_list_to_inactive(supp_list_t *active_supp_list, supp_list_t return; } - tr_debug("PAE: to inactive, eui-64: %s", trace_array(kmp_address_eui_64_get(entry->addr), 8)); + tr_debug("PAE: to inactive, eui-64: %s", trace_array(entry->addr.eui_64, 8)); if (entry->access_revoked) { - tr_info("Access revoked; deleted, eui-64: %s", trace_array(kmp_address_eui_64_get(entry->addr), 8)); + tr_info("Access revoked; deleted, eui-64: %s", trace_array(entry->addr.eui_64, 8)); ws_pae_lib_supp_list_remove(active_supp_list, entry); return; } @@ -314,9 +311,9 @@ void ws_pae_lib_supp_list_to_inactive(supp_list_t *active_supp_list, supp_list_t entry->ticks = 0; // Removes relay address data - kmp_addr_t *addr = kmp_address_create(KMP_ADDR_EUI_64, kmp_address_eui_64_get(entry->addr)); - kmp_address_delete(entry->addr); - entry->addr = addr; + entry->addr.type = KMP_ADDR_EUI_64; + entry->addr.port = 0; + memset(entry->addr.relay_address, 0, 16); } uint16_t ws_pae_lib_supp_list_kmp_count(supp_list_t *supp_list, kmp_type_e type) diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.h index a9d239b950e..2569637dee1 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.h @@ -33,7 +33,7 @@ typedef NS_LIST_HEAD(kmp_entry_t, link) kmp_list_t; typedef struct { kmp_list_t kmp_list; /**< Ongoing KMP negotiations */ - kmp_addr_t *addr; /**< EUI-64 (Relay IP address, Relay port) */ + kmp_addr_t addr; /**< EUI-64 (Relay IP address, Relay port) */ sec_prot_keys_t sec_keys; /**< Security keys */ uint32_t ticks; /**< Ticks */ uint16_t retry_ticks; /**< Retry ticks */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c index bf07505771e..7cb2f42af8a 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c @@ -35,6 +35,7 @@ #define PAE_NVM_NW_INFO_TAG 1 #define PAE_NVM_KEYS_TAG 2 +#define PAE_NVM_FRAME_COUNTER_TAG 3 // pan_id (2) + network name (33) + (GTK set (1) + GTK lifetime (4) + GTK (16)) * 4 #define PAE_NVM_NW_INFO_LEN 2 + 33 + (1 + 4 + GTK_LEN) * GTK_NUM @@ -42,12 +43,17 @@ // PTK EUI-64 set (1) + PTK EUI-64 (8) + PMK set (1) + PMK (32) + PMK replay counter (8) + PTK set (1) + PTK (48) #define PAE_NVM_KEYS_LEN 1 + 8 + 1 + PMK_LEN + 8 + 1 + PTK_LEN -nvm_tlv_entry_t *ws_pae_nvm_store_nw_info_tlv_create(uint16_t pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks) +// GTK hash (8), frame counter (4), index (1) +#define PAE_NVM_FRAME_COUNTER_LEN 8 + 4 + 1 + +nvm_tlv_entry_t *ws_pae_buffer_allocate(void) +{ + //Allocate worts case buffer + return ns_dyn_mem_temporary_alloc(sizeof(nvm_tlv_entry_t) + PAE_NVM_NW_INFO_LEN); +} + +void ws_pae_nvm_store_nw_info_tlv_create(nvm_tlv_entry_t *tlv_entry, uint16_t pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks) { - nvm_tlv_entry_t *tlv_entry = ns_dyn_mem_temporary_alloc(sizeof(nvm_tlv_entry_t) + PAE_NVM_NW_INFO_LEN); - if (!tlv_entry) { - return NULL; - } tlv_entry->tag = PAE_NVM_NW_INFO_TAG; tlv_entry->len = PAE_NVM_NW_INFO_LEN; @@ -78,7 +84,6 @@ nvm_tlv_entry_t *ws_pae_nvm_store_nw_info_tlv_create(uint16_t pan_id, char *nw_n tr_debug("NVM NW_INFO write PAN ID %i name: %s", pan_id, nw_name); - return tlv_entry; } int8_t ws_pae_nvm_store_nw_info_tlv_read(nvm_tlv_entry_t *tlv_entry, uint16_t *pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks) @@ -117,13 +122,8 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nvm_tlv_entry_t *tlv_entry, uint16_t *p return 0; } -nvm_tlv_entry_t *ws_pae_nvm_store_keys_tlv_create(sec_prot_keys_t *sec_keys) +void ws_pae_nvm_store_keys_tlv_create(nvm_tlv_entry_t *tlv_entry, sec_prot_keys_t *sec_keys) { - nvm_tlv_entry_t *tlv_entry = ns_dyn_mem_temporary_alloc(sizeof(nvm_tlv_entry_t) + PAE_NVM_KEYS_LEN); - if (!tlv_entry) { - return NULL; - } - tlv_entry->tag = PAE_NVM_KEYS_TAG; tlv_entry->len = PAE_NVM_KEYS_LEN; @@ -164,7 +164,6 @@ nvm_tlv_entry_t *ws_pae_nvm_store_keys_tlv_create(sec_prot_keys_t *sec_keys) tr_debug("NVM KEYS write"); - return tlv_entry; } int8_t ws_pae_nvm_store_keys_tlv_read(nvm_tlv_entry_t *tlv_entry, sec_prot_keys_t *sec_keys) @@ -209,5 +208,44 @@ int8_t ws_pae_nvm_store_keys_tlv_read(nvm_tlv_entry_t *tlv_entry, sec_prot_keys_ return 0; } +void ws_pae_nvm_store_frame_counter_tlv_create(nvm_tlv_entry_t *tlv_entry, uint8_t index, uint8_t *hash, uint32_t frame_counter) +{ + + tlv_entry->tag = PAE_NVM_FRAME_COUNTER_TAG; + tlv_entry->len = PAE_NVM_FRAME_COUNTER_LEN; + + uint8_t *tlv = ((uint8_t *) &tlv_entry->tag) + NVM_TLV_FIXED_LEN; + + memcpy(tlv, hash, GTK_HASH_LEN); + tlv += GTK_HASH_LEN; + tlv = common_write_32_bit(frame_counter, tlv); + *tlv = index; + + tr_debug("NVM FRAME COUNTER write"); +} + +int8_t ws_pae_nvm_store_frame_counter_tlv_read(nvm_tlv_entry_t *tlv_entry, uint8_t *index, uint8_t *hash, uint32_t *frame_counter) +{ + if (!tlv_entry || !frame_counter) { + return -1; + } + + if (tlv_entry->tag != PAE_NVM_FRAME_COUNTER_TAG || tlv_entry->len != PAE_NVM_FRAME_COUNTER_LEN) { + return -1; + } + + uint8_t *tlv = ((uint8_t *) &tlv_entry->tag) + NVM_TLV_FIXED_LEN; + + memcpy(hash, tlv, GTK_HASH_LEN); + tlv += GTK_HASH_LEN; + *frame_counter = common_read_32_bit(tlv); + tlv += 4; + *index = *tlv; + + tr_debug("NVM FRAME COUNTER read"); + + return 0; +} + #endif /* HAVE_WS */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h index 109017a7006..ce763d7844b 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h @@ -27,6 +27,7 @@ /** * ws_pae_nvm_store_nw_info_tlv_create create NVM network info TLV * + * \param tlv_entry TLV entry pointer * \param pan_id PAN ID * \param nw_name network name * \param gtks GTK keys @@ -34,7 +35,7 @@ * \return TLV entry or NULL * */ -nvm_tlv_entry_t *ws_pae_nvm_store_nw_info_tlv_create(uint16_t pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks); +void ws_pae_nvm_store_nw_info_tlv_create(nvm_tlv_entry_t *tlv_entry, uint16_t pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks); /** * ws_pae_nvm_store_nw_info_tlv_read read from NVM network info TLV @@ -53,12 +54,11 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nvm_tlv_entry_t *tlv_entry, uint16_t *p /** * ws_pae_nvm_store_keys_tlv_create create NVM keys TLV * + * \param tlv_entry TLV entry buffer pointer * \param sec_keys security keys * - * \return TLV entry or NULL - * */ -nvm_tlv_entry_t *ws_pae_nvm_store_keys_tlv_create(sec_prot_keys_t *sec_keys); +void ws_pae_nvm_store_keys_tlv_create(nvm_tlv_entry_t *tlv_entry, sec_prot_keys_t *sec_keys); /** * ws_pae_nvm_store_nw_info_tlv_read read from NVM keys TLV @@ -72,4 +72,32 @@ nvm_tlv_entry_t *ws_pae_nvm_store_keys_tlv_create(sec_prot_keys_t *sec_keys); */ int8_t ws_pae_nvm_store_keys_tlv_read(nvm_tlv_entry_t *tlv_entry, sec_prot_keys_t *sec_keys); +/** + * ws_pae_nvm_store_frame_counter_tlv_create create NVM frame counter TLV + * + * \param tlv_entry TLV entry buffer pointer + * \param index index + * \param hash hash + * \param frame_counter frame counter + * + * + */ +void ws_pae_nvm_store_frame_counter_tlv_create(nvm_tlv_entry_t *tlv_entry, uint8_t index, uint8_t *hash, uint32_t frame_counter); + +/** + * ws_pae_nvm_store_frame_counter_tlv_read read from NVM frame counter TLV + * + * \param tlv_entry TLV entry + * \param index index + * \param hash hash + * \param frame_counter frame counter + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_nvm_store_frame_counter_tlv_read(nvm_tlv_entry_t *tlv_entry, uint8_t *index, uint8_t *hash, uint32_t *frame_counter); + +nvm_tlv_entry_t *ws_pae_buffer_allocate(void); + #endif /* WS_PAE_NVM_DATA_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c index 1c1b357af9a..aa873bdf865 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c @@ -193,6 +193,10 @@ static int8_t ws_pae_nvm_store_read(const char *file_name, nvm_tlv_list_t *tlv_l fclose(fp); if (failure) { + ns_list_foreach_safe(nvm_tlv_entry_t, entry, tlv_list) { + ns_list_remove(tlv_list, entry); + ns_dyn_mem_free(entry); + } tr_error("NVM read error %s", file_name); return PAE_NVM_FILE_READ_ERROR; } else { diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h index 130ae73f034..84838ef6f37 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h @@ -27,7 +27,12 @@ // tag + length #define NVM_TLV_FIXED_LEN 4 -typedef struct { +// file names +#define NW_INFO_FILE_NAME "pae_nw_info" +#define KEYS_FILE_NAME "pae_keys" +#define FRAME_COUNTER_FILE_NAME "pae_frame_counter" + +typedef struct nvm_tlv_entry { ns_list_link_t link; /**< Link */ uint16_t tag; /**< Unique tag */ uint16_t len; /**< Number of the bytes after the length field */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c index fea7d9ce2b7..4eea7843cb5 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c @@ -73,9 +73,6 @@ #define INITIAL_KEY_TIMER_MIN 3 #define INITIAL_KEY_TIMER_MAX 30 -const char *NW_INFO_FILE = "pae_nw_info"; -const char *KEYS_FILE = "pae_keys"; - typedef struct { char network_name[33]; /**< Network name for keys */ sec_prot_gtk_keys_t *gtks; /**< Link to GTKs */ @@ -106,6 +103,7 @@ typedef struct { bool timer_running : 1; /**< Timer is running */ bool new_br_eui_64_set : 1; /**< Border router address has been set */ bool new_br_eui_64_fresh : 1; /**< Border router address is fresh (set during this authentication attempt) */ + bool entry_address_active: 1; } pae_supp_t; @@ -151,6 +149,9 @@ static const eapol_pdu_recv_cb_data_t eapol_pdu_recv_cb_data = { .receive = kmp_eapol_pdu_if_receive }; +static const char *NW_INFO_FILE = NW_INFO_FILE_NAME; +static const char *KEYS_FILE = KEYS_FILE_NAME; + static int8_t tasklet_id = -1; static NS_LIST_DEFINE(pae_supp_list, pae_supp_t, link); @@ -185,7 +186,8 @@ int8_t ws_pae_supp_authenticate(protocol_interface_info_entry_t *interface_ptr, // Stores target/parent address kmp_address_init(KMP_ADDR_EUI_64, &pae_supp->target_addr, dest_eui_64); // Sets target address in use - pae_supp->entry.addr = (kmp_addr_t *) &pae_supp->target_addr; + pae_supp->entry.addr = pae_supp->target_addr; + pae_supp->entry_address_active = true; pae_supp->auth_requested = true; @@ -326,7 +328,6 @@ int8_t ws_pae_supp_nw_key_index_update(protocol_interface_info_entry_t *interfac } if (sec_prot_keys_gtk_status_active_set(&pae_supp->gtks, index) >= 0) { - tr_info("NW send key index set: %i", index + 1); pae_supp->nw_key_index_set(interface_ptr, index); } else { tr_info("NW send key index: %i, no changes", index + 1); @@ -349,21 +350,26 @@ static void ws_pae_supp_nvm_update(pae_supp_t *pae_supp) ws_pae_supp_nvm_keys_write(pae_supp); sec_prot_keys_updated_reset(&pae_supp->entry.sec_keys); } + + } static int8_t ws_pae_supp_nvm_nw_info_write(pae_supp_t *pae_supp) { + nvm_tlv_entry_t *tlv_entry = ws_pae_controller_nvm_tlv_get(pae_supp->interface_ptr); + if (!tlv_entry) { + return -1; + } + nvm_tlv_list_t tlv_list; ns_list_init(&tlv_list); - nvm_tlv_entry_t *tlv_entry = ws_pae_nvm_store_nw_info_tlv_create(pae_supp->sec_keys_nw_info.key_pan_id, - pae_supp->sec_keys_nw_info.network_name, - &pae_supp->gtks); + ws_pae_nvm_store_nw_info_tlv_create(tlv_entry, pae_supp->sec_keys_nw_info.key_pan_id, + pae_supp->sec_keys_nw_info.network_name, + &pae_supp->gtks); ns_list_add_to_end(&tlv_list, tlv_entry); ws_pae_nvm_store_tlv_file_write(NW_INFO_FILE, &tlv_list); - ns_list_remove(&tlv_list, tlv_entry); - ns_dyn_mem_free(tlv_entry); return 0; } @@ -388,15 +394,18 @@ static int8_t ws_pae_supp_nvm_nw_info_read(pae_supp_t *pae_supp) static int8_t ws_pae_supp_nvm_keys_write(pae_supp_t *pae_supp) { + nvm_tlv_entry_t *tlv_entry = ws_pae_controller_nvm_tlv_get(pae_supp->interface_ptr); + if (!tlv_entry) { + return -1; + } + nvm_tlv_list_t tlv_list; ns_list_init(&tlv_list); - nvm_tlv_entry_t *tlv_entry = ws_pae_nvm_store_keys_tlv_create(&pae_supp->entry.sec_keys); + ws_pae_nvm_store_keys_tlv_create(tlv_entry, &pae_supp->entry.sec_keys); ns_list_add_to_end(&tlv_list, tlv_entry); ws_pae_nvm_store_tlv_file_write(KEYS_FILE, &tlv_list); - ns_list_remove(&tlv_list, tlv_entry); - ns_dyn_mem_free(tlv_entry); return 0; } @@ -438,7 +447,7 @@ static int8_t ws_pae_supp_initial_key_send(pae_supp_t *pae_supp) // Stores target/parent address kmp_address_init(KMP_ADDR_EUI_64, &pae_supp->target_addr, parent_eui_64); // Sets parent address in use - pae_supp->entry.addr = (kmp_addr_t *) &pae_supp->target_addr; + pae_supp->entry.addr = pae_supp->target_addr; ws_pae_lib_supp_timer_ticks_set(&pae_supp->entry, WAIT_FOR_REAUTHENTICATION_TICKS); tr_info("PAE wait for auth seconds: %i", WAIT_FOR_REAUTHENTICATION_TICKS / 10); @@ -449,9 +458,9 @@ static int8_t ws_pae_supp_initial_key_send(pae_supp_t *pae_supp) return -1; } - tr_info("EAPOL target: %s", trace_array(kmp_address_eui_64_get(pae_supp->entry.addr), 8)); + tr_info("EAPOL target: %s", trace_array(kmp_address_eui_64_get(&pae_supp->entry.addr), 8)); - kmp_api_create_request(kmp, IEEE_802_1X_MKA_KEY, pae_supp->entry.addr, &pae_supp->entry.sec_keys); + kmp_api_create_request(kmp, IEEE_802_1X_MKA_KEY, &pae_supp->entry.addr, &pae_supp->entry.sec_keys); return 0; } @@ -735,8 +744,7 @@ void ws_pae_supp_fast_timer(uint16_t ticks) tr_debug("PAE idle"); // Sets target/parent address to null - pae_supp->entry.addr = NULL; - + pae_supp->entry_address_active = false; // If not already completed, restart bootstrap ws_pae_supp_authenticate_response(pae_supp, false); @@ -846,8 +854,8 @@ static int8_t ws_pae_supp_eapol_pdu_address_check(protocol_interface_info_entry_ } // Message from EAPOL target node, route to self - if (pae_supp->entry.addr) { - if (memcmp(eui_64, kmp_address_eui_64_get(pae_supp->entry.addr), 8) == 0) { + if (pae_supp->entry_address_active) { + if (memcmp(eui_64, pae_supp->entry.addr.eui_64, 8) == 0) { return 0; } } @@ -945,7 +953,7 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ return NULL; } - if (!pae_supp->entry.addr) { + if (!pae_supp->entry_address_active) { // Does no longer wait for authentication, ignores message return NULL; } @@ -954,7 +962,7 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ pae_supp->auth_trickle_running = false; // Updates parent address - kmp_address_copy(pae_supp->entry.addr, addr); + kmp_address_copy(&pae_supp->entry.addr, addr); // Check if ongoing kmp_api_t *kmp = ws_pae_lib_kmp_list_type_get(&pae_supp->entry.kmp_list, type); @@ -991,7 +999,7 @@ static kmp_api_t *ws_pae_supp_kmp_create_and_start(kmp_service_t *service, kmp_t } // Updates parent address - kmp_api_addr_set(kmp, pae_supp->entry.addr); + kmp_api_addr_set(kmp, &pae_supp->entry.addr); // Sets security keys to KMP kmp_api_sec_keys_set(kmp, &pae_supp->entry.sec_keys); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.c new file mode 100644 index 00000000000..85f25112213 --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2018-2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "nsconfig.h" +#include "ns_types.h" +#include "ns_trace.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_common.h" +#include "ws_management_api.h" + +#define TRACE_GROUP "wsst" + +#ifdef HAVE_WS + +int ws_statistics_start(int8_t interface_id, ws_statistics_t *stats_ptr) +{ + if (!stats_ptr) { + return -1; + } + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur)) { + return -1; + } + cur->ws_info->stored_stats_ptr = stats_ptr; + return 0; +} + +int ws_statistics_stop(int8_t interface_id) +{ + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur)) { + return -1; + } + cur->ws_info->stored_stats_ptr = NULL; + return 0; +} + +void ws_stats_update(protocol_interface_info_entry_t *cur, ws_stats_type_t type, uint32_t update_val) +{ + if (!cur || !ws_info(cur)) { + return; + } + ws_statistics_t *stored_stats = cur->ws_info->stored_stats_ptr; + + if (stored_stats) { + switch (type) { + case STATS_WS_ASYNCH_TX: + stored_stats->asynch_tx_count += update_val; + break; + case STATS_WS_ASYNCH_RX: + stored_stats->asynch_rx_count += update_val; + break; + } + } +} +#endif // HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.h new file mode 100644 index 00000000000..8f7776d97d5 --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_stats.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2018-2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_STATS_H_ +#define WS_STATS_H_ + +#ifdef HAVE_WS + +typedef enum { + STATS_WS_ASYNCH_TX, + STATS_WS_ASYNCH_RX +} ws_stats_type_t; + +void ws_stats_update(protocol_interface_info_entry_t *cur, ws_stats_type_t type, uint32_t update_val); + +#endif // HAVE_WS + +#endif // WS_STATS_H_ diff --git a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c index 3dfac3c936c..bcd659f9b99 100644 --- a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c +++ b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c @@ -1037,10 +1037,7 @@ buffer_t *icmpv6_up(buffer_t *buf) cur = buf->interface; - if (buf->options.ll_security_bypass_rx) { - tr_debug("ICMP: Drop by EP"); - goto drop; - } + if (data_len < 4) { //tr_debug("Ic1"); @@ -1051,6 +1048,13 @@ buffer_t *icmpv6_up(buffer_t *buf) buf->options.type = *dptr++; buf->options.code = *dptr++; + if (buf->options.ll_security_bypass_rx) { + if (!ws_info(buf->interface) || !(buf->options.type == ICMPV6_TYPE_INFO_RPL_CONTROL && buf->options.code == ICMPV6_CODE_RPL_DIS)) { + //tr_debug("ICMP: Drop by EP"); + goto drop; + } + } + /* Check FCS first */ if (buffer_ipv6_fcf(buf, IPV6_NH_ICMPV6)) { tr_warn("ICMP cksum error!"); @@ -1369,6 +1373,21 @@ void ack_remove_neighbour_cb(struct buffer *buffer_ptr, uint8_t status) } +static void icmpv6_aro_cb(buffer_t *buf, uint8_t status) +{ + uint8_t ll_address[16]; + if (buf->dst_sa.addr_type == ADDR_IPV6) { + /*Full IPv6 address*/ + memcpy(ll_address, buf->dst_sa.address, 16); + } else if (buf->dst_sa.addr_type == ADDR_802_15_4_LONG) { + // Build link local address from long MAC address + memcpy(ll_address, ADDR_LINK_LOCAL_PREFIX, 8); + memcpy(ll_address + 8, &buf->dst_sa.address[2], 8); + ll_address[8] ^= 2; + } + rpl_control_address_register_done(buf->interface, ll_address, status); +} + buffer_t *icmpv6_build_ns(protocol_interface_info_entry_t *cur, const uint8_t target_addr[16], const uint8_t *prompting_src_addr, bool unicast, bool unspecified_source, const aro_t *aro) { if (!cur || addr_is_ipv6_multicast(target_addr)) { @@ -1444,7 +1463,7 @@ buffer_t *icmpv6_build_ns(protocol_interface_info_entry_t *cur, const uint8_t ta /* If ARO Success sending is omitted, MAC ACK is used instead */ /* Setting callback for receiving ACK from adaptation layer */ if (aro && cur->ipv6_neighbour_cache.omit_na_aro_success) { - buf->ack_receive_cb = rpl_control_address_register_done; + buf->ack_receive_cb = icmpv6_aro_cb; } } if (unicast && (!aro && cur->ipv6_neighbour_cache.omit_na)) { @@ -1677,6 +1696,10 @@ buffer_t *icmpv6_build_na(protocol_interface_info_entry_t *cur, bool solicited, } if (ws_info(cur) && aro && aro->status != ARO_SUCCESS) { /*If Aro failed we will kill the neigbour after we have succeeded in sending message*/ + if (!ws_common_negative_aro_mark(cur, aro->eui64)) { + tr_debug("Neighbour removed for negative response send"); + return buffer_free(buf); + } buf->ack_receive_cb = ack_remove_neighbour_cb; } diff --git a/features/nanostack/sal-stack-nanostack/source/Core/include/ns_address_internal.h b/features/nanostack/sal-stack-nanostack/source/Core/include/ns_address_internal.h index 651d15cf2a7..cce42c64478 100644 --- a/features/nanostack/sal-stack-nanostack/source/Core/include/ns_address_internal.h +++ b/features/nanostack/sal-stack-nanostack/source/Core/include/ns_address_internal.h @@ -96,8 +96,6 @@ typedef struct if_address_entry { bool temporary: 1; // RFC 4941 temporary address bool tentative: 1; // Tentative address (Duplicate Address Detection running) bool group_added: 1; // Solicited-Node group added - uint8_t addr_reg_pend; // Bitmask for pending address registrations. Based on RPL path control bits - uint8_t addr_reg_done; // Bitmask for address registration done. Based on RPL path control bits if_address_source_t source; // if_address_callback_fn *cb; // Address protocol callback function void *data; // Address protocol data diff --git a/features/nanostack/sal-stack-nanostack/source/Core/include/ns_monitor.h b/features/nanostack/sal-stack-nanostack/source/Core/include/ns_monitor.h new file mode 100644 index 00000000000..6ed6d3a9e4f --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/source/Core/include/ns_monitor.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file ns_monitor.h + * \brief Utility functions concerning IPv6 stack monitoring. + * + * Module can monitor nanostack heap usage and release memory if heap usage is too high. + * Mmeory monitoring can work if memory statistics are enabled in nsdynmemLIB. + * + */ + +#ifndef _NS_MONITOR_H +#define _NS_MONITOR_H + +int ns_monitor_init(void); + +int ns_monitor_clear(void); + +void ns_monitor_timer(uint16_t seconds); + +int ns_monitor_heap_gc_threshold_set(uint8_t percentage_high, uint8_t percentage_critical); + +#endif // _NS_MONITOR_H + diff --git a/features/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c b/features/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c index ec884a39076..ca998f361eb 100644 --- a/features/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c +++ b/features/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c @@ -865,7 +865,6 @@ void addr_fast_timer(protocol_interface_info_entry_t *cur, uint_fast16_t ticks) } #endif } else { - addr->addr_reg_done = 0; addr_cb(cur, addr, ADDR_CALLBACK_TIMER); } diff --git a/features/nanostack/sal-stack-nanostack/source/Core/ns_monitor.c b/features/nanostack/sal-stack-nanostack/source/Core/ns_monitor.c new file mode 100644 index 00000000000..7b17edbad30 --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/source/Core/ns_monitor.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file ns_monitor.c + * \brief Utility functions for nanostack maintenance + * + * This module tracks stack current heap usage and triggers GC if heap usage is too high. + * GC is triggered by: + * 1. Heap usage is above HEAP_USAGE_HIGH + * 2. Heap usage is above HEAP_USAGE_CRITICAL + * 3. If nsdynmemLIB memory allocation has failed since last check + */ + +#include "nsconfig.h" +#include "ns_types.h" +#define HAVE_DEBUG +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "ipv6_stack/ipv6_routing_table.h" +#include "NWK_INTERFACE/Include/protocol.h" + +#define TRACE_GROUP "mntr" + +typedef enum { + NS_MONITOR_STATE_HEAP_GC_IDLE = 0, + NS_MONITOR_STATE_HEAP_GC_HIGH, + NS_MONITOR_STATE_GC_CRITICAL +} ns_monitor_state_e; + +#define HEAP_HIGH_WATERWARK (0.95) /* Heap usage HIGH threshold */ +#define HEAP_CRITICAL_WATERMARK (0.99) /* Heap usage CRITICAL threshold */ + +#define NS_MAINTENANCE_TIMER_INTERVAL 10 // Maintenance interval + +typedef struct ns_monitor__s { + ns_mem_heap_size_t heap_high_watermark; + ns_mem_heap_size_t heap_critical_watermark; + uint32_t prev_heap_alloc_fail_cnt; + ns_monitor_state_e ns_monitor_heap_gc_state; + const mem_stat_t *mem_stats; + uint16_t ns_maintenance_timer; +} ns_monitor_t; + +static ns_monitor_t *ns_monitor_ptr = NULL; + +typedef void (ns_maintenance_gc_cb)(bool full_gc); + +/* + * Garbage collection functions. + * Add more GC performing functions to the table + * + */ +static ns_maintenance_gc_cb *ns_maintenance_gc_functions[] = { + ipv6_destination_cache_forced_gc +}; + +static void ns_monitor_heap_gc(bool full_gc) +{ + (void) full_gc; + + for (unsigned int i = 0; i < sizeof(ns_maintenance_gc_functions) / sizeof(ns_maintenance_gc_functions[0]); i++) { + if (ns_maintenance_gc_functions[i]) { + (ns_maintenance_gc_functions[i])(full_gc); + } + } +} + +static void ns_monitor_periodic_heap_health_check(void) +{ + if (ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes > ns_monitor_ptr->heap_critical_watermark) { + // Heap usage above CRITICAL + if (ns_monitor_ptr->ns_monitor_heap_gc_state != NS_MONITOR_STATE_GC_CRITICAL) { + ns_mem_heap_size_t prev_heap_sector_allocated_bytes = ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes; + tr_debug("heap %lu/%lu", (unsigned long)ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes, (unsigned long)ns_monitor_ptr->mem_stats->heap_sector_size); + ns_monitor_heap_gc(true); + ns_monitor_ptr->ns_monitor_heap_gc_state = NS_MONITOR_STATE_GC_CRITICAL; + tr_info("Stack GC critical: freed %lu bytes", (unsigned long)(prev_heap_sector_allocated_bytes - ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes)); + } + } else if (ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes > ns_monitor_ptr->heap_high_watermark) { + // Heap usage above HIGH + if (ns_monitor_ptr->ns_monitor_heap_gc_state == NS_MONITOR_STATE_HEAP_GC_IDLE) { + ns_mem_heap_size_t prev_heap_sector_allocated_bytes = ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes; + tr_debug("heap %lu/%lu", (unsigned long)ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes, (unsigned long)ns_monitor_ptr->mem_stats->heap_sector_size); + ns_monitor_heap_gc(false); + ns_monitor_ptr->ns_monitor_heap_gc_state = NS_MONITOR_STATE_HEAP_GC_HIGH; + tr_info("Stack GC high: freed %lu bytes", (unsigned long)(prev_heap_sector_allocated_bytes - ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes)); + } + } else if (ns_monitor_ptr->mem_stats->heap_sector_allocated_bytes <= ns_monitor_ptr->heap_high_watermark) { + // Heap usage in normal range + ns_monitor_ptr->ns_monitor_heap_gc_state = NS_MONITOR_STATE_HEAP_GC_IDLE; + } +} + +void ns_monitor_timer(uint16_t seconds) +{ + if (ns_monitor_ptr) { + ns_monitor_ptr->ns_maintenance_timer += seconds; + + if (ns_monitor_ptr->mem_stats->heap_alloc_fail_cnt > ns_monitor_ptr->prev_heap_alloc_fail_cnt) { + // Heap allocation failure occurred since last check + ns_monitor_ptr->prev_heap_alloc_fail_cnt = ns_monitor_ptr->mem_stats->heap_alloc_fail_cnt; + if (ns_monitor_ptr->ns_monitor_heap_gc_state != NS_MONITOR_STATE_GC_CRITICAL) { + ns_monitor_ptr->ns_monitor_heap_gc_state = NS_MONITOR_STATE_GC_CRITICAL; + ns_monitor_heap_gc(true); + ns_monitor_ptr->ns_maintenance_timer = 0; + } + } + + if (ns_monitor_ptr->ns_maintenance_timer >= NS_MAINTENANCE_TIMER_INTERVAL) { + ns_monitor_ptr->ns_maintenance_timer -= NS_MAINTENANCE_TIMER_INTERVAL; + ns_monitor_periodic_heap_health_check(); + } + } +} + +int ns_monitor_init(void) +{ + if (ns_monitor_ptr || !ns_dyn_mem_get_mem_stat()) { + // already initialized or memory statistics not available + return -2; + } + + ns_monitor_ptr = ns_dyn_mem_alloc(sizeof(ns_monitor_t)); + + if (ns_monitor_ptr) { + ns_monitor_ptr->mem_stats = ns_dyn_mem_get_mem_stat(); + ns_monitor_ptr->heap_high_watermark = ns_monitor_ptr->mem_stats->heap_sector_size * HEAP_HIGH_WATERWARK; + ns_monitor_ptr->heap_critical_watermark = ns_monitor_ptr->mem_stats->heap_sector_size * HEAP_CRITICAL_WATERMARK; + ns_monitor_ptr->ns_monitor_heap_gc_state = NS_MONITOR_STATE_HEAP_GC_IDLE; + ns_monitor_ptr->ns_maintenance_timer = 0; + ns_monitor_ptr->prev_heap_alloc_fail_cnt = 0; + return 0; + } + + return -1; +} + +int ns_monitor_clear(void) +{ + if (ns_monitor_ptr) { + ns_dyn_mem_free(ns_monitor_ptr); + ns_monitor_ptr = NULL; + return 0; + } + + return -1; +} + +int ns_monitor_heap_gc_threshold_set(uint8_t percentage_high, uint8_t percentage_critical) +{ + if (ns_monitor_ptr && (percentage_critical <= 100) && (percentage_high < percentage_critical)) { + ns_monitor_ptr->heap_high_watermark = ns_monitor_ptr->mem_stats->heap_sector_size * percentage_high / 100; + ns_monitor_ptr->heap_critical_watermark = ns_monitor_ptr->mem_stats->heap_sector_size * percentage_critical / 100; + tr_debug("Monitor set high:%lu, critical:%lu total:%lu", (unsigned long)ns_monitor_ptr->heap_high_watermark, (unsigned long)ns_monitor_ptr->heap_critical_watermark, (unsigned long)ns_monitor_ptr->mem_stats->heap_sector_size); + return 0; + } + + return -1; +} diff --git a/features/nanostack/sal-stack-nanostack/source/DHCPv6_Server/DHCPv6_Server_service.c b/features/nanostack/sal-stack-nanostack/source/DHCPv6_Server/DHCPv6_Server_service.c index be3c6c927fe..7e172f7fde2 100644 --- a/features/nanostack/sal-stack-nanostack/source/DHCPv6_Server/DHCPv6_Server_service.c +++ b/features/nanostack/sal-stack-nanostack/source/DHCPv6_Server/DHCPv6_Server_service.c @@ -147,6 +147,11 @@ int DHCPV6_server_service_request_handler(uint16_t instance_id, uint32_t msg_tr_ replyPacket.T1 = dhcp_ia_non_temporal_params.T1; replyPacket.iaId = dhcp_ia_non_temporal_params.iaId; replyPacket.transaction_ID = msg_tr_id; + + uint16_t duid_length = libdhcpv6_duid_option_size(replyPacket.clientDUID.linkType); + duid_length -= 8; + tr_debug("Response dhcp sol %s clientDUID", trace_array(replyPacket.clientDUID.linkID, duid_length)); + //Check First Current list if (DHCPv6_server_respond_client(serverBase, &replyPacket, &dhcp_ia_non_temporal_params, &responseBuf, true) == 0) { //Respond diff --git a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_api.h b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_api.h index 472b9ff8f2e..60c2ff7f52a 100644 --- a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_api.h +++ b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_api.h @@ -100,7 +100,7 @@ void dhcp_client_global_address_delete(int8_t interface, uint8_t *dhcp_addr, uin void dhcp_relay_agent_enable(int8_t interface, uint8_t border_router_address[static 16]); -int dhcp_client_server_address_update(int8_t interface, uint8_t prefix[static 16], uint8_t server_address[static 16]); +int dhcp_client_server_address_update(int8_t interface, uint8_t *prefix, uint8_t server_address[static 16]); diff --git a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c index 5ed52098937..511ac2affe9 100644 --- a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c +++ b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c @@ -96,7 +96,7 @@ void dhcp_client_delete(int8_t interface) { protocol_interface_info_entry_t *cur = NULL; dhcpv6_client_server_data_t *srv_data_ptr; - + uint8_t temporary_address[16]; dhcp_service_delete(dhcp_client.service_instance); @@ -110,9 +110,11 @@ void dhcp_client_delete(int8_t interface) srv_data_ptr = libdhcpv6_nonTemporal_entry_get_by_instance(dhcp_client.libDhcp_instance); if (srv_data_ptr != NULL) { tr_debug("Free DHCPv6 Client\n"); + memcpy(temporary_address, srv_data_ptr->iaNontemporalAddress.addressPrefix, 16); dhcp_service_req_remove(srv_data_ptr->transActionId);// remove all pending retransmissions - addr_delete(cur, srv_data_ptr->iaNontemporalAddress.addressPrefix); libdhcvp6_nontemporalAddress_server_data_free(srv_data_ptr); + addr_delete(cur, temporary_address); + } } while (srv_data_ptr != NULL); dhcp_client.service_instance = 0; @@ -234,6 +236,9 @@ int dhcp_client_get_global_address(int8_t interface, uint8_t dhcp_addr[static 16 dhcpv6_renew(protocol_stack_interface_info_get_by_id(interface), NULL, ADDR_CALLBACK_TIMER); } return 0; + } else if (dhcp_client_server_address_update(interface, prefix, dhcp_addr) == 0) { + //DHCP server address OK + return 0; } } return -1; @@ -302,7 +307,7 @@ int dhcp_client_get_global_address(int8_t interface, uint8_t dhcp_addr[static 16 return 0; } -int dhcp_client_server_address_update(int8_t interface, uint8_t prefix[static 16], uint8_t server_address[static 16]) +int dhcp_client_server_address_update(int8_t interface, uint8_t *prefix, uint8_t server_address[static 16]) { dhcpv6_client_server_data_t *srv_data_ptr = NULL; @@ -446,6 +451,7 @@ void dhcpv6_renew(protocol_interface_info_entry_t *interface, if_address_entry_t // Default retry values are modified from specification update to message dhcp_service_set_retry_timers(srv_data_ptr->transActionId, dhcp_client.sol_timeout, dhcp_client.sol_max_rt, dhcp_client.sol_max_rc); } + tr_error("DHCP renew send OK"); } static bool dhcpv6_client_set_address(int8_t interface_id, dhcpv6_client_server_data_t *srv_data_ptr) diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_indirect_data.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_indirect_data.c index fcfdb26586d..51af386bddd 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_indirect_data.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_indirect_data.c @@ -148,7 +148,6 @@ uint8_t mac_indirect_data_req_handle(mac_pre_parsed_frame_t *buf, protocol_inter /* If the Ack we sent for the Data Request didn't have frame pending set, we shouldn't transmit - child may have slept */ if (!buf->ack_pendinfg_status) { - //tr_debug("Drop by pending"); if (mac_ptr->indirect_pd_data_request_queue) { tr_error("Wrongly dropped"); } diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c index 4035ec7ddf0..39609e4dacb 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c @@ -74,6 +74,8 @@ static void mac_pd_data_confirm_failure_handle(protocol_interface_rf_mac_setup_s static int8_t mac_tasklet_event_handler = -1; +static uint32_t ns_dyn_mem_rate_limiting_threshold = 0xFFFFFFFF; + /** * Get PHY time stamp. * @@ -233,7 +235,6 @@ void mcps_sap_data_req_handler_ext(protocol_interface_rf_mac_setup_s *rf_mac_set if (!rf_mac_setup->macUpState || rf_mac_setup->scan_active) { status = MLME_TRX_OFF; - tr_debug("Drop MAC tx packet when mac disabled"); goto verify_status; } @@ -614,11 +615,6 @@ static uint8_t mac_data_interface_decrypt_packet(mac_pre_parsed_frame_t *b, mlme ccm_ptr.data_ptr = (mcps_mac_payload_pointer_get(b) + openPayloadLength); ccm_ptr.data_len = b->mac_payload_length - openPayloadLength; if (ccm_process_run(&ccm_ptr) != 0) { - tr_warning("MIC Fail adata %s", trace_array(ccm_ptr.adata_ptr, ccm_ptr.adata_len)); - tr_warning("Nonce %s", trace_array(ccm_ptr.exp_nonce, 13)); - if (openPayloadLength) { - tr_warning("%s", tr_array(ccm_ptr.data_ptr, ccm_ptr.data_len)); - } return MLME_SECURITY_FAIL; } @@ -660,7 +656,6 @@ static void mcps_comm_status_indication_generate(uint8_t status, mac_pre_parsed_ static int8_t mac_data_interface_host_accept_data(mcps_data_ind_t *data_ind, protocol_interface_rf_mac_setup_s *rf_mac_setup) { if ((data_ind->DstAddrMode == MAC_ADDR_MODE_16_BIT) && (data_ind->DstAddr[0] == 0xff && data_ind->DstAddr[1] == 0xff)) { - tr_debug("Drop Multicast packet"); return -1; } @@ -686,6 +681,7 @@ static int8_t mac_data_sap_rx_handler(mac_pre_parsed_frame_t *buf, protocol_inte { int8_t retval = -1; uint8_t status; + //allocate Data ind primitiv and parse packet to that mcps_data_ind_t *data_ind = ns_dyn_mem_temporary_alloc(sizeof(mcps_data_ind_t)); @@ -720,7 +716,6 @@ static int8_t mac_data_sap_rx_handler(mac_pre_parsed_frame_t *buf, protocol_inte } if (!mac_payload_information_elements_parse(buf)) { - tr_debug("Drop by Paylod IE"); goto DROP_PACKET; } data_ind->msduLength = buf->mac_payload_length; @@ -738,7 +733,6 @@ static int8_t mac_data_sap_rx_handler(mac_pre_parsed_frame_t *buf, protocol_inte if (buf->fcf_dsn.frameVersion == MAC_FRAME_VERSION_2015) { if (!rf_mac_setup->mac_extension_enabled) { - tr_debug("No Ext reg"); goto DROP_PACKET; } mcps_data_ie_list_t ie_list; @@ -900,7 +894,6 @@ static void mac_data_interface_parse_beacon(mac_pre_parsed_frame_t *buf, protoco } if (!mac_payload_information_elements_parse(buf)) { - tr_debug("Drop by Paylod IE"); return; } @@ -921,7 +914,6 @@ static void mac_data_interface_parse_beacon(mac_pre_parsed_frame_t *buf, protoco if (len < gts_field_length) { return; } -// gts_info = ptr; len -= gts_field_length; ptr += gts_field_length; } @@ -976,7 +968,6 @@ static void mac_data_interface_frame_handler(mac_pre_parsed_frame_t *buf) { protocol_interface_rf_mac_setup_s *rf_mac_setup = buf->mac_class_ptr; if (!rf_mac_setup) { - tr_debug("Drop by no mac class"); mcps_sap_pre_parsed_frame_buffer_free(buf); return; } @@ -1081,13 +1072,11 @@ static int8_t mac_ack_sap_rx_handler(mac_pre_parsed_frame_t *buf, protocol_inter if (buf->fcf_dsn.securityEnabled) { uint8_t status = mac_data_interface_decrypt_packet(buf, &key); if (status != MLME_SUCCESS) { - tr_debug("ACK Decrypt fail"); return -1; } } if (buf->mac_payload_length && !mac_payload_information_elements_parse(buf)) { - tr_debug("Drop ACK by Paylod IE"); return -1; } @@ -2068,6 +2057,12 @@ void mcps_sap_pre_parsed_frame_buffer_free(mac_pre_parsed_frame_t *buf) mac_pre_parsed_frame_t *mcps_sap_pre_parsed_frame_buffer_get(const uint8_t *data_ptr, uint16_t frame_length) { + // check that system has enough space to handle the new packet + const mem_stat_t *ns_dyn_mem_stat = ns_dyn_mem_get_mem_stat(); + if (ns_dyn_mem_stat && ns_dyn_mem_stat->heap_sector_allocated_bytes > ns_dyn_mem_rate_limiting_threshold) { + return NULL; + } + mac_pre_parsed_frame_t *buffer = ns_dyn_mem_temporary_alloc(sizeof(mac_pre_parsed_frame_t) + frame_length); if (buffer) { @@ -2075,6 +2070,7 @@ mac_pre_parsed_frame_t *mcps_sap_pre_parsed_frame_buffer_get(const uint8_t *data buffer->frameLength = frame_length; memcpy(mac_header_message_start_pointer(buffer), data_ptr, frame_length); } + return buffer; } @@ -2298,3 +2294,15 @@ uint8_t mcps_sap_purge_reg_handler(protocol_interface_rf_mac_setup_s *rf_mac_set return confirmation.status; } + +int mcps_packet_ingress_rate_limit_by_memory(uint8_t free_heap_percentage) +{ + const mem_stat_t *ns_dyn_mem_stat = ns_dyn_mem_get_mem_stat(); + + if (ns_dyn_mem_stat && free_heap_percentage < 100) { + ns_dyn_mem_rate_limiting_threshold = ns_dyn_mem_stat->heap_sector_size / 100 * (100 - free_heap_percentage); + return 0; + } + + return -1; +} diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h index a4f4baeb73c..b69ec96aa2c 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, Arm Limited and affiliates. + * Copyright (c) 2016-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -216,4 +216,6 @@ int8_t mcps_pd_data_rebuild(struct protocol_interface_rf_mac_setup *rf_ptr, mac_ int8_t mcps_generic_ack_build(struct protocol_interface_rf_mac_setup *rf_ptr, const mac_fcf_sequence_t *fcf, const uint8_t *data_ptr, const mcps_ack_data_payload_t *ack_payload); +int mcps_packet_ingress_rate_limit_by_memory(uint8_t free_heap_percentage); + #endif /* MAC_IEEE802_15_4_MAC_MCPS_SAP_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c index bea62f26763..c247f01b216 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c @@ -232,7 +232,6 @@ uint8_t mac_mlme_beacon_req_tx(protocol_interface_rf_mac_setup_s *rf_ptr) buf->fcf_dsn.DstPanPresents = true; buf->fcf_dsn.SrcPanPresents = false; - tr_debug("BEA REQ tx"); mcps_sap_pd_req_queue_write(rf_ptr, buf); return 1; } @@ -843,7 +842,6 @@ static void mlme_scan_operation(protocol_interface_rf_mac_setup_s *rf_mac_setup) channel = mlme_scan_analyze_next_channel(&rf_mac_setup->mac_channel_list, true); if (channel > 0xff || rf_mac_setup->mac_mlme_scan_resp->ResultListSize == MLME_MAC_RES_SIZE_MAX) { resp->status = MLME_SUCCESS; - tr_debug("Scan Complete..Halt MAC"); platform_enter_critical(); mac_mlme_mac_radio_disabled(rf_mac_setup); if (resp->ResultListSize == 0 && rf_mac_setup->scan_type == MAC_ACTIVE_SCAN) { @@ -855,7 +853,6 @@ static void mlme_scan_operation(protocol_interface_rf_mac_setup_s *rf_mac_setup) platform_exit_critical(); //Scan Confirmation mac_generic_event_trig(MAC_MLME_SCAN_CONFIRM_HANDLER, rf_mac_setup, false); - tr_debug("Trig confirm"); rf_mac_setup->scan_active = false; } else { mac_mlme_scan_init((uint8_t) channel, rf_mac_setup); @@ -987,7 +984,6 @@ static void mac_mlme_free_scan_temporary_data(protocol_interface_rf_mac_setup_s rf_mac_setup->scan_active = false; if (rf_mac_setup->mac_mlme_scan_resp) { mlme_scan_conf_t *r = rf_mac_setup->mac_mlme_scan_resp; - tr_debug("%02x", r->ResultListSize); if (r->ED_values) { ns_dyn_mem_free(r->ED_values); r->ED_values = NULL; @@ -995,12 +991,10 @@ static void mac_mlme_free_scan_temporary_data(protocol_interface_rf_mac_setup_s uint8_t i = 0; while (i < r->ResultListSize) { if (r->PAN_values[i]) { - tr_debug("Free PAN result"); ns_dyn_mem_free(r->PAN_values[i]); } i++; } - tr_debug("Free Response"); ns_dyn_mem_free(rf_mac_setup->mac_mlme_scan_resp); rf_mac_setup->mac_mlme_scan_resp = NULL; } @@ -1399,11 +1393,6 @@ static void mac_mlme_start_confirm_handler(protocol_interface_rf_mac_setup_s *rf static void mac_mlme_scan_confirm_handler(protocol_interface_rf_mac_setup_s *rf_ptr, const mlme_scan_conf_t *conf) { - if (conf->ScanType == MAC_ACTIVE_SCAN) { - tr_debug("Active Scan Result"); - } else if (conf->ScanType == MAC_ED_SCAN_TYPE) { - tr_debug("ED Scan Result"); - } if (rf_ptr->tun_extension_rf_driver) { virtual_data_req_t scan_conf; uint8_t buf_temp[2]; diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c index 9157c444545..ae789614997 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c @@ -487,7 +487,8 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r return 0; } else { // Do not update CCA count when Ack is received, it was already updated with PHY_LINK_TX_SUCCESS event - if ((status != PHY_LINK_TX_DONE) && (status != PHY_LINK_TX_DONE_PENDING)) { + // Do not update CCA count when CCA_OK is received, PHY_LINK_TX_SUCCESS will update it + if ((status != PHY_LINK_TX_DONE) && (status != PHY_LINK_TX_DONE_PENDING) && (status != PHY_LINK_CCA_OK)) { /* For PHY_LINK_TX_SUCCESS and PHY_LINK_CCA_FAIL cca_retry must always be > 0. * PHY_LINK_TX_FAIL either happened during transmission or when waiting Ack -> we must use the CCA count given by PHY. */ diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c index 2fe2b8fbeb2..e009d042561 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c @@ -126,7 +126,7 @@ static void mac_sec_mib_key_device_description_remove_from_list(mlme_key_descrip *prev = *cur; } else if (cur->DeviceDescriptorHandle == device_descriptor_handle) { removed_entry = true; - tr_debug("Remove user %u from key", device_descriptor_handle); + //tr_debug("Remove user %u from key", device_descriptor_handle); } prev = cur; cur++; @@ -244,10 +244,10 @@ int8_t mac_sec_mib_device_description_set(uint8_t atribute_index, mlme_device_de if (memcmp(device_ptr->ExtAddress, device_descriptor->ExtAddress, 8)) { //Remove last handles key user's mac_sec_mib_device_description_remove(rf_mac_setup, atribute_index); - tr_debug("Over write %u, mac16 %x mac64: %s, %"PRIu32, atribute_index, device_ptr->ShortAddress, trace_array(device_ptr->ExtAddress, 8), device_ptr->FrameCounter); + //tr_debug("Over write %u, mac16 %x mac64: %s, %"PRIu32, atribute_index, device_ptr->ShortAddress, trace_array(device_ptr->ExtAddress, 8), device_ptr->FrameCounter); } - tr_debug("Set %u, mac16 %x mac64: %s, %"PRIu32, atribute_index, device_descriptor->ShortAddress, trace_array(device_descriptor->ExtAddress, 8), device_descriptor->FrameCounter); + //tr_debug("Set %u, mac16 %x mac64: %s, %"PRIu32, atribute_index, device_descriptor->ShortAddress, trace_array(device_descriptor->ExtAddress, 8), device_descriptor->FrameCounter); *device_ptr = *device_descriptor; return 0; @@ -485,7 +485,7 @@ void mac_sec_mib_device_description_blacklist(protocol_interface_rf_mac_setup_s for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { descriptor = mac_sec_mib_key_device_description_discover_from_list(&rf_mac_setup->key_description_table[i], device_handle); if (descriptor) { - tr_debug("Black listed device %u lookup%s", device_handle, trace_array(rf_mac_setup->key_description_table[i].Key, 16)); + tr_debug("Black listed device %u", device_handle); descriptor->Blacklisted = true; } diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c index 3650d7c794c..ca31fe949d8 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c @@ -699,3 +699,19 @@ void sw_mac_stats_update(protocol_interface_rf_mac_setup_s *setup, mac_stats_typ } } } + +uint32_t ns_sw_mac_read_current_timestamp(struct mac_api_s *mac_api) +{ + if (!mac_api) { + return 0; + } + + // Get a pointer to MAC setup structure + protocol_interface_rf_mac_setup_s *mac_setup = get_sw_mac_ptr_by_mac_api(mac_api); + if (!mac_setup) { + return 0; + } + uint32_t time_stamp_buffer; + mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_GET_TIMESTAMP, (uint8_t *)&time_stamp_buffer); + return time_stamp_buffer; +} diff --git a/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h b/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h index 7a0ec035295..3bdba330b8d 100644 --- a/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h +++ b/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h @@ -515,5 +515,6 @@ extern void protocol_core_dhcpv6_allocated_address_remove(protocol_interface_inf extern void nwk_bootsrap_state_update(arm_nwk_interface_status_type_e posted_event, protocol_interface_info_entry_t *cur); void bootsrap_next_state_kick(icmp_state_t new_state, protocol_interface_info_entry_t *cur); int8_t protocol_interface_address_compare(const uint8_t *addr); +bool protocol_address_prefix_cmp(protocol_interface_info_entry_t *cur, const uint8_t *prefix, uint8_t prefix_len); bool protocol_interface_any_address_match(const uint8_t *prefix, uint8_t prefix_len); #endif /* _NS_PROTOCOL_H */ diff --git a/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c b/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c index a05ac5f55eb..1564cdf6a6c 100644 --- a/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c +++ b/features/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c @@ -24,6 +24,7 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "Core/include/ns_socket.h" +#include "Core/include/ns_monitor.h" #include "NWK_INTERFACE/Include/protocol.h" #include "NWK_INTERFACE/Include/protocol_timer.h" #include "platform/arm_hal_interrupt.h" @@ -175,6 +176,7 @@ void protocol_root_tasklet(arm_event_t *event) switch (event_type) { case ARM_LIB_TASKLET_INIT_EVENT: tr_debug("NS Root task Init"); + ns_monitor_init(); break; case ARM_IN_PROTOCOL_TIMER_EVENT: { @@ -306,8 +308,7 @@ void core_timer_event_handle(uint16_t ticksUpdate) ws_pae_controller_slow_timer(seconds); #endif protocol_6lowpan_mle_timer(seconds); - /* This limit bad behaviour device's MLE link reject generation */ - + ns_monitor_timer(seconds); } else { protocol_core_seconds_timer -= ticksUpdate; } @@ -387,7 +388,6 @@ void protocol_core_init(void) protocol_core_timer_info.core_security_ticks_counter = SEC_LIB_X_100MS_COUNTER; protocol_timer_start(PROTOCOL_TIMER_STACK_TIM, protocol_core_cb, 100); - } void protocol_core_interface_info_reset(protocol_interface_info_entry_t *entry) @@ -1140,9 +1140,9 @@ int8_t protocol_interface_address_compare(const uint8_t *addr) return -1; } -static bool protocol_address_prefix_cmp(protocol_interface_info_entry_t *interface, const uint8_t *prefix, uint8_t prefix_len) +bool protocol_address_prefix_cmp(protocol_interface_info_entry_t *cur, const uint8_t *prefix, uint8_t prefix_len) { - ns_list_foreach(if_address_entry_t, adr, &interface->ip_addresses) { + ns_list_foreach(if_address_entry_t, adr, &cur->ip_addresses) { if (bitsequal(adr->address, prefix, prefix_len)) { /* Prefix stil used at list so stop checking */ return true; diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c index 963b2f3c194..f54d1c2ad37 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c @@ -171,68 +171,85 @@ void rpl_control_unpublish_address(rpl_domain_t *domain, const uint8_t addr[16]) } } -static if_address_entry_t *rpl_instance_reg_addr_get(protocol_interface_info_entry_t *interface) +void rpl_control_request_parent_link_confirmation(bool requested) { - ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { - if (!address->addr_reg_done && !addr_is_ipv6_link_local(address->address)) { - return address; - } - } - - return NULL; + rpl_policy_set_parent_confirmation_request(requested); } /* Send address registration to either specified address, or to non-registered address */ -void rpl_control_register_address(protocol_interface_info_entry_t *interface, if_address_entry_t *addr) +void rpl_control_register_address(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) { - if_address_entry_t *reg_addr = addr; - - if (!reg_addr) { - reg_addr = rpl_instance_reg_addr_get(interface); - - if (!reg_addr) { - return; - } + if (!rpl_policy_parent_confirmation_requested()) { + return; } ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { - rpl_instance_send_address_registration(interface, instance, reg_addr); + rpl_instance_send_address_registration(instance, addr); } } -void rpl_control_address_register_done(struct buffer *buf, uint8_t status) +void rpl_control_address_register_done(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16], uint8_t status) { - ns_list_foreach(if_address_entry_t, addr, &buf->interface->ip_addresses) { - - /* Optimize, ll addresses are not registered anyway.. */ - if (addr_is_ipv6_link_local(addr->address) || !addr->addr_reg_pend) { - continue; - } + if (!interface->rpl_domain) { + return; + } + if (!rpl_policy_parent_confirmation_requested()) { + return; + } - ns_list_foreach(struct rpl_instance, instance, &buf->interface->rpl_domain->instances) { - if (rpl_instance_address_registration_done(buf->interface, instance, addr, status)) { - return; - } + ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { + rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id); + if (neighbour) { + rpl_instance_address_registration_done(interface, instance, neighbour, status); } } } -bool rpl_control_is_dodag_parent(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16]) +bool rpl_control_is_dodag_parent(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16], bool selected) { + if (!interface->rpl_domain) { + return false; + } // go through instances and parents and check if they match the address. ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { - if (rpl_instance_address_is_parent(instance, ll_addr)) { + if (rpl_instance_address_is_parent(instance, ll_addr, selected)) { return true; } } return false; } + +uint16_t rpl_control_parent_candidate_list_size(protocol_interface_info_entry_t *interface, bool parent_list) +{ + if (!interface->rpl_domain) { + return 0; + } + + uint16_t parent_list_size = 0; + + // go through instances and parents and check if they match the address. + ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { + uint16_t current_size = rpl_instance_address_candidate_count(instance, parent_list); + if (current_size > parent_list_size) { + parent_list_size = current_size; + } + } + return parent_list_size; +} + + void rpl_control_neighbor_delete(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16]) { + if (!interface->rpl_domain) { + return; + } // go through instances and delete address. ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { - rpl_instance_neighbor_delete(instance, ll_addr); + + rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id); + if (neighbour) { + rpl_delete_neighbour(instance, neighbour); + } } - return; } /* Address changes need to trigger DAO target re-evaluation */ @@ -686,13 +703,12 @@ static void rpl_control_process_prefix_options(protocol_interface_info_entry_t * uint32_t preferred = common_read_32_bit(ptr + 8); const uint8_t *prefix = ptr + 16; - if (!pref_parent || neighbour == pref_parent) { + if (rpl_upward_accept_prefix_update(dodag, neighbour, pref_parent)) { /* Store prefixes for possible forwarding */ /* XXX if leaf - don't bother? Or do we want to remember them for * when we switch DODAG, as mentioned above? */ - prefix_entry_t *prefix_entry = rpl_dodag_update_dio_prefix(dodag, prefix, prefix_len, flags, valid, preferred, false, true); if (prefix_entry && pref_parent) { rpl_control_process_prefix_option(prefix_entry, cur); @@ -840,7 +856,6 @@ static void rpl_control_dao_trigger_request(rpl_instance_t *instance, rpl_dodag_ static buffer_t *rpl_control_dio_handler(protocol_interface_info_entry_t *cur, rpl_domain_t *domain, buffer_t *buf) { if (!rpl_control_options_well_formed_in_buffer(buf, 24)) { - tr_error("DIO format"); malformed: protocol_stats_update(STATS_RPL_MALFORMED_MESSAGE, 1); return buffer_free(buf); @@ -993,7 +1008,7 @@ static buffer_t *rpl_control_dio_handler(protocol_interface_info_entry_t *cur, r rpl_control_process_prefix_options(cur, instance, dodag, neighbour, ptr, buffer_data_end(buf)); - rpl_dodag_update_implicit_system_routes(dodag, neighbour); + //rpl_dodag_update_implicit_system_routes(dodag, neighbour); rpl_control_process_route_options(instance, dodag, version, neighbour, rank, ptr, buffer_data_end(buf)); //rpl_control_process_metric_containers(neighbour, ptr, buffer_data_end(buf)) @@ -1137,7 +1152,7 @@ void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entr } else { prefix->options &= ~ PIO_R; - if (rpl_dodag_mop(dodag) == RPL_MODE_NON_STORING && prefix->lifetime != 0) { + if (rpl_dodag_mop(dodag) == RPL_MODE_NON_STORING && (prefix->lifetime != 0 || !(prefix->options & PIO_A))) { continue; } } @@ -1175,7 +1190,7 @@ void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entr ns_list_foreach_safe(prefix_entry_t, prefix, prefixes) { /* See equivalent checks in length calculation above */ if ((prefix->options & (PIO_L | RPL_PIO_PUBLISHED)) == PIO_L || - (!(prefix->options & PIO_R) && rpl_dodag_mop(dodag) == RPL_MODE_NON_STORING && prefix->lifetime != 0)) { + (!(prefix->options & PIO_R) && rpl_dodag_mop(dodag) == RPL_MODE_NON_STORING && (prefix->lifetime != 0 || !(prefix->options & PIO_A)))) { continue; } @@ -1252,7 +1267,6 @@ void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entr static buffer_t *rpl_control_dis_handler(protocol_interface_info_entry_t *cur, rpl_domain_t *domain, buffer_t *buf, bool multicast) { if (!rpl_control_options_well_formed_in_buffer(buf, 2)) { - tr_error("DIS format"); protocol_stats_update(STATS_RPL_MALFORMED_MESSAGE, 1); return buffer_free(buf); } @@ -1380,7 +1394,6 @@ static buffer_t *rpl_control_dao_ack_handler(protocol_interface_info_entry_t *cu if (buffer_data_length(buf) < 4) { format_error: - tr_error("DAO-ACK format"); protocol_stats_update(STATS_RPL_MALFORMED_MESSAGE, 1); return buffer_free(buf); } @@ -1464,7 +1477,6 @@ static buffer_t *rpl_control_dao_handler(protocol_interface_info_entry_t *cur, r { if (buffer_data_length(buf) < 4) { format_error: - tr_error("DAO format"); protocol_stats_update(STATS_RPL_MALFORMED_MESSAGE, 1); return buffer_free(buf); } diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h index 20b82351ce4..cbe6cfd1648 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h @@ -147,10 +147,13 @@ void rpl_control_set_callback(rpl_domain_t *domain, rpl_domain_callback_t callba /* Target publishing */ void rpl_control_publish_host_address(rpl_domain_t *domain, const uint8_t addr[16], uint32_t lifetime); void rpl_control_unpublish_address(rpl_domain_t *domain, const uint8_t addr[16]); -void rpl_control_register_address(struct protocol_interface_info_entry *interface, if_address_entry_t *addr); -void rpl_control_address_register_done(struct buffer *buf, uint8_t status); -bool rpl_control_is_dodag_parent(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); +bool rpl_control_is_dodag_parent(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], bool selected); +uint16_t rpl_control_parent_candidate_list_size(struct protocol_interface_info_entry *interface, bool parent_list); void rpl_control_neighbor_delete(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); +/* Parent link confirmation API extension */ +void rpl_control_request_parent_link_confirmation(bool requested); +void rpl_control_register_address(struct protocol_interface_info_entry *interface, const uint8_t addr[16]); +void rpl_control_address_register_done(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint8_t status); /* Configure and return the routing lookup predicate for a specified RPL instance ID */ ipv6_route_predicate_fn_t *rpl_control_get_route_predicate(rpl_domain_t *domain, uint8_t instance_id, const uint8_t src[16], const uint8_t dst[16]); @@ -172,7 +175,7 @@ uint16_t rpl_control_current_rank(const struct rpl_instance *instance); #define rpl_control_slow_timer(seconds) ((void) 0) #define rpl_control_remove_domain_from_interface(cur) ((void) 0) #define rpl_control_register_address(interface, addr) ((void) 0) -#define rpl_control_address_register_done NULL +#define rpl_control_address_register_done(interface, ll_addr, status) ((void) 0) #endif /* HAVE_RPL */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c index a0359ecaeae..3c6da959dad 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c @@ -372,6 +372,12 @@ void rpl_instance_publish_dao_target(rpl_instance_t *instance, const uint8_t *pr target->descriptor_present = want_descriptor; target->descriptor = descriptor; target->path_control = 0xFF; /* Use as much path control as we can (PCS limits) */ + target->response_wait_time = 0; + target->active_confirmation_state = false; + target->trig_confirmation_state = true; + //Activate allways registration + instance->pending_neighbour_confirmation = rpl_policy_parent_confirmation_requested(); + tr_debug("New Target %s", trace_ipv6(target->prefix)); /* Path lifetime left as 0 for now - will be filled in on transmission, along with refresh timer */ rpl_instance_dao_trigger(instance, 0); } @@ -383,7 +389,7 @@ void rpl_instance_dao_trigger(rpl_instance_t *instance, uint16_t delay) } if (instance->delay_dao_timer == 0 || instance->delay_dao_timer > delay) { instance->delay_dao_timer = delay; - tr_debug("DAO trigger %" PRIu16, delay); + //tr_debug("DAO trigger %" PRIu16, delay); } } @@ -583,63 +589,63 @@ static void rpl_downward_reset_assigning(rpl_instance_t *instance, uint8_t pcs_m } } - -void rpl_instance_send_address_registration(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, if_address_entry_t *addr) +static void rpl_instance_unconfirm_parent_info(rpl_instance_t *instance) { - aro_t aro; - buffer_t *buf; + ns_list_foreach_safe(rpl_neighbour_t, n, &instance->candidate_neighbours) { + if (n->dao_path_control == 0) { + continue; + } + n->confirmed = false; - aro.status = ARO_SUCCESS; - aro.present = true; - aro.lifetime = (addr->valid_lifetime / 60) + 1; - memcpy(aro.eui64, interface->mac, 8); + } +} - // go through neighbour list, and send to all assigned parents. - ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { - if (neighbour->dao_path_control) { - tr_debug("Send ARO %s to %s", trace_ipv6(addr->address), trace_ipv6(neighbour->ll_address)); - buf = icmpv6_build_ns(interface, neighbour->ll_address, addr->address, true, false, &aro); - addr->addr_reg_pend |= neighbour->dao_path_control; - protocol_push(buf); - } else { - tr_debug("Skip ARO to %s - no pc", trace_ipv6(neighbour->ll_address)); +static rpl_dao_target_t *rpl_instance_get_pending_target_confirmation_for_address(rpl_instance_t *instance, const uint8_t address[16]) +{ + ns_list_foreach_safe(rpl_dao_target_t, n, &instance->dao_targets) { + if (memcmp(n->prefix, address, 16) == 0) { + return n; } } + return NULL; } -bool rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, if_address_entry_t *addr, uint8_t status) +static rpl_dao_target_t *rpl_instance_get_pending_target_confirmation(rpl_instance_t *instance) { - ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { - // Check path control mask - if (!(addr->addr_reg_pend & neighbour->dao_path_control)) { + ns_list_foreach_safe(rpl_dao_target_t, n, &instance->dao_targets) { + if (!n->trig_confirmation_state) { continue; } + n->trig_confirmation_state = false; + n->active_confirmation_state = true; + instance->wait_response = NULL; + rpl_instance_unconfirm_parent_info(instance); + return n; + } + return NULL; +} - tr_debug("Address %s register to %s", trace_ipv6(addr->address), trace_ipv6(neighbour->ll_address)); - - /* Clear pending flag */ - addr->addr_reg_pend &= ~neighbour->dao_path_control; - - if (status == SOCKET_TX_DONE) { - addr->addr_reg_done |= neighbour->dao_path_control; - /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ - addr->state_timer = (addr->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); - } else { - tr_error("Address registration failed"); - rpl_delete_neighbour(instance, neighbour); +void rpl_instance_send_address_registration(rpl_instance_t *instance, const uint8_t addr[16]) +{ + if (addr) { + rpl_dao_target_t *target = rpl_instance_get_pending_target_confirmation_for_address(instance, addr); + if (!target) { + return; } - /* If that was last one to reply, send next one. */ - if (!addr->addr_reg_pend) { - rpl_control_register_address(interface, NULL); + if (instance->pending_neighbour_confirmation && (target->active_confirmation_state || target->trig_confirmation_state)) { + return; + } + target->trig_confirmation_state = true; + } else if (!instance->pending_neighbour_confirmation) { + ns_list_foreach_safe(rpl_dao_target_t, n, &instance->dao_targets) { + n->trig_confirmation_state = true; } - - return true; } - - return false; + instance->pending_neighbour_confirmation = true; } + /* We are optimised for sending updates to existing targets to current parents; * we track the state of what information DAO parents have, and manage the * updates together with message coalescing and ack tracking. @@ -673,6 +679,12 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) return; } + //Verify that no pending address registartion to parent + if (instance->pending_neighbour_confirmation) { + rpl_instance_dao_trigger(instance, 6 * 10); + return; + } + if (instance->dao_in_transit) { // Force current DAO timeout to be cut short, then // when it times out, it will re-evaluate the situation, @@ -1689,4 +1701,145 @@ void rpl_downward_print_instance(rpl_instance_t *instance, route_print_fn_t *pri } } +rpl_dao_target_t *rpl_instance_get_active_target_confirmation(rpl_instance_t *instance) +{ + ns_list_foreach_safe(rpl_dao_target_t, n, &instance->dao_targets) { + if (!n->active_confirmation_state) { + continue; + } + return n; + + } + return NULL; +} + +static rpl_neighbour_t *rpl_instance_get_unconfirmed_parent_info(rpl_instance_t *instance) +{ + ns_list_foreach_safe(rpl_neighbour_t, n, &instance->candidate_neighbours) { + if (n->dao_path_control != 0 && !n->confirmed) { + return n; + } + + } + return NULL; +} + +static bool rpl_instance_push_address_registration(protocol_interface_info_entry_t *interface, rpl_neighbour_t *neighbour, if_address_entry_t *addr) +{ + aro_t aro; + + aro.status = ARO_SUCCESS; + aro.present = true; + aro.lifetime = (addr->valid_lifetime / 60) + 1; + memcpy(aro.eui64, interface->mac, 8); + + buffer_t *buf = icmpv6_build_ns(interface, neighbour->ll_address, addr->address, true, false, &aro); + if (!buf) { + return false; + } + tr_debug("Send ARO %s to %s", trace_ipv6(addr->address), trace_ipv6(neighbour->ll_address)); + protocol_push(buf); + return true; +} +static if_address_entry_t *rpl_interface_addr_get(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) +{ + ns_list_foreach(if_address_entry_t, entry, &interface->ip_addresses) { + if (memcmp(entry->address, addr, 16) == 0) { + return entry; + } + } + return NULL; +} + + + +void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint16_t seconds) +{ + if (!instance->pending_neighbour_confirmation) { + return; //No need validate any confirmation + } + + //Get Pendig active target + rpl_dao_target_t *dao_target = rpl_instance_get_active_target_confirmation(instance); + if (!dao_target) { + dao_target = rpl_instance_get_pending_target_confirmation(instance); + if (!dao_target) { + instance->pending_neighbour_confirmation = false; + return; + } + + tr_debug("Register Address to parent %s", trace_ipv6(dao_target->prefix)); + } + + if (instance->wait_response) { + uint16_t wait_time = dao_target->response_wait_time; + if (seconds < wait_time) { + //Must Wait response time untill finish + dao_target->response_wait_time -= seconds; + return; + } + dao_target->response_wait_time = 0; + instance->wait_response = NULL; + } + + //Get Next Parent for confirmation + rpl_neighbour_t *neighbour = rpl_instance_get_unconfirmed_parent_info(instance); + if (!neighbour) { + dao_target->active_confirmation_state = false; + return; + } + + //Get address and buffer + protocol_interface_info_entry_t *interface = protocol_stack_interface_info_get_by_id(neighbour->interface_id); + if (!interface) { + dao_target->response_wait_time = 0; + instance->wait_response = NULL; + dao_target->active_confirmation_state = false; + return; + } + + if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); + if (!address) { + dao_target->response_wait_time = 0; + instance->wait_response = NULL; + dao_target->active_confirmation_state = false; + return; + } + + + if (rpl_instance_push_address_registration(interface, neighbour, address)) { + instance->wait_response = neighbour; + dao_target->response_wait_time = 5; + } + +} + +void rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status) +{ + + if (!instance->pending_neighbour_confirmation) { + return; + } + + rpl_dao_target_t *dao_target = rpl_instance_get_active_target_confirmation(instance); + if (!dao_target || instance->wait_response != neighbour) { + return; + } + + tr_debug("Address %s register to %s", trace_ipv6(dao_target->prefix), trace_ipv6(neighbour->ll_address)); + + if (status == SOCKET_TX_DONE) { + /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ + if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); + if (address) { + address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); + } + neighbour->confirmed = true; + dao_target->response_wait_time = 6; + } else { + tr_error("Address registration failed"); + rpl_delete_neighbour(instance, neighbour); + } +} + #endif /* HAVE_RPL */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.h index 15d40bae7ad..a8c66a79b70 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.h @@ -40,9 +40,10 @@ struct rpl_dao_target *rpl_instance_match_dao_target(struct rpl_instance *instan void rpl_instance_dao_request(struct rpl_instance *instance, struct rpl_neighbour *neighbour); void rpl_instance_dao_trigger(struct rpl_instance *instance, uint16_t delay); void rpl_instance_dao_acked(struct rpl_instance *instance, const uint8_t src[16], int8_t interface_id, uint8_t dao_sequence, uint8_t status); - -void rpl_instance_send_address_registration(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, if_address_entry_t *addr); -bool rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, if_address_entry_t *addr, uint8_t status); +void rpl_instance_parent_address_reg_timer_update(struct rpl_instance *instance, uint16_t seconds); +void rpl_instance_send_address_registration(rpl_instance_t *instance, const uint8_t addr[16]); +void rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status); +struct rpl_dao_target *rpl_instance_get_active_target_confirmation(struct rpl_instance *instance); #ifdef HAVE_RPL_DAO_HANDLING bool rpl_instance_dao_received(struct rpl_instance *instance, const uint8_t src[16], int8_t interface_id, bool multicast, const uint8_t *opts, uint16_t opts_len, uint8_t *status_out); diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c index f31a51ec138..30488983339 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c @@ -34,6 +34,8 @@ #define TRACE_GROUP "RPLy" +static bool rpl_policy_parent_confirmation_req = false; + /* TODO - application API to control when to join new instances / DODAGs * * Eg, allow application to ignore local DODAGs, or specify known instance IDs, @@ -318,6 +320,17 @@ uint16_t rpl_policy_mrhof_parent_switch_threshold(const rpl_domain_t *domain) return 192; } +void rpl_policy_set_parent_confirmation_request(bool confirmation_requested) +{ + rpl_policy_parent_confirmation_req = confirmation_requested; +} + + +bool rpl_policy_parent_confirmation_requested(void) +{ + return rpl_policy_parent_confirmation_req; +} + #ifdef RPL_STRUCTURES_H_ #error "rpl_structures.h should not be included by rpl_policy.c" diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h index 469656f474a..dc1094e5cd5 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h @@ -54,5 +54,7 @@ uint_fast8_t rpl_policy_mrhof_parent_set_size(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_max_link_metric(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_parent_switch_threshold(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_max_rank_stretch_for_extra_parents(const rpl_domain_t *domain); +bool rpl_policy_parent_confirmation_requested(void); +void rpl_policy_set_parent_confirmation_request(bool confirmation_requested); #endif /* RPL_POLICY_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h index fac901ccd48..107ff9b6eb9 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h @@ -52,6 +52,7 @@ struct rpl_neighbour { bool was_dodag_parent: 1; // Was a DODAG parent (used only during parent selection) bool have_global_address: 1; // Global address known bool considered: 1; // Have considered at least once for parent selection + bool confirmed: 1; // Confirmed unsigned dodag_pref: 4; // Preference indication for DODAG parents (0=best) uint8_t dao_path_control; // Path control bit assignments for DAO parent uint8_t old_dao_path_control; @@ -136,6 +137,7 @@ struct rpl_dao_target { uint8_t prefix_len; uint8_t path_sequence; uint8_t path_control; + uint8_t response_wait_time; int8_t interface_id; uint32_t lifetime; /* Seconds */ uint32_t descriptor; /* Target descriptor */ @@ -146,6 +148,8 @@ struct rpl_dao_target { bool descriptor_present: 1; /* Target descriptor specified */ bool need_seq_inc: 1; bool connected: 1; /* We know this target has a path to the root */ + bool trig_confirmation_state: 1; /* Enable confirmation to parent's */ + bool active_confirmation_state: 1; union { #ifdef HAVE_RPL_ROOT rpl_dao_root_t root; /* Info specific to a non-storing root */ @@ -175,12 +179,14 @@ struct rpl_instance { bool dio_not_consistent: 1; /* Something changed - not consistent this period */ bool dao_in_transit: 1; /* If we have a DAO in transit */ bool requested_dao_ack: 1; /* If we requested an ACK (so we retry if no ACK, rather than assuming success) */ + bool pending_neighbour_confirmation: 1; /* if we have not finished address registration state to parent */ uint8_t poison_count; uint8_t repair_dis_count; uint16_t repair_dis_timer; uint32_t last_dao_trigger_time; uint16_t srh_error_count; /* SRH errors since last DAO trigger */ NS_LIST_HEAD(rpl_dodag_t, link) dodags; /* List of DODAGs */ + rpl_neighbour_t *wait_response; rpl_neighbour_list_t candidate_neighbours; /* Candidate neighbour set */ // rpl_neighbour_list_t old_neighbours; /* Old neighbours (without a live DODAG version) */ rpl_dodag_version_t *current_dodag_version; /* Pointer to DODAG version we are a member of (if any) */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c index 1f18507dadc..625e17ae8bc 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c @@ -343,6 +343,8 @@ void rpl_instance_trigger_parent_selection(rpl_instance_t *instance, uint16_t de static void rpl_instance_parent_selection_timer(rpl_instance_t *instance, uint16_t seconds) { + + if (instance->parent_selection_timer > seconds) { instance->parent_selection_timer -= seconds; } else if (instance->parent_selection_timer != 0) { @@ -405,6 +407,7 @@ rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *version, const uint8_ neighbour->g_mop_prf = g_mop_prf; neighbour->dtsn = dtsn; neighbour->dao_path_control = 0; + neighbour->confirmed = 0; /* Need to limit number of neighbours here - chucking worst neighbour */ @@ -423,6 +426,11 @@ rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *version, const uint8_ void rpl_delete_neighbour(rpl_instance_t *instance, rpl_neighbour_t *neighbour) { + rpl_dao_target_t *dao_target = rpl_instance_get_active_target_confirmation(instance); + if (dao_target && instance->wait_response == neighbour) { + instance->wait_response = NULL; + } + rpl_downward_neighbour_gone(instance, neighbour); ns_list_remove(&instance->candidate_neighbours, neighbour); if (neighbour->dao_path_control) { @@ -1280,7 +1288,7 @@ static void rpl_instance_update_system_dio_route(rpl_instance_t *instance, rpl_n uint8_t metric = ipv6_route_pref_to_metric(pref) + parent->dodag_pref; - ipv6_route_add_metric(route->prefix, route->prefix_len, parent->interface_id, parent->ll_address, ROUTE_RPL_DIO, parent, instance->id, rpl_aged_lifetime(route->lifetime, parent->dio_timestamp), metric); + ipv6_route_add_metric(route->prefix, route->prefix_len, parent->interface_id, parent->ll_address, ROUTE_RPL_DIO, parent, instance->id, route->lifetime, metric); } /* Called when a DIO has been received */ @@ -1290,14 +1298,14 @@ void rpl_dodag_update_implicit_system_routes(rpl_dodag_t *dodag, rpl_neighbour_t return; } - uint32_t aged_default = rpl_aged_lifetime(rpl_default_lifetime(dodag), parent->dio_timestamp); + uint32_t default_lifetime = rpl_default_lifetime(dodag); uint8_t metric = IPV6_ROUTE_DEFAULT_METRIC + parent->dodag_pref; /* Always add the "root" default route - only used for per-instance lookup */ - ipv6_route_add_metric(NULL, 0, parent->interface_id, parent->ll_address, ROUTE_RPL_INSTANCE, parent, dodag->instance->id, aged_default, metric); + ipv6_route_add_metric(NULL, 0, parent->interface_id, parent->ll_address, ROUTE_RPL_INSTANCE, parent, dodag->instance->id, default_lifetime, metric); /* Also add a specific route to the DODAGID */ - ipv6_route_add_metric(dodag->id, 128, parent->interface_id, parent->ll_address, ROUTE_RPL_ROOT, parent, dodag->instance->id, aged_default, metric); + ipv6_route_add_metric(dodag->id, 128, parent->interface_id, parent->ll_address, ROUTE_RPL_ROOT, parent, dodag->instance->id, default_lifetime, metric); } @@ -1365,7 +1373,8 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) } ns_list_foreach_safe(rpl_neighbour_t, n, &instance->candidate_neighbours) { - if (rpl_aged_lifetime(rpl_default_lifetime(n->dodag_version->dodag), n->dio_timestamp) == 0) { + //Remove a Parent candidates which are not heared a long time ago and not slected ones + if (!n->dodag_parent && (rpl_aged_lifetime(rpl_default_lifetime(n->dodag_version->dodag), n->dio_timestamp) == 0)) { rpl_delete_neighbour(instance, n); continue; } @@ -1406,6 +1415,9 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) if (original_preferred != preferred_parent) { protocol_stats_update(STATS_RPL_PARENT_CHANGE, 1); + if (preferred_parent) { + tr_debug("New preferred parent %s", trace_array(preferred_parent->ll_address, 16)); + } } // Sets new preferred parent @@ -1605,19 +1617,48 @@ uint16_t rpl_instance_current_rank(const rpl_instance_t *instance) return instance->current_rank; } -bool rpl_instance_address_is_parent(rpl_instance_t *instance, const uint8_t *ipv6_addr) +bool rpl_instance_address_is_parent(rpl_instance_t *instance, const uint8_t *ipv6_addr, bool selected) { ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { - if (neighbour->dodag_parent && addr_ipv6_equal(neighbour->ll_address, ipv6_addr)) { - return true; - } - if (!neighbour->dodag_parent) { + if (selected && !neighbour->dodag_parent) { // list is ordered so first encounter of false means no more parents in list return false; } + + if (addr_ipv6_equal(neighbour->ll_address, ipv6_addr)) { + if (!selected) { + return true; + } + if (!neighbour->dodag_parent) { + return false; + } + + return true; + } + } return false; } + +uint16_t rpl_instance_address_candidate_count(rpl_instance_t *instance, bool selected_parents) +{ + uint16_t parent_list = 0; + + ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { + + + if (selected_parents) { + if (neighbour->dodag_parent) { + parent_list++; + } + } else { + parent_list++; + } + } + return parent_list; +} + + void rpl_instance_neighbor_delete(rpl_instance_t *instance, const uint8_t *ipv6_addr) { ns_list_foreach_safe(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { @@ -1633,6 +1674,8 @@ void rpl_instance_slow_timer(rpl_instance_t *instance, uint16_t seconds) ns_list_foreach(rpl_dodag_t, dodag, &instance->dodags) { rpl_dodag_slow_timer(dodag, seconds); } + + rpl_instance_parent_address_reg_timer_update(instance, seconds); rpl_instance_parent_selection_timer(instance, seconds); if (!rpl_instance_preferred_parent(instance)) { protocol_stats_update(STATS_RPL_TIME_NO_NEXT_HOP, 1); @@ -1665,6 +1708,10 @@ void rpl_upward_dio_timer(rpl_instance_t *instance, uint16_t ticks) if (rpl_dodag_am_leaf(dodag) && !instance->poison_count) { return; } + /* If we are waiting for DAO or DAO registration is needed we dont send periodic DIOs */ + if (instance->dao_in_transit || instance->delay_dao_timer > 0) { + return; + } if (trickle_timer(&instance->dio_timer, &dodag->dio_timer_params, ticks)) { instance->dio_not_consistent = false; rpl_instance_dio_trigger(instance, NULL, NULL); @@ -1845,4 +1892,26 @@ bool rpl_upward_read_dodag_info(const rpl_instance_t *instance, rpl_dodag_info_t return true; } +bool rpl_upward_accept_prefix_update(const rpl_dodag_t *dodag_info, const rpl_neighbour_t *neighbour, const rpl_neighbour_t *pref_parent) +{ + //Accept allways from Pref parent or before it is selected + if (!pref_parent || neighbour == pref_parent) { + return true; + } + + //Accept only same or higher version number + if (rpl_dodag_version_compare(neighbour->dodag_version, pref_parent->dodag_version) & (RPL_CMP_EQUAL | RPL_CMP_GREATER)) { + //Calculate Time between from last dio from parent and this neighbour + //neighbour dio_timestamp >= pref_parent's, because it's a newly-received message + uint32_t time_between_parent = neighbour->dio_timestamp - pref_parent->dio_timestamp; + uint32_t accepted_time = (uint32_t)dodag_info->dio_timer_params.Imax * 2; + //Accept prefix Update If Time from last DIO is more than 2 x Max + if (accepted_time < time_between_parent) { + return true; + } + } + + return false; +} + #endif /* HAVE_RPL */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h index b34e15c9c5c..3e1146a11e7 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h @@ -83,7 +83,8 @@ void rpl_instance_dio_trigger(rpl_instance_t *instance, struct protocol_interfac void rpl_instance_set_local_repair(rpl_instance_t *instance, bool repair); bool rpl_instance_local_repair(const rpl_instance_t *instance); uint16_t rpl_instance_current_rank(const rpl_instance_t *instance); -bool rpl_instance_address_is_parent(rpl_instance_t *instance, const uint8_t *ipv6_addr); +bool rpl_instance_address_is_parent(rpl_instance_t *instance, const uint8_t *ipv6_addr, bool selected); +uint16_t rpl_instance_address_candidate_count(rpl_instance_t *instance, bool selected_parents); void rpl_instance_neighbor_delete(rpl_instance_t *instance, const uint8_t *ipv6_addr); void rpl_instance_slow_timer(rpl_instance_t *instance, uint16_t seconds); @@ -139,11 +140,14 @@ void rpl_neighbour_update_dodag_version(rpl_neighbour_t *neighbour, rpl_dodag_ve bool rpl_neighbour_update_dtsn(rpl_neighbour_t *neighbour, uint8_t dtsn); rpl_instance_t *rpl_neighbour_instance(const rpl_neighbour_t *neighbour); + void rpl_instance_neighbours_changed(rpl_instance_t *instance, const rpl_dodag_t *dodag); void rpl_instance_run_parent_selection(rpl_instance_t *instance); void rpl_upward_print_instance(rpl_instance_t *instance, route_print_fn_t *print_fn); bool rpl_upward_read_dodag_info(const rpl_instance_t *instance, struct rpl_dodag_info_t *dodag_info); +bool rpl_upward_accept_prefix_update(const rpl_dodag_t *dodag_info, const rpl_neighbour_t *neighbour, const rpl_neighbour_t *pref_parent); uint16_t rpl_upward_read_dao_target_list_size(const rpl_instance_t *instance, const uint8_t *target_prefix); + #endif /* RPL_UPWARD_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c index 07146da65c3..b4596c9f4af 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c @@ -989,6 +989,7 @@ void tls_server_finnish_handle_start(sec_suite_t *tls_suite) #ifdef PANA_SERVER_API static buffer_t *tls_verify_handler(uint8_t certi_rx, tls_header_t *tls_header_ptr, buffer_t *buf, sec_suite_t *tls_suite) { + (void) certi_rx; tls_heap_t *tls_heap = tls_suite->tls_session->tls_heap; tls_heap->client_verify_buf_len = tls_header_ptr->length; if (tls_heap->client_verify_buf) { diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.c b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.c index bbff7bdad8c..a09ab4ea741 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.c @@ -33,65 +33,15 @@ #define TRACE_GROUP "kmar" -#define KMP_ADDR_DYN_ALLOC 0x80 -#define KMP_ADDR_TYPE_MASK 0x0F - -typedef struct { - uint8_t type; - uint8_t eui_64[8]; - address_t ip_addr; - uint16_t port; -} kmp_eui_64_ip_addr_t; - -kmp_addr_t *kmp_address_create(kmp_addr_e type, const uint8_t *eui_64) -{ - uint8_t size; - if (type == KMP_ADDR_EUI_64) { - size = sizeof(kmp_addr_t); - } else if (type == KMP_ADDR_EUI_64_AND_IP) { - size = sizeof(kmp_eui_64_ip_addr_t); - } else { - return 0; - } - - kmp_addr_t *addr = ns_dyn_mem_alloc(size); - if (!addr) { - return 0; - } - - kmp_address_init(type, addr, eui_64); - - addr->type |= KMP_ADDR_DYN_ALLOC; - - return addr; -} - void kmp_address_init(kmp_addr_e type, kmp_addr_t *addr, const uint8_t *eui_64) { - uint8_t size; - if (type == KMP_ADDR_EUI_64) { - size = sizeof(kmp_addr_t); - } else if (type == KMP_ADDR_EUI_64_AND_IP) { - size = sizeof(kmp_eui_64_ip_addr_t); - } else { - return; - } - - kmp_addr_t *kmp_addr = addr; - - memset(addr, 0, size); - kmp_addr->type = type; + memset(addr, 0, sizeof(kmp_addr_t)); + addr->type = type; if (eui_64) { - memcpy(kmp_addr->eui_64, eui_64, 8); + memcpy(addr->eui_64, eui_64, 8); } } -void kmp_address_delete(kmp_addr_t *addr) -{ - if (addr && (addr->type & KMP_ADDR_DYN_ALLOC)) { - ns_dyn_mem_free(addr); - } -} const uint8_t *kmp_address_eui_64_get(const kmp_addr_t *addr) { @@ -104,20 +54,11 @@ const uint8_t *kmp_address_eui_64_get(const kmp_addr_t *addr) const uint8_t *kmp_address_ip_get(const kmp_addr_t *addr) { - if (!addr || (addr->type & KMP_ADDR_TYPE_MASK) != KMP_ADDR_EUI_64_AND_IP) { + if (!addr || addr->type != KMP_ADDR_EUI_64_AND_IP) { return NULL; } - return ((kmp_eui_64_ip_addr_t *)addr)->ip_addr; -} - -uint16_t kmp_address_port_get(const kmp_addr_t *addr) -{ - if (!addr || (addr->type & KMP_ADDR_TYPE_MASK) != KMP_ADDR_EUI_64_AND_IP) { - return 0; - } - - return ((kmp_eui_64_ip_addr_t *)addr)->port; + return addr->relay_address; } int8_t kmp_address_eui_64_set(kmp_addr_t *addr, const uint8_t *eui64) @@ -130,26 +71,6 @@ int8_t kmp_address_eui_64_set(kmp_addr_t *addr, const uint8_t *eui64) return 0; } -int8_t kmp_address_ip_set(kmp_addr_t *addr, const uint8_t *ip_addr) -{ - if (!addr || !ip_addr || (addr->type & KMP_ADDR_TYPE_MASK) != KMP_ADDR_EUI_64_AND_IP) { - return -1; - } - - memcpy(((kmp_eui_64_ip_addr_t *)addr)->ip_addr, ip_addr, sizeof(address_t)); - return 0; -} - -int8_t kmp_address_port_set(kmp_addr_t *addr, const uint16_t port) -{ - if (!addr || (addr->type & KMP_ADDR_TYPE_MASK) != KMP_ADDR_EUI_64_AND_IP) { - return -1; - } - - ((kmp_eui_64_ip_addr_t *)addr)->port = port; - return 0; -} - int8_t kmp_address_copy(kmp_addr_t *to_addr, const kmp_addr_t *from_addr) { if (!to_addr || !from_addr) { @@ -158,16 +79,13 @@ int8_t kmp_address_copy(kmp_addr_t *to_addr, const kmp_addr_t *from_addr) memcpy(to_addr->eui_64, from_addr->eui_64, 8); - kmp_eui_64_ip_addr_t *to_ip_addr = (kmp_eui_64_ip_addr_t *) to_addr; - kmp_eui_64_ip_addr_t *from_ip_addr = (kmp_eui_64_ip_addr_t *) from_addr; - - if ((to_ip_addr->type & KMP_ADDR_TYPE_MASK) == KMP_ADDR_EUI_64_AND_IP - && (from_ip_addr->type & KMP_ADDR_TYPE_MASK) == KMP_ADDR_EUI_64_AND_IP) { - memcpy(to_ip_addr->ip_addr, from_ip_addr->ip_addr, sizeof(address_t)); - to_ip_addr->port = from_ip_addr->port; - } else if ((to_ip_addr->type & KMP_ADDR_TYPE_MASK) == KMP_ADDR_EUI_64_AND_IP) { - memset(to_ip_addr->ip_addr, 0, sizeof(address_t)); - to_ip_addr->port = 0; + if (to_addr->type == KMP_ADDR_EUI_64_AND_IP + && from_addr->type == KMP_ADDR_EUI_64_AND_IP) { + memcpy(to_addr->relay_address, from_addr->relay_address, sizeof(address_t)); + to_addr->port = from_addr->port; + } else if (to_addr->type == KMP_ADDR_EUI_64_AND_IP) { + memset(to_addr->relay_address, 0, sizeof(address_t)); + to_addr->port = 0; } return 0; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.h b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.h index 967839707c4..43b549a77cb 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_addr.h @@ -26,19 +26,10 @@ typedef enum { typedef struct { uint8_t type; uint8_t eui_64[8]; + address_t relay_address; + uint16_t port; } kmp_addr_t; -/** - * kmp_address_create creates address - * - * \param type address type - * \param eui_64 EUI-64 - * - * \return address - * - */ -kmp_addr_t *kmp_address_create(kmp_addr_e type, const uint8_t *eui_64); - /** * kmp_address_init initializes address * @@ -49,13 +40,6 @@ kmp_addr_t *kmp_address_create(kmp_addr_e type, const uint8_t *eui_64); */ void kmp_address_init(kmp_addr_e type, kmp_addr_t *addr, const uint8_t *eui_64); -/** - * kmp_address_delete deletes address - * - * \param addr address - * - */ -void kmp_address_delete(kmp_addr_t *addr); /** * kmp_address_eui_64_get get EUI-64 @@ -77,15 +61,6 @@ const uint8_t *kmp_address_eui_64_get(const kmp_addr_t *addr); */ const uint8_t *kmp_address_ip_get(const kmp_addr_t *addr); -/** - * kmp_address_port_get get port - * - * \param addr address - * - * \return port - * - */ -uint16_t kmp_address_port_get(const kmp_addr_t *addr); /** * kmp_address_eui_64_set set EUI-64 @@ -99,30 +74,6 @@ uint16_t kmp_address_port_get(const kmp_addr_t *addr); */ int8_t kmp_address_eui_64_set(kmp_addr_t *addr, const uint8_t *eui64); -/** - * kmp_address_ip_set set IP address - * - * \param addr address - * \param ip_addr IP address - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t kmp_address_ip_set(kmp_addr_t *addr, const uint8_t *ip_addr); - -/** - * kmp_address_port_set set port address - * - * \param addr address - * \param port port - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t kmp_address_port_set(kmp_addr_t *addr, const uint16_t port); - /** * kmp_address_copy copies address * diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c index 479f0d15bbb..35d541f1565 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c @@ -251,10 +251,10 @@ static void kmp_sec_prot_eui64_addr_get(sec_prot_t *prot, uint8_t *local_eui64, kmp->service->addr_get(kmp->service, kmp, &local_addr, &remote_addr); if (local_eui64) { - memcpy(local_eui64, kmp_address_eui_64_get(&local_addr), 8); + memcpy(local_eui64, local_addr.eui_64, 8); } if (remote_eui64) { - memcpy(remote_eui64, kmp_address_eui_64_get(&remote_addr), 8); + memcpy(remote_eui64, remote_addr.eui_64, 8); } } diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_socket_if.c b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_socket_if.c index d4dc4a32a8b..8bb7f262ba2 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_socket_if.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_socket_if.c @@ -129,9 +129,9 @@ static int8_t kmp_socket_if_send(kmp_service_t *service, kmp_type_e kmp_id, cons //Build UPD Relay uint8_t *ptr = pdu; - memcpy(ptr, kmp_address_ip_get(addr), 16); + memcpy(ptr, addr->relay_address, 16); ptr += 16; - ptr = common_write_16_bit(kmp_address_port_get(addr), ptr); + ptr = common_write_16_bit(addr->port, ptr); memcpy(ptr, kmp_address_eui_64_get(addr), 8); ptr += 8; *ptr = kmp_id; @@ -169,14 +169,15 @@ static void kmp_socket_if_socket_cb(void *ptr) ns_dyn_mem_free(pdu); return; } - uint8_t *relay_address, *euid64; - uint16_t relay_port; + kmp_addr_t addr; + addr.type = KMP_ADDR_EUI_64_AND_IP; + uint8_t *data_ptr = pdu; - relay_address = data_ptr; + memcpy(addr.relay_address, data_ptr, 16); data_ptr += 16; - relay_port = common_read_16_bit(data_ptr); + addr.port = common_read_16_bit(data_ptr); data_ptr += 2; - euid64 = data_ptr; + memcpy(addr.eui_64, data_ptr, 8); data_ptr += 8; kmp_type_e type = kmp_api_type_from_id_get(*data_ptr++); @@ -185,17 +186,8 @@ static void kmp_socket_if_socket_cb(void *ptr) return; } - kmp_addr_t *addr = kmp_address_create(KMP_ADDR_EUI_64_AND_IP, euid64); - if (!addr) { - ns_dyn_mem_free(pdu); - return; - } - - kmp_address_ip_set(addr, relay_address); - kmp_address_port_set(addr, relay_port); - kmp_service_msg_if_receive(socket_if->kmp_service, type, addr, data_ptr, cb_data->d_len - 27); - kmp_address_delete(addr); + kmp_service_msg_if_receive(socket_if->kmp_service, type, &addr, data_ptr, cb_data->d_len - 27); ns_dyn_mem_free(pdu); } diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c index ff7d126a253..470d854639b 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c @@ -272,7 +272,7 @@ int8_t sec_prot_lib_pmkid_calc(const uint8_t *pmk, const uint8_t *auth_eui64, co const uint8_t pmk_string_val[] = {"PMK Name"}; const uint8_t pmk_string_val_len = sizeof(pmk_string_val) - 1; - const uint8_t data_len = pmk_string_val_len + EUI64_LEN + EUI64_LEN; + uint8_t data_len = pmk_string_val_len + EUI64_LEN + EUI64_LEN; uint8_t data[data_len]; uint8_t *ptr = data; memcpy(ptr, pmk_string_val, pmk_string_val_len); @@ -294,7 +294,7 @@ int8_t sec_prot_lib_ptkid_calc(const uint8_t *ptk, const uint8_t *auth_eui64, co const uint8_t ptk_string_val[] = {"PTK Name"}; const uint8_t ptk_string_val_len = sizeof(ptk_string_val) - 1; - const uint8_t data_len = ptk_string_val_len + EUI64_LEN + EUI64_LEN; + uint8_t data_len = ptk_string_val_len + EUI64_LEN + EUI64_LEN; uint8_t data[data_len]; uint8_t *ptr = data; memcpy(ptr, ptk_string_val, ptk_string_val_len); diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 56f02ab3fe0..0232bc3178b 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -97,6 +97,11 @@ static void tls_sec_prot_lib_debug(void *ctx, int level, const char *file, int l #endif #ifdef MBEDTLS_PLATFORM_MEMORY +// Disable for now +//#define TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY static void *tls_sec_prot_lib_mem_calloc(size_t count, size_t size); static void tls_sec_prot_lib_mem_free(void *ptr); #endif @@ -105,9 +110,8 @@ int8_t tls_sec_prot_lib_init(tls_security_t *sec) { const char *pers = "ws_tls"; -#ifdef MBEDTLS_PLATFORM_MEMORY - // Disable for now - //mbedtls_platform_set_calloc_free(tls_sec_prot_lib_mem_calloc, tls_sec_prot_lib_mem_free); +#ifdef TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY + mbedtls_platform_set_calloc_free(tls_sec_prot_lib_mem_calloc, tls_sec_prot_lib_mem_free); #endif @@ -497,7 +501,7 @@ static int tls_sec_lib_entropy_poll(void *ctx, unsigned char *output, size_t len return (0); } -#ifdef MBEDTLS_PLATFORM_MEMORY +#ifdef TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY static void *tls_sec_prot_lib_mem_calloc(size_t count, size_t size) { void *mem_ptr = ns_dyn_mem_temporary_alloc(count * size); diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/blacklist/blacklist.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/blacklist/blacklist.c index a614ed12c1d..25d06666389 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/blacklist/blacklist.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/blacklist/blacklist.c @@ -100,7 +100,6 @@ bool blacklist_reject(const uint8_t *ll64_address) tr_debug("blacklist full reject"); return true; } else { - tr_debug("blacklist not found %s", trace_array(ll64_address + 8, 8)); return false; } } @@ -144,7 +143,6 @@ void blacklist_update(const uint8_t *ll64_address, bool success) } /* TTL is blacklist entry lifetime + from 1.0 to 1.5 * interval */ blacklist_entry->ttl = blacklist_data->blacklist_entry_lifetime + randLIB_randomise_base(blacklist_entry->interval, 0x8000, 0xC000); - tr_debug("Blacklist updated, ttl=%"PRIu16, blacklist_entry->ttl); } else { tr_debug("Blacklist add"); blacklist_entry_add(ll64_address + 8); diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/etx/etx.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/etx/etx.c index 802b85dccd5..2e8dcc1cdd2 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/etx/etx.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/etx/etx.c @@ -157,7 +157,7 @@ static bool etx_update_possible(etx_sample_storage_t *storage, etx_storage_t *en } } - tr_debug("ETX update possible %u attempts, %u rx ack", storage->attempts_count, storage->received_acks); + //tr_debug("ETX update possible %u attempts, %u rx ack", storage->attempts_count, storage->received_acks); return true; @@ -318,9 +318,6 @@ uint16_t etx_read(int8_t interface_id, addrtype_t addr_type, const uint8_t *addr } attribute_index = mac_neighbor->index; - - //tr_debug("Etx Read from atribute %u", attribute_index); - etx_storage_t *entry = etx_storage_entry_get(interface_id, attribute_index); if (!entry) { @@ -330,8 +327,6 @@ uint16_t etx_read(int8_t interface_id, addrtype_t addr_type, const uint8_t *addr uint16_t etx = etx_current_calc(entry->etx, entry->accumulated_failures); etx >>= 4; - //tr_debug("Etx value %u", etx); - return etx; } @@ -632,7 +627,6 @@ void etx_max_update_set(uint16_t etx_max_update) etx_storage_t *etx_storage_entry_get(int8_t interface_id, uint8_t attribute_index) { if (etx_info.interface_id != interface_id || !etx_info.etx_storage_list || attribute_index >= etx_info.ext_storage_list_size) { - tr_debug("Unknow ID or un initilized ETX %u", attribute_index); return NULL; } @@ -745,7 +739,7 @@ static void etx_accum_failures_callback_needed_check(etx_storage_t *entry, uint8 void etx_neighbor_remove(int8_t interface_id, uint8_t attribute_index) { - tr_debug("Remove attribute %u", attribute_index); + //tr_debug("Remove attribute %u", attribute_index); uint16_t stored_diff_etx; etx_storage_t *entry = etx_storage_entry_get(interface_id, attribute_index); if (entry && etx_info.callback_ptr) { @@ -780,7 +774,7 @@ void etx_neighbor_remove(int8_t interface_id, uint8_t attribute_index) void etx_neighbor_add(int8_t interface_id, uint8_t attribute_index) { - tr_debug("Add attribute %u", attribute_index); + //tr_debug("Add attribute %u", attribute_index); uint16_t stored_diff_etx; etx_storage_t *entry = etx_storage_entry_get(interface_id, attribute_index); if (entry && etx_info.callback_ptr) { @@ -804,12 +798,7 @@ void etx_cache_timer(int8_t interface_id, uint16_t seconds_update) } protocol_interface_info_entry_t *interface = protocol_stack_interface_info_get_by_id(interface_id); - if (!interface) { - return; - } - - - if (!mac_neighbor_info(interface)) { + if (!interface || !mac_neighbor_info(interface)) { return; } diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.c index 350c9e0e076..511c07aa985 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.c @@ -71,7 +71,7 @@ fhss_structure_t *fhss_enable(fhss_api_t *fhss_api, const fhss_configuration_t * fhss_struct->fhss_event_timer = eventOS_callback_timer_register(fhss_event_timer_cb); fhss_struct->bs->fhss_configuration = *fhss_configuration; - fhss_struct->bs->fhss_stats_ptr = fhss_statistics; + fhss_struct->fhss_stats_ptr = fhss_statistics; fhss_struct->number_of_channels = channel_count; // set a invalid id to tasklet_id, so we know that one is not started yet diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.h b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.h index baf89e6b20c..1f09840cbd1 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.h +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss.h @@ -97,7 +97,6 @@ struct fhss_bs { uint16_t channel_list_counter; uint16_t synch_panid; uint32_t synch_interval; - struct fhss_statistics *fhss_stats_ptr; struct fhss_beacon_info *fhss_beacon_info_store; struct fhss_configuration fhss_configuration; struct fhss_synch_configuration synch_configuration; diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_common.h b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_common.h index 1c9dbceb7a4..35e1d0cc461 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_common.h +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_common.h @@ -48,6 +48,7 @@ struct fhss_structure { struct fhss_ws *ws; struct fhss_timer platform_functions; struct fhss_callback callbacks; + struct fhss_statistics *fhss_stats_ptr; fhss_failed_tx_list_t fhss_failed_tx_list; uint8_t synch_parent[8]; }; diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_configuration_interface.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_configuration_interface.c index c1acfc38ac3..5ac0f81a4e7 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_configuration_interface.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_configuration_interface.c @@ -24,6 +24,7 @@ #include "Service_Libs/fhss/fhss.h" #include "Service_Libs/fhss/fhss_common.h" #include "Service_Libs/fhss/fhss_ws.h" +#include "Service_Libs/fhss/fhss_statistics.h" #include "ns_trace.h" #define TRACE_GROUP "fhss" @@ -138,3 +139,12 @@ int ns_fhss_ws_set_hop_count(const fhss_api_t *fhss_api, const uint8_t hop_count } return fhss_ws_set_hop_count(fhss_structure, hop_count); } + +int ns_fhss_statistics_start(const fhss_api_t *fhss_api, fhss_statistics_t *fhss_statistics) +{ + fhss_structure_t *fhss_structure = fhss_get_object_with_api(fhss_api); + if (!fhss_structure) { + return -1; + } + return fhss_statistics_start(fhss_structure, fhss_statistics); +} diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.c index 2ab1702ed51..b4ee75c48f9 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.c @@ -24,23 +24,35 @@ void fhss_stats_update(fhss_structure_t *fhss_structure, fhss_stats_type_t type, uint32_t update_val) { - if (fhss_structure->bs->fhss_stats_ptr) { + if (fhss_structure->fhss_stats_ptr) { switch (type) { case STATS_FHSS_DRIFT_COMP: - fhss_structure->bs->fhss_stats_ptr->fhss_drift_compensation = update_val; + fhss_structure->fhss_stats_ptr->fhss_drift_compensation = update_val; break; case STATS_FHSS_HOP_COUNT: - fhss_structure->bs->fhss_stats_ptr->fhss_hop_count = update_val; + fhss_structure->fhss_stats_ptr->fhss_hop_count = update_val; break; case STATS_FHSS_SYNCH_INTERVAL: - fhss_structure->bs->fhss_stats_ptr->fhss_synch_interval = update_val; + fhss_structure->fhss_stats_ptr->fhss_synch_interval = update_val; break; case STATS_FHSS_AVG_SYNCH_FIX: - fhss_structure->bs->fhss_stats_ptr->fhss_prev_avg_synch_fix = update_val; + fhss_structure->fhss_stats_ptr->fhss_prev_avg_synch_fix = update_val; break; case STATS_FHSS_SYNCH_LOST: - fhss_structure->bs->fhss_stats_ptr->fhss_synch_lost += update_val; + fhss_structure->fhss_stats_ptr->fhss_synch_lost += update_val; + break; + case STATS_FHSS_UNKNOWN_NEIGHBOR: + fhss_structure->fhss_stats_ptr->fhss_unknown_neighbor += update_val; + break; + case STATS_FHSS_CHANNEL_RETRY: + fhss_structure->fhss_stats_ptr->fhss_channel_retry += update_val; break; } } } + +int fhss_statistics_start(fhss_structure_t *fhss_structure, fhss_statistics_t *fhss_statistics) +{ + fhss_structure->fhss_stats_ptr = fhss_statistics; + return 0; +} diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.h b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.h index 42ddaa0af19..bd2f81eaef4 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.h +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_statistics.h @@ -23,8 +23,11 @@ typedef enum { STATS_FHSS_SYNCH_INTERVAL, STATS_FHSS_AVG_SYNCH_FIX, STATS_FHSS_SYNCH_LOST, + STATS_FHSS_UNKNOWN_NEIGHBOR, + STATS_FHSS_CHANNEL_RETRY } fhss_stats_type_t; void fhss_stats_update(fhss_structure_t *fhss_structure, fhss_stats_type_t type, uint32_t update_val); +int fhss_statistics_start(fhss_structure_t *fhss_structure, fhss_statistics_t *fhss_statistics); #endif /* FHSS_STATISTICS_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c index 7cf0cd94732..8d4f159ee45 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c @@ -20,6 +20,7 @@ #include "fhss_config.h" #include "fhss.h" #include "fhss_common.h" +#include "fhss_statistics.h" #include "channel_list.h" #include "channel_functions.h" #include "fhss_ws.h" @@ -143,7 +144,7 @@ fhss_structure_t *fhss_ws_enable(fhss_api_t *fhss_api, const fhss_ws_configurati fhss_struct->fhss_event_timer = eventOS_callback_timer_register(fhss_event_timer_cb); fhss_struct->ws->fhss_configuration = *fhss_configuration; fhss_struct->number_of_channels = channel_count; - fhss_struct->own_hop = 0xff; + fhss_ws_set_hop_count(fhss_struct, 0xff); fhss_struct->rx_channel = fhss_configuration->unicast_fixed_channel; fhss_struct->ws->min_synch_interval = DEFAULT_MIN_SYNCH_INTERVAL; fhss_set_txrx_slot_length(fhss_struct); @@ -472,6 +473,7 @@ static int fhss_ws_tx_handle_callback(const fhss_api_t *api, bool is_broadcast_a if (fhss_structure->fhss_state == FHSS_SYNCHRONIZED) { fhss_ws_neighbor_timing_info_t *neighbor_timing_info = fhss_structure->ws->get_neighbor_info(api, destination_address); if (!neighbor_timing_info) { + fhss_stats_update(fhss_structure, STATS_FHSS_UNKNOWN_NEIGHBOR, 1); return -2; } // TODO: WS bootstrap has to store neighbors number of channels @@ -687,6 +689,7 @@ static bool fhss_ws_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, // Create new failure handle and return true to retransmit fhss_failed_handle_add(fhss_structure, handle, fhss_structure->rx_channel); } + fhss_stats_update(fhss_structure, STATS_FHSS_CHANNEL_RETRY, 1); return true; } @@ -858,9 +861,11 @@ int fhss_ws_set_parent(fhss_structure_t *fhss_structure, const uint8_t eui64[8], drift_per_ms_tmp = -MAX_DRIFT_COMPENSATION_STEP; } fhss_structure->ws->drift_per_millisecond_ns += drift_per_ms_tmp; + fhss_stats_update(fhss_structure, STATS_FHSS_DRIFT_COMP, NS_TO_US(fhss_structure->ws->drift_per_millisecond_ns * bc_timing_info->broadcast_dwell_interval)); } tr_debug("synch to parent: %s, drift: %"PRIi32"ms in %"PRIu32" seconds, compensation: %"PRIi32"ns per ms", trace_array(eui64, 8), true_bc_interval_offset - own_bc_interval_offset + ((int32_t)(fhss_structure->ws->bc_slot - own_bc_slot) * bc_timing_info->broadcast_interval), US_TO_S(time_since_last_synch_us), fhss_structure->ws->drift_per_millisecond_ns); } + fhss_stats_update(fhss_structure, STATS_FHSS_SYNCH_INTERVAL, US_TO_S(time_since_last_synch_us)); return 0; } @@ -915,6 +920,8 @@ int fhss_ws_configuration_set(fhss_structure_t *fhss_structure, const fhss_ws_co int fhss_ws_set_hop_count(fhss_structure_t *fhss_structure, const uint8_t hop_count) { fhss_structure->own_hop = hop_count; + fhss_stats_update(fhss_structure, STATS_FHSS_HOP_COUNT, fhss_structure->own_hop); return 0; } + #endif // HAVE_WS diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/mac_neighbor_table/mac_neighbor_table.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/mac_neighbor_table/mac_neighbor_table.c index 89ebcce39e1..3f1960fb5bc 100644 --- a/features/nanostack/sal-stack-nanostack/source/Service_Libs/mac_neighbor_table/mac_neighbor_table.c +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/mac_neighbor_table/mac_neighbor_table.c @@ -26,8 +26,6 @@ #include "Core/include/ns_address_internal.h" #include "platform/topo_trace.h" -#define TRACE_GROUP "mnei" - mac_neighbor_table_t *mac_neighbor_table_create(uint8_t table_size, neighbor_entry_remove_notify *remove_cb, neighbor_entry_nud_notify *nud_cb, void *user_indentifier) { mac_neighbor_table_t *table_class = ns_dyn_mem_alloc(sizeof(mac_neighbor_table_t) + sizeof(mac_neighbor_table_entry_t) * table_size); @@ -111,11 +109,9 @@ void mac_neighbor_table_neighbor_timeout_update(mac_neighbor_table_t *table_clas if (table_class->user_nud_notify_cb(cur, table_class->table_user_identifier)) { table_class->active_nud_process++; cur->nud_active = true; - tr_debug("Nud started index %u : %"PRIu32" time ", cur->index, cur->lifetime); } } else { - tr_debug("Node index %u time out ", cur->index); neighbor_table_class_remove_entry(table_class, cur); } } @@ -176,7 +172,6 @@ void mac_neighbor_table_neighbor_refresh(mac_neighbor_table_t *table_class, mac_ neighbor_entry->lifetime = life_time; neighbor_entry->link_lifetime = life_time; if (neighbor_entry->nud_active) { - tr_debug("Node index NUD response %u : %"PRIu32" time ", neighbor_entry->index, neighbor_entry->lifetime); neighbor_entry->nud_active = false; table_class->active_nud_process--; } diff --git a/features/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_conf.c b/features/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_conf.c new file mode 100644 index 00000000000..54ebbbe8a8f --- /dev/null +++ b/features/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_conf.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2017-2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "nsconfig.h" +#include "ns_types.h" + +#include "Core/include/ns_monitor.h" +#include "mac_api.h" // for mcps_packet_ingress_rate_limit_by_memory +#include "MAC/IEEE802_15_4/mac_mcps_sap.h" // for mcps_packet_ingress_rate_limit_by_memory + +int ns_conf_gc_threshold_set(uint8_t percentage_high, uint8_t percentage_critical) +{ + return ns_monitor_heap_gc_threshold_set(percentage_high, percentage_critical); +} + +int ns_conf_packet_ingress_rate_limit_by_mem(uint8_t free_heap_percentage) +{ + return mcps_packet_ingress_rate_limit_by_memory(free_heap_percentage); +} diff --git a/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.c b/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.c index d51eb029d30..711159c4d57 100644 --- a/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.c +++ b/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.c @@ -303,9 +303,15 @@ ipv6_neighbour_t *ipv6_neighbour_lookup_or_create(ipv6_neighbour_cache_t *cache, { uint_fast16_t count = 0; ipv6_neighbour_t *entry = NULL; + ipv6_neighbour_t *garbage_possible_entry = NULL; ns_list_foreach(ipv6_neighbour_t, cur, &cache->list) { - count++; + + if (cur->type == IP_NEIGHBOUR_GARBAGE_COLLECTIBLE) { + garbage_possible_entry = cur; + count++; + } + if (addr_ipv6_equal(cur->ip_address, address)) { if (cur != ns_list_get_first(&cache->list)) { ns_list_remove(&cache->list, cur); @@ -315,9 +321,9 @@ ipv6_neighbour_t *ipv6_neighbour_lookup_or_create(ipv6_neighbour_cache_t *cache, } } - if (count >= neighbour_cache_config.max_entries) { - entry = ns_list_get_last(&cache->list); - ipv6_neighbour_entry_remove(cache, entry); + if (count >= neighbour_cache_config.max_entries && garbage_possible_entry) { + //Remove Last storaged IP_NEIGHBOUR_GARBAGE_COLLECTIBLE type entry + ipv6_neighbour_entry_remove(cache, garbage_possible_entry); } // Allocate new - note we have a basic size, plus enough for the LL address, @@ -1066,6 +1072,23 @@ void ipv6_destination_redirect(const uint8_t *dest_addr, const uint8_t *sender_a } #endif +void ipv6_destination_cache_forced_gc(bool full_gc) +{ + int gc_count = ns_list_count(&ipv6_destination_cache); + + /* Minimize size of destination cache: + * - keep absolutely minimum number of entries if not full gc + * - clear all entries in case of full gc + **/ + ns_list_foreach_reverse_safe(ipv6_destination_t, entry, &ipv6_destination_cache) { + if (entry->lifetime == 0 || gc_count > destination_cache_config.long_term_entries || full_gc) { + ns_list_remove(&ipv6_destination_cache, entry); + ipv6_destination_release(entry); + gc_count--; + } + } +} + static void ipv6_destination_release(ipv6_destination_t *dest) { if (--dest->refcount == 0) { diff --git a/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.h b/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.h index 291077527b0..944439843e5 100644 --- a/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.h +++ b/features/nanostack/sal-stack-nanostack/source/ipv6_stack/ipv6_routing_table.h @@ -73,7 +73,7 @@ typedef enum ipv6_route_src { ROUTE_RPL_DAO, /* Explicitly advertised in DAO, Storing mode */ ROUTE_RPL_DAO_SR, /* Explicitly advertised in DAO, Root Source Routes in Non-Storing mode */ ROUTE_RPL_SRH, /* Not in routing table - used in buffers to represent on-link inferred from SRH */ - ROUTE_RPL_ROOT, /* Implicit route to DODAG route */ + ROUTE_RPL_ROOT, /* Implicit route to DODAG root */ ROUTE_RPL_INSTANCE, /* Implicit instance-specific default upward route (not for general search) */ ROUTE_RPL_FWD_ERROR, /* Not in routing table - used in buffers to represent Forwarding-Error bounce */ ROUTE_MULTICAST, /* Not in routing table - used to represent multicast interface selection */ @@ -222,6 +222,7 @@ void ipv6_destination_cache_timer(uint8_t ticks); #ifdef HAVE_IPV6_ND void ipv6_destination_redirect(const uint8_t *dest_addr, const uint8_t *sender_addr, const uint8_t *redirect_addr, int8_t interface_id, addrtype_t ll_type, const uint8_t *ll_address); #endif +void ipv6_destination_cache_forced_gc(bool full_gc); /* Combined Routing Table (RFC 4191) and Prefix List (RFC 4861) */ /* On-link prefixes have the on_link flag set and next_hop is unset */ diff --git a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c index b784904dd87..5356eda2fb2 100644 --- a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c +++ b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c @@ -828,6 +828,8 @@ void dhcp_service_send_message(msg_tr_t *msg_tr_ptr) } if (retval != 0) { tr_warn("dhcp service socket_sendto fails: %i", retval); + } else { + tr_warn("dhcp service socket_sendto %s", trace_ipv6(msg_tr_ptr->addr.address)); } } bool dhcp_service_timer_tick(uint16_t ticks) diff --git a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c index 53beaaadc3d..5b7b3ffb8be 100644 --- a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c +++ b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c @@ -208,7 +208,7 @@ dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_transactionId(ui dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_prefix(int8_t interfaceId, uint8_t *prefix) { ns_list_foreach(dhcpv6_client_server_data_t, cur, &dhcpv6_client_nonTemporal_list) { - if ((cur->interfaceId == interfaceId)) { + if (cur->interfaceId == interfaceId) { if (memcmp(cur->iaNontemporalAddress.addressPrefix, prefix, 8) == 0) { return cur; } diff --git a/features/nanostack/sal-stack-nanostack/sources.mk b/features/nanostack/sal-stack-nanostack/sources.mk index f71f088bdfa..40c75cbe0b6 100644 --- a/features/nanostack/sal-stack-nanostack/sources.mk +++ b/features/nanostack/sal-stack-nanostack/sources.mk @@ -39,6 +39,7 @@ SRCS += \ source/6LoWPAN/ws/ws_eapol_auth_relay.c \ source/6LoWPAN/ws/ws_eapol_relay_lib.c \ source/6LoWPAN/ws/ws_eapol_pdu.c \ + source/6LoWPAN/ws/ws_stats.c \ source/BorderRouter/border_router.c \ source/Common_Protocols/icmpv6.c \ source/Common_Protocols/icmpv6_prefix.c \ @@ -51,6 +52,7 @@ SRCS += \ source/Common_Protocols/tcp.c \ source/Common_Protocols/udp.c \ source/Core/ns_address_internal.c \ + source/Core/ns_monitor.c \ source/Core/buffer_dyn.c \ source/Core/sockbuf.c \ source/Core/ns_socket.c \ @@ -195,6 +197,7 @@ SRCS += \ source/Service_Libs/utils/ns_crc.c \ source/Service_Libs/utils/isqrt.c \ source/Service_Libs/utils/ns_file_system.c \ + source/Service_Libs/utils/ns_conf.c \ source/Service_Libs/mdns/ns_mdns_api.c \ source/Service_Libs/mdns/ns_fnet_port.c \ source/Service_Libs/mdns/ns_fnet_events.c \ diff --git a/features/netsocket/nsapi_dns.cpp b/features/netsocket/nsapi_dns.cpp index e8f245b7cac..a5087de5cb3 100644 --- a/features/netsocket/nsapi_dns.cpp +++ b/features/netsocket/nsapi_dns.cpp @@ -131,6 +131,13 @@ static bool dns_timer_running = false; // DNS server configuration extern "C" nsapi_error_t nsapi_dns_add_server(nsapi_addr_t addr, const char *interface_name) { + // check if addr was already added + for (int i = 0; i < DNS_SERVERS_SIZE; i++) { + if (memcmp(&addr, &dns_servers[i], sizeof(nsapi_addr_t)) == 0) { + return NSAPI_ERROR_OK; + } + } + memmove(&dns_servers[1], &dns_servers[0], (DNS_SERVERS_SIZE - 1)*sizeof(nsapi_addr_t)); @@ -717,7 +724,7 @@ nsapi_value_or_error_t nsapi_dns_query_multiple_async(NetworkStack *stack, const if (!dns_timer_running) { if (nsapi_dns_call_in(query->call_in_cb, DNS_TIMER_TIMEOUT, mbed::callback(nsapi_dns_query_async_timeout)) != NSAPI_ERROR_OK) { - delete query->host; + delete[] query->host; delete query; dns_mutex->unlock(); return NSAPI_ERROR_NO_MEMORY; diff --git a/features/storage/TESTS/blockdevice/heap_block_device/main.cpp b/features/storage/TESTS/blockdevice/heap_block_device/main.cpp index fe65308a3bf..6567e4dcd1c 100644 --- a/features/storage/TESTS/blockdevice/heap_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/heap_block_device/main.cpp @@ -26,7 +26,7 @@ using namespace utest::v1; // TODO HACK, replace with available ram/heap property #if defined(TARGET_MTB_MTS_XDOT) #error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#endif +#else #define TEST_BLOCK_SIZE 128 #define TEST_BLOCK_DEVICE_SIZE 32*TEST_BLOCK_SIZE @@ -186,3 +186,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp b/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp index 489107b5adc..5569f73a2f3 100644 --- a/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp @@ -27,7 +27,7 @@ using namespace utest::v1; // TODO HACK, replace with available ram/heap property #if defined(TARGET_MTB_MTS_XDOT) #error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#endif +#else #define BLOCK_COUNT 16 #define BLOCK_SIZE 512 @@ -250,3 +250,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/features/storage/TESTS/blockdevice/util_block_device/main.cpp b/features/storage/TESTS/blockdevice/util_block_device/main.cpp index 0f0fe103afb..ddc6e989b5d 100644 --- a/features/storage/TESTS/blockdevice/util_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/util_block_device/main.cpp @@ -29,7 +29,7 @@ using namespace utest::v1; // TODO HACK, replace with available ram/heap property #if defined(TARGET_MTB_MTS_XDOT) #error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#endif +#else #define BLOCK_COUNT 16 #define BLOCK_SIZE 512 @@ -308,3 +308,5 @@ int main() { return !Harness::run(specification); } + +#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/features/storage/TESTS/filesystem/fat_filesystem/main.cpp b/features/storage/TESTS/filesystem/fat_filesystem/main.cpp index 86f7b68dd1f..1dffa0d7c86 100644 --- a/features/storage/TESTS/filesystem/fat_filesystem/main.cpp +++ b/features/storage/TESTS/filesystem/fat_filesystem/main.cpp @@ -27,7 +27,7 @@ using namespace utest::v1; #ifndef MBED_EXTENDED_TESTS #error [NOT_SUPPORTED] Filesystem tests not supported by default -#endif +#else static const int mem_alloc_threshold = 32 * 1024; @@ -189,3 +189,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_EXTENDED_TESTS diff --git a/features/storage/TESTS/filesystem/general_filesystem/main.cpp b/features/storage/TESTS/filesystem/general_filesystem/main.cpp index 732d0ca94ea..ca14531288b 100644 --- a/features/storage/TESTS/filesystem/general_filesystem/main.cpp +++ b/features/storage/TESTS/filesystem/general_filesystem/main.cpp @@ -30,6 +30,7 @@ #error [NOT_SUPPORTED] storage test not supported on this platform #endif +#if COMPONENT_SPIF || COMPONENT_SD using namespace utest::v1; using namespace mbed; @@ -2105,3 +2106,5 @@ int main() { return !Harness::run(specification); } + +#endif // COMPONENT_SPIF || COMPONENT_SD diff --git a/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp b/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp index 8f983ba5bf5..300439f6f32 100644 --- a/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp +++ b/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp @@ -29,7 +29,7 @@ using namespace utest::v1; #ifndef MBED_EXTENDED_TESTS #error [NOT_SUPPORTED] Filesystem tests not supported by default -#endif +#else static const int mem_alloc_threshold = 32 * 1024; @@ -304,3 +304,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_EXTENDED_TESTS diff --git a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp index 3c31f6859f7..f4ef1b13aaa 100644 --- a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp +++ b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp @@ -17,7 +17,7 @@ #ifndef COMPONENT_FLASHIAP #error [NOT_SUPPORTED] Target must have internal FlashIAP for this test -#endif +#else #include "mbed.h" #include @@ -360,3 +360,5 @@ int main() { return !Harness::run(specification); } + +#endif // COMPONENT_FLASHIAP diff --git a/features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp b/features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp index f13ee3f3090..da9e6e51485 100644 --- a/features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp +++ b/features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp @@ -29,7 +29,7 @@ #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels -#endif +#else #define FSST_TEST_NUM_OF_THREADS 5 @@ -521,3 +521,4 @@ int main() return !Harness::run(specification); } +#endif // !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) diff --git a/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp b/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp index 4ff52eb1e4d..1568693d3e2 100644 --- a/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp +++ b/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp @@ -31,7 +31,7 @@ using namespace mbed; #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels -#endif +#else static const char data[] = "data"; static const char key[] = "key"; @@ -855,3 +855,5 @@ int main() return !Harness::run(specification); } + +#endif // !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) diff --git a/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp b/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp index 4f701d97340..aa8105e8aac 100644 --- a/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp +++ b/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp @@ -31,7 +31,7 @@ using namespace mbed; #if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) #error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels -#endif +#else static const char data[] = "data"; static const char key[] = "key"; @@ -858,3 +858,5 @@ int main() return !Harness::run(specification); } + +#endif // !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) diff --git a/features/storage/TESTS/kvstore/securestore_whitebox/main.cpp b/features/storage/TESTS/kvstore/securestore_whitebox/main.cpp index de8a628230e..af2bb1d5f15 100644 --- a/features/storage/TESTS/kvstore/securestore_whitebox/main.cpp +++ b/features/storage/TESTS/kvstore/securestore_whitebox/main.cpp @@ -34,13 +34,9 @@ #include #include -#if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM) -#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels -#endif - -#if !SECURESTORE_ENABLED -#error [NOT_SUPPORTED] KVStore & SecureStore need to be enabled for this test -#endif +#if (!defined(TARGET_K64F) && !defined(TARGET_ARM_FM)) || !SECURESTORE_ENABLED +#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels. KVStore & SecureStore need to be enabled for this test +#else using namespace mbed; @@ -534,3 +530,5 @@ int main() { return !Harness::run(specification); } + +#endif // (!defined(TARGET_K64F) && !defined(TARGET_ARM_FM)) || !SECURESTORE_ENABLED diff --git a/features/storage/blockdevice/BufferedBlockDevice.cpp b/features/storage/blockdevice/BufferedBlockDevice.cpp index 4eeb7bf2e11..eaa188532a6 100644 --- a/features/storage/blockdevice/BufferedBlockDevice.cpp +++ b/features/storage/blockdevice/BufferedBlockDevice.cpp @@ -28,7 +28,7 @@ static inline uint32_t align_down(bd_size_t val, bd_size_t size) } BufferedBlockDevice::BufferedBlockDevice(BlockDevice *bd) - : _bd(bd), _bd_program_size(0), _bd_read_size(0), _write_cache_addr(0), _write_cache_valid(false), + : _bd(bd), _bd_program_size(0), _bd_read_size(0), _bd_size(0), _write_cache_addr(0), _write_cache_valid(false), _write_cache(0), _read_buf(0), _init_ref_count(0), _is_initialized(false) { } diff --git a/features/storage/filesystem/fat/ChaN/ff.cpp b/features/storage/filesystem/fat/ChaN/ff.cpp index 7e4561d8098..e98bb3e43c2 100644 --- a/features/storage/filesystem/fat/ChaN/ff.cpp +++ b/features/storage/filesystem/fat/ChaN/ff.cpp @@ -2719,7 +2719,7 @@ void get_fileinfo ( if (wc == 0) { di = 0; break; } /* Buffer overflow? */ di += wc; #else /* ANSI/OEM output */ - fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ + if (di <= FF_SFN_BUF) fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ #endif } fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */ @@ -4938,7 +4938,7 @@ FRESULT f_mkdir ( res = sync_fs(fs); } } else { - remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ + res = remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ } } FREE_NAMBUF(); @@ -4967,7 +4967,8 @@ FRESULT f_rename ( DEF_NAMBUF - get_ldnumber(&path_new); /* Snip the drive number of new name off */ + int vol = get_ldnumber(&path_new); /* Snip the drive number of new name off */ + if (vol < 0) return FR_INVALID_DRIVE; res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ if (res == FR_OK) { djo.obj.fs = fs; diff --git a/features/storage/filesystem/fat/FATFileSystem.cpp b/features/storage/filesystem/fat/FATFileSystem.cpp index 297ac109e90..415aac41ad4 100644 --- a/features/storage/filesystem/fat/FATFileSystem.cpp +++ b/features/storage/filesystem/fat/FATFileSystem.cpp @@ -282,6 +282,7 @@ extern "C" DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) FATFileSystem::FATFileSystem(const char *name, BlockDevice *bd) : FileSystem(name), _id(-1) { + _fs = { 0 }; if (bd) { mount(bd); } diff --git a/features/storage/filesystem/littlefs/LittleFileSystem.cpp b/features/storage/filesystem/littlefs/LittleFileSystem.cpp index 23c749c1dd8..34ee5f60934 100644 --- a/features/storage/filesystem/littlefs/LittleFileSystem.cpp +++ b/features/storage/filesystem/littlefs/LittleFileSystem.cpp @@ -149,6 +149,9 @@ LittleFileSystem::LittleFileSystem(const char *name, BlockDevice *bd, , _prog_size(prog_size) , _block_size(block_size) , _lookahead(lookahead) + , _lfs() + , _config() + , _bd(NULL) { if (bd) { mount(bd); diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem/dirs/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem/dirs/main.cpp index 8225baba11e..41d965116b6 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem/dirs/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem/dirs/main.cpp @@ -32,7 +32,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -681,3 +681,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem/files/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem/files/main.cpp index e852a0ee7b3..d32aef0c20c 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem/files/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem/files/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -447,3 +447,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem/interspersed/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem/interspersed/main.cpp index 51f198af4e7..60cb96b2224 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem/interspersed/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem/interspersed/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -405,3 +405,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem/seek/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem/seek/main.cpp index 0b41321c31d..b8286dc8463 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem/seek/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem/seek/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -641,3 +641,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_integration/format/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_integration/format/main.cpp index eab5359c680..a086c2a8881 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_integration/format/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_integration/format/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -197,3 +197,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience/main.cpp index 802fb65a841..2d9660c2c86 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience/main.cpp @@ -26,7 +26,7 @@ using namespace utest::v1; // test configuration #ifndef MBED_TEST_SIM_BLOCKDEVICE #error [NOT_SUPPORTED] Simulation block device required for resilience tests -#endif +#else #ifndef MBED_TEST_SIM_BLOCKDEVICE_DECL #define MBED_TEST_SIM_BLOCKDEVICE_DECL MBED_TEST_SIM_BLOCKDEVICE bd(MBED_TEST_BLOCK_COUNT*512, 1, 1, 512) @@ -102,3 +102,5 @@ int main() { Harness::run(specification); } + +#endif // MBED_TEST_SIM_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience_functional/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience_functional/main.cpp index f0ea4afe233..a3ba52109a9 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience_functional/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/resilience_functional/main.cpp @@ -30,7 +30,7 @@ using namespace utest::v1; // test configuration #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required for resilience_functional tests -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -117,3 +117,5 @@ int main() GREENTEA_TESTSUITE_RESULT(CMD_STATUS_PASS == cmd_status); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/wear_leveling/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/wear_leveling/main.cpp index a9b8973ce89..ab349c78abd 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/wear_leveling/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_recovery/wear_leveling/main.cpp @@ -27,7 +27,7 @@ using namespace utest::v1; // test configuration #ifndef MBED_TEST_SIM_BLOCKDEVICE #error [NOT_SUPPORTED] Simulation block device required for wear leveling tests -#endif +#else #ifndef MBED_TEST_SIM_BLOCKDEVICE_DECL #define MBED_TEST_SIM_BLOCKDEVICE_DECL MBED_TEST_SIM_BLOCKDEVICE bd(MBED_TEST_BLOCK_COUNT*512, 1, 1, 512) @@ -118,3 +118,5 @@ int main() { Harness::run(specification); } + +#endif // MBED_TEST_SIM_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/dirs/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/dirs/main.cpp index 8793040512b..85b1f354c46 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/dirs/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/dirs/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -682,3 +682,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/files/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/files/main.cpp index 120eff16128..661e3a8d5a4 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/files/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/files/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -447,3 +447,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/interspersed/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/interspersed/main.cpp index 46ee79d4474..71724e92442 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/interspersed/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/interspersed/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -405,3 +405,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/seek/main.cpp b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/seek/main.cpp index 6e904fce209..9efd14fc6a3 100644 --- a/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/seek/main.cpp +++ b/features/storage/filesystem/littlefs/TESTS/filesystem_retarget/seek/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #ifndef MBED_TEST_BLOCKDEVICE #error [NOT_SUPPORTED] Non-volatile block device required -#endif +#else #ifndef MBED_TEST_BLOCKDEVICE_DECL #define MBED_TEST_BLOCKDEVICE_DECL MBED_TEST_BLOCKDEVICE bd @@ -639,3 +639,5 @@ int main() { return !Harness::run(specification); } + +#endif // MBED_TEST_BLOCKDEVICE diff --git a/features/storage/filesystem/littlefs/littlefs/lfs.c b/features/storage/filesystem/littlefs/littlefs/lfs.c index 40d2b86ddc7..477addb1243 100644 --- a/features/storage/filesystem/littlefs/littlefs/lfs.c +++ b/features/storage/filesystem/littlefs/littlefs/lfs.c @@ -924,7 +924,7 @@ int lfs_mkdir(lfs_t *lfs, const char *path) { // build up new directory lfs_alloc_ack(lfs); - lfs_dir_t dir; + lfs_dir_t dir = { 0 }; err = lfs_dir_alloc(lfs, &dir); if (err) { return err; @@ -2106,7 +2106,7 @@ int lfs_format(lfs_t *lfs, const struct lfs_config *cfg) { lfs_alloc_ack(lfs); // create superblock dir - lfs_dir_t superdir; + lfs_dir_t superdir = { 0 }; err = lfs_dir_alloc(lfs, &superdir); if (err) { goto cleanup; diff --git a/features/storage/kvstore/filesystemstore/FileSystemStore.cpp b/features/storage/kvstore/filesystemstore/FileSystemStore.cpp index 01ac336e3e4..36f8d138d8d 100644 --- a/features/storage/kvstore/filesystemstore/FileSystemStore.cpp +++ b/features/storage/kvstore/filesystemstore/FileSystemStore.cpp @@ -62,7 +62,8 @@ static char *string_ndup(const char *src, size_t size); // Class Functions FileSystemStore::FileSystemStore(FileSystem *fs) : _fs(fs), - _is_initialized(false) + _is_initialized(false), _cfg_fs_path(NULL), _cfg_fs_path_size(0), + _full_path_key(NULL), _cur_inc_data_size(0), _cur_inc_set_handle(NULL) { } @@ -532,7 +533,7 @@ int FileSystemStore::iterator_next(iterator_t it, char *key, size_t key_size) key_it = (key_iterator_handle_t *)it; - if (key_name_size < strlen(key_it->prefix)) { + if ((key_it->prefix != NULL) && (key_name_size < strlen(key_it->prefix))) { status = MBED_ERROR_INVALID_SIZE; goto exit_point; } @@ -577,9 +578,8 @@ int FileSystemStore::iterator_close(iterator_t it) delete[] key_it->prefix; } - ((Dir *)(key_it->dir_handle))->close(); - if (key_it->dir_handle != NULL) { + ((Dir *)(key_it->dir_handle))->close(); delete ((Dir *)(key_it->dir_handle)); } delete key_it; diff --git a/features/storage/kvstore/kv_map/KVMap.cpp b/features/storage/kvstore/kv_map/KVMap.cpp index e86f8bee043..45ce0daa4db 100644 --- a/features/storage/kvstore/kv_map/KVMap.cpp +++ b/features/storage/kvstore/kv_map/KVMap.cpp @@ -65,7 +65,7 @@ int KVMap::attach(const char *partition_name, kvstore_config_t *kv_config) goto exit; } - kv_partition_name = new char[strlen(partition_name + 1)]; + kv_partition_name = new char[strlen(partition_name) + 1]; strcpy(kv_partition_name, partition_name); _kv_map_table[_kv_num_attached_kvs].partition_name = kv_partition_name; _kv_map_table[_kv_num_attached_kvs].kv_config = kv_config; @@ -251,10 +251,7 @@ KVStore *KVMap::get_internal_kv_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->internal_store; @@ -269,10 +266,7 @@ KVStore *KVMap::get_external_kv_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->external_store; @@ -287,10 +281,7 @@ KVStore *KVMap::get_main_kv_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->kvstore_main_instance; @@ -305,10 +296,7 @@ BlockDevice *KVMap::get_internal_blockdevice_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->internal_bd; @@ -323,10 +311,7 @@ BlockDevice *KVMap::get_external_blockdevice_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->external_bd; @@ -341,14 +326,11 @@ FileSystem *KVMap::get_external_filesystem_instance(const char *name) size_t key_index = 0; int ret = config_lookup(name, &kv_config, &key_index); - if (ret != MBED_SUCCESS) { - goto exit; - } -exit: + _mutex->unlock(); return ret != MBED_SUCCESS ? NULL : kv_config->external_fs; } -} +} // namespace mbed diff --git a/features/storage/kvstore/securestore/SecureStore.cpp b/features/storage/kvstore/securestore/SecureStore.cpp index 17207481a7e..e291316cb9c 100644 --- a/features/storage/kvstore/securestore/SecureStore.cpp +++ b/features/storage/kvstore/securestore/SecureStore.cpp @@ -109,7 +109,7 @@ int encrypt_decrypt_start(mbedtls_aes_context &enc_aes_ctx, uint8_t *iv, const c int encrypt_decrypt_data(mbedtls_aes_context &enc_aes_ctx, const uint8_t *in_buf, uint8_t *out_buf, uint32_t chunk_size, uint8_t *ctr_buf, size_t &aes_offs) { - uint8_t stream_block[enc_block_size]; + uint8_t stream_block[enc_block_size] = { 0 }; return mbedtls_aes_crypt_ctr(&enc_aes_ctx, chunk_size, &aes_offs, ctr_buf, stream_block, in_buf, out_buf); diff --git a/features/storage/kvstore/tdbstore/TDBStore.cpp b/features/storage/kvstore/tdbstore/TDBStore.cpp index 0ab8dcecb31..4ace1fcc32f 100644 --- a/features/storage/kvstore/tdbstore/TDBStore.cpp +++ b/features/storage/kvstore/tdbstore/TDBStore.cpp @@ -125,8 +125,14 @@ static uint32_t calc_crc(uint32_t init_crc, uint32_t data_size, const void *data TDBStore::TDBStore(BlockDevice *bd) : _ram_table(0), _max_keys(0), _num_keys(0), _bd(bd), _buff_bd(0), _free_space_offset(0), _master_record_offset(0), _master_record_size(0), _is_initialized(false), _active_area(0), _active_area_version(0), _size(0), - _prog_size(0), _work_buf(0), _key_buf(0), _variant_bd_erase_unit_size(false), _inc_set_handle(0) + _area_params{}, _prog_size(0), _work_buf(0), _key_buf(0), _variant_bd_erase_unit_size(false), _inc_set_handle(0) { + for (int i = 0; i < _num_areas; i++) { + _area_params[i] = { 0 }; + } + for (int i = 0; i < _max_open_iterators; i++) { + _iterator_table[i] = { 0 }; + } } TDBStore::~TDBStore() @@ -391,8 +397,8 @@ int TDBStore::set_start(set_handle_t *handle, const char *key, size_t final_data uint32_t create_flags) { int ret; - uint32_t offset; - uint32_t hash, ram_table_ind; + uint32_t offset = 0; + uint32_t hash = 0, ram_table_ind = 0; inc_set_handle_t *ih; bool need_gc = false; @@ -412,6 +418,8 @@ int TDBStore::set_start(set_handle_t *handle, const char *key, size_t final_data // in the upper layers). ih->bd_base_offset = _master_record_offset; ih->new_key = false; + ram_table_ind = 0; + hash = 0; } else { _mutex.lock(); diff --git a/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp b/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp index ab8752b74b4..5bd263bd877 100644 --- a/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp +++ b/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp @@ -29,7 +29,7 @@ #if !NVSTORE_ENABLED #error [NOT_SUPPORTED] NVSTORE needs to be enabled for this test -#endif +#else using namespace utest::v1; @@ -697,3 +697,5 @@ int main() { return !Harness::run(specification); } + +#endif // !NVSTORE_ENABLED diff --git a/features/storage/nvstore/source/nvstore.cpp b/features/storage/nvstore/source/nvstore.cpp index 2e14109df34..f69ee3e5a7d 100644 --- a/features/storage/nvstore/source/nvstore.cpp +++ b/features/storage/nvstore/source/nvstore.cpp @@ -145,9 +145,12 @@ static uint32_t crc32(uint32_t init_crc, uint32_t data_size, uint8_t *data_buf) } NVStore::NVStore() : _init_done(0), _init_attempts(0), _active_area(0), _max_keys(NVSTORE_MAX_KEYS), - _active_area_version(0), _free_space_offset(0), _size(0), _mutex(0), _offset_by_key(0), _flash(0), - _min_prog_size(0), _page_buf(0) + _active_area_version(0), _free_space_offset(0), _size(0), _mutex(0), _offset_by_key(0), _flash_area_params{}, + _flash(0), _min_prog_size(0), _page_buf(0) { + for (int i = 0; i < NVSTORE_NUM_AREAS; i++) { + _flash_area_params[i] = { 0 }; + } } NVStore::~NVStore() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..cb430a41643 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_peripherals(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..9abc7f0f4ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c new file mode 100644 index 00000000000..c2a2e7fce0e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h new file mode 100644 index 00000000000..8fe28073847 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U +#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U +#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U +#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_BT_UART_CLK_DIV_NUM 1U +#define CYBSP_CSD_CLK_DIV_ENABLED 1U +#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CSD_CLK_DIV_NUM 0U +#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U +#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..90f1013f8a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 00000000000..c58abf46e9f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,155 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 1UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 12, + .enableMsbFirst = false, + .dataWidth = 9UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_HIGH, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC; +uint32_t CYBSP_RADIO_rca = 0u; +const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = +{ + .emmc = false, + .dmaType = CY_SD_HOST_DMA_SDMA, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &CYBSP_RADIO_cardType, + .rca = &CYBSP_RADIO_rca, + .cardCapacity = &CYBSP_RADIO_cardCapacity, +}; +const cy_stc_smif_config_t CYBSP_QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t CYBSP_RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 00000000000..ffdd990d9fe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#include "cy_scb_ezi2c.h" +#include "cy_sd_host.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_CAPSENSE_ENABLED 1U +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 144000000u +#define CY_CAPSENSE_PERI_CLK 72000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 0u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CYBSP_CAPSENSE_HW CSD0 +#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn +#define CYBSP_BT_UART_ENABLED 1U +#define CYBSP_BT_UART_HW SCB2 +#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn +#define CYBSP_CSD_COMM_ENABLED 1U +#define CYBSP_CSD_COMM_HW SCB3 +#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn +#define CYBSP_DEBUG_UART_ENABLED 1U +#define CYBSP_DEBUG_UART_HW SCB5 +#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn +#define CYBSP_RADIO_ENABLED 1U +#define CYBSP_RADIO_HW SDHC0 +#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn +#define CYBSP_QSPI_ENABLED 1U +#define CYBSP_QSPI_HW SMIF0 +#define CYBSP_QSPI_IRQ smif_interrupt_IRQn +#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_DATALINES0_1 (1UL) +#define CYBSP_QSPI_DATALINES2_3 (1UL) +#define CYBSP_QSPI_DATALINES4_5 (0UL) +#define CYBSP_QSPI_DATALINES6_7 (0UL) +#define CYBSP_QSPI_SS0 (1UL) +#define CYBSP_QSPI_SS1 (0UL) +#define CYBSP_QSPI_SS2 (0UL) +#define CYBSP_QSPI_SS3 (0UL) +#define CYBSP_QSPI_DESELECT_DELAY 7 +#define CYBSP_MCWDT_ENABLED 1U +#define CYBSP_MCWDT_HW MCWDT_STRUCT0 +#define CYBSP_RTC_ENABLED 1U +#define CYBSP_RTC_10_MONTH_OFFSET (28U) +#define CYBSP_RTC_MONTH_OFFSET (24U) +#define CYBSP_RTC_10_DAY_OFFSET (20U) +#define CYBSP_RTC_DAY_OFFSET (16U) +#define CYBSP_RTC_1000_YEAR_OFFSET (12U) +#define CYBSP_RTC_100_YEAR_OFFSET (8U) +#define CYBSP_RTC_10_YEAR_OFFSET (4U) +#define CYBSP_RTC_YEAR_OFFSET (0U) + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; +extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; +extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config; +extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity; +extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType; +extern uint32_t CYBSP_RADIO_rca; +extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config; +extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg; +extern const cy_stc_smif_config_t CYBSP_QSPI_config; +extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config; +extern const cy_stc_rtc_config_t CYBSP_RTC_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..b9069ac8d5f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c @@ -0,0 +1,883 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED5_RGB_G_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED5_RGB_R_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SW4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_SW4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_DAT0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_DAT1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_DAT2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_DAT3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SDHC0_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, + .hsiom = CYBSP_BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DEBUG_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DEBUG_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_DEBUG_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_DEBUG_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED5_RGB_B_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); + + Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); + + Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config); + + Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_G_PORT, CYBSP_LED5_RGB_G_PIN, &CYBSP_LED5_RGB_G_config); + + Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config); + + + Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_R_PORT, CYBSP_LED5_RGB_R_PIN, &CYBSP_LED5_RGB_R_config); + + Cy_GPIO_Pin_Init(CYBSP_SW4_PORT, CYBSP_SW4_PIN, &CYBSP_SW4_config); + + Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT0_PORT, CYBSP_SDHC0_DAT0_PIN, &CYBSP_SDHC0_DAT0_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT1_PORT, CYBSP_SDHC0_DAT1_PIN, &CYBSP_SDHC0_DAT1_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT2_PORT, CYBSP_SDHC0_DAT2_PIN, &CYBSP_SDHC0_DAT2_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT3_PORT, CYBSP_SDHC0_DAT3_PIN, &CYBSP_SDHC0_DAT3_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_CMD_PORT, CYBSP_SDHC0_CMD_PIN, &CYBSP_SDHC0_CMD_config); + + Cy_GPIO_Pin_Init(CYBSP_SDHC0_CLK_PORT, CYBSP_SDHC0_CLK_PIN, &CYBSP_SDHC0_CLK_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); + + Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); + + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config); + + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config); + + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RTS_PORT, CYBSP_DEBUG_UART_RTS_PIN, &CYBSP_DEBUG_UART_RTS_config); + + Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_CTS_PORT, CYBSP_DEBUG_UART_CTS_PIN, &CYBSP_DEBUG_UART_CTS_config); + + Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); + + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); + + + + Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_B_PORT, CYBSP_LED5_RGB_B_PIN, &CYBSP_LED5_RGB_B_config); + + + + + + + + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..af252206f02 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h @@ -0,0 +1,621 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_WCO_IN_ENABLED 1U +#define CYBSP_WCO_IN_PORT GPIO_PRT0 +#define CYBSP_WCO_IN_PIN 0U +#define CYBSP_WCO_IN_NUM 0U +#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_WCO_OUT_ENABLED 1U +#define CYBSP_WCO_OUT_PORT GPIO_PRT0 +#define CYBSP_WCO_OUT_PIN 1U +#define CYBSP_WCO_OUT_NUM 1U +#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_SW2_ENABLED 1U +#define CYBSP_SW2_PORT GPIO_PRT0 +#define CYBSP_SW2_PIN 4U +#define CYBSP_SW2_NUM 4U +#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_LED5_RGB_G_ENABLED 1U +#define CYBSP_LED5_RGB_G_PORT GPIO_PRT0 +#define CYBSP_LED5_RGB_G_PIN 5U +#define CYBSP_LED5_RGB_G_NUM 5U +#define CYBSP_LED5_RGB_G_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED5_RGB_G_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_5_HSIOM + #define ioss_0_port_0_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED5_RGB_G_HSIOM ioss_0_port_0_pin_5_HSIOM +#define CYBSP_LED5_RGB_G_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_LED9_ENABLED 1U +#define CYBSP_LED9_PORT GPIO_PRT11 +#define CYBSP_LED9_PIN 1U +#define CYBSP_LED9_NUM 1U +#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED9_HSIOM ioss_0_port_11_pin_1_HSIOM +#define CYBSP_LED9_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_SS0_ENABLED 1U +#define CYBSP_QSPI_SS0_PORT GPIO_PRT11 +#define CYBSP_QSPI_SS0_PIN 2U +#define CYBSP_QSPI_SS0_NUM 2U +#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_DATA3_ENABLED 1U +#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11 +#define CYBSP_QSPI_DATA3_PIN 3U +#define CYBSP_QSPI_DATA3_NUM 3U +#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_DATA2_ENABLED 1U +#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11 +#define CYBSP_QSPI_DATA2_PIN 4U +#define CYBSP_QSPI_DATA2_NUM 4U +#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_DATA1_ENABLED 1U +#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11 +#define CYBSP_QSPI_DATA1_PIN 5U +#define CYBSP_QSPI_DATA1_NUM 5U +#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_DATA0_ENABLED 1U +#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11 +#define CYBSP_QSPI_DATA0_PIN 6U +#define CYBSP_QSPI_DATA0_NUM 6U +#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U +#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define CYBSP_QSPI_SPI_CLOCK_PIN 7U +#define CYBSP_QSPI_SPI_CLOCK_NUM 7U +#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_CSD_TX_ENABLED 1U +#define CYBSP_CSD_TX_PORT GPIO_PRT1 +#define CYBSP_CSD_TX_PIN 0U +#define CYBSP_CSD_TX_NUM 0U +#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_LED5_RGB_R_ENABLED 1U +#define CYBSP_LED5_RGB_R_PORT GPIO_PRT1 +#define CYBSP_LED5_RGB_R_PIN 1U +#define CYBSP_LED5_RGB_R_NUM 1U +#define CYBSP_LED5_RGB_R_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED5_RGB_R_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED5_RGB_R_HSIOM ioss_0_port_1_pin_1_HSIOM +#define CYBSP_LED5_RGB_R_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_SW4_ENABLED 1U +#define CYBSP_SW4_PORT GPIO_PRT1 +#define CYBSP_SW4_PIN 4U +#define CYBSP_SW4_NUM 4U +#define CYBSP_SW4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_SW4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_4_HSIOM + #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW4_HSIOM ioss_0_port_1_pin_4_HSIOM +#define CYBSP_SW4_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_LED8_ENABLED 1U +#define CYBSP_LED8_PORT GPIO_PRT1 +#define CYBSP_LED8_PIN 5U +#define CYBSP_LED8_NUM 5U +#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_SDHC0_DAT0_ENABLED 1U +#define CYBSP_SDHC0_DAT0_PORT GPIO_PRT2 +#define CYBSP_SDHC0_DAT0_PIN 0U +#define CYBSP_SDHC0_DAT0_NUM 0U +#define CYBSP_SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_DAT0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM +#define CYBSP_SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_SDHC0_DAT1_ENABLED 1U +#define CYBSP_SDHC0_DAT1_PORT GPIO_PRT2 +#define CYBSP_SDHC0_DAT1_PIN 1U +#define CYBSP_SDHC0_DAT1_NUM 1U +#define CYBSP_SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_DAT1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_1_HSIOM + #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM +#define CYBSP_SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_SDHC0_DAT2_ENABLED 1U +#define CYBSP_SDHC0_DAT2_PORT GPIO_PRT2 +#define CYBSP_SDHC0_DAT2_PIN 2U +#define CYBSP_SDHC0_DAT2_NUM 2U +#define CYBSP_SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_DAT2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_2_HSIOM + #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM +#define CYBSP_SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_SDHC0_DAT3_ENABLED 1U +#define CYBSP_SDHC0_DAT3_PORT GPIO_PRT2 +#define CYBSP_SDHC0_DAT3_PIN 3U +#define CYBSP_SDHC0_DAT3_NUM 3U +#define CYBSP_SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_DAT3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_3_HSIOM + #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM +#define CYBSP_SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_SDHC0_CMD_ENABLED 1U +#define CYBSP_SDHC0_CMD_PORT GPIO_PRT2 +#define CYBSP_SDHC0_CMD_PIN 4U +#define CYBSP_SDHC0_CMD_NUM 4U +#define CYBSP_SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_4_HSIOM + #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM +#define CYBSP_SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_SDHC0_CLK_ENABLED 1U +#define CYBSP_SDHC0_CLK_PORT GPIO_PRT2 +#define CYBSP_SDHC0_CLK_PIN 5U +#define CYBSP_SDHC0_CLK_NUM 5U +#define CYBSP_SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_SDHC0_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_5_HSIOM + #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM +#define CYBSP_SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn +#define CYBSP_BT_UART_RX_ENABLED 1U +#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 +#define CYBSP_BT_UART_RX_PIN 0U +#define CYBSP_BT_UART_RX_NUM 0U +#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM +#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_UART_TX_ENABLED 1U +#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 +#define CYBSP_BT_UART_TX_PIN 1U +#define CYBSP_BT_UART_TX_NUM 1U +#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM +#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_UART_RTS_ENABLED 1U +#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 +#define CYBSP_BT_UART_RTS_PIN 2U +#define CYBSP_BT_UART_RTS_NUM 2U +#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_2_HSIOM + #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM +#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_UART_CTS_ENABLED 1U +#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 +#define CYBSP_BT_UART_CTS_PIN 3U +#define CYBSP_BT_UART_CTS_NUM 3U +#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_3_HSIOM + #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM +#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_POWER_ENABLED 1U +#define CYBSP_BT_POWER_PORT GPIO_PRT3 +#define CYBSP_BT_POWER_PIN 4U +#define CYBSP_BT_POWER_NUM 4U +#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF +#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_4_HSIOM + #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM +#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_HOST_WAKE_ENABLED 1U +#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3 +#define CYBSP_BT_HOST_WAKE_PIN 5U +#define CYBSP_BT_HOST_WAKE_NUM 5U +#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_3_pin_5_HSIOM + #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM +#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn +#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U +#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4 +#define CYBSP_BT_DEVICE_WAKE_PIN 0U +#define CYBSP_BT_DEVICE_WAKE_NUM 0U +#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM +#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#define CYBSP_DEBUG_UART_RX_ENABLED 1U +#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5 +#define CYBSP_DEBUG_UART_RX_PIN 0U +#define CYBSP_DEBUG_UART_RX_NUM 0U +#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_0_HSIOM + #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM +#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_DEBUG_UART_TX_ENABLED 1U +#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5 +#define CYBSP_DEBUG_UART_TX_PIN 1U +#define CYBSP_DEBUG_UART_TX_NUM 1U +#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_DEBUG_UART_RTS_ENABLED 1U +#define CYBSP_DEBUG_UART_RTS_PORT GPIO_PRT5 +#define CYBSP_DEBUG_UART_RTS_PIN 2U +#define CYBSP_DEBUG_UART_RTS_NUM 2U +#define CYBSP_DEBUG_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_DEBUG_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_2_HSIOM + #define ioss_0_port_5_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_RTS_HSIOM ioss_0_port_5_pin_2_HSIOM +#define CYBSP_DEBUG_UART_RTS_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_DEBUG_UART_CTS_ENABLED 1U +#define CYBSP_DEBUG_UART_CTS_PORT GPIO_PRT5 +#define CYBSP_DEBUG_UART_CTS_PIN 3U +#define CYBSP_DEBUG_UART_CTS_NUM 3U +#define CYBSP_DEBUG_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_DEBUG_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_3_HSIOM + #define ioss_0_port_5_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_DEBUG_UART_CTS_HSIOM ioss_0_port_5_pin_3_HSIOM +#define CYBSP_DEBUG_UART_CTS_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_EZI2C_SCL_ENABLED 1U +#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 +#define CYBSP_EZI2C_SCL_PIN 0U +#define CYBSP_EZI2C_SCL_NUM 0U +#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_EZI2C_SDA_ENABLED 1U +#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 +#define CYBSP_EZI2C_SDA_PIN 1U +#define CYBSP_EZI2C_SDA_NUM 1U +#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT6 +#define CYBSP_SWDCK_PIN 7U +#define CYBSP_SWDCK_NUM 7U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_CINA_ENABLED 1U +#define CYBSP_CINA_PORT GPIO_PRT7 +#define CYBSP_CINA_PIN 1U +#define CYBSP_CINA_NUM 1U +#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_CINB_ENABLED 1U +#define CYBSP_CINB_PORT GPIO_PRT7 +#define CYBSP_CINB_PIN 2U +#define CYBSP_CINB_NUM 2U +#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_LED5_RGB_B_ENABLED 1U +#define CYBSP_LED5_RGB_B_PORT GPIO_PRT7 +#define CYBSP_LED5_RGB_B_PIN 3U +#define CYBSP_LED5_RGB_B_NUM 3U +#define CYBSP_LED5_RGB_B_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED5_RGB_B_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_3_HSIOM + #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED5_RGB_B_HSIOM ioss_0_port_7_pin_3_HSIOM +#define CYBSP_LED5_RGB_B_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_CMOD_ENABLED 1U +#define CYBSP_CMOD_PORT GPIO_PRT7 +#define CYBSP_CMOD_PIN 7U +#define CYBSP_CMOD_NUM 7U +#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CYBSP_CSD_BTN0_ENABLED 1U +#define CYBSP_CSD_BTN0_PORT GPIO_PRT8 +#define CYBSP_CSD_BTN0_PIN 1U +#define CYBSP_CSD_BTN0_NUM 1U +#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_BTN1_ENABLED 1U +#define CYBSP_CSD_BTN1_PORT GPIO_PRT8 +#define CYBSP_CSD_BTN1_PIN 2U +#define CYBSP_CSD_BTN1_NUM 2U +#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_SLD0_ENABLED 1U +#define CYBSP_CSD_SLD0_PORT GPIO_PRT8 +#define CYBSP_CSD_SLD0_PIN 3U +#define CYBSP_CSD_SLD0_NUM 3U +#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_SLD1_ENABLED 1U +#define CYBSP_CSD_SLD1_PORT GPIO_PRT8 +#define CYBSP_CSD_SLD1_PIN 4U +#define CYBSP_CSD_SLD1_NUM 4U +#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_SLD2_ENABLED 1U +#define CYBSP_CSD_SLD2_PORT GPIO_PRT8 +#define CYBSP_CSD_SLD2_PIN 5U +#define CYBSP_CSD_SLD2_NUM 5U +#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_SLD3_ENABLED 1U +#define CYBSP_CSD_SLD3_PORT GPIO_PRT8 +#define CYBSP_CSD_SLD3_PIN 6U +#define CYBSP_CSD_SLD3_NUM 6U +#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CSD_SLD4_ENABLED 1U +#define CYBSP_CSD_SLD4_PORT GPIO_PRT8 +#define CYBSP_CSD_SLD4_PIN 7U +#define CYBSP_CSD_SLD4_NUM 7U +#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn + +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SW4_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..0d3609cfc2f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,265 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xEBU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xD8U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x38U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x00040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x00000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 520U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 134000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 340U +}; + +const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x10000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { + &S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..846f62c018a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,50 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_DEVICE_NUM 1 + +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CY_SMIF_MEMCONFIG_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.c new file mode 100644 index 00000000000..ae79008829d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.c @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +#include "cy_device_headers.h" + +void init_cycfg_routing(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..d69bf20d16f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN +#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00 +#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01 +#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02 +#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03 +#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD +#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD +#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX +#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX +#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS +#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS +#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_5_pin_2_HSIOM P5_2_SCB5_UART_RTS +#define ioss_0_port_5_pin_3_HSIOM P5_3_SCB5_UART_CTS +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..d2a75240e61 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c @@ -0,0 +1,464 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 144UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 36, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); +} +__STATIC_INLINE void Cy_SysClk_ClkHf4Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(1U); +} +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_ClkTimerInit() +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_system(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..92f9d43bc52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#include "cy_gpio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_altsystickclk_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define srss_0_clock_0_hfclk_4_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF4 4UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_timerclk_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U + +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg new file mode 100644 index 00000000000..a561643dcf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg @@ -0,0 +1,2 @@ +set SMIF_BANKS { +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h new file mode 100644 index 00000000000..f35b123cc29 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h @@ -0,0 +1,154 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" +#include "PortNames.h" +#include "cyhal_pin_package.h" +#include "cyhal_utils.h" + +typedef cyhal_gpio_t PinName; + +// Arduino connector namings +#define A0 P10_0 +#define A1 P10_1 +#define A2 P10_2 +#define A3 P10_3 +#define A4 P10_4 +#define A5 P10_5 + +#define D0 P5_0 +#define D1 P5_1 +#define D2 P5_2 +#define D3 P5_3 +#define D4 P5_4 +#define D5 P5_5 +#define D6 P5_6 +#define D7 P0_2 +#define D8 P13_0 +#define D9 P13_1 +#define D10 P12_3 +#define D11 P12_0 +#define D12 P12_1 +#define D13 P12_2 +#define D14 P6_1 +#define D15 P6_0 + + +// Generic signal names + +#define I2C_SCL P6_0 +#define I2C_SDA P6_1 + +#define UART_RX P5_0 +#define UART_TX P5_1 +#define UART_RTS P5_2 +#define UART_CTS P5_3 + +#define SPI_MOSI P12_0 +#define SPI_MISO P12_1 +#define SPI_CLK P12_2 +#define SPI_CS P12_4 + +#define UART_RX P5_0 +#define UART_TX P5_1 +#define UART_RTS P5_2 +#define UART_CTS P5_3 + +#define BT_UART_RX P3_0 +#define BT_UART_TX P3_1 +#define BT_UART_CTS P3_3 +#define BT_UART_RTS P3_2 + +#define BT_PIN_POWER P3_4 +#define BT_PIN_HOST_WAKE P3_5 +#define BT_PIN_DEVICE_WAKE P4_0 +// Reset pin unavailable + +#define SWITCH2 P0_4 +#define LED1 P13_7 +#define LED2 NC +#define LED3 NC +#define LED4 NC +#define LED_RED LED1 + +#define USER_BUTTON SWITCH2 +#define BUTTON1 USER_BUTTON + +#define PDM_DATA P10_5 +#define PDM_CLK P10_4 +#define THERM_OUT_1 P10_1 +#define THERM_OUT_2 P10_2 +#define THERM_OUT THERM_OUT_1 +#define THERM_VDD P10_3 +#define THERM_GND P10_0 + +#define CARD_DETECT_1 P13_5 +#define CARD_DETECT_2 P12_1 +#define CARD_DETECT CARD_DETECT_1 +#define SD_CMD P12_4 +#define SD_CLK P12_5 +#define SD_IO_0 P13_0 +#define SD_IO_1 P13_1 +#define SD_IO_2 P13_2 +#define SD_IO_3 P13_3 + +#define QSPI_CLK P11_7 +#define QSPI_IO_0 P11_6 +#define QSPI_IO_1 P11_5 +#define QSPI_IO_2 P11_4 +#define QSPI_IO_3 P11_3 +#define QSPI_SEL P11_2 + +#define QSPI_FLASH1_IO0 QSPI_IO_0 +#define QSPI_FLASH1_IO1 QSPI_IO_1 +#define QSPI_FLASH1_IO2 QSPI_IO_2 +#define QSPI_FLASH1_IO3 QSPI_IO_3 +#define QSPI_FLASH1_SCK QSPI_CLK +#define QSPI_FLASH1_CSN QSPI_SEL + +// Standardized interfaces names +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART_CTS UART_CTS +#define STDIO_UART_RTS UART_RTS + +#define CY_STDIO_UART_RX STDIO_UART_RX +#define CY_STDIO_UART_TX STDIO_UART_TX +#define CY_STDIO_UART_CTS STDIO_UART_CTS +#define CY_STDIO_UART_RTS STDIO_UART_RTS + +#define CY_BT_UART_RX BT_UART_RX +#define CY_BT_UART_TX BT_UART_TX +#define CY_BT_UART_CTS BT_UART_CTS +#define CY_BT_UART_RTS BT_UART_RTS + +#define CY_BT_PIN_POWER BT_PIN_POWER +#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE +#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE + +#define USBTX UART_TX +#define USBRX UART_RX + +#define CY_WIFI_HOST_WAKE P2_7 + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.c new file mode 100644 index 00000000000..d121e3fec48 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.c @@ -0,0 +1,67 @@ +/***************************************************************************//** +* \file CY8CKIT-062S2-43012/cybsp_cy8ckit_062s2_43012.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062S2-43012 pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp_cy8ckit_062s2_43012.h" +#include "cyhal_utils.h" +#include "cyhal_implementation.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + + init_cycfg_system(); + +#ifndef __MBED__ + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + result |= cybsp_led_init(CYBSP_USER_LED3); + result |= cybsp_led_init(CYBSP_USER_LED4); + result |= cybsp_led_init(CYBSP_USER_LED5); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + result |= cybsp_btn_init(CYBSP_USER_BTN2); + + CY_ASSERT(CY_RSLT_SUCCESS == result); + + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.h new file mode 100644 index 00000000000..575831ee1d7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.h @@ -0,0 +1,74 @@ +/***************************************************************************//** +* \file CY8CKIT-062S2-43012/cybsp_cy8ckit_062s2_43012.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062S2-43012 pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012 +* \ingroup group_bsp +* \{ +* The CY8CKIT-062S2-43012 PSoC 6 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs. +* It comes with a Murata LBEE5KL1DX module, based on the CYW43012 combo device, industry-leading CapSense for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. This kit is designed with a snap-away form-factor, allowing the user to separate the different components and features that come with this kit and use independently. +* In addition, support for Digilent's Pmod interface is also provided with this kit. +* +*
Kit Features:
+*
    +*
  • Support of up to 2MB Flash and 1MB SRAM
    • +*
  • Dedicated SDHC to interface with WICED wireless devices.
    • +*
  • Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ as the secondary processor for low-power operations.
    • +*
  • Supports Full-Speed USB, capacitive-sensing with CapSense, a PDM-PCM digital microphone interface, a Quad-SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.
    • +*
+* +*
Kit Contents:
+*
    +*
  • PSoC 6 Wi-Fi BT Pioneer Board
    • +*
  • USB Type-A to Micro-B cable
    • +*
  • Quick Start Guide
    • +*
+* +* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros +* \defgroup group_bsp_cy8ckit_062s2_43012_functions Functions +* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types +*/ + + +#pragma once + +#include "cybsp_api_core.h" +#ifdef __MBED__ +#include "cybsp_api_wifi.h" +#else +#include "cybsp_retarget.h" +#include "cybsp_serial_flash.h" +#endif /* __MBED__ */ + +#if defined(__cplusplus) +extern "C" { +#endif + + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062s2_43012 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h new file mode 100644 index 00000000000..395e75bd254 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h @@ -0,0 +1,274 @@ +/***************************************************************************//** +* \file CY8CKIT-062S2-43012/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062S2-43012 kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012 +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros +* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_bsp_cy8ckit_062s2_43012_macros +* \{ +*/ + +// Arduino connector namings +/** Arduino A0 */ +#define CYBSP_A0 P10_0 +/** Arduino A1 */ +#define CYBSP_A1 P10_1 +/** Arduino A2 */ +#define CYBSP_A2 P10_2 +/** Arduino A3 */ +#define CYBSP_A3 P10_3 +/** Arduino A4 */ +#define CYBSP_A4 P10_4 +/** Arduino A5 */ +#define CYBSP_A5 P10_5 +/** Arduino D0 */ +#define CYBSP_D0 P5_0 +/** Arduino D1 */ +#define CYBSP_D1 P5_1 +/** Arduino D2 */ +#define CYBSP_D2 P5_2 +/** Arduino D3 */ +#define CYBSP_D3 P5_3 +/** Arduino D4 */ +#define CYBSP_D4 P5_4 +/** Arduino D5 */ +#define CYBSP_D5 P5_5 +/** Arduino D6 */ +#define CYBSP_D6 P5_6 +/** Arduino D7 */ +#define CYBSP_D7 P0_2 +/** Arduino D8 */ +#define CYBSP_D8 P13_0 +/** Arduino D9 */ +#define CYBSP_D9 P13_1 +/** Arduino D10 */ +#define CYBSP_D10 P12_3 +/** Arduino D11 */ +#define CYBSP_D11 P12_0 +/** Arduino D12 */ +#define CYBSP_D12 P12_1 +/** Arduino D13 */ +#define CYBSP_D13 P12_2 +/** Arduino D14 */ +#define CYBSP_D14 P6_1 +/** Arduino D15 */ +#define CYBSP_D15 P6_0 + + +/** Pin: WCO input */ +#define CYBSP_WCO_IN P0_0 +/** Pin: WCO output */ +#define CYBSP_WCO_OUT P0_1 + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 P2_0 +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 P2_1 +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 P2_2 +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 P2_3 +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD P2_4 +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK P2_5 +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON P2_6 +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE P4_1 + +/** Pin: BT UART RX */ +#define CYBSP_BT_UART_RX P3_0 +/** Pin: BT UART TX */ +#define CYBSP_BT_UART_TX P3_1 +/** Pin: BT UART RTS */ +#define CYBSP_BT_UART_RTS P3_2 +/** Pin: BT UART CTS */ +#define CYBSP_BT_UART_CTS P3_3 +/** Pin: BT Power */ +#define CYBSP_BT_POWER P3_4 +/** Pin: BT Host Wakeup */ +#define CYBSP_BT_HOST_WAKE P3_5 +/** Pin: BT Device Wakeup */ +#define CYBSP_BT_DEVICE_WAKE P4_0 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RTS P5_2 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_CTS P5_3 + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL P6_0 +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA P6_1 + +/** Pin: SWO */ +#define CYBSP_SWO P6_4 +/** Pin: SWDIO */ +#define CYBSP_SWDIO P6_6 +/** Pin: SWDCK */ +#define CYBSP_SWDCK P6_7 + +/** Pin: CapSesnse TX */ +#define CYBSP_CSD_TX P1_0 +/** Pin: CapSesnse CINA */ +#define CYBSP_CINA P7_1 +/** Pin: CapSesnse CINB */ +#define CYBSP_CINB P7_2 +/** Pin: CapSesnse CMOD */ +#define CYBSP_CMOD P7_7 +/** Pin: CapSesnse Button 0 */ +#define CYBSP_CSD_BTN0 P8_1 +/** Pin: CapSesnse Button 1 */ +#define CYBSP_CSD_BTN1 P8_2 +/** Pin: CapSesnse Slider 0 */ +#define CYBSP_CSD_SLD0 P8_3 +/** Pin: CapSesnse Slider 1 */ +#define CYBSP_CSD_SLD1 P8_4 +/** Pin: CapSesnse Slider 2 */ +#define CYBSP_CSD_SLD2 P8_5 +/** Pin: CapSesnse Slider 3 */ +#define CYBSP_CSD_SLD3 P8_6 +/** Pin: CapSesnse Slider 4 */ +#define CYBSP_CSD_SLD4 P8_7 + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS P11_2 +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 P11_3 +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 P11_4 +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 P11_5 +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 P11_6 +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK P11_7 + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE + +/** BSP user LED reference designator to pin mapping */ +#define LED9_R P11_1 +/** BSP user LED reference designator to pin mapping */ +#define LED8_O P1_5 +/** BSP user LED reference designator to pin mapping */ +#define LED5_RGB_R P1_1 +/** BSP user LED reference designator to pin mapping */ +#define LED5_RGB_G P0_5 +/** BSP user LED reference designator to pin mapping */ +#define LED5_RGB_B P7_3 + +/** BSP LED defines by LED color */ +#define CYBSP_LED_RED LED5_RGB_R +/** BSP LED defines by LED color */ +#define CYBSP_LED_GREEN LED5_RGB_G +/** BSP LED defines by LED color */ +#define CYBSP_LED_BLUE LED5_RGB_B +/** BSP LED defines by LED color */ +#define CYBSP_LED_ORANGE LED8 + + +/** BSP user button reference designator to pin mapping */ +#define SW2 P0_4 +/** BSP user button reference designator to pin mapping */ +#define SW4 P1_4 + + +/** \} group_bsp_cy8ckit_062s2_43012_macros */ + +/** +* \addtogroup group_bsp_cy8ckit_062s2_43012_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + + +/** Enum defining the different user LEDs available on the board. */ +typedef enum +{ + CYBSP_LED_RGB_RED = LED5_RGB_R, + CYBSP_LED_RGB_GREEN = LED5_RGB_G, + CYBSP_LED_RGB_BLUE = LED5_RGB_B, + + CYBSP_USER_LED1 = LED9_R, + CYBSP_USER_LED2 = LED8_O, + CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, + CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, + CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, + CYBSP_USER_LED = CYBSP_USER_LED1, +} cybsp_led_t; + + +/** Enum defining the different user buttons available on the board. */ +typedef enum +{ + CYBSP_USER_BTN1 = SW2, + CYBSP_USER_BTN2 = SW4, + CYBSP_USER_BTN = CYBSP_USER_BTN1, +} cybsp_btn_t; + + +/** \} group_bsp_cy8ckit_062s2_43012_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062s2_43012 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus new file mode 100644 index 00000000000..dade5c7a457 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus @@ -0,0 +1,951 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralNames.h new file mode 100644 index 00000000000..bbb6aa1e86a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralNames.h @@ -0,0 +1,124 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)SCB0_BASE, + UART_1 = (int)SCB1_BASE, + UART_2 = (int)SCB2_BASE, + UART_3 = (int)SCB3_BASE, + UART_4 = (int)SCB4_BASE, + UART_5 = (int)SCB5_BASE, + UART_6 = (int)SCB6_BASE, + UART_7 = (int)SCB7_BASE, + /* SCB_8 does not support UART mode */ + UART_9 = (int)SCB9_BASE, + UART_10 = (int)SCB10_BASE, + UART_11 = (int)SCB11_BASE, + UART_12 = (int)SCB12_BASE, +} UARTName; + +#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES + +typedef enum { + SPI_0 = (int)SCB0_BASE, + SPI_1 = (int)SCB1_BASE, + SPI_2 = (int)SCB2_BASE, + SPI_3 = (int)SCB3_BASE, + SPI_4 = (int)SCB4_BASE, + SPI_5 = (int)SCB5_BASE, + SPI_6 = (int)SCB6_BASE, + SPI_7 = (int)SCB7_BASE, + SPI_8 = (int)SCB8_BASE, + /* SCB_9 - SCB_12 does not support SPI mode */ +} SPIName; + +typedef enum { + I2C_0 = (int)SCB0_BASE, + I2C_1 = (int)SCB1_BASE, + I2C_2 = (int)SCB2_BASE, + I2C_3 = (int)SCB3_BASE, + I2C_4 = (int)SCB4_BASE, + I2C_5 = (int)SCB5_BASE, + I2C_6 = (int)SCB6_BASE, + I2C_7 = (int)SCB7_BASE, + I2C_8 = (int)SCB8_BASE, + I2C_9 = (int)SCB9_BASE, + I2C_10 = (int)SCB10_BASE, + I2C_11 = (int)SCB11_BASE, + I2C_12 = (int)SCB12_BASE, +} I2CName; + +typedef enum { + PWM_32b_0 = TCPWM0_BASE, + PWM_32b_1, + PWM_32b_2, + PWM_32b_3, + PWM_32b_4, + PWM_32b_5, + PWM_32b_6, + PWM_32b_7, + PWM_16b_0 = TCPWM1_BASE, + PWM_16b_1, + PWM_16b_2, + PWM_16b_3, + PWM_16b_4, + PWM_16b_5, + PWM_16b_6, + PWM_16b_7, + PWM_16b_8, + PWM_16b_9, + PWM_16b_10, + PWM_16b_11, + PWM_16b_12, + PWM_16b_13, + PWM_16b_14, + PWM_16b_15, + PWM_16b_16, + PWM_16b_17, + PWM_16b_18, + PWM_16b_19, + PWM_16b_20, + PWM_16b_21, + PWM_16b_22, + PWM_16b_23, +} PWMName; + +typedef enum { + ADC_0 = (int)SAR_BASE, +} ADCName; + +typedef enum { + QSPI_0, +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c new file mode 100644 index 00000000000..b6c226f5327 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c @@ -0,0 +1,493 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, + {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, + {P2_4, UART_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)}, + {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)}, + {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P5_4, UART_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, + {P8_4, UART_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, + {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, + {P13_4, UART_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, + {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, + {P2_5, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)}, + {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)}, + {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P5_5, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, + {P8_5, UART_11, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB11_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, + {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, + {P13_5, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)}, + {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, + {P2_6, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)}, + {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P5_6, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, + {P8_6, UART_11, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB11_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, + {P13_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)}, + {P13_6, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)}, + {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, + {P2_7, UART_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)}, + {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P5_7, UART_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, + {P8_7, UART_11, CYHAL_PIN_IN_FUNCTION(P8_7_SCB11_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, + {P13_3, UART_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)}, + {P13_7, UART_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, + {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, + {P2_4, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)}, + {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)}, + {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, + {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, + {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, + {P13_4, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, + {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, + {P2_5, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)}, + {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)}, + {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, + {P8_5, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_5_SCB11_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, + {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, + {P13_5, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, + {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, + {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)}, + {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, + {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, + {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, + {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)}, + {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, + {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)}, + {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, + {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, + {P13_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)}, + {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, + {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, + {P13_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, + {P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)}, + {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, + {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, + {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, + {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, + {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, + {P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)}, + {P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)}, + {P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)}, + {P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)}, + {P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)}, + {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, + {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, + {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, + {P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, + {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, + {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, + {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, + {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, + {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, + {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, + {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, + {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, + {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, + {P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)}, + {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, + {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, + {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, + {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, + {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, + {P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)}, + {P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)}, + {P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)}, + {P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, + {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, + {P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, + {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, + {P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)}, + {P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, + {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, + {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, + {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, + {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, + {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, + {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, + {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, + {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, + {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, + {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, + {P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)}, + {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, + {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, + {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, + {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, + {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, + {P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)}, + {P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)}, + {P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)}, + {P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)}, + //{P4_2, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P4_2_TCPWM0_LINE6)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)}, + {P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)}, + {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, + {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, + {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, + {P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, + {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, + {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, + {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, + {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, + {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, + {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, + {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, + {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, + {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, + {P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)}, + {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, + {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, + {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, + {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, + {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, + {P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)}, + {P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)}, + {P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)}, + {P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)}, + //{P4_3, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P4_3_TCPWM0_LINE_COMPL6)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, + {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, + {P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, + {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, + {P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)}, + {P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, + {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, + {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, + {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, + {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, + {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, + {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, + {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, + {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, + {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, + {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus + {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus + {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus + {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus + {P9_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_5 pin through the AMUXA bus + {P9_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_6 pin through the AMUXA bus + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin + {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_QSPI +const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 + {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0} +}; + +const PinMap PinMap_QSPI_SSEL[] = { + {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA0[] = { + {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA1[] = { + {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA2[] = { + {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA3[] = { + {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, + }; +#endif // DEVICE_QSPI + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct new file mode 100644 index 00000000000..e39ef20f7cd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -0,0 +1,308 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.50 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START 0x08047600 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 00000000000..c1a7ad8ed4f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,218 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$Base| +__Vectors DCD |Image$$ARM_LIB_STACK$$Base| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld new file mode 100644 index 00000000000..ca0a58be38f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -0,0 +1,468 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm0plus.ld +* \version 2.50 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START 0x08047600 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 00000000000..3fed47b01f1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,367 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf new file mode 100644 index 00000000000..bd95799b077 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -0,0 +1,287 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm0plus.icf +* \version 2.50 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = 0x08047600; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S new file mode 100644 index 00000000000..3b77acffe37 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S @@ -0,0 +1,317 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c new file mode 100644 index 00000000000..010eac6188e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c @@ -0,0 +1,710 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.50 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) + { + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; + } +#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + CY_SECTION(".cy_sharedmem") + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 00000000000..f684a0cb0e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.50 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00200000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000FD800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Size and start address of the Cortex-M0+ application image +#define FLASH_CM0P_SIZE 0x2000 +#define FLASH_CM0P_START FLASH_START + +; Size and start address of the Cortex-M4 application image +#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE) +#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE) + + +; Cortex-M0+ application image +LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application image +LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..ed6da9fd49c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,706 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$Base| +__Vectors DCD |Image$$ARM_LIB_STACK$$Base| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 00000000000..d1e01ff2bfa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,464 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.50 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00200000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000FD800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Size and start address of the Cortex-M0+ application image */ +FLASH_CM0P_SIZE = 0x2000; +FLASH_CM0P_START = ORIGIN(flash); +/* Size and start address of the Cortex-M4 application image */ +FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE; +FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE; + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application image */ + .cy_m0p_image FLASH_CM0P_START : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Cortex-M4 application image */ + .text FLASH_CM4_START : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..1ebcac39f8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 00000000000..2ee6f7c67d1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,279 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.icf +* \version 2.50 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00200000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x000FD800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application image */ +place in IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..ade874af4d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -0,0 +1,1267 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c new file mode 100644 index 00000000000..a5408385ee6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.50 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h new file mode 100644 index 00000000000..53bc71262c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h @@ -0,0 +1,675 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.50 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h new file mode 100644 index 00000000000..ab0c1c0cb58 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h @@ -0,0 +1,132 @@ +/* + * $ Copyright Cypress Semiconductor $ + */ + +#ifndef INCLUDED_NVRAM_IMAGE_H_ +#define INCLUDED_NVRAM_IMAGE_H_ + +#include +#include +#include "generated_mac_address.txt" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Character array of NVRAM image generated from + * cyw943012csp_ty1LV.TXT + */ +static const char wifi_nvram_image[] = + "NVRAMRev=$Rev: 351687 $" "\x00" + "sromrev=11" "\x00" + "cckdigfilttype=4" "\x00" + "cckpwroffset0=3" "\x00" + "bphyscale=0x20" "\x00" + "boardflags3=0x40000100" "\x00" + "vendid=0x14e4" "\x00" + "devid=0xA804" "\x00" + "manfid=0x2d0" "\x00" + "prodid=0x052e" "\x00" + NVRAM_GENERATED_MAC_ADDRESS "\x00" + "mac_clkgating=1" "\x00" + "nocrc=1" "\x00" + "boardtype=0x0842" "\x00" + "boardrev=0x1100" "\x00" + "xtalfreq=37400" "\x00" + "boardflags2=0xc0000000" "\x00" + "boardflags=0x00000000" "\x00" + "etmode=0x11" "\x00" + "extpagain2g=2" "\x00" + "extpagain5g=2" "\x00" + "ccode=0" "\x00" + "regrev=0" "\x00" + "antswitch = 0" "\x00" + "rxgains2gelnagaina0=0" "\x00" + "rxgains2gtrisoa0=15" "\x00" + "rxgains2gtrelnabypa0=0" "\x00" + "rxgains5gelnagaina0=0" "\x00" + "rxgains5gtrisoa0=9" "\x00" + "rxgains5gtrelnabypa0=0" "\x00" + "pdgain5g=0" "\x00" + "pdgain2g=0" "\x00" + "tworangetssi2g=0" "\x00" + "tworangetssi5g=0" "\x00" + "rxchain=1" "\x00" + "txchain=1" "\x00" + "aa2g=1" "\x00" + "aa5g=1" "\x00" + "tssipos5g=0" "\x00" + "tssipos2g=0" "\x00" + "femctrl=17" "\x00" + "subband5gver=4" "\x00" + "pa2ga0=-108,5627,-638" "\x00" + "pa5ga0=-41,6533,-726,-29,6654,-746,9,6914,-772,12,7008,-806" "\x00" + "pdoffset40ma0=0" "\x00" + "pdoffset80ma0=0" "\x00" + "lowpowerrange2g=0" "\x00" + "lowpowerrange5g=0" "\x00" + "ed_thresh2g=-63" "\x00" + "ed_thresh5g=-63" "\x00" + "swctrlmap_2g=0x10101010,0x20202020,0x10101010,0x414040,0x3ff" "\x00" + "swctrlmapext_2g=0x00000000,0x01000100,0x01000100,0x010000,0x301" "\x00" + "swctrlmap_5g=0x80808080,0x00000000,0x80808080,0x404040,0x3ff" "\x00" + "swctrlmapext_5g=0x01000100,0x01000100,0x00000000,0x000100,0x303" "\x00" + "ulpnap=0" "\x00" + "ulpadc=1" "\x00" + "ssagc_en=0" "\x00" + "ds1_nap=0" "\x00" + "spurcan_ch_list_MHz=2422,2427,2432,2437,2462,2467,2472" "\x00" + "spurcan_sp_freq_KHz=9000,4000,-1000,-6000,6400,1400,-3600" "\x00" + "spurcan_NumSpur=7" "\x00" + "epacal2g=0" "\x00" + "epacal5g=0" "\x00" + "papdcck=0" "\x00" + "epacal2g_mask=0x3fff" "\x00" + "maxp2ga0=82" "\x00" + "ofdmlrbw202gpo=0x0077" "\x00" + "dot11agofdmhrbw202gpo=0x8888" "\x00" + "mcsbw202gpo=0x99999999" "\x00" + "maxp5ga0=82,82,82,82" "\x00" + "mcsbw205glpo=0x99999999" "\x00" + "mcsbw205gmpo=0x99999999" "\x00" + "mcsbw205ghpo=0x99999999" "\x00" + "femctrlwar=0" "\x00" + "use5gpllfor2g=1" "\x00" + "pt5db_gaintbl=0" "\x00" + "txwbpapden=1" "\x00" + "wb_rxattn=0x0303" "\x00" + "wb_txattn=0x0203" "\x00" + "wb_papdcalidx=0x0808" "\x00" + "wb_papdcalidx_5g=0x00101010" "\x00" + "wb_eps_offset=0x01ba01a8" "\x00" + "wb_eps_offset_5g=0x01ba01bc" "\x00" + "wb_bbmult=0x2040" "\x00" + "wb_bbmult_5g=0x00303030" "\x00" + "wb_calref_db=0x1c2e" "\x00" + "wb_tia_gain_mode=0x0606" "\x00" + "wb_txbuf_offset=0x1e1e" "\x00" + "wb_frac_del=0x6991" "\x00" + "wb_g_frac_bits=0xab" "\x00" + "nb_rxattn=0x0404" "\x00" + "nb_txattn=0x0404" "\x00" + "nb_papdcalidx=0x1414" "\x00" + "nb_eps_offset=0x01d701d7" "\x00" + "nb_bbmult=0x5A5A" "\x00" + "nb_tia_gain_mode=0x0000" "\x00" + "AvVmid_c0=6,100,7,70,7,70,7,70,7,70" "\x00" + "tssisleep_en=0x5" "\x00" + "lpflags=0x28" "\x00" + "lpo_select=4" "\x00" + "paprrmcsgamma2g=450,500,550,600,675,950,950,950,950,950,950,950" "\x00" + "paprrmcsgamma5g20=450,500,550,600,800,950,1100,1100,1100,1100,1100,1100" "\x00" + "\x00\x00"; +#ifdef __cplusplus +} /*extern "C" */ +#endif + +#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ +#error Wi-Fi NVRAM image included twice +#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c index f6a59217502..7c57d780fec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c @@ -60,9 +60,16 @@ void gpio_mode(gpio_t *obj, PinMode mode) } } -void gpio_dir(MBED_UNUSED gpio_t *obj, MBED_UNUSED PinDirection direction) +void gpio_dir(gpio_t *obj, PinDirection direction) { - // mbed reads from input buffer instead of DR even for output pins so always leave input buffer enabled + if (direction == PIN_INPUT) { + cyhal_gpio_direction(obj->pin, CYHAL_GPIO_DIR_INPUT); + gpio_mode(obj, CYHAL_GPIO_DRIVE_ANALOG); + } else if (direction == PIN_OUTPUT) { + // mbed reads from input buffer instead of DR even for output pins so always leave input buffer enabled + cyhal_gpio_direction(obj->pin, CYHAL_GPIO_DIR_BIDIRECTIONAL); + gpio_mode(obj, CYHAL_GPIO_DRIVE_STRONG); + } } #ifdef __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c index 55830784f71..7ef30bb7de0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c @@ -17,6 +17,8 @@ #include "i2c_api.h" #include "cyhal_i2c.h" +#include "cyhal_utils.h" +#include "cyhal_hwmgr.h" #include "mbed_error.h" #include "mbed_assert.h" #include "mbed_critical.h" @@ -84,12 +86,24 @@ static void cy_i2c_event_handler(void *handler_arg, cyhal_i2c_irq_event_t event) void i2c_init(i2c_t *obj, PinName sda, PinName scl) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_init(&(i2c->hal_i2c), sda, scl, NULL)) { + cy_rslt_t result = cyhal_i2c_init(&(i2c->hal_i2c), sda, scl, NULL); + if (result == CYHAL_HWMGR_RSLT_ERR_INUSE) { + // MBED I2C driver currently does not support free, so we will allow I2C to be reallocated. + // TODO: once the the I2C driver properly supports free, this need to be fixed so that clocks and pins are no longer leaked. + cyhal_hwmgr_free(&(i2c->hal_i2c.resource)); + cyhal_hwmgr_set_unconfigured(i2c->hal_i2c.resource.type, i2c->hal_i2c.resource.block_num, i2c->hal_i2c.resource.channel_num); + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda); + cyhal_hwmgr_free(&pin_rsc); + pin_rsc = cyhal_utils_get_gpio_resource(scl); + cyhal_hwmgr_free(&pin_rsc); + result = cyhal_i2c_init(&(i2c->hal_i2c), sda, scl, NULL); + } + if (CY_RSLT_SUCCESS != result) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_init"); } i2c->cfg.is_slave = false; i2c->cfg.address = 0; - i2c->cfg.frequencyhal_hz = 400; + i2c->cfg.frequencyhal_hz = 400000; i2c->async_handler = NULL; cyhal_i2c_register_irq(&(i2c->hal_i2c), &cy_i2c_event_handler, obj); cyhal_i2c_irq_enable(&(i2c->hal_i2c), (cyhal_i2c_irq_event_t)(CYHAL_I2C_SLAVE_READ_EVENT | CYHAL_I2C_SLAVE_WRITE_EVENT | CYHAL_I2C_SLAVE_ERR_EVENT | CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_ERR_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | CYHAL_I2C_MASTER_WR_CMPLT_EVENT), true); @@ -112,14 +126,17 @@ int i2c_start(i2c_t *obj) int i2c_stop(i2c_t *obj) { - // Not supported; start/stop is generated by i2c_read/i2c_write - return -1; + struct i2c_s *i2c = cy_get_i2c(obj); + if (i2c->hal_i2c.context.state != CY_SCB_I2C_IDLE) { + return Cy_SCB_I2C_MasterSendStop(i2c->hal_i2c.base, CY_I2C_DEFAULT_TIMEOUT, &(i2c->hal_i2c.context)); + } + return 0; } int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_master_recv(&(i2c->hal_i2c), address >> 1, (uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_master_read(&(i2c->hal_i2c), address >> 1, (uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { return (int)I2C_ERROR_NO_SLAVE; } return length; @@ -128,7 +145,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_master_send(&(i2c->hal_i2c), address >> 1, (const uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_master_write(&(i2c->hal_i2c), address >> 1, (const uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { return (int)I2C_ERROR_NO_SLAVE; } // NOTE: HAL does not report how many bytes were actually sent in case of early NAK @@ -153,7 +170,10 @@ int i2c_byte_read(i2c_t *obj, int last) int i2c_byte_write(i2c_t *obj, int data) { struct i2c_s *i2c = cy_get_i2c(obj); - cy_en_scb_i2c_status_t status = Cy_SCB_I2C_MasterWriteByte(i2c->hal_i2c.base, (uint8_t)data, CY_I2C_DEFAULT_TIMEOUT, &(i2c->hal_i2c.context)); + // If we have not yet written the address, the first byte being sent is the address. + cy_en_scb_i2c_status_t status = i2c->hal_i2c.context.state == CY_SCB_I2C_IDLE + ? Cy_SCB_I2C_MasterSendStart(i2c->hal_i2c.base, data >> 1, CY_SCB_I2C_WRITE_XFER, CY_I2C_DEFAULT_TIMEOUT, &(i2c->hal_i2c.context)) + : Cy_SCB_I2C_MasterWriteByte(i2c->hal_i2c.base, (uint8_t)data, CY_I2C_DEFAULT_TIMEOUT, &(i2c->hal_i2c.context)); switch (status) { case CY_SCB_I2C_MASTER_MANUAL_TIMEOUT: return 2; @@ -203,7 +223,7 @@ int i2c_slave_receive(i2c_t *obj) int i2c_slave_read(i2c_t *obj, char *data, int length) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_slave_recv(&(i2c->hal_i2c), (uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_slave_config_read_buff(&(i2c->hal_i2c), (uint8_t *)data, (uint16_t)length)) { return 0; } return 1; @@ -212,7 +232,7 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) int i2c_slave_write(i2c_t *obj, const char *data, int length) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_slave_send(&(i2c->hal_i2c), (const uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_slave_config_write_buff(&(i2c->hal_i2c), (const uint8_t *)data, (uint16_t)length)) { return 0; } return 1; @@ -239,8 +259,8 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, i2c->async_rx_size = rx_length; i2c->async_handler = (void (*)(void))handler; core_util_critical_section_exit(); - if (CY_RSLT_SUCCESS != cyhal_i2c_transfer_async(&(i2c->hal_i2c), tx, tx_length, rx, rx_length, address)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_transfer_async"); + if (CY_RSLT_SUCCESS != cyhal_i2c_master_transfer_async(&(i2c->hal_i2c), address, tx, tx_length, rx, rx_length)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_master_transfer_async"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c index b2363969a21..4a6e9a51451 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c @@ -112,7 +112,9 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) if (CY_RSLT_SUCCESS != cyhal_spi_init(&(spi->hal_spi), mosi, miso, sclk, ssel, NULL, (uint8_t)bits, hal_mode, slave != 0)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_init"); } - spi_frequency(obj, hz); + if (spi->hz != 0) { + spi_frequency(obj, hz); + } } void spi_frequency(spi_t *obj, int hz) @@ -127,11 +129,14 @@ void spi_frequency(spi_t *obj, int hz) int spi_master_write(spi_t *obj, int value) { struct spi_s *spi = cy_get_spi(obj); - uint8_t received; - if (CY_RSLT_SUCCESS != cyhal_spi_transfer(&(spi->hal_spi), (const uint8_t *)value, 1, &received, 1, 0)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_transfer"); + uint32_t received; + if (CY_RSLT_SUCCESS != cyhal_spi_write(&(spi->hal_spi), (uint32_t)value)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_write"); + } + if (CY_RSLT_SUCCESS != cyhal_spi_read(&(spi->hal_spi), &received)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_read"); } - return received; + return (int)received; } int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h index 196877fb0a8..6bbb218aca7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h @@ -350,7 +350,7 @@ typedef struct { uint16_t pending; void *rx_buffer; uint32_t rx_buffer_size; - void *tx_buffer; + const void *tx_buffer; uint32_t tx_buffer_size; bool is_async; #else diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index 87de28f75ce..7322c042b48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -68,6 +68,17 @@ extern "C" { * \{ */ +/** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency + * + * @param[in] frequency The desired frequency + * @param[in] frac_bits The number of fractional bits that the divider has + * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1) + */ +static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bits) +{ + return ((cy_PeriClkFreqHz * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; +} + /** Converts the provided gpio pin to a resource instance object * * @param[in] pin The pin to get a resource object for diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c index a262b418790..4a6eff8ae85 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c @@ -33,8 +33,20 @@ #define PENDING_TX 2 #define PENDING_TX_RX 3 -#define SCB_PERI_CLOCK_SLAVE 15000000 -#define SCB_PERI_CLOCK_MASTER 1800000 +/* Must be between 1.55 MHz and 12.8 MHz for running i2c master at 100KHz */ +#define SCB_PERI_CLOCK_SLAVE_STD 8000000 +/* Must be between 7.82 MHz and 15.38 MHz for running i2c master at 400KHz */ +#define SCB_PERI_CLOCK_SLAVE_FST 12500000 +/* Must be between 15.84 MHz and 89.0 MHz for running i2c master at 1MHz */ +#define SCB_PERI_CLOCK_SLAVE_FSTP 50000000 +/* Must be between 1.55 MHz and 3.2 MHz for running i2c slave at 100KHz */ +#define SCB_PERI_CLOCK_MASTER_STD 2000000 +/* Must be between 7.82 MHz and 10 MHz for running i2c slave at 400KHz */ +#define SCB_PERI_CLOCK_MASTER_FST 8500000 +/* Must be between 14.32 MHz and 25.8 MHz for running i2c slave at 1MHz */ +#define SCB_PERI_CLOCK_MASTER_FSTP 20000000 + +#define CYHAL_I2C_MASTER_DEFAULT_FREQ 100000 static const cy_stc_scb_i2c_config_t default_i2c_config = { .i2cMode = CY_SCB_I2C_MASTER, @@ -429,10 +441,45 @@ static void (*cyhal_i2c_interrupts_dispatcher_table[CY_IP_MXSCB_INSTANCES])(void #endif }; -static uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bits) +static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_slave) { - /* I2C use peripheral clock */ - return ((cy_PeriClkFreqHz * (1 << frac_bits)) + (frequency / 2)) / frequency; + /* Return the actual data rate on success, 0 otherwise */ + uint32_t peri_freq = 0; + if (freq == 0) + { + return 0; + } + if (freq <= CY_SCB_I2C_STD_DATA_RATE) + { + peri_freq = is_slave ? SCB_PERI_CLOCK_SLAVE_STD : SCB_PERI_CLOCK_MASTER_STD; + } + else if (freq <= CY_SCB_I2C_FST_DATA_RATE) + { + peri_freq = is_slave ? SCB_PERI_CLOCK_SLAVE_FST : SCB_PERI_CLOCK_MASTER_FST; + } + else if (freq <= CY_SCB_I2C_FSTP_DATA_RATE) + { + peri_freq = is_slave ? SCB_PERI_CLOCK_SLAVE_FSTP : SCB_PERI_CLOCK_MASTER_FSTP; + } + else + { + return 0; + } + Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)get_scb_cls(obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); + Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + + /* According to PDL API Reference Guide - Cy_SysClk_PeriphGetFrequency() use only for i2c master role */ + if(!is_slave) + { + return Cy_SCB_I2C_SetDataRate(obj->base, freq, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); + } + else + { + return Cy_SCB_I2C_GetDataRate(obj->base, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); + } + } /* Start API implementing */ @@ -454,13 +501,12 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c { return CYHAL_I2C_RSLT_ERR_INVALID_PIN; } - const cyhal_resource_inst_t *rsc = scl_map->inst; - cy_rslt_t result = cyhal_hwmgr_reserve(rsc); + obj->resource = *(scl_map->inst); + cy_rslt_t result = cyhal_hwmgr_reserve(&(obj->resource)); if (result != CY_RSLT_SUCCESS) { return result; } - obj->resource = *rsc; /* Reserve the SDA pin */ cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda); @@ -468,7 +514,7 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c if (result == CY_RSLT_SUCCESS) { obj->pin_sda = sda; - } + } Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_DM_OD_DRIVESLOW); @@ -481,10 +527,10 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c if (result == CY_RSLT_SUCCESS) { obj->pin_scl = scl; - } + } Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_DM_OD_DRIVESLOW); - + } obj->base = CY_SCB_BASE_ADDRESSES[obj->resource.block_num]; @@ -504,18 +550,12 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c if (result == CY_RSLT_SUCCESS) { - /* Connect assigned divider to be a clock source for I2C */ - Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)get_scb_cls(obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); - - /* I2C slave desired data rate is 400 kbps. - * To support this data rate the clk_scb frequency must be in range 7.82 – 15.38 MHz. - * Find clk_scb valid ranges in TRM section I2C sub-section Oversampling and Bit Rate. - * For clk_peri = 50 MHz, select divider value 4 and get clk_scb = (50 MHz / 4) = 12.5 MHz. - * This clock frequency meets requirements above. - */ - Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(SCB_PERI_CLOCK_SLAVE, 0u)); - Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + uint32_t dataRate = cyhal_set_peri_divider(obj, CYHAL_I2C_MASTER_DEFAULT_FREQ, false); + if (dataRate == 0) + { + /* Can not reach desired data rate */ + result = CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR; + } } bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); @@ -528,6 +568,7 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c (void) Cy_SCB_I2C_Enable(obj->base); Cy_SysInt_Init(&irqCfg, cyhal_i2c_interrupts_dispatcher_table[obj->resource.block_num]); NVIC_EnableIRQ(CY_SCB_IRQ_N[obj->resource.block_num]); + obj->irq_cause = CYHAL_I2C_IRQ_NONE; cyhal_i2c_config_structs[obj->resource.block_num] = obj; cyhal_i2c_config_structs[obj->resource.block_num]->irq_cause = CYHAL_I2C_IRQ_NONE; result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); @@ -542,9 +583,12 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c void cyhal_i2c_free(cyhal_i2c_t *obj) { CY_ASSERT(NULL != obj); - + if (CYHAL_RSC_INVALID != obj->resource.type) { + IRQn_Type irqn = CY_SCB_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; @@ -570,9 +614,8 @@ void cyhal_i2c_free(cyhal_i2c_t *obj) cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) { (void) Cy_SCB_I2C_Disable(obj->base, &obj->context); - uint32_t dataRate; - cy_stc_scb_i2c_config_t config_structure = default_i2c_config; + cy_stc_scb_i2c_config_t config_structure = default_i2c_config; config_structure.i2cMode = (cfg->is_slave) ? CY_SCB_I2C_SLAVE : CY_SCB_I2C_MASTER; @@ -586,28 +629,13 @@ cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) } /* Set data rate */ - if (!cfg->is_slave) + uint32_t dataRate = cyhal_set_peri_divider(obj, cfg->frequencyhal_hz, cfg->is_slave); + if (dataRate == 0) { - Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)get_scb_cls(obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); - - /* I2C master desired data rate is 100 kbps. - * To support this data rate the clk_scb frequency must be in range 1.55 - 3.2 MHz. - * Find clk_scb valid ranges in TRM section I2C sub-section Oversampling and Bit Rate. - * For clk_peri = 50 MHz, select divider value 32 and get clk_scb = (50 MHz / 32) = 1.563 MHz. - * This clock frequency meets requirements above. - */ - Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphSetDivider (obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(SCB_PERI_CLOCK_MASTER, 0u)); - Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); - - dataRate = Cy_SCB_I2C_SetDataRate(obj->base, (uint32_t)cfg->frequencyhal_hz, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); - - if ((dataRate > cfg->frequencyhal_hz) || (dataRate == 0U)) - { - /* Can not reach desired data rate */ - return CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR; - } + /* Can not reach desired data rate */ + return CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR; } + cy_rslt_t result = (cy_rslt_t)Cy_SCB_I2C_Init(obj->base, &config_structure, &(obj->context)); (void) Cy_SCB_I2C_Enable(obj->base); @@ -615,7 +643,7 @@ cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) return result; } -cy_rslt_t cyhal_i2c_master_send(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout) { cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; @@ -649,7 +677,7 @@ cy_rslt_t cyhal_i2c_master_send(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8 return status; } -cy_rslt_t cyhal_i2c_master_recv(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout) { cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK; @@ -687,25 +715,25 @@ cy_rslt_t cyhal_i2c_master_recv(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *da return status; } -cy_rslt_t cyhal_i2c_slave_send(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size) { - if (obj->context.state == CY_SCB_I2C_IDLE) + if (obj->context.state == CY_SCB_I2C_IDLE) { Cy_SCB_I2C_SlaveConfigReadBuf(obj->base, (uint8_t *)data, size, &obj->context); - } + } return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_i2c_slave_recv(cyhal_i2c_t *obj, uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size) { if (obj->context.state == CY_SCB_I2C_IDLE) - { + { Cy_SCB_I2C_SlaveConfigWriteBuf(obj->base, (uint8_t *)data, size, &obj->context); } return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_i2c_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout) { cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; @@ -753,7 +781,7 @@ cy_rslt_t cyhal_i2c_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_a return status; } -cy_rslt_t cyhal_i2c_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout) { cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK; @@ -779,7 +807,7 @@ cy_rslt_t cyhal_i2c_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_ad { status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)(mem_addr & 0x00FF), timeout, &obj->context); } - + if (status == CY_SCB_I2C_SUCCESS) { status = Cy_SCB_I2C_MasterSendReStart(obj->base, address, CY_SCB_I2C_READ_XFER, timeout, &obj->context); @@ -814,7 +842,7 @@ cy_rslt_t cyhal_i2c_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_ad return status; } -cy_rslt_t cyhal_i2c_transfer_async(cyhal_i2c_t *obj, const void *tx, size_t tx_size, void *rx, size_t rx_size, uint16_t address) +cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size) { obj->rx_config.slaveAddress = address; obj->tx_config.slaveAddress = address; @@ -906,7 +934,7 @@ static cyhal_i2c_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) break; case CY_SCB_I2C_MASTER_ERR_EVENT: cause = CYHAL_I2C_MASTER_ERR_EVENT; - break; + break; default: cause = CYHAL_I2C_IRQ_NONE; break; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c index 9038e79a525..c6347358e17 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c @@ -26,6 +26,7 @@ #include #include #include "cyhal_implementation.h" +#include "cyhal_hwmgr.h" #ifdef CY_IP_MXSCB @@ -300,7 +301,6 @@ static void (*cyhal_spi_cb_wrapper_table[CY_IP_MXSCB_INSTANCES])(uint32_t event) static void cyhal_spi_interrupts_dispatcher_IRQHandler(uint32_t spi_num) { cyhal_spi_t *obj = cyhal_spi_config_structs[spi_num]; - void *buf; if (NULL == obj) { @@ -320,15 +320,15 @@ static void cyhal_spi_interrupts_dispatcher_IRQHandler(uint32_t spi_num) { /* Start TX Transfer */ obj->pending = PENDING_TX; - buf = obj->tx_buffer; + const uint8_t *buf = obj->tx_buffer; obj->tx_buffer = NULL; - Cy_SCB_SPI_Transfer(obj->base, buf, NULL, obj->tx_buffer_size, &obj->context); + Cy_SCB_SPI_Transfer(obj->base, (uint8_t *)buf, NULL, obj->tx_buffer_size, &obj->context); } else if (obj->rx_buffer) { /* Start RX Transfer */ obj->pending = PENDING_RX; - buf = obj->rx_buffer; + uint8_t *buf = obj->rx_buffer; obj->rx_buffer = NULL; Cy_SCB_SPI_Transfer(obj->base, NULL, buf, obj->rx_buffer_size, &obj->context); @@ -497,6 +497,7 @@ static void cyhal_spi_install_irq(cyhal_spi_t *obj) Cy_SysInt_Init(&irqCfg, cyhal_spi_interrupts_dispatcher_table[idx]); NVIC_EnableIRQ(CY_SCB_IRQ_N[idx]); cyhal_spi_config_structs[idx] = obj; + cyhal_spi_config_structs[idx]->irq_cause = CYHAL_SPI_IRQ_NONE; } static cy_en_scb_spi_sclk_mode_t cyhal_convert_mode_sclk(cyhal_spi_mode_t mode) @@ -542,7 +543,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave) { CY_ASSERT(NULL != obj); - + cy_rslt_t result = CY_RSLT_SUCCESS; cyhal_resource_inst_t pin_rsc; uint8_t ovr_sample_val = SPI_OVERSAMPLE_MIN; @@ -556,12 +557,12 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, if ((NC == sclk) || ((NC == mosi) && (NC == miso))) return CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED; - + const cyhal_resource_pin_mapping_t *mosi_map = NULL; const cyhal_resource_pin_mapping_t *miso_map = NULL; const cyhal_resource_pin_mapping_t *sclk_map = NULL; const cyhal_resource_pin_mapping_t *ssel_map = NULL; - + // Reserve the SPI if (is_slave) { @@ -595,7 +596,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, } sclk_map = CY_UTILS_GET_RESOURCE(sclk, cyhal_pin_map_scb_spi_m_clk); } - + if ( ((NC != mosi) && (NULL == mosi_map)) || ((NC != miso) && (NULL == miso_map)) || (NULL == sclk_map) @@ -652,7 +653,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, //reseve the SSEL pin if ((result == CY_RSLT_SUCCESS) && (NC != ssel)) { - if (is_slave) + if (is_slave) { pin_rsc = cyhal_utils_get_gpio_resource(ssel); result = cyhal_hwmgr_reserve(&pin_rsc); @@ -718,7 +719,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, { result = cyhal_connect_pin(ssel_map); } - else + else { result = cyhal_gpio_init(ssel, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); } @@ -767,6 +768,9 @@ void cyhal_spi_free(cyhal_spi_t *obj) if (obj->resource.type != CYHAL_RSC_INVALID) { + IRQn_Type irqn = CY_SCB_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); obj->resource.type = CYHAL_RSC_INVALID; @@ -805,12 +809,6 @@ void cyhal_spi_free(cyhal_spi_t *obj) } } -static uint32_t cyhal_divider_value(uint32_t frequency) -{ - /* SPI use peripheral clock */ - return cy_PeriClkFreqHz / frequency; -} - static inline uint32_t min(uint32_t lhs, uint32_t rhs) { return lhs > rhs ? rhs : lhs; @@ -827,7 +825,7 @@ static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t { return CYHAL_SPI_RSLT_BAD_ARGUMENT; } - + cy_rslt_t result = CY_RSLT_SUCCESS; uint8_t oversample_value; uint32_t divider_value; @@ -854,8 +852,8 @@ static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t continue; } - divider_value = cyhal_divider_value(hz * oversample_value); - divided_freq = cy_PeriClkFreqHz /divider_value; + divider_value = cyhal_divider_value(hz * oversample_value, 0); + divided_freq = cy_PeriClkFreqHz /(divider_value + 1); diff = max(oversampled_freq, divided_freq) - min(oversampled_freq, divided_freq); if (diff < last_diff) @@ -874,16 +872,16 @@ static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t else { /* Slave requires such frequency: fclk_scb = N / ((0.5 * tclk_scb) – 20 nsec - tDSI, - * N is 3 when "Enable Input Glitch Filter" is false and 4 when true. + * N is 3 when "Enable Input Glitch Filter" is false and 4 when true. * tDSI Is external master delay which is assumed to be 16.66 nsec */ float desired_period_us = 1 / (float)hz * 1e6; uint32_t required_frequency = (uint32_t)(3e6 / (0.5f * desired_period_us - 36.66f / 1e3)); - + if (required_frequency > cy_PeriClkFreqHz) { return CYHAL_SPI_RSLT_CLOCK_ERROR; } - + /* Use maximum available clock for slave to make it able to work with any master environment */ last_dvdr_val = 1; } @@ -915,7 +913,7 @@ static void cyhal_set_ssel(cyhal_spi_t *obj) static void cyhal_reset_ssel(cyhal_spi_t *obj) { - if ((!obj->is_slave) && (CYHAL_NC_PIN_VALUE != obj->pin_ssel)) + if ((!obj->is_slave) && (CYHAL_NC_PIN_VALUE != obj->pin_ssel)) { cyhal_gpio_write(obj->pin_ssel, SSEL_INACTIVE); } @@ -974,7 +972,7 @@ cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t *value) { return CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED; } - + while (read_value == CY_SCB_SPI_RX_NO_DATA) { read_value = Cy_SCB_SPI_Read(obj->base); @@ -1003,7 +1001,7 @@ cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value) { return CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED; } - + if (!obj->is_slave) { rx_count = Cy_SCB_SPI_GetNumInRxFifo(obj->base); @@ -1019,11 +1017,11 @@ cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value) count = Cy_SCB_SPI_Write(obj->base, value); } - if (!obj->is_slave) + if (!obj->is_slave) { while (Cy_SCB_SPI_IsTxComplete(obj->base) == false) ; - while (( Cy_SCB_SPI_GetNumInRxFifo(obj->base) == rx_count ) && (rx_count != Cy_SCB_GetFifoSize(obj->base))) + while (( Cy_SCB_SPI_GetNumInRxFifo(obj->base) == rx_count ) && (rx_count != Cy_SCB_GetFifoSize(obj->base))) { /* Wait for RX FIFO not empty */ } cyhal_reset_ssel(obj); } @@ -1037,7 +1035,6 @@ cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_leng { uint32_t remaining_rx, remaining_tx, xfr_length; uint8_t dummy[MAX_DUMMY_SIZE]; - uint8_t *bufptr; if (NULL == obj) { @@ -1059,71 +1056,67 @@ cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_leng xfr_length = (uint32_t) rx_length; remaining_rx = 0; remaining_tx = (uint32_t) (tx_length - rx_length); - Cy_SCB_SPI_Transfer(obj->base, (uint8_t *) tx, rx, xfr_length, &(obj->context)); + if (xfr_length != 0) + { + Cy_SCB_SPI_Transfer(obj->base, (uint8_t *) tx, rx, xfr_length, &(obj->context)); - while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; + while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; + } - bufptr = obj->data_bits == 8 ? - (uint8_t *)(((uint8_t *)tx) + xfr_length) : - (uint8_t *)(((uint16_t *)tx) + xfr_length); + const uint8_t *bufptr = tx + (obj->data_bits <= 8 ? xfr_length : (xfr_length * 2)); - Cy_SCB_SPI_Transfer(obj->base, bufptr, NULL, remaining_tx, &(obj->context)); + Cy_SCB_SPI_Transfer(obj->base, (uint8_t *)bufptr, NULL, remaining_tx, &(obj->context)); while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; - } + } else if (tx_length < rx_length) { xfr_length = (uint32_t) tx_length; remaining_rx = (uint32_t) (rx_length - tx_length); - Cy_SCB_SPI_Transfer(obj->base, (uint8_t *) tx, rx, xfr_length, &(obj->context)); + if (xfr_length != 0) + { + Cy_SCB_SPI_Transfer(obj->base, (uint8_t *) tx, rx, xfr_length, &(obj->context)); - while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; + while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; + } memset(dummy, write_fill, sizeof(dummy)); while (remaining_rx) { - if (remaining_rx <= MAX_DUMMY_SIZE) - { - bufptr = obj->data_bits == 8 ? - (uint8_t *)(((uint8_t *)rx) + xfr_length) : - (uint8_t *)(((uint16_t *)rx) + xfr_length); - + uint8_t *bufptr = rx + (obj->data_bits <= 8 ? xfr_length : (xfr_length * 2)); + if (remaining_rx <= MAX_DUMMY_SIZE) + { Cy_SCB_SPI_Transfer(obj->base, dummy, bufptr, remaining_rx, &(obj->context)); remaining_rx = 0; - } - else - { - bufptr = obj->data_bits == 8 ? - (uint8_t *)(((uint8_t *)rx) + xfr_length) : - (uint8_t *)(((uint16_t *)rx) + xfr_length); - + } + else + { Cy_SCB_SPI_Transfer(obj->base, dummy, bufptr, MAX_DUMMY_SIZE, &(obj->context)); remaining_rx -= MAX_DUMMY_SIZE; xfr_length += MAX_DUMMY_SIZE; - } + } - while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; + while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; } - } - else + } + else if (tx_length != 0) // tx_length == rx_length { xfr_length = (uint32_t) tx_length; Cy_SCB_SPI_Transfer(obj->base, (uint8_t *) tx, rx, xfr_length, &(obj->context)); while ( CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(obj->base, &(obj->context))) { }; } - + if (!obj->is_slave) { cyhal_reset_ssel(obj); } - + return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length) { cy_en_scb_spi_status_t spi_status; - uint8_t *bufptr; if (NULL == obj) { @@ -1137,24 +1130,21 @@ cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t t cyhal_set_ssel(obj); obj->is_async = true; - + /* Setup transfer */ - if (tx_length > rx_length) + if (tx_length > rx_length) { - if (rx_length > 0) + if (rx_length > 0) { /* I) write + read, II) write only */ obj->pending = PENDING_TX_RX; obj->rx_buffer = NULL; - bufptr = obj->data_bits == 8 ? - (uint8_t *)(((uint8_t *)tx) + rx_length) : - (uint8_t *)(((uint16_t *)tx) + rx_length); - obj->tx_buffer = bufptr; + obj->tx_buffer = tx + (obj->data_bits <= 8 ? rx_length : (rx_length * 2)); obj->tx_buffer_size = tx_length - rx_length; spi_status = Cy_SCB_SPI_Transfer(obj->base, (void *)tx, rx, rx_length, &obj->context); - } - else + } + else { /* I) write only */ obj->pending = PENDING_TX; @@ -1163,24 +1153,21 @@ cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t t spi_status = Cy_SCB_SPI_Transfer(obj->base, (void *)tx, NULL, tx_length, &obj->context); } - } - else if (rx_length > tx_length) + } + else if (rx_length > tx_length) { - if (tx_length > 0) + if (tx_length > 0) { /* I) write + read, II) read only */ obj->pending = PENDING_TX_RX; - bufptr = obj->data_bits == 8 ? - (uint8_t *)(((uint8_t *)rx) + tx_length) : - (uint8_t *)(((uint16_t *)rx) + tx_length); - obj->rx_buffer = bufptr; + obj->rx_buffer = rx + (obj->data_bits <= 8 ? tx_length : (tx_length * 2)); obj->rx_buffer_size = rx_length - tx_length; obj->tx_buffer = NULL; spi_status = Cy_SCB_SPI_Transfer(obj->base, (void *)tx, rx, tx_length, &obj->context); - } - else + } + else { /* I) read only. */ obj->pending = PENDING_RX; @@ -1189,8 +1176,8 @@ cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t t spi_status = Cy_SCB_SPI_Transfer(obj->base, NULL, rx, rx_length, &obj->context); } - } - else + } + else { /* RX and TX of the same size: I) write + read. */ obj->pending = PENDING_TX_RX; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c index f61597b0b40..4fee067b176 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c @@ -689,13 +689,6 @@ static uint32_t cyhal_uart_baud_perdif(uint32_t desired_baud, uint32_t actual_ba return perdif; } -static uint32_t cyhal_divider_value(uint32_t frequency) -{ - CY_ASSERT(frequency != 0); - /* UARTs use peripheral clock */ - return (((cy_PeriClkFreqHz) + (frequency / 2)) / frequency) - 1; -} - static uint8_t cyhal_uart_best_oversample(uint32_t baudrate) { uint8_t differences[UART_OVERSAMPLE_MAX + 1]; @@ -704,7 +697,7 @@ static uint8_t cyhal_uart_best_oversample(uint32_t baudrate) for(index = UART_OVERSAMPLE_MIN; index < UART_OVERSAMPLE_MAX + 1; index++) { - divider = cyhal_divider_value(baudrate * index); + divider = cyhal_divider_value(baudrate * index, 0); differences[index] = cyhal_uart_baud_perdif(baudrate, cyhal_uart_actual_baud(divider, index)); } @@ -736,7 +729,7 @@ cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actual oversample_value = cyhal_uart_best_oversample(baudrate); obj->config.oversample = oversample_value; - divider = cyhal_divider_value(baudrate * oversample_value); + divider = cyhal_divider_value(baudrate * oversample_value, 0); /* Set baud rate */ if ((obj->clock.div_type == CY_SYSCLK_DIV_16_5_BIT) || (obj->clock.div_type == CY_SYSCLK_DIV_24_5_BIT)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/serial_api.c index 8cfb4b68739..a39c23b4785 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/serial_api.c @@ -196,13 +196,6 @@ static IRQn_Type serial_irq_allocate_channel(serial_obj_t *obj) #endif // M0 } -static void serial_irq_release_channel(IRQn_Type channel, uint32_t serial_id) -{ -#if defined (TARGET_MCU_PSOC6_M0) - cy_m0_nvic_release_channel(channel, CY_SERIAL_IRQN_ID + serial_id); -#endif //M0 -} - static int serial_irq_setup_channel(serial_obj_t *obj) { cy_stc_sysint_t irq_config; @@ -230,6 +223,23 @@ static int serial_irq_setup_channel(serial_obj_t *obj) return 0; } +static void serial_irq_release_channel(serial_obj_t *obj) +{ + irq_info_t *info = &irq_info[obj->serial_id]; + + if (info->irqn != unconnected_IRQn) { + MBED_ASSERT(info->serial_obj == obj); + NVIC_DisableIRQ(info->irqn); + +#if defined (TARGET_MCU_PSOC6_M0) + cy_m0_nvic_release_channel(info->irqn, CY_SERIAL_IRQN_ID + obj->serial_id); +#endif //M0 + info->irqn = unconnected_IRQn; + info->serial_obj = NULL; + info->handler = NULL; + } +} + /* * Calculates fractional divider value. */ @@ -292,6 +302,12 @@ static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudr return status; } +static void serial_deinit_clock(serial_obj_t *obj) +{ + Cy_SysClk_PeriphDisableDivider(obj->div_type, obj->div_num); + cy_clk_free_divider(obj->div_type, obj->div_num); +} + /* * Initializes i/o pins for UART tx/rx. */ @@ -328,6 +344,21 @@ static void serial_init_flow_pins(serial_obj_t *obj) } } +static void serial_deinit_pins(serial_obj_t *obj) +{ + if (obj->pin_tx != NC) { + pin_function(obj->pin_tx, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullDown, PIN_INPUT)); + } + if (obj->pin_rx != NC) { + pin_function(obj->pin_rx, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullDown, PIN_INPUT)); + } + if (obj->pin_rts != NC) { + pin_function(obj->pin_rts, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullDown, PIN_INPUT)); + } + if (obj->pin_cts != NC) { + pin_function(obj->pin_cts, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullDown, PIN_INPUT)); + } +} /* * Initializes and enables UART/SCB. @@ -446,6 +477,24 @@ void serial_init(serial_t *obj_in, PinName tx, PinName rx) } } +void serial_free(serial_t *obj_in) +{ + serial_obj_t *obj = OBJ_P(obj_in); + bool is_stdio = (obj->pin_tx == CY_STDIO_UART_TX) || (obj->pin_rx == CY_STDIO_UART_RX); + + if (is_stdio && stdio_uart_inited) { + /* stdio_uart just can't be released */ + return; + } + + Cy_SCB_UART_Disable(obj->base, NULL); + Cy_SysPm_UnregisterCallback(&obj->pm_callback_handler); + serial_irq_release_channel(obj); + serial_deinit_pins(obj); + Cy_SCB_UART_DeInit(obj->base); + serial_deinit_clock(obj); +} + void serial_baud(serial_t *obj_in, int baudrate) { serial_obj_t *obj = OBJ_P(obj_in); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c index ff6fc2a856d..1453e4239a1 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c @@ -192,10 +192,8 @@ int i2c_byte_read(i2c_t *obj, int last) base->C1 |= I2C_C1_TXAK_MASK; // NACK } - data = (base->D & 0xFF); - - /* Change direction to Tx to avoid extra clocks. */ - base->C1 |= I2C_C1_TX_MASK; + /* Read dummy to release the bus. */ + data = base->D; /* Wait until data transfer complete. */ while (!(base->S & kI2C_IntPendingFlag)) @@ -205,6 +203,11 @@ int i2c_byte_read(i2c_t *obj, int last) /* Clear the IICIF flag. */ base->S = kI2C_IntPendingFlag; + /* Change direction to Tx to avoid extra clocks. */ + base->C1 |= I2C_C1_TX_MASK; + + data = (base->D & 0xFF); + return data; } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c index f4d92aa073c..6264fe93a18 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c @@ -34,6 +34,7 @@ #include "pinmap.h" #include "PeripheralPins.h" #include "qspi_device.h" +#include "platform/mbed_critical.h" /* Look-up table entry indices */ #define LUT1_SEQ_INDEX 0 // Pre-defined read sequence @@ -267,6 +268,7 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void return QSPI_STATUS_INVALID_PARAMETER; } + core_util_critical_section_enter(); /* Prepare the write command */ qspi_prepare_command(obj, command, data, to_write, NULL, 0); @@ -295,6 +297,7 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void if (to_write) { QSPI_WriteBlocking(base, (uint32_t *)data_send, to_write); } + core_util_critical_section_exit(); while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) { } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/us_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/us_ticker.c index 5b03a141b88..621cd398e01 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/us_ticker.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/us_ticker.c @@ -141,6 +141,7 @@ void us_ticker_clear_interrupt(void) void us_ticker_free(void) { nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_STOP); + nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_SHUTDOWN); nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); NVIC_DisableIRQ(TIMER1_IRQn); us_ticker_initialized = false; diff --git a/targets/TARGET_NUVOTON/nu_timer.c b/targets/TARGET_NUVOTON/nu_timer.c index a58e7b2f5cb..ef3d3489caf 100644 --- a/targets/TARGET_NUVOTON/nu_timer.c +++ b/targets/TARGET_NUVOTON/nu_timer.c @@ -65,65 +65,3 @@ void nu_busy_wait_us(uint32_t us) prev = cur; } } - -/* Delay 4 cycles per round by hand-counting instruction cycles - * - * The delay function here is implemented by just hand-counting instruction cycles rather than preferred - * H/W timer since it is to use in cases where H/W timer is not available. Usually, it can delay at least - * 4-cycles per round. - * - * In modern pipeline core, plus flash performance and other factors, we cannot rely accurately on hand- - * counting instruction cycles for expected delay cycles. - */ -#if defined(__CC_ARM) -MBED_NOINLINE -__asm void nu_delay_cycle_x4(uint32_t rounds) -{ -// AStyle should not format inline assembly -// *INDENT-OFF* -1 -#if !defined(__CORTEX_M0) - NOP // 1 cycle -#endif - SUBS a1, a1, #1 // 1 cycle - BCS %BT1 // 3 cycles(M0)/2 cycles(non-M0) - BX lr -// *INDENT-ON* -} -#elif defined (__ICCARM__) -MBED_NOINLINE -void nu_delay_cycle_x4(uint32_t rounds) -{ - __asm volatile( - "loop: \n" -#if !defined(__CORTEX_M0) - " NOP \n" // 1 cycle -#endif - " SUBS %0, %0, #1 \n" // 1 cycle - " BCS.n loop\n" // 3 cycles(M0)/2 cycles(non-M0) - : "+r"(rounds) - : - : "cc" - ); -} -#elif defined ( __GNUC__ ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -MBED_NOINLINE -void nu_delay_cycle_x4(uint32_t rounds) -{ - __asm__ volatile( - "%=:\n\t" -#if !defined(__CORTEX_M0) - "NOP\n\t" // 1 cycle -#endif -#if defined(__thumb__) && !defined(__thumb2__) && !defined(__ARMCC_VERSION) - "SUB %0, #1\n\t" // 1 cycle -#else - "SUBS %0, %0, #1\n\t" // 1 cycle -#endif - "BCS %=b\n\t" // 3 cycles(M0)/2 cycles(non-M0) - : "+l"(rounds) - : - : "cc" - ); -} -#endif diff --git a/targets/TARGET_NUVOTON/nu_timer.h b/targets/TARGET_NUVOTON/nu_timer.h index f3d4d867bb2..4b9f359e2e6 100644 --- a/targets/TARGET_NUVOTON/nu_timer.h +++ b/targets/TARGET_NUVOTON/nu_timer.h @@ -74,9 +74,6 @@ void nu_countdown_free(struct nu_countdown_ctx_s *ctx); */ void nu_busy_wait_us(uint32_t us); -/* Delay 4 cycles per round by hand-counting instruction cycles */ -void nu_delay_cycle_x4(uint32_t rounds); - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct index 969cf89f7e2..13dc91ce831 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct @@ -54,7 +54,12 @@ ; Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM #define VECTOR_SIZE 0x1D8 -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 + +#define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + +#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+MBED_CRASH_REPORT_RAM_SIZE) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region @@ -64,7 +69,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region .ANY (+RO) } - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data + RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + + + RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data .ANY (+RW +ZI) } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld index d9392aa594f..37753f771b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld @@ -12,6 +12,8 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE; +M_CRASH_DATA_RAM_SIZE = 0x100; + /* Linker script to configure memory regions. */ MEMORY { @@ -91,6 +93,18 @@ SECTIONS __etext = .; _sidata = .; + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM + .data : AT (__etext) { __data_start__ = .; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf index 384bdb68094..95b7097c0fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf @@ -9,14 +9,21 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 320kb = 0x50000] Vector table dynamic copy: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x200001D7; -define symbol __region_RAM_start__ = 0x200001D8; /* Aligned on 8 bytes */ +define symbol __region_CRASH_DATA_RAM_start__ = 0x200001D8; +define symbol __region_CRASH_DATA_RAM_end__ = 0x200002D7; +define symbol __region_RAM_start__ = 0x200002D8; /* Aligned on 8 bytes */ define symbol __region_RAM_end__ = 0x2004FFFF; /* Memory regions */ define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + /* Stack and Heap */ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; @@ -33,4 +40,4 @@ do not initialize { section .noinit }; place at address mem:__intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; \ No newline at end of file +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h index 070149e4802..1d8e0cf0ee7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h @@ -54,4 +54,8 @@ extern const pwm_apb_map_t pwm_apb_map_table[]; #endif // DEVICE_PWMOUT +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c index 284257ec116..6a83252cdbc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c @@ -969,6 +969,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(chnum)->HCCHAR = tmpreg; + reactivate = 1; } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); // MBED: changed diff --git a/targets/targets.json b/targets/targets.json index 1a6b9a1f89a..b99e31b3f4a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8345,6 +8345,7 @@ "SPISLAVE", "STDIO_MESSAGES", "TRNG", + "USBDEVICE", "USTICKER" ], "release_versions": ["5"], @@ -8382,6 +8383,24 @@ "network-default-interface-type": "WIFI" } }, + "CY8CMOD_062S2_43012": { + "inherits": ["MCU_PSOC6_M4"], + "features": ["BLE"], + "device_has_remove": ["ANALOGOUT"], + "extra_labels_add": [ + "PSOC6_02", + "CM0P_SLEEP", + "WHD", + "43012", + "CYW43XXX", + "CORDIO" + ], + "macros_add": ["CY8C624ABZI_D44", "CYBSP_WIFI_CAPABLE"], + "public": false, + "overrides": { + "network-default-interface-type": "WIFI" + } + }, "CY8CKIT_062_WIFI_BT": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], @@ -8399,6 +8418,10 @@ "post_binary_hook": { "function": "PSOC6Code.complete" }, + "bootloader_supported": true, + "mbed_rom_start": "0x10000000", + "mbed_rom_size": "0x100000", + "sectors": [[268435456, 512]], "overrides": { "network-default-interface-type": "WIFI" }, @@ -8407,12 +8430,25 @@ "CY8CPROTO_062_4343W": { "inherits": ["CY8CMOD_062_4343W"], "detect_code": ["1901"], + "post_binary_hook": { + "function": "PSOC6Code.complete" + }, + "bootloader_supported": true, + "mbed_rom_start": "0x10000000", + "mbed_rom_size": "0x200000", + "sectors": [[268435456, 512]] + }, + "CY8CKIT_062S2_43012": { + "inherits": ["CY8CMOD_062S2_43012"], + "supported_form_factors": ["ARDUINO"], + "detect_code": ["190B"], "post_binary_hook": { "function": "PSOC6Code.complete" } }, "CY8CKIT_062_BLE": { "inherits": ["MCU_PSOC6_M4"], + "device_has_remove": ["USBDEVICE"], "supported_form_factors": ["ARDUINO"], "extra_labels_add": [ "PSOC6_01", @@ -8451,7 +8487,7 @@ "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "FUTURE_SEQUANA"], "extra_labels_remove": ["PSOC6"], - "device_has_remove": ["TRNG", "CRC", "I2CSLAVE"], + "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE"], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["6000"], "post_binary_hook": { @@ -8480,7 +8516,7 @@ "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "CORDIO"], "extra_labels_remove": ["PSOC6"], - "device_has_remove": ["TRNG", "CRC", "I2CSLAVE"], + "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE"], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["6000"], "hex_filename": "psoc63_m0_default_1.03.hex", diff --git a/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhyHw.h b/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhyHw.h new file mode 100644 index 00000000000..cacace0b02b --- /dev/null +++ b/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhyHw.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USBPHYHW_H +#define USBPHYHW_H + +#include "USBPhy.h" +#include "cyhal_usb_dev.h" + +class USBPhyHw : public USBPhy { +public: + USBPhyHw(); + virtual ~USBPhyHw(); + virtual void init(USBPhyEvents *events); + virtual void deinit(); + virtual bool powered(); + virtual void connect(); + virtual void disconnect(); + virtual void configure(); + virtual void unconfigure(); + virtual void sof_enable(); + virtual void sof_disable(); + virtual void set_address(uint8_t address); + virtual void remote_wakeup(); + virtual const usb_ep_table_t *endpoint_table(); + virtual void suspend(bool suspended); + + virtual uint32_t ep0_set_max_packet(uint32_t max_packet); + virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size); + virtual void ep0_read(uint8_t *data, uint32_t size); + virtual uint32_t ep0_read_result(); + virtual void ep0_write(uint8_t *buffer, uint32_t size); + virtual void ep0_stall(); + + virtual bool endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type); + virtual void endpoint_remove(usb_ep_t endpoint); + virtual void endpoint_stall(usb_ep_t endpoint); + virtual void endpoint_unstall(usb_ep_t endpoint); + + virtual bool endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual uint32_t endpoint_read_result(usb_ep_t endpoint); + virtual bool endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual void endpoint_abort(usb_ep_t endpoint); + + virtual void process(); + + USBPhyEvents *events; + + uint8_t in_event_mask; + uint8_t out_event_mask; + +private: + virtual void usb_dev_execute_ep_callbacks(void); + static void _usbisr(void); + cyhal_usb_dev_t obj; +}; + +#endif diff --git a/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhy_PSOC6.cpp b/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhy_PSOC6.cpp new file mode 100644 index 00000000000..11850f93aa5 --- /dev/null +++ b/usb/device/targets/TARGET_Cypress/TARGET_PSOC6/USBPhy_PSOC6.cpp @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "USBPhyHw.h" +#include "mbed_assert.h" + +#if defined(DEVICE_USBDEVICE) + +#define USB_EP_ATTR_DATA_EP (USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_ALLOW_ISO) +#define USB_EP_ATTR_NON_ISO (USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT) +#define USB_DEV_EP_NON_ISOC_MAX_PACKET (64U) +#define USB_DEV_EP_ISOC_MAX_PACKET (128U) +#define USB_DEV_IN_DIR (0x80U) + +// Converts endpoint to the bit mask +#define USB_DEV_EP_BIT(endpoint) (1U << CYHAL_USB_DEV_GET_EP_IDX(endpoint)) + +// Callbacks to notify stack about event occurrence +static void usb_dev_bus_reset_callback(void); +static void usb_dev_ep0_setup_callback(void); +static void usb_dev_ep0_in_callback(void); +static void usb_dev_ep0_out_callback(void); +static void usb_dev_sof_callback(uint32_t frame_number); +static void usb_dev_endpoint_callback(cyhal_usb_dev_ep_t endpoint); + +static USBPhyHw *instance; + +USBPhy *get_usb_phy() +{ + static USBPhyHw usbphy; + return &usbphy; +} + +USBPhyHw::USBPhyHw(): events(NULL) +{ +} + +USBPhyHw::~USBPhyHw() +{ +} + +void USBPhyHw::init(USBPhyEvents *events) +{ + // Get access to the CYHAL USB object + cyhal_usb_dev_t *hal_obj = &obj; + + // Disable IRQ + cyhal_usb_dev_irq_enable(hal_obj, false); + + // Initialize instance to access class data + instance = this; + + // Store events + instance->events = events; + + // Initialize USB Device (CYHAL find required resources). + cy_rslt_t ret = cyhal_usb_dev_init(hal_obj, USBDP, USBDM, NULL); + MBED_ASSERT(CY_RSLT_SUCCESS == ret); + + // Hook device handlers to be called by driver + cyhal_usb_dev_register_event_callback(hal_obj, CYHAL_USB_DEV_EVENT_BUS_RESET, &usb_dev_bus_reset_callback); + cyhal_usb_dev_register_event_callback(hal_obj, CYHAL_USB_DEV_EVENT_EP0_SETUP, &usb_dev_ep0_setup_callback); + cyhal_usb_dev_register_event_callback(hal_obj, CYHAL_USB_DEV_EVENT_EP0_IN, &usb_dev_ep0_in_callback); + cyhal_usb_dev_register_event_callback(hal_obj, CYHAL_USB_DEV_EVENT_EP0_OUT, &usb_dev_ep0_out_callback); + + // Hook SOF callback + cyhal_usb_dev_register_sof_callback(hal_obj, &usb_dev_sof_callback); + + // Divide hardware buffer (512 bytes) statically accordingly to the lpc_table + // Only 6 endpoint out of 8 (supported by hardware) are supported because of buffer space limitation + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 1U, USB_DEV_EP_NON_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_BULK); + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 2U, USB_DEV_EP_NON_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_BULK); + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 3U, USB_DEV_EP_NON_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_BULK); + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 4U, USB_DEV_EP_NON_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_BULK); + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 5U, USB_DEV_EP_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_ISO); + (void) cyhal_usb_dev_endpoint_add(hal_obj, true, false, 6U, USB_DEV_EP_ISOC_MAX_PACKET, CYHAL_USB_DEV_EP_TYPE_ISO); + + // Clear IN and OUT data endpoint event masks + in_event_mask = 0; + out_event_mask = 0; + + // Configure interrupt and hook interrupt handler + cyhal_usb_dev_register_irq(hal_obj, (cyhal_usb_dev_irq_handler_t)&_usbisr); + cyhal_usb_dev_irq_enable(hal_obj, true); +} + +static void usb_dev_bus_reset_callback(void) +{ + instance->events->reset(); +} + +static void usb_dev_ep0_setup_callback(void) +{ + // Process endpoint 0 SETUP packet (Setup stages) + instance->events->ep0_setup(); +} + +static void usb_dev_ep0_in_callback(void) +{ + // Process endpoint 0 IN packet (Data stage) + instance->events->ep0_in(); +} + +static void usb_dev_ep0_out_callback(void) +{ + // Process endpoint 0 OUT packet (Data stages) + instance->events->ep0_out(); +} + +static void usb_dev_sof_callback(uint32_t frame_number) +{ + // Calls SOF packet callback + instance->events->sof(frame_number); +} + +static void usb_dev_endpoint_callback(cyhal_usb_dev_ep_t endpoint) +{ + if (CYHAL_USB_DEV_IS_IN_EP(endpoint)) { + instance->in_event_mask |= USB_DEV_EP_BIT(endpoint); + } else { + instance->out_event_mask |= USB_DEV_EP_BIT(endpoint); + } +} + +void USBPhyHw::usb_dev_execute_ep_callbacks(void) +{ + if ((0 != in_event_mask) || (0 != out_event_mask)) { + uint32_t mask; + uint32 endpoint; + + // USBPhy must send IN endpoint events before OUT endpoint events if both are pending. + + // Notify IN endpoint transfer complete events + endpoint = 1U; + mask = (uint32_t) in_event_mask; + while (0 != mask) { + if (0 != (mask & 0x1U)) { + events->in(USB_DEV_IN_DIR | endpoint); + } + + mask >>= 1U; + ++endpoint; + } + + // Notify OUT endpoint transfer complete events + endpoint = 1U; + mask = (uint32_t) out_event_mask; + while (0 != mask) { + if (0 != (mask & 0x1U)) { + events->out(endpoint); + } + + mask >>= 1U; + ++endpoint; + } + + out_event_mask = 0; + in_event_mask = 0; + } +} + +void USBPhyHw::deinit() +{ + cyhal_usb_dev_free(&obj); +} + +bool USBPhyHw::powered() +{ + // Not implemented for this target + return true; +} + +void USBPhyHw::connect() +{ + cyhal_usb_dev_connect(&obj); +} + +void USBPhyHw::disconnect() +{ + cyhal_usb_dev_disconnect(&obj); +} + +void USBPhyHw::configure() +{ + cyhal_usb_dev_configure(&obj); +} + +void USBPhyHw::unconfigure() +{ + cyhal_usb_dev_unconfigure(&obj); +} + +void USBPhyHw::sof_enable() +{ + cyhal_usb_dev_sof_enable(&obj, true); +} + +void USBPhyHw::sof_disable() +{ + cyhal_usb_dev_sof_enable(&obj, false); +} + +void USBPhyHw::set_address(uint8_t address) +{ + cyhal_usb_dev_set_address(&obj, address); +} + +void USBPhyHw::remote_wakeup() +{ + // Not implemented for this target +} + +void USBPhyHw::suspend(bool suspended) +{ + // Not implemented for this target + (void) suspended; +} + +const usb_ep_table_t *USBPhyHw::endpoint_table() +{ + static const usb_ep_table_t lpc_table = { + 512, + // CY USB IP has hardware buffer of 512 bytes that is shared among 8 data endpoint. + // The buffer has static allocation as follows: + // - 4 endpoints of 64 that supports BULK and INT. + // - 2 endpoints of 128 that support ISOC, BULK and INT. + // The static allocation of max packet for BULK and INT allows to handle change interface + // alternates properly if endpoint size is changed (the endpoint is not overlapped with + // endpoints of neighborhood interface). + // The CY USB IP has separate endpoint 0 hardware buffer of 8 bytes. + { + {USB_EP_ATTR_ALLOW_CTRL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, + {USB_EP_ATTR_NON_ISO | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {USB_EP_ATTR_NON_ISO | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {USB_EP_ATTR_NON_ISO | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {USB_EP_ATTR_NON_ISO | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {USB_EP_ATTR_DATA_EP | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {USB_EP_ATTR_DATA_EP | USB_EP_ATTR_DIR_IN_OR_OUT, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + } + }; + + return &lpc_table; +} + +uint32_t USBPhyHw::ep0_set_max_packet(uint32_t max_packet) +{ + // Ignore max packet because endpoint 0 has dedicated hardware buffer + (void) max_packet; + + return cyhal_usb_dev_ep0_get_max_packet(&obj); +} + +void USBPhyHw::ep0_setup_read_result(uint8_t *buffer, uint32_t size) +{ + cyhal_usb_dev_ep0_setup_read_result(&obj, buffer, size); +} + +void USBPhyHw::ep0_read(uint8_t *data, uint32_t size) +{ + cyhal_usb_dev_ep0_read(&obj, data, size); +} + +uint32_t USBPhyHw::ep0_read_result() +{ + return cyhal_usb_dev_ep0_read_result(&obj); +} + +void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size) +{ + cyhal_usb_dev_ep0_write(&obj, buffer, size); +} + +void USBPhyHw::ep0_stall() +{ + cyhal_usb_dev_ep0_stall(&obj); +} + +bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type) +{ + bool result = false; + + // The endpoint type is USB spec defined therefore it is safe to cast into the different type used for the same + result = (CY_RSLT_SUCCESS == cyhal_usb_dev_endpoint_add(&obj, false, true, endpoint, max_packet, (cyhal_usb_dev_ep_type_t) type)); + + if (result) { + // Hook endpoint callback to get a notification about transfer completion events + cyhal_usb_dev_register_endpoint_callback(&obj, endpoint, &usb_dev_endpoint_callback); + } + + return result; +} + +void USBPhyHw::endpoint_remove(usb_ep_t endpoint) +{ + (void) cyhal_usb_dev_endpoint_remove(&obj, endpoint); + + // Clear endpoint masks + in_event_mask &= ~USB_DEV_EP_BIT(endpoint); + out_event_mask &= ~USB_DEV_EP_BIT(endpoint); +} + +void USBPhyHw::endpoint_stall(usb_ep_t endpoint) +{ + cy_rslt_t ret = cyhal_usb_dev_endpoint_stall(&obj, endpoint); + MBED_ASSERT(CY_RSLT_SUCCESS == ret); +} + +void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) +{ + cy_rslt_t ret = cyhal_usb_dev_endpoint_unstall(&obj, endpoint); + MBED_ASSERT(CY_RSLT_SUCCESS == ret); +} + +bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + return (CY_RSLT_SUCCESS == cyhal_usb_dev_endpoint_read(&obj, endpoint, data, size)); +} + +uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint) +{ + uint32_t actSize = 0; + + // The read result return actual size zero in case of failure + cy_rslt_t ret = cyhal_usb_dev_endpoint_read_result(&obj, endpoint, &actSize); + MBED_ASSERT(CY_RSLT_SUCCESS == ret); + + return actSize; +} + +bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + return (CY_RSLT_SUCCESS == cyhal_usb_dev_endpoint_write(&obj, endpoint, data, size)); +} + +void USBPhyHw::endpoint_abort(usb_ep_t endpoint) +{ + cy_rslt_t ret = cyhal_usb_dev_endpoint_abort(&obj, endpoint); + MBED_ASSERT(CY_RSLT_SUCCESS == ret); +} + +void USBPhyHw::process() +{ + // Process interrupt + cyhal_usb_dev_process_irq(&obj); + + // Calls data endpoint IN and OUT event in the required order + usb_dev_execute_ep_callbacks(); + + // Enable interrupt after interrupt processing completed + cyhal_usb_dev_irq_enable(&obj, true); +} + +void USBPhyHw::_usbisr(void) +{ + cyhal_usb_dev_t *hal_obj = &(instance->obj); + + // Disable interrupt before start interrupt processing + cyhal_usb_dev_irq_enable(hal_obj, false); + instance->events->start_process(); +} + +#endif /* (DEVICE_USBDEVICE) */