LPC MCUXpresso: Remove extra I2C transaction on byte write #11003
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@mmahadevan108, thank you for your changes. |
An extra start signal was observed on the bus which was discovered by the FPGA test shield. This is because the hardware sends out a transaction as soon as a write to the START bit. Hence the write to the START bit is delayed by using a flag. Signed-off-by: Mahesh Mahadevan <[email protected]>
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c1728p9
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0xc0170
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Jul 10, 2019
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Test run: SUCCESSSummary: 11 of 11 test jobs passed |
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Description
An extra start signal was observed on the bus which was discovered by the FPGA test shield.
This is because the hardware sends out a transaction as soon as a write to the START bit. Hence the write to the START bit is delayed by using a flag.
Pull request type