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LPC43xx port from Micromint
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‎libraries/mbed/targets/cmsis/NXP/TARGET_LPC43XX/LPC43xx.h

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‎libraries/mbed/targets/cmsis/NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx.sct

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LR_IROM1 0x14000000 0x00400000 { ; load region size_region
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ER_IROM1 0x14000000 0x00400000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118
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; 128KB - 0x0118 = 0x0001FEE8
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RW_IRAM1 0x10000118 0x1FEE8 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x10080000 0x12000 { ; RW data
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.ANY (IRAM2)
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}
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RW_IRAM3 0x20000000 0x8000 { ; RW data
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.ANY (AHBSRAM0)
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}
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RW_IRAM4 0x20008000 0x4000 { ; RW data
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.ANY (AHBSRAM1)
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}
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RW_IRAM5 0x2000C000 0x4000 { ; RW data
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.ANY (AHBSRAM2)
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}
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}

‎libraries/mbed/targets/cmsis/NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/startup_LPC43xx.s

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;/***********************************************************************
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; * @brief: LPC18xx/43xx M3/M4 startup code
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; *
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; * @note
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; * Copyright(C) NXP Semiconductors, 2012
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; * All rights reserved.
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; *
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; * @par
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; * Software that is described herein is for illustrative purposes only
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; * which provides customers with programming information regarding the
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; * LPC products. This software is supplied "AS IS" without any warranties of
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; * any kind, and NXP Semiconductors and its licensor disclaim any and
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; * all warranties, express or implied, including all implied warranties of
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; * merchantability, fitness for a particular purpose and non-infringement of
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; * intellectual property rights. NXP Semiconductors assumes no responsibility
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; * or liability for the use of the software, conveys no license or rights under any
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; * patent, copyright, mask work right, or any other intellectual property rights in
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; * or to any products. NXP Semiconductors reserves the right to make changes
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; * in the software without notification. NXP Semiconductors also makes no
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; * representation or warranty that such application will be suitable for the
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; * specified use without further testing or modification.
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; *
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; * @par
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; * Permission to use, copy, modify, and distribute this software and its
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; * documentation is hereby granted, under NXP Semiconductors' and its
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; * licensor's relevant copyrights in the software, without fee, provided that it
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; * is used in conjunction with NXP Semiconductors microcontrollers. This
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; * copyright, permission, and disclaimer notice must appear in all copies of
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; * this code.
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; */
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__initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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Sign_Value EQU 0x5A5A5A5A
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__Vectors DCD __initial_sp ; 0 Top of Stack
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DCD Reset_Handler ; 1 Reset Handler
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DCD NMI_Handler ; 2 NMI Handler
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DCD HardFault_Handler ; 3 Hard Fault Handler
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DCD MemManage_Handler ; 4 MPU Fault Handler
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DCD BusFault_Handler ; 5 Bus Fault Handler
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DCD UsageFault_Handler ; 6 Usage Fault Handler
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DCD Sign_Value ; 7 Reserved
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DCD UnHandled_Vector ; 8 Reserved
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DCD UnHandled_Vector ; 9 Reserved
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DCD UnHandled_Vector ; 10 Reserved
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DCD SVC_Handler ; 11 SVCall Handler
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DCD DebugMon_Handler ; 12 Debug Monitor Handler
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DCD UnHandled_Vector ; 13 Reserved
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DCD PendSV_Handler ; 14 PendSV Handler
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DCD SysTick_Handler ; 15 SysTick Handler
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; External Interrupts
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DCD DAC_IRQHandler ; 16 D/A Converter
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DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
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DCD DMA_IRQHandler ; 18 General Purpose DMA
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DCD UnHandled_Vector ; 19 Reserved
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DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
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DCD ETH_IRQHandler ; 21 Ethernet
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DCD SDIO_IRQHandler ; 22 SD/MMC
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DCD LCD_IRQHandler ; 23 LCD
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DCD USB0_IRQHandler ; 24 USB0
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DCD USB1_IRQHandler ; 25 USB1
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DCD SCT_IRQHandler ; 26 State Configurable Timer
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DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
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DCD TIMER0_IRQHandler ; 28 Timer0
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DCD TIMER1_IRQHandler ; 29 Timer1
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DCD TIMER2_IRQHandler ; 30 Timer2
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DCD TIMER3_IRQHandler ; 31 Timer3
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DCD MCPWM_IRQHandler ; 32 Motor Control PWM
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DCD ADC0_IRQHandler ; 33 A/D Converter 0
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DCD I2C0_IRQHandler ; 34 I2C0
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DCD I2C1_IRQHandler ; 35 I2C1
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DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
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DCD ADC1_IRQHandler ; 37 A/D Converter 1
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DCD SSP0_IRQHandler ; 38 SSP0
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DCD SSP1_IRQHandler ; 39 SSP1
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DCD UART0_IRQHandler ; 40 UART0
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DCD UART1_IRQHandler ; 41 UART1
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DCD UART2_IRQHandler ; 42 UART2
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DCD UART3_IRQHandler ; 43 UART3
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DCD I2S0_IRQHandler ; 44 I2S0
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DCD I2S1_IRQHandler ; 45 I2S1
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DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
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DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
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DCD GPIO0_IRQHandler ; 48 GPIO0
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DCD GPIO1_IRQHandler ; 49 GPIO1
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DCD GPIO2_IRQHandler ; 50 GPIO2
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DCD GPIO3_IRQHandler ; 51 GPIO3
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DCD GPIO4_IRQHandler ; 52 GPIO4
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DCD GPIO5_IRQHandler ; 53 GPIO5
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DCD GPIO6_IRQHandler ; 54 GPIO6
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DCD GPIO7_IRQHandler ; 55 GPIO7
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DCD GINT0_IRQHandler ; 56 GINT0
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DCD GINT1_IRQHandler ; 57 GINT1
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DCD EVRT_IRQHandler ; 58 Event Router
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DCD CAN1_IRQHandler ; 59 C_CAN1
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DCD UnHandled_Vector ; 60 Reserved
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DCD VADC_IRQHandler ; 61 VADC
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DCD ATIMER_IRQHandler ; 62 ATIMER
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DCD RTC_IRQHandler ; 63 RTC
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DCD UnHandled_Vector ; 64 Reserved
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DCD WDT_IRQHandler ; 65 WDT
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DCD UnHandled_Vector ; 66 M0s
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DCD CAN0_IRQHandler ; 67 C_CAN0
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DCD QEI_IRQHandler ; 68 QEI
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; IF :LNOT::DEF:NO_CRP
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; AREA |.ARM.__at_0x02FC|, CODE, READONLY
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;CRP_Key DCD 0xFFFFFFFF
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; ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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IMPORT SystemInit
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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UnHandled_Vector PROC
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EXPORT UnHandled_Vector [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DAC_IRQHandler [WEAK]
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EXPORT MX_CORE_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT FLASHEEPROM_IRQHandler [WEAK]
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EXPORT ETH_IRQHandler [WEAK]
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EXPORT SDIO_IRQHandler [WEAK]
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EXPORT LCD_IRQHandler [WEAK]
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EXPORT USB0_IRQHandler [WEAK]
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EXPORT USB1_IRQHandler [WEAK]
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EXPORT SCT_IRQHandler [WEAK]
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EXPORT RIT_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT MCPWM_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT I2S0_IRQHandler [WEAK]
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EXPORT I2S1_IRQHandler [WEAK]
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EXPORT SPIFI_IRQHandler [WEAK]
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EXPORT SGPIO_IRQHandler [WEAK]
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EXPORT GPIO0_IRQHandler [WEAK]
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EXPORT GPIO1_IRQHandler [WEAK]
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EXPORT GPIO2_IRQHandler [WEAK]
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EXPORT GPIO3_IRQHandler [WEAK]
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EXPORT GPIO4_IRQHandler [WEAK]
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EXPORT GPIO5_IRQHandler [WEAK]
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EXPORT GPIO6_IRQHandler [WEAK]
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EXPORT GPIO7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT EVRT_IRQHandler [WEAK]
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EXPORT CAN1_IRQHandler [WEAK]
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EXPORT VADC_IRQHandler [WEAK]
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EXPORT ATIMER_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT CAN0_IRQHandler [WEAK]
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EXPORT QEI_IRQHandler [WEAK]
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DAC_IRQHandler
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MX_CORE_IRQHandler
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DMA_IRQHandler
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FLASHEEPROM_IRQHandler
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ETH_IRQHandler
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SDIO_IRQHandler
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LCD_IRQHandler
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USB0_IRQHandler
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USB1_IRQHandler
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SCT_IRQHandler
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RIT_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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MCPWM_IRQHandler
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ADC0_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI_IRQHandler
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ADC1_IRQHandler
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SSP0_IRQHandler
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SSP1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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I2S0_IRQHandler
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I2S1_IRQHandler
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SPIFI_IRQHandler
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SGPIO_IRQHandler
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GPIO0_IRQHandler
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GPIO1_IRQHandler
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GPIO2_IRQHandler
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GPIO3_IRQHandler
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GPIO4_IRQHandler
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GPIO5_IRQHandler
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GPIO6_IRQHandler
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GPIO7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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EVRT_IRQHandler
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CAN1_IRQHandler
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VADC_IRQHandler
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ATIMER_IRQHandler
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RTC_IRQHandler
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WDT_IRQHandler
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CAN0_IRQHandler
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QEI_IRQHandler
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B .
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ENDP
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ALIGN
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END

‎libraries/mbed/targets/cmsis/NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp

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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif

‎libraries/mbed/targets/cmsis/NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld

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/*
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* LPC43XX Dual core Blinky stand-alone Cortex-M4 LD script
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*/
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MEMORY
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{
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/* Define each memory region */
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RO_MEM (rx) : ORIGIN = 0x14000000, LENGTH = 0x40000 /* 256K */
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RW_MEM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
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RW_MEM1 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x4000 /* 16K */
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SH_MEM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
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FAT12_MEM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8k */
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}
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__top_RW_MEM = 0x10000000 + 0x8000;
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INCLUDE "lpc43xx_dualcore_lib.ld"
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INCLUDE "lpc43xx_dualcore.ld"

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