Merge pull request #11816 from d-kato/rza1_fix_non_os

Fix failure of building non-RTOS for GR-PEACH, GR-LYCHEE and VK-RZ/A1H

Author: 0xc0170

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c

@@ -22,28 +22,25 @@
  * limitations under the License.
  */
 
-#ifdef MBED_CONF_RTOS_PRESENT
-
-#include "os_tick.h"
 #include "irq_ctrl.h"
 #include "cmsis.h"
 #include "mbed_drv_cfg.h"
 
+// Define OS Timer channel and interrupt number
+#define OSTM                        (OSTM0)
+#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "os_tick.h"
 
 // Define OS TImer interrupt priority
 #ifndef OSTM_IRQ_PRIORITY
 #define OSTM_IRQ_PRIORITY           0xFFU
 #endif
 
-// Define OS Timer channel and interrupt number
-#define OSTM                        (OSTM0)
-#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
-
-
 static uint32_t OSTM_Clock;         // Timer tick frequency
 static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
 
-
 // Setup OS Tick.
 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
 {
@@ -190,10 +187,10 @@ uint32_t OS_Tick_GetOverflow (void)
 {
   return (IRQ_GetPending(OSTM_IRQn));
 }
+#endif
 
 // Get Cortex-A9 OS Timer interrupt number
 IRQn_ID_t mbed_get_a9_tick_irqn(){
   return OSTM_IRQn;
 }
-#endif
 

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c

@@ -22,28 +22,25 @@
  * limitations under the License.
  */
 
-#ifdef MBED_CONF_RTOS_PRESENT
-
-#include "os_tick.h"
 #include "irq_ctrl.h"
 #include "cmsis.h"
 #include "mbed_drv_cfg.h"
 
+// Define OS Timer channel and interrupt number
+#define OSTM                        (OSTM0)
+#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "os_tick.h"
 
 // Define OS TImer interrupt priority
 #ifndef OSTM_IRQ_PRIORITY
 #define OSTM_IRQ_PRIORITY           0xFFU
 #endif
 
-// Define OS Timer channel and interrupt number
-#define OSTM                        (OSTM0)
-#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
-
-
 static uint32_t OSTM_Clock;         // Timer tick frequency
 static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
 
-
 // Setup OS Tick.
 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
 {
@@ -190,10 +187,10 @@ uint32_t OS_Tick_GetOverflow (void)
 {
   return (IRQ_GetPending(OSTM_IRQn));
 }
+#endif
 
 // Get Cortex-A9 OS Timer interrupt number
 IRQn_ID_t mbed_get_a9_tick_irqn(){
   return OSTM_IRQn;
 }
-#endif
 

targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c

@@ -22,28 +22,25 @@
  * limitations under the License.
  */
 
-#ifdef MBED_CONF_RTOS_PRESENT
-
-#include "os_tick.h"
 #include "irq_ctrl.h"
 #include "cmsis.h"
 #include "mbed_drv_cfg.h"
 
+// Define OS Timer channel and interrupt number
+#define OSTM                        (OSTM0)
+#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "os_tick.h"
 
 // Define OS TImer interrupt priority
 #ifndef OSTM_IRQ_PRIORITY
 #define OSTM_IRQ_PRIORITY           0xFFU
 #endif
 
-// Define OS Timer channel and interrupt number
-#define OSTM                        (OSTM0)
-#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
-
-
 static uint32_t OSTM_Clock;         // Timer tick frequency
 static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
 
-
 // Setup OS Tick.
 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
 {
@@ -190,11 +187,10 @@ uint32_t OS_Tick_GetOverflow (void)
 {
   return (IRQ_GetPending(OSTM_IRQn));
 }
+#endif
 
 // Get Cortex-A9 OS Timer interrupt number
 IRQn_ID_t mbed_get_a9_tick_irqn(){
   return OSTM_IRQn;
 }
 
-#endif
-

targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c

@@ -128,6 +128,17 @@ void hal_deepsleep(void) {
     wk_CPGSTBCR13 = CPGSTBCR13;
 #endif
 
+    /* Waits for the serial transmission to complete */
+    const struct st_scif *SCIF[SCIF_COUNT] = SCIF_ADDRESS_LIST;
+
+    for (int uart = 0; uart < SCIF_COUNT; uart++) {
+        if ((wk_CPGSTBCR4 & (1 << (7 - uart))) == 0) {     // Is the power turned on?
+            if ((SCIF[uart]->SCSCR & 0x00A0) == 0x00A0) {  // Is transmission enabled? (TE = 1, TIE = 1)
+                while ((SCIF[uart]->SCFSR & 0x0040) == 0); // Waits for the transmission to complete (TEND = 1)
+            }
+        }
+    }
+
     /* MTU2 (for low power ticker) */
     CPGSTBCR3  |= ~(CPG_STBCR3_BIT_MSTP33);
     dummy_8    = CPGSTBCR3;