Skip to content

Commit b56ab51

Browse files
author
Cruz Monrreal
authored
Merge pull request #9562 from SenRamakri/sen_feature-armc6-update-29-Jan
LPC546XX, MIMXRT1050: Update to fix ARMC6 build failures
2 parents b506b03 + 00477dd commit b56ab51

File tree

7 files changed

+28
-28
lines changed

7 files changed

+28
-28
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_common.h

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -238,16 +238,16 @@ _Pragma("diag_suppress=Pm120")
238238
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
239239
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
240240
#endif
241-
#elif defined(__ARMCC_VERSION)
241+
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
242242
/*! Macro to define a variable with alignbytes alignment */
243-
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
243+
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
244244
/*! Macro to define a variable with L1 d-cache line size alignment */
245245
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
246-
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
246+
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
247247
#endif
248248
/*! Macro to define a variable with L2 cache line size alignment */
249249
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
250-
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
250+
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
251251
#endif
252252
#elif defined(__GNUC__)
253253
/*! Macro to define a variable with alignbytes alignment */
@@ -295,19 +295,19 @@ _Pragma("diag_suppress=Pm120")
295295
#define AT_NONCACHEABLE_SECTION_INIT(var) var
296296
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
297297
#endif
298-
#elif(defined(__ARMCC_VERSION))
298+
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
299299
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
300300
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
301301
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
302-
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
302+
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
303303
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
304304
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
305-
__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
305+
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
306306
#else
307307
#define AT_NONCACHEABLE_SECTION(var) var
308-
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
308+
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
309309
#define AT_NONCACHEABLE_SECTION_INIT(var) var
310-
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
310+
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
311311
#endif
312312
#elif(defined(__GNUC__))
313313
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
@@ -446,10 +446,10 @@ _Pragma("diag_suppress=Pm120")
446446
}
447447

448448
/*!
449-
* @brief Enaable the global IRQ
449+
* @brief Enable the global IRQ
450450
*
451451
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
452-
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
452+
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
453453
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
454454
*
455455
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737
* Code
3838
******************************************************************************/
3939
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
40-
#if defined(__CC_ARM) || defined(__GNUC__)
40+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
4141
__attribute__((section(".boot_hdr.conf")))
4242
#elif defined(__ICCARM__)
4343
#pragma location = ".boot_hdr.conf"

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535

3636
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
3737
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
38-
#if defined(__CC_ARM) || defined(__GNUC__)
38+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
3939
__attribute__((section(".boot_hdr.dcd_data")))
4040
#elif defined(__ICCARM__)
4141
#pragma location = ".boot_hdr.dcd_data"

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#ifndef MBED_CMSIS_NVIC_H
3232
#define MBED_CMSIS_NVIC_H
3333

34-
#if defined(__CC_ARM)
34+
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
3535
extern uint32_t Image$$VECTOR_RAM$$Base[];
3636
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
3737
#else

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -249,16 +249,16 @@ _Pragma("diag_suppress=Pm120")
249249
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
250250
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
251251
#endif
252-
#elif defined(__ARMCC_VERSION)
252+
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
253253
/*! Macro to define a variable with alignbytes alignment */
254-
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
254+
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
255255
/*! Macro to define a variable with L1 d-cache line size alignment */
256256
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
257-
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
257+
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
258258
#endif
259259
/*! Macro to define a variable with L2 cache line size alignment */
260260
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
261-
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
261+
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
262262
#endif
263263
#elif defined(__GNUC__)
264264
/*! Macro to define a variable with alignbytes alignment */
@@ -306,19 +306,19 @@ _Pragma("diag_suppress=Pm120")
306306
#define AT_NONCACHEABLE_SECTION_INIT(var) var
307307
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
308308
#endif
309-
#elif(defined(__ARMCC_VERSION))
309+
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
310310
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
311311
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
312312
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
313-
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
313+
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
314314
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
315315
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
316-
__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
316+
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
317317
#else
318318
#define AT_NONCACHEABLE_SECTION(var) var
319-
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
319+
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
320320
#define AT_NONCACHEABLE_SECTION_INIT(var) var
321-
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
321+
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
322322
#endif
323323
#elif(defined(__GNUC__))
324324
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
@@ -459,10 +459,10 @@ _Pragma("diag_suppress=Pm120")
459459
}
460460

461461
/*!
462-
* @brief Enaable the global IRQ
462+
* @brief Enable the global IRQ
463463
*
464464
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
465-
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
465+
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
466466
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
467467
*
468468
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
#include "fsl_flexspi_nor_boot.h"
3535

3636
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
37-
#if defined(__CC_ARM) || defined(__GNUC__)
37+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
3838
__attribute__((section(".boot_hdr.ivt")))
3939
#elif defined(__ICCARM__)
4040
#pragma location=".boot_hdr.ivt"
@@ -53,7 +53,7 @@ const ivt image_vector_table = {
5353
IVT_RSVD /* Reserved = 0 */
5454
};
5555

56-
#if defined(__CC_ARM) || defined(__GNUC__)
56+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
5757
__attribute__((section(".boot_hdr.boot_data")))
5858
#elif defined(__ICCARM__)
5959
#pragma location=".boot_hdr.boot_data"

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ typedef struct _ivt_ {
8383
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
8484

8585
/* Set resume entry */
86-
#if defined(__CC_ARM)
86+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
8787
extern uint32_t __Vectors[];
8888
extern uint32_t Image$$RW_m_config_text$$Base[];
8989
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)

0 commit comments

Comments
 (0)