Skip to content

Commit 8993dcf

Browse files
theamirocohentheamirocohen
committed
Print peripheral on ACL violation from debug blinky example
Print the name of a peripheral when faulting on an address belonging to a perhipheral. The memory maps of K64F and STM32F4 were added.
1 parent cb903b0 commit 8993dcf

File tree

5 files changed

+330
-1
lines changed

5 files changed

+330
-1
lines changed

‎mbed-os.lib

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
https://github.com/ARMmbed/mbed-os/#98ba8acb83cfc65f30a8a0771a27c71443ab093a
1+
https://github.com/ARMmbed/mbed-os/#9c1fd485299861c65e0c0e477dc111bebe40ae5c

‎source/main.cpp

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "uvisor-lib/uvisor-lib.h"
1818
#include "mbed.h"
1919
#include "main-hw.h"
20+
#include "mem_map.h"
2021

2122
/* Create ACLs for main box. */
2223
MAIN_ACL(g_main_acl);
@@ -25,6 +26,26 @@ MAIN_ACL(g_main_acl);
2526
UVISOR_SET_MODE_ACL(UVISOR_ENABLED, g_main_acl);
2627
UVISOR_SET_PAGE_HEAP(8 * 1024, 5);
2728

29+
static void example_halt_error(THaltError reason, const THaltInfo *halt_info);
30+
31+
UVISOR_PUBLIC_BOX_DEBUG_DRIVER(example_halt_error);
32+
33+
static void example_halt_error(THaltError reason, const THaltInfo *halt_info) {
34+
35+
const MemMap * map = NULL;
36+
if (halt_info->bfar) {
37+
map = memory_map_name(halt_info->bfar);
38+
}
39+
40+
printf("\n\r");
41+
printf(" Address: 0x%08X\n\r", halt_info->bfar);
42+
printf(" Region/Peripheral: %s\n\r", (map ? map->name : "[not available]"));
43+
printf(" Base address: 0x%08X\n\r", (map ? map->base : halt_info->bfar));
44+
printf(" End address: 0x%08X\n\r", (map ? map->end : halt_info->bfar));
45+
46+
return;
47+
}
48+
2849
/* Targets with an ARMv7-M MPU needs this space adjustment to prevent a runtime
2950
* memory overflow error. The code below has been output directly by uVisor. */
3051
#if defined(TARGET_EFM32GG_STK3700) || defined(TARGET_DISCO_F429ZI)

‎source/mem_map/mem_map.cpp

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
/*
2+
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
3+
* SPDX-License-Identifier: Apache-2.0
4+
*
5+
* Licensed under the Apache License, Version 2.0 (the "License"); you may
6+
* not use this file except in compliance with the License.
7+
* You may obtain a copy of the License at
8+
*
9+
* http://www.apache.org/licenses/LICENSE-2.0
10+
*
11+
* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
13+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
18+
#include "uvisor-lib/uvisor-lib.h"
19+
#include "mbed.h"
20+
#include "main-hw.h"
21+
#include "mem_map.h"
22+
#include "plat_mem_map.h"
23+
24+
const MemMap* memory_map_name(uint32_t addr)
25+
{
26+
int i;
27+
const MemMap * map = NULL;
28+
29+
/* find system memory region */
30+
map = g_mem_map;
31+
for(i = 0; i < UVISOR_ARRAY_COUNT(g_mem_map); i++) {
32+
if((addr >= map->base) && (addr <= map->end)) {
33+
return map;
34+
}
35+
else {
36+
map++;
37+
}
38+
}
39+
40+
return NULL;
41+
}
42+

‎source/mem_map/mem_map.h

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
/*
2+
* Copyright (c) 2013-2015, ARM Limited, All Rights Reserved
3+
* SPDX-License-Identifier: Apache-2.0
4+
*
5+
* Licensed under the Apache License, Version 2.0 (the "License"); you may
6+
* not use this file except in compliance with the License.
7+
* You may obtain a copy of the License at
8+
*
9+
* http://www.apache.org/licenses/LICENSE-2.0
10+
*
11+
* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
13+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
#ifndef __MEM_MAP_H__
18+
#define __MEM_MAP_H__
19+
20+
typedef struct mem_map {
21+
const char * name;
22+
uint32_t base;
23+
uint32_t end;
24+
} MemMap;
25+
26+
const MemMap * memory_map_name(uint32_t addr);
27+
28+
#endif/*__MEM_MAP_H__*/

‎source/mem_map/plat_mem_map.h

Lines changed: 238 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,238 @@
1+
/*
2+
* Copyright (c) 2013-2015, ARM Limited, All Rights Reserved
3+
* SPDX-License-Identifier: Apache-2.0
4+
*
5+
* Licensed under the Apache License, Version 2.0 (the "License"); you may
6+
* not use this file except in compliance with the License.
7+
* You may obtain a copy of the License at
8+
*
9+
* http://www.apache.org/licenses/LICENSE-2.0
10+
*
11+
* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
13+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
#ifndef __PLAT_MEM_MAP_H__
18+
#define __PLAT_MEM_MAP_H__
19+
20+
#if defined(TARGET_K64F)
21+
const MemMap g_mem_map[] = {
22+
{"Flash", 0x00000000, 0x000FFFFF}, /* available Flash */
23+
{">FlexBus", 0x08000000, 0x0FFFFFFF}, /* (alias) FlexBus */
24+
{"Acc. RAM", 0x14000000, 0x14000FFF}, /* Programming acceleration RAM */
25+
{">FlexBus", 0x18000000, 0x1BFFFFFF}, /* (alias) FlexBus */
26+
{"SRAM", 0x1FFF0000, 0x2002FFFF}, /* available SRAM */
27+
{">TCMU", 0x22000000, 0x23FFFFFF}, /* (alias) TCMU SRAM */
28+
{">Flash D.", 0x30000000, 0x3007FFFF}, /* (alias) Flash Data */
29+
{">Flash F.", 0x34000000, 0x3FFFFFFF}, /* (alias) Flash Flex */
30+
{"AIPS0", 0x40000000, 0x40000210}, /* start of AIPS0 */
31+
{"AXBS", 0x40004000, 0x40007410},
32+
{"DMA", 0x40008000, 0x4000C800},
33+
{"FB", 0x4000C000, 0x4000C190},
34+
{"MPU", 0x4000D000, 0x4000F0C0},
35+
{"FMC", 0x4001F000, 0x4001FA00},
36+
{"FTFE", 0x40020000, 0x40020060},
37+
{"DMAMUX", 0x40021000, 0x40021040},
38+
{"CAN0", 0x40024000, 0x40026300},
39+
{"RNG", 0x40029000, 0x40029040},
40+
{"SPI0", 0x4002C000, 0x4002C230},
41+
{"SPI1", 0x4002D000, 0x4002D230},
42+
{"I2S0", 0x4002F000, 0x4002F420},
43+
{"CRC", 0x40032000, 0x40032030},
44+
{"USBDCD", 0x40035000, 0x40035070},
45+
{"PDB0", 0x40036000, 0x40036680},
46+
{"PIT", 0x40037000, 0x40037500},
47+
{"FTM0", 0x40038000, 0x40038270},
48+
{"FTM1", 0x40039000, 0x40039270},
49+
{"FTM2", 0x4003A000, 0x4003A270},
50+
{"ADC0", 0x4003B000, 0x4003B1C0},
51+
{"RTC", 0x4003D000, 0x4003F020},
52+
{"RFVBAT", 0x4003E000, 0x4003E080},
53+
{"LPTMR0", 0x40040000, 0x40040040},
54+
{"RFSYS", 0x40041000, 0x40041080},
55+
{"SIM", 0x40047000, 0x40048068},
56+
{"PORTA", 0x40049000, 0x40049330},
57+
{"PORTB", 0x4004A000, 0x4004A330},
58+
{"PORTC", 0x4004B000, 0x4004B330},
59+
{"PORTD", 0x4004C000, 0x4004C330},
60+
{"PORTE", 0x4004D000, 0x4004D330},
61+
{"WDOG", 0x40052000, 0x40052060},
62+
{"EWM", 0x40061000, 0x40061010},
63+
{"CMT", 0x40062000, 0x40062030},
64+
{"MCG", 0x40064000, 0x40064038},
65+
{"OSC", 0x40065000, 0x40065004},
66+
{"I2C0", 0x40066000, 0x40066030},
67+
{"I2C1", 0x40067000, 0x40067030},
68+
{"UART0", 0x4006A000, 0x4006A080},
69+
{"UART1", 0x4006B000, 0x4006B080},
70+
{"UART2", 0x4006C000, 0x4006C080},
71+
{"UART3", 0x4006D000, 0x4006D080},
72+
{"USB0", 0x40072000, 0x40072574},
73+
{"CMP0", 0x40073000, 0x40073018},
74+
{"CMP1", 0x40073008, 0x40073020},
75+
{"CMP2", 0x40073010, 0x40073028},
76+
{"VREF", 0x40074000, 0x40074008},
77+
{"LLWU", 0x4007C000, 0x4007C02C},
78+
{"PMC", 0x4007D000, 0x4007D00C},
79+
{"SMC", 0x4007E000, 0x4007E010},
80+
{"RCM", 0x4007F000, 0x4007F020}, /* end of AIPS0 */
81+
{"AIPS1", 0x40080000, 0x40080210}, /* start of AIPS1 */
82+
{"SPI2", 0x400AC000, 0x400AC230},
83+
{"SDHC", 0x400B1000, 0x400B1400},
84+
{"FTM3", 0x400B9000, 0x400B9270},
85+
{"ADC1", 0x400BB000, 0x400BB1C0},
86+
{"ENET", 0x400C0000, 0x400C18A0},
87+
{"DAC0", 0x400CC000, 0x400CC090},
88+
{"DAC1", 0x400CD000, 0x400CD090},
89+
{"I2C2", 0x400E6000, 0x400E6030},
90+
{"UART4", 0x400EA000, 0x400EA080},
91+
{"UART5", 0x400EB000, 0x400EB080}, /* end of AIPS1 */
92+
{"PTA", 0x400FF000, 0x400FF060}, /* start of GPIO */
93+
{"PTB", 0x400FF040, 0x400FF0A0},
94+
{"PTC", 0x400FF080, 0x400FF0E0},
95+
{"PTD", 0x400FF0C0, 0x400FF120},
96+
{"PTE", 0x400FF100, 0x400FF160}, /* end of GPIO */
97+
{">AIPS-GPIO", 0x42000000, 0x43FFFFFF}, /* (alias) AIPS0, AIPS1, GPIO */
98+
{"FlexBusWB", 0x60000000, 0x7FFFFFFF}, /* FlexBus (Write-Back) */
99+
{"FlexBusWT", 0x80000000, 0x9FFFFFFF}, /* FlexBus (Write-Through) */
100+
{"FlexBusXN", 0xA0000000, 0xDFFFFFFF}, /* FlexBus (peripherals, XN) */
101+
{"ITM", 0xE0000000, 0xE0000FFF}, /* start of PPB */
102+
{"DWT", 0xE0001000, 0xE0001FFF},
103+
{"FPB", 0xE0002000, 0xE0002FFF},
104+
{"SCS", 0xE000E000, 0xE000EFFF},
105+
{"TPIU", 0xE0040000, 0xE0040FFF},
106+
{"ETM", 0xE0041000, 0xE0041FFF},
107+
{"ETB", 0xE0042000, 0xE0042FFF},
108+
{"ETF", 0xE0043000, 0xE0043FFF},
109+
{"MCM", 0xE0080000, 0xE0080FFF},
110+
{"MMCAU", 0xE0081000, 0xE0081FFF},
111+
{"ROMTable", 0xE00FF000, 0xE00FFFFF}, /* end of PPB */
112+
};
113+
114+
#elif defined(TARGET_STM32F4)
115+
static const MemMap g_mem_map[] = {
116+
{">Flash", 0x00000000, FLASH_END - FLASH_BASE },
117+
{"Flash", FLASH_BASE, FLASH_END },
118+
{"CCM", CCMDATARAM_BASE, CCMDATARAM_END, },
119+
{"SRAM1", SRAM1_BASE, SRAM2_BASE - 1 },
120+
{"SRAM2", SRAM2_BASE, SRAM3_BASE - 1 },
121+
{"SRAM3", SRAM3_BASE, SRAM3_BASE + 0x10000 - 1 },
122+
{"TIM2", TIM2_BASE, TIM2_BASE + sizeof(TIM_TypeDef) },
123+
{"TIM3", TIM3_BASE, TIM3_BASE + sizeof(TIM_TypeDef) },
124+
{"TIM4", TIM4_BASE, TIM4_BASE + sizeof(TIM_TypeDef) },
125+
{"TIM5", TIM5_BASE, TIM5_BASE + sizeof(TIM_TypeDef) },
126+
{"TIM6", TIM6_BASE, TIM6_BASE + sizeof(TIM_TypeDef) },
127+
{"TIM7", TIM7_BASE, TIM7_BASE + sizeof(TIM_TypeDef) },
128+
{"TIM12", TIM12_BASE, TIM12_BASE + sizeof(TIM_TypeDef) },
129+
{"TIM13", TIM13_BASE, TIM13_BASE + sizeof(TIM_TypeDef) },
130+
{"TIM14", TIM14_BASE, TIM14_BASE + sizeof(TIM_TypeDef) },
131+
{"RTC", RTC_BASE, RTC_BASE + sizeof(RTC_TypeDef) },
132+
{"WWDG", WWDG_BASE, WWDG_BASE + sizeof(WWDG_TypeDef) },
133+
{"IWDG", IWDG_BASE, IWDG_BASE + sizeof(IWDG_TypeDef) },
134+
{"I2S2e", I2S2ext_BASE, I2S2ext_BASE + sizeof(SPI_TypeDef) },
135+
{"SPI2", SPI2_BASE, SPI2_BASE + sizeof(SPI_TypeDef) },
136+
{"SPI3", SPI3_BASE, SPI3_BASE + sizeof(SPI_TypeDef) },
137+
{"I2S3e", I2S3ext_BASE, I2S3ext_BASE + sizeof(SPI_TypeDef) },
138+
{"USART2", USART2_BASE, USART2_BASE + sizeof(USART_TypeDef) },
139+
{"USART3", USART3_BASE, USART3_BASE + sizeof(USART_TypeDef) },
140+
{"UART4", UART4_BASE, UART4_BASE + sizeof(USART_TypeDef) },
141+
{"UART5", UART5_BASE, UART5_BASE + sizeof(USART_TypeDef) },
142+
{"I2C1", I2C1_BASE, I2C1_BASE + sizeof(I2C_TypeDef) },
143+
{"I2C2", I2C2_BASE, I2C2_BASE + sizeof(I2C_TypeDef) },
144+
{"I2C3", I2C3_BASE, I2C3_BASE + sizeof(I2C_TypeDef) },
145+
{"CAN1", CAN1_BASE, CAN1_BASE + sizeof(CAN_TypeDef) },
146+
{"CAN2", CAN2_BASE, CAN2_BASE + sizeof(CAN_TypeDef) },
147+
{"PWR", PWR_BASE, PWR_BASE + sizeof(PWR_TypeDef) },
148+
{"DAC", DAC_BASE, DAC_BASE + sizeof(DAC_TypeDef) },
149+
{"UART7", UART7_BASE, UART7_BASE + sizeof(USART_TypeDef) },
150+
{"UART8", UART8_BASE, UART8_BASE + sizeof(USART_TypeDef) },
151+
{"TIM1", TIM1_BASE, TIM1_BASE + sizeof(TIM_TypeDef) },
152+
{"TIM8", TIM8_BASE, TIM8_BASE + sizeof(TIM_TypeDef) },
153+
{"USART1", USART1_BASE, USART1_BASE + sizeof(USART_TypeDef) },
154+
{"USART6", USART6_BASE, USART6_BASE + sizeof(USART_TypeDef) },
155+
{"ADC1", ADC1_BASE, ADC1_BASE + sizeof(ADC_TypeDef) },
156+
{"ADC2", ADC2_BASE, ADC2_BASE + sizeof(ADC_TypeDef) },
157+
{"ADC3", ADC3_BASE, ADC3_BASE + sizeof(ADC_TypeDef) },
158+
{"ADC", ADC_BASE, ADC_BASE + sizeof(ADC_Common_TypeDef) },
159+
{"SDIO", SDIO_BASE, SDIO_BASE + sizeof(SDIO_TypeDef) },
160+
{"SPI1", SPI1_BASE, SPI1_BASE + sizeof(SPI_TypeDef) },
161+
{"SPI4", SPI4_BASE, SPI4_BASE + sizeof(SPI_TypeDef) },
162+
{"SYSCFG", SYSCFG_BASE, SYSCFG_BASE + sizeof(SYSCFG_TypeDef) },
163+
{"EXTI", EXTI_BASE, EXTI_BASE + sizeof(EXTI_TypeDef) },
164+
{"TIM9", TIM9_BASE, TIM9_BASE + sizeof(TIM_TypeDef) },
165+
{"TIM10", TIM10_BASE, TIM10_BASE + sizeof(TIM_TypeDef) },
166+
{"TIM11", TIM11_BASE, TIM11_BASE + sizeof(TIM_TypeDef) },
167+
{"SPI5", SPI5_BASE, SPI5_BASE + sizeof(SPI_TypeDef) },
168+
{"SPI6", SPI6_BASE, SPI6_BASE + sizeof(SPI_TypeDef) },
169+
{"SAI1", SAI1_BASE, SAI1_BASE + sizeof(SAI_TypeDef) },
170+
{"SAI1bA", SAI1_Block_A_BASE, SAI1_Block_A_BASE + sizeof(SAI_Block_TypeDef) },
171+
{"SAI1bB", SAI1_Block_B_BASE, SAI1_Block_B_BASE + sizeof(SAI_Block_TypeDef) },
172+
{"LTDC", LTDC_BASE, LTDC_BASE + sizeof(LTDC_TypeDef) },
173+
{"LTDCl1", LTDC_Layer1_BASE, LTDC_Layer1_BASE + sizeof(LTDC_Layer_TypeDef) },
174+
{"LTDCl2", LTDC_Layer2_BASE, LTDC_Layer2_BASE + sizeof(LTDC_Layer_TypeDef) },
175+
{"GPIOA", GPIOA_BASE, GPIOA_BASE + sizeof(GPIO_TypeDef) },
176+
{"GPIOB", GPIOB_BASE, GPIOB_BASE + sizeof(GPIO_TypeDef) },
177+
{"GPIOC", GPIOC_BASE, GPIOC_BASE + sizeof(GPIO_TypeDef) },
178+
{"GPIOD", GPIOD_BASE, GPIOD_BASE + sizeof(GPIO_TypeDef) },
179+
{"GPIOE", GPIOE_BASE, GPIOE_BASE + sizeof(GPIO_TypeDef) },
180+
{"GPIOF", GPIOF_BASE, GPIOF_BASE + sizeof(GPIO_TypeDef) },
181+
{"GPIOG", GPIOG_BASE, GPIOG_BASE + sizeof(GPIO_TypeDef) },
182+
{"GPIOH", GPIOH_BASE, GPIOH_BASE + sizeof(GPIO_TypeDef) },
183+
{"GPIOI", GPIOI_BASE, GPIOI_BASE + sizeof(GPIO_TypeDef) },
184+
{"GPIOJ", GPIOJ_BASE, GPIOJ_BASE + sizeof(GPIO_TypeDef) },
185+
{"GPIOK", GPIOK_BASE, GPIOK_BASE + sizeof(GPIO_TypeDef) },
186+
{"CRC", CRC_BASE, CRC_BASE + sizeof(CRC_TypeDef) },
187+
{"RCC", RCC_BASE, RCC_BASE + sizeof(RCC_TypeDef) },
188+
{"FLASHr", FLASH_R_BASE, FLASH_R_BASE + sizeof(FLASH_TypeDef) },
189+
{"BKPSRAM", BKPSRAM_BASE, BKPSRAM_BASE + 0x1000 - 1 },
190+
{"DMA1", DMA1_BASE, DMA1_BASE + sizeof(DMA_TypeDef) },
191+
{"DMA1s0", DMA1_Stream0_BASE, DMA1_Stream0_BASE + sizeof(DMA_Stream_TypeDef) },
192+
{"DMA1s1", DMA1_Stream1_BASE, DMA1_Stream1_BASE + sizeof(DMA_Stream_TypeDef) },
193+
{"DMA1s2", DMA1_Stream2_BASE, DMA1_Stream2_BASE + sizeof(DMA_Stream_TypeDef) },
194+
{"DMA1s3", DMA1_Stream3_BASE, DMA1_Stream3_BASE + sizeof(DMA_Stream_TypeDef) },
195+
{"DMA1s4", DMA1_Stream4_BASE, DMA1_Stream4_BASE + sizeof(DMA_Stream_TypeDef) },
196+
{"DMA1s5", DMA1_Stream5_BASE, DMA1_Stream5_BASE + sizeof(DMA_Stream_TypeDef) },
197+
{"DMA1s6", DMA1_Stream6_BASE, DMA1_Stream6_BASE + sizeof(DMA_Stream_TypeDef) },
198+
{"DMA1s7", DMA1_Stream7_BASE, DMA1_Stream7_BASE + sizeof(DMA_Stream_TypeDef) },
199+
{"DMA2", DMA2_BASE, DMA2_BASE + sizeof(TIM_TypeDef) },
200+
{"DMA2s0", DMA2_Stream0_BASE, DMA2_Stream0_BASE + sizeof(DMA_Stream_TypeDef) },
201+
{"DMA2s1", DMA2_Stream1_BASE, DMA2_Stream1_BASE + sizeof(DMA_Stream_TypeDef) },
202+
{"DMA2s2", DMA2_Stream2_BASE, DMA2_Stream2_BASE + sizeof(DMA_Stream_TypeDef) },
203+
{"DMA2s3", DMA2_Stream3_BASE, DMA2_Stream3_BASE + sizeof(DMA_Stream_TypeDef) },
204+
{"DMA2s4", DMA2_Stream4_BASE, DMA2_Stream4_BASE + sizeof(DMA_Stream_TypeDef) },
205+
{"DMA2s5", DMA2_Stream5_BASE, DMA2_Stream5_BASE + sizeof(DMA_Stream_TypeDef) },
206+
{"DMA2s6", DMA2_Stream6_BASE, DMA2_Stream6_BASE + sizeof(DMA_Stream_TypeDef) },
207+
{"DMA2s7", DMA2_Stream7_BASE, DMA2_Stream7_BASE + sizeof(DMA_Stream_TypeDef) },
208+
{"ETH", ETH_BASE, ETH_BASE + sizeof(ETH_TypeDef) },
209+
{"DMA2D", DMA2D_BASE, DMA2D_BASE + sizeof(DMA2D_TypeDef) },
210+
{"UOTGhs", USB_OTG_HS_PERIPH_BASE, USB_OTG_HS_PERIPH_BASE + sizeof(USB_OTG_GlobalTypeDef)},
211+
{"UOTGfs", USB_OTG_FS_PERIPH_BASE, USB_OTG_FS_PERIPH_BASE + sizeof(USB_OTG_GlobalTypeDef)},
212+
{"DCMI", DCMI_BASE, DCMI_BASE + sizeof(DCMI_TypeDef) },
213+
{"RNG", RNG_BASE, RNG_BASE + sizeof(RNG_TypeDef) },
214+
{"FMCb1", FMC_Bank1_R_BASE, FMC_Bank1_R_BASE + sizeof(FMC_Bank1_TypeDef) },
215+
{"FMCb1e", FMC_Bank1E_R_BASE, FMC_Bank1E_R_BASE + sizeof(FMC_Bank1E_TypeDef) },
216+
{"FMCb23", FMC_Bank2_3_R_BASE, FMC_Bank2_3_R_BASE + sizeof(FMC_Bank2_3_TypeDef) },
217+
{"FMCb4", FMC_Bank4_R_BASE, FMC_Bank4_R_BASE + sizeof(FMC_Bank4_TypeDef) },
218+
{"FMCb56", FMC_Bank5_6_R_BASE, FMC_Bank5_6_R_BASE + sizeof(FMC_Bank5_6_TypeDef) },
219+
{"ITM", ITM_BASE, ITM_BASE + sizeof(ITM_Type) },
220+
{"DWT", DWT_BASE, DWT_BASE + sizeof(DWT_Type) },
221+
{"SCS", SCS_BASE, SCS_BASE + sizeof(SCnSCB_Type) },
222+
{"SysT", SysTick_BASE, SysTick_BASE + sizeof(SysTick_Type) },
223+
{"NVIC", NVIC_BASE, NVIC_BASE + sizeof(NVIC_Type) },
224+
{"SCB", SCB_BASE, SCB_BASE + sizeof(SCB_Type) },
225+
{"MPU", MPU_BASE, MPU_BASE + sizeof(MPU_Type) },
226+
{"CrDbg", CoreDebug_BASE, CoreDebug_BASE + sizeof(CoreDebug_Type) },
227+
{"FPU", FPU_BASE, FPU_BASE + sizeof(FPU_Type) },
228+
{"TPI", TPI_BASE, TPI_BASE + sizeof(TPI_Type) },
229+
};
230+
231+
#else
232+
const MemMap g_mem_map[] = {
233+
{"[not available]", 0x00000000, 0x00000000}
234+
};
235+
236+
#endif
237+
#endif/*__PLAT_MEM_MAP_H__*/
238+

0 commit comments

Comments
 (0)