`AnalogInput` reporting incorrect values

[bparks13]

Using the attached workflow below, the AnalogOutput node is sending a range of values from -5 to +5 volts, but the AnalogInput node is reporting values ranging from -3.2 to 1.5 volts.

Connecting the output to an oscilloscope, the actual values being delivered by the device are correct:

@cjsha mentioned it could be related to this issue: #8

Bonsai Workflow

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[jonnew]

This needs more information to be useful. its very unlikely this has to do with this library. What hardware was this reported on?

[bparks13]

@cjsha this was tested on both breakout boards and had similar results on both, correct?

[cjsha]

The screenshot in bparks13's original post is from the breakout board on bpark13's remote setup. This screenshot below is from the breakout board on jonnew's workstation.

It has the same behavior where the waveform looks roughly correct but the range of the sawtooth on the analog output (+/- 5V) is totally different from what the range read by the analog input (which is about from -6.5V to +3V). On bparks13 setup, the AnalogInput read the sawtooth waveform in the -3.2 to +1.5V range. Here's the same screenshot as before, except AnalogInput "DataValue" property is set to "S16" instead of "Volts"

The undesired behavior persists with S16 instead of Volts, which I think points away from some weird S16->Volts conversion problem. It might instead be a hardware problem as both bparks13 and jonnew mentioned.

[aacuevas]

How does plugging a signal generator to the analog input behave?
This seems maybe an issue with the analog input instead of the output

[cjsha]

@aacuevas it's the same result. Here's a 4Hz sinewave, no vertical offset

The AnalogInput is showing offset + voltage peak-to-peak error from the input signal.

[aacuevas]

What is the input range configured for the analog input? Are the offset and scaling issues constant (or scaled) with different settings for the range?

[cjsha]

The previous screenshot was taken with +/- 10V.

The following screenshot was taken with +/- 2.5V.

The following screenshot was taken with +/- 5V.

all screenshots taken with the same input

[cjsha]

We grounded one channel to look at the zero offset during tech talk. Here are the results from that (Aaron's notes from tech talk):

• Peak-to-peak amplitude is good at all settings
• Zero-point has an offset that scales with the input range (~1.8v at 10/-10, ~0.9 at 5/-5 ~0.45 at 2.5/-2.5)
• Points to a hw issue with the input scaler

The following screenshot is created using a 5Vpp sine wave centered at zero:

[cjsha]

I probed the V0AGND and V0A pins while sending a zero-offset 5Vpp sine wave signal through the breakout board's analog input. Here's the o-scope measurement.:

• Ch1 (yellow) is the zero-offset 5Vpp sine wave connected directly from the signal generator to AIN0 and the o-scope by BNC
• Ch2 (green) is V0AGND
• Ch3 (orange) is the signal propagated to V0A

Ch1 and Ch3 overlap, so the yellow trace is obscured by the orange trace.

Here's the measurement by the fmc's analog input:

I also shorted V0A and V0AGND, the offset's like -5984 bits which isn't really much different.

[cjsha]

Although the pseudo-differential signal at the inputs of the ADC do not exhibit any offset, the ADC seems to be creating an offset regardless, considering that the offset is causing saturation at -2.5V when sending a 5Vpp sine wave. This might be due to some misconfiguration of the ADC's registers or perhaps some external wiring. Per issue-sorting meeting today, @jonnew volunteered to go through the AD7616's datasheet and try to understand any potential misconfiguration.

I should note that the following bodges mentioned here are true:

1. Replace AD1617 with AD1616 (16-bit version that i was original using before chip shortage)
2. Remove R63 and bodge REFSEL to DGND

Here's the relevant configuration:
https://github.com/open-ephys/onix-common-hdl/blob/8576acc83722b716af3c1a23855ac502d64bc44a/devices/ad7617_device.vhd#L141-L148

[jonnew]

I am beginning to suspect this is caused by improper !RESET behavior. This chip has several requirements for the its !RESET pin, basically none of which are followed.

Full vs. Partial reset

• Full Reset: Determines if hardware (strap pins) or software (SPI registers) are used to determine chip operation.
• Partial Reset: Resets the ADC, SPI interface etc. Does not resample if hardware or software mode is selected.

Requirements

• !RESET should be held low for 1 msec after power supplies stabilize. It is defaulted high by the gateware so it will be forced high whenever the FPGA has power. I'm not sure what the relationship is with AD7616's VCC but its not enforced in any case.
• !RESET should be held low for 1.2 usec after that to issue full reset
• Given the RC filter on this pin, I'm not sure if its ever effectively toggled by the short partial resets were issuing.

Issue

The overall story is that the signal going to the !RESET pin was not properly considered. We need to investigate its power on behavior and behavior during operation. Its very possible that the chip is getting stuck in some hardware controlled state and all SPI configuration commands are being ignored.

• Potentially replace RC with zero ohm Resistor and 10k pulldown where C is to forced RESET during power up that must be released by firmware
• Investigate power on state of FPGA pin
• Investigate if Partial reset is even making it to the pin given the RC